Display device comprising an auxiliary layer

Abstract

A display device is provided, comprising a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer comprises Si. A second lower gate electrode overlaps with a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second lower gate electrode. A second upper gate electrode and a light-blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second upper gate electrode and the light-blocking layer. The first semiconductor layer overlaps with the light-blocking layer. The first semiconductor layer comprises an oxide semiconductor. A first gate electrode overlaps with a channel region of the first semiconductor layer. The first auxiliary layer comprises an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer comprises SiN. x SiO x and at least one compound of SiON.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0107688, filed on August 30, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to display devices, and more particularly to display devices including an auxiliary layer. Background Technology

[0004] The display panel may include multiple pixels and driving circuitry for controlling the multiple pixels. The driving circuitry may include at least one thin-film transistor. The thin-film transistor constituting the driving circuitry supplies electrical signals for controlling the multiple pixels to the respective pixels.

[0005] Each of the plurality of pixels may include a pixel driving circuit and a display element connected to the pixel driving circuit. The pixel driving circuit may include at least one thin-film transistor and a capacitor. The thin-film transistor and capacitor constituting the pixel driving circuit control the display element according to an electrical signal supplied from the driving circuit. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a display device is provided, the display device including a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer includes Si. A second lower gate electrode overlaps with a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second lower gate electrode. A second upper gate electrode and a light-blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second upper gate electrode and the light-blocking layer. The first semiconductor layer overlaps with the light-blocking layer. The first semiconductor layer includes an oxide semiconductor. A first gate electrode overlaps with a channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C, the insulating layer including SiN. x SiO x and at least one compound of SiON.

[0007] According to an exemplary embodiment of the present invention, the content of at least one material selected from F, Cl and C included in the first auxiliary layer is three times or more than the content of at least one material selected from F, Cl and C included in the second gate insulating layer.

[0008] According to an exemplary embodiment of the present invention, the thickness of the first auxiliary layer is in the range of 1 Å to 100 Å.

[0009] According to an exemplary embodiment of the present invention, the second gate electrode and the light-blocking layer comprise the same material.

[0010] According to an exemplary embodiment of the present invention, the light-blocking layer overlaps with the first semiconductor layer and has a region similar to that of the first semiconductor layer.

[0011] According to an exemplary embodiment of the present invention, a third gate insulating layer is disposed between the first semiconductor layer and the first gate electrode. The third gate insulating layer overlaps with the first semiconductor layer.

[0012] According to an exemplary embodiment of the present invention, a third gate insulating layer is disposed between the first semiconductor layer and the first gate electrode. The third gate insulating layer overlaps with the channel region of the first semiconductor layer, but does not overlap with the source and drain regions of the first semiconductor layer.

[0013] According to an exemplary embodiment of the present invention, a second auxiliary layer is disposed on the first gate electrode. The second auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer includes a material selected from SiN. x SiO x And at least one compound selected from SiON. The content of at least one material selected from F, Cl and C included in the second auxiliary layer is three or more times the content of at least one material selected from F, Cl and C included in the second gate insulating layer.

[0014] According to an exemplary embodiment of the present invention, a third gate insulating layer is disposed between the first semiconductor layer and the first gate electrode. The third gate insulating layer overlaps with the first semiconductor layer.

[0015] According to an exemplary embodiment of the present invention, a third gate insulating layer is disposed between the first semiconductor layer and the first gate electrode. The third gate insulating layer overlaps with the channel region of the first semiconductor layer, but does not overlap with the source and drain regions of the first semiconductor layer.

[0016] According to an exemplary embodiment of the present invention, a third auxiliary layer is disposed between the second gate lower electrode and the second gate insulating layer. The third auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer includes materials selected from SiN. x SiO x And at least one compound selected from SiON. The content of at least one material selected from F, Cl and C included in the third auxiliary layer is three or more times the content of at least one material selected from F, Cl and C included in the second gate insulating layer.

[0017] According to an exemplary embodiment of the present invention, a third gate insulating layer is disposed between the first semiconductor layer and the first gate electrode. The third gate insulating layer overlaps with the first semiconductor layer.

[0018] According to an exemplary embodiment of the present invention, a third gate insulating layer is disposed between the first semiconductor layer and the first gate electrode. The third gate insulating layer overlaps with the channel region of the first semiconductor layer, but does not overlap with the source and drain regions of the first semiconductor layer.

[0019] According to an exemplary embodiment of the present invention, a second auxiliary layer is disposed on the first gate electrode. A third auxiliary layer is disposed between the second gate lower electrode and the second gate insulating layer. Each of the second and third auxiliary layers includes an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer includes SiN. x SiO x And at least one compound of SiON. The content of at least one material selected from F, Cl and C included in the second auxiliary layer and the third auxiliary layer is three or more times the content of at least one material selected from F, Cl and C included in the second gate insulating layer.

[0020] According to an exemplary embodiment of the present invention, a third gate insulating layer is disposed between the first semiconductor layer and the first gate electrode. The third gate insulating layer overlaps with the first semiconductor layer.

[0021] According to an exemplary embodiment of the present invention, a third gate insulating layer is disposed between the first semiconductor layer and the first gate electrode. The third gate insulating layer overlaps with the channel region of the first semiconductor layer, but does not overlap with the source and drain regions of the first semiconductor layer.

[0022] According to an exemplary embodiment of the present invention, a display device is provided, the display device including a substrate. A first transistor and a second transistor are disposed on the substrate. The first transistor includes a first semiconductor layer. The first semiconductor layer includes an oxide semiconductor and a first gate electrode. The second transistor includes a second semiconductor layer. The second semiconductor layer includes a Si semiconductor, a second lower gate electrode, and a second upper gate electrode. A first auxiliary layer is disposed between the second upper gate electrode and the first semiconductor layer, and the first auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C.

[0023] According to an exemplary embodiment of the present invention, the light-blocking layer and the second gate electrode are disposed on the same layer. A first auxiliary layer is disposed on the second gate electrode and the light-blocking layer.

[0024] According to an exemplary embodiment of the present invention, a second auxiliary layer is disposed on the first gate electrode. The second auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer includes a material selected from SiN. x SiO x and at least one compound of SiON.

[0025] According to an exemplary embodiment of the present invention, a third auxiliary layer is disposed between the second lower gate electrode and the second upper gate electrode. The third auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer includes a material selected from SiN. x SiO x and at least one compound of SiON.

[0026] According to an exemplary embodiment of the present invention, a display device is provided, the display device including a substrate. A transistor is disposed on the substrate. The transistor includes an oxide semiconductor layer. An auxiliary layer is disposed on the transistor. The auxiliary layer includes an insulating layer and at least one charge carrier material. The at least one charge carrier material is configured to migrate to the semiconductor layer during conduction current. Attached Figure Description

[0027] Figure 1 A cross-sectional view schematically showing a portion of a display device according to an exemplary embodiment of the present invention is shown;

[0028] Figure 2 Show Figure 1 A portion of the first transistor TR1;

[0029] Figure 3 This illustrates the principle of supplying charge carriers to a first semiconductor layer in a display device according to an exemplary embodiment of the present invention;

[0030] Figure 4 The measurement results of the conduction current in a display device according to an exemplary embodiment of the present invention are shown when the first auxiliary layer is included (Embodiment 1) and when the first auxiliary layer is not included (Embodiment 2);

[0031] Figure 5 The results of fluoride concentration measurements are shown when the first auxiliary layer is included (Example 1) and when the first auxiliary layer is not included (Example 2);

[0032] Figure 6 Show along Figure 3 The concentrations of Si, O, F, and C were measured by line AA′;

[0033] Figure 7 The exemplary embodiments of the present invention are shown in the corresponding Figure 1 The cross section of the cross section;

[0034] Figure 8 The exemplary embodiments of the present invention are shown in the corresponding Figure 1 The cross section of the cross section;

[0035] Figure 9 A cross-section of a display device according to an exemplary embodiment of the present invention is shown;

[0036] Figure 10 A cross-section of a display device according to an exemplary embodiment of the present invention is shown;

[0037] Figure 11 A cross-section of a display device according to an exemplary embodiment of the present invention is shown;

[0038] Figure 12 A cross-section of a display device according to an exemplary embodiment of the present invention is shown;

[0039] Figure 13 A cross-section of a display device according to an exemplary embodiment of the present invention is shown;

[0040] Figure 14 A circuit diagram of a display device according to an exemplary embodiment of the present invention is shown; and

[0041] Figure 15 A circuit diagram of a display device according to an exemplary embodiment of the present invention is shown. Detailed Implementation

[0042] The invention will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.

[0043] In the accompanying drawings, the thickness and dimensions of layers, films, panels, areas, etc., may be enlarged for clarity.

[0044] It should be understood that when an element, such as a layer, film, region, or substrate, is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly" on another element, there are no intermediate elements present. Furthermore, the terms "above" or "on" mean located on or below a portion of an object, and do not necessarily mean located on the upper side of the object based on the direction of gravity.

[0045] A display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

[0046] Figure 1 A cross-sectional view schematically showing a portion of a display device according to an exemplary embodiment of the present invention is shown; Figure 1 The main illustration shows a light-emitting diode (LED) connected to a second transistor TR2, a first transistor TR1, and a second transistor TR2 in a display device. The first transistor TR1 can be a switching transistor. The second transistor TR2 can be a driving transistor.

[0047] A buffer layer 111 is disposed on a substrate 110. The substrate 110 may include at least one compound selected from the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. The substrate 110 may include a flexible material that can be bent or folded, and may be a single layer or multiple layers.

[0048] Buffer layer 111 may have a single-layer or multi-layer structure. Although buffer layer 111 in Figure 1 While shown as a single layer, buffer layer 111 can be multiple layers according to exemplary embodiments and may include organic or inorganic insulating materials. For example, buffer layer 111 may include silicon nitride, silicon oxide, and / or silicon oxynitride.

[0049] The second semiconductor layer 130 is disposed on the buffer layer 111. The second semiconductor layer 130 may include amorphous silicon, polycrystalline silicon, and / or monocrystalline silicon. The second semiconductor layer 130 may include a source region 131, a channel region 132, and a drain region 133.

[0050] The source region 131 of the second semiconductor layer 130 is connected to the second source electrode SE2, and the drain region 133 of the second semiconductor layer 130 is connected to the second drain electrode DE2.

[0051] A first gate insulating layer 141 is disposed on the second semiconductor layer 130. The first gate insulating layer 141 may include silicon nitride and / or silicon oxide.

[0052] The second gate lower electrode GE2-U is disposed on the first gate insulating layer 141. The second gate insulating layer 142 is disposed on the second gate lower electrode GE2-U. The second gate insulating layer 142 may include silicon nitride and / or silicon oxide.

[0053] The second upper gate electrode GE2-L is disposed on the second gate insulating layer 142. The second lower gate electrode GE2-U and the second upper gate electrode GE2-L overlap each other (e.g., in the thickness direction), with the second gate insulating layer 142 interposed between them. The second upper gate electrode GE2-L and the second lower gate electrode GE2-U constitute the second gate electrode GE2. The second gate electrode GE2 overlaps with the channel region 132 of the second semiconductor layer 130 in a direction perpendicular to the upper surface of the substrate 110 (e.g., in the thickness direction).

[0054] The second semiconductor layer 130, the second gate electrode GE2, the second source electrode SE2, and the second drain electrode DE2 constitute the second transistor TR2. As will be described later, the second transistor TR2 may be a driver transistor connected to a light-emitting diode (LED).

[0055] Return to reference Figure 1 A light-blocking layer 115 is disposed on the second gate insulating layer 142. The light-blocking layer 115 and the second gate upper electrode GE2-L are disposed on the same layer. The light-blocking layer 115 can be formed using the same process as the second gate upper electrode GE2-L, and may include the same material as the second gate upper electrode GE2-L. The upper surface of the light-blocking layer 115 may be disposed at a lower level than the upper surface of the second gate upper electrode GE2-L. The second gate upper electrode GE2-L and the light-blocking layer 115 may include the same material and have the same thickness. The light-blocking layer 115 overlaps with the first semiconductor layer 135 and has a region similar to that of the first semiconductor layer 135.

[0056] A first auxiliary layer 151 is disposed in a corresponding shape on the upper surface of the light-blocking layer 115, the upper surface of the second gate upper electrode GE2-L, and the exposed upper surface of the second gate insulating layer 142. The first auxiliary layer 151 may include fluorine. For example, the first auxiliary layer 151 may include SiN. x SiO x And / or SiON and fluorine. For example, the first auxiliary layer 151 may include SiN. x :F、SiO x :F or SiON:F. Additionally, the first auxiliary layer 151 may include Cl and / or C. For example, the first auxiliary layer 151 may include SiN. x Cl, SiN x C, SiO x Cl, SiO x :C, SiON:C, and / or SiON:Cl. The subscript x can be an integer between 1 and 4.

[0057] For example, the first auxiliary layer 151 may include an insulating layer and charge carriers, the insulating layer comprising materials selected from SiN. x SiO x And at least one compound of SiON. For example, the charge carriers may be at least one material selected from F, Cl and C included in the insulating layer. In an exemplary embodiment of the invention, the first auxiliary layer 151 may include F, and may further include Cl and / or C in addition to F.

[0058] Thus, the first auxiliary layer 151, which includes at least one material selected from F, Cl, and C, can increase the conduction current by supplying charge carriers to the first transistor TR1.

[0059] For example, the fluorine content in the first auxiliary layer 151 may be three times or more than the fluorine content in the second gate insulating layer 142 or the first insulating layer 161. Even when the first auxiliary layer 151 includes C and / or Cl, the C and / or Cl content in the first auxiliary layer 151 may be three times or more than the C and / or Cl content in the second gate insulating layer 142 or the first insulating layer 161.

[0060] The thickness of the first auxiliary layer 151 can be from 1 Å to 100 Å. When the thickness of the first auxiliary layer 151 is greater than 100 Å, it may affect the interface characteristics of each layer, and too many charge carriers may be supplied to the first transistor TR1.

[0061] A first insulating layer 161 is disposed on the first auxiliary layer 151. The first insulating layer 161 may include silicon nitride and / or silicon oxide. For example, the first insulating layer 161 may be composed of SiN x Layers and SiO x The layer consists of multiple layers. The first insulating layer 161 includes SiN... x The layer can be set to include SiO x The layer is closer to the substrate 110.

[0062] The first semiconductor layer 135 is disposed on the first insulating layer 161.

[0063] The first semiconductor layer 135 may include an oxide semiconductor. The oxide semiconductor may include at least one compound selected from: primary metal-based oxides, such as indium oxide, tin oxide, or zinc oxide; binary metal-based oxides, such as In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and / or In-Ga-based oxides; ternary metal-based oxides, such as In-Ga-Zn-based oxides, In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-P... Oxides based on r-Zn, oxides based on In-Nd-Zn, oxides based on In-Sm-Zn, oxides based on In-Eu-Zn, oxides based on In-Gd-Zn, oxides based on In-Tb-Zn, oxides based on In-Dy-Zn, oxides based on In-Ho-Zn, oxides based on In-Er-Zn, oxides based on In-Tm-Zn, oxides based on In-Yb-Zn and / or oxides based on In-Lu-Zn; and oxides based on quaternary metals, such as oxides based on In-Sn-Ga-Zn, oxides based on In-Hf-Ga-Zn, oxides based on In-Al-Ga-Zn, oxides based on In-Sn-Al-Zn, oxides based on In-Sn-Hf-Zn and / or oxides based on In-Hf-Al-Zn. For example, the first semiconductor layer 135 may include indium gallium zinc oxide (IGZO) in an In-Ga-Zn based oxide.

[0064] The first semiconductor layer 135 may include a source region 136, a channel region 137, and a drain region 138. The source region 136 of the first semiconductor layer 135 is connected to the first source electrode SE1, and the drain region 138 of the first semiconductor layer 135 is connected to the first drain electrode DE1.

[0065] A third gate insulating layer 143 is disposed on the first semiconductor layer 135. Figure 1 In the exemplary embodiment of the invention depicted herein, the third gate insulating layer 143 may be disposed on the entire upper surface of the first insulating layer 161 and the first semiconductor layer 135. However, the third gate insulating layer 143 may be disposed only between the first gate electrode GE1 and the first semiconductor layer 135. For example, the third gate insulating layer 143 may overlap with the channel region 137 of the first semiconductor layer 135 and may not overlap with the source region 136 or the drain region 138.

[0066] The first gate electrode GE1 is disposed on the third gate insulating layer 143. The first gate electrode GE1 may overlap with the channel region 137 of the first semiconductor layer 135 in a direction perpendicular to the substrate 110 (e.g., the thickness direction).

[0067] The first gate electrode GE1, the first semiconductor layer 135, the first source electrode SE1, and the first drain electrode DE1 constitute the first transistor TR1. The first transistor TR1 can be a switching transistor used to switch the second transistor TR2.

[0068] The second insulating layer 162 is disposed on the first gate electrode GE1. The first source electrode SE1, the first drain electrode DE1, and the second source electrode SE2 are disposed on the second insulating layer 162.

[0069] The first source electrode SE1 is connected to the source region 136 of the first semiconductor layer 135 through the first opening OP1. The first drain electrode DE1 is connected to the drain region 138 of the first semiconductor layer 135 through the second opening OP2.

[0070] The second source electrode SE2 is connected to the source region 131 of the second semiconductor layer 130 through the third opening OP3.

[0071] The third insulating layer 163 is disposed on the upper surface of the first source electrode SE1, the first drain electrode DE1, and the second source electrode SE2.

[0072] The second drain electrode DE2 is disposed on the third insulating layer 163. The second drain electrode DE2 is connected to the drain region 133 of the second semiconductor layer 130 through the fourth opening OP4. Figure 1 The diagram shows a configuration in which the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 are disposed on different layers, but they can be disposed on the same layer. For example, the second drain electrode DE2 can be connected to the first electrode 191 via a separate connecting member.

[0073] A fourth insulating layer 180 is disposed on the second drain electrode DE2. The first electrode 191 and the second drain electrode DE2 are in contact with each other in an opening 185 of the fourth insulating layer 180. A partition wall 350 is disposed on the first electrode 191, and the opening of the partition wall 350 overlaps with the first electrode 191. A light-emitting element layer 370 is disposed in the opening of the partition wall 350. A second electrode 270 is disposed on the light-emitting element layer 370 and the partition wall 350. The first electrode 191, the light-emitting element layer 370, and the second electrode 270 constitute a light-emitting diode (LED).

[0074] As mentioned above, in Figure 1In the display device depicted according to an exemplary embodiment of the present invention, the first transistor TR1, serving as a switching transistor, comprises an oxide semiconductor, and the second transistor TR2, serving as a driving transistor, comprises a silicon semiconductor. Thus, the switching transistor and the driving transistor can comprise different semiconductor materials, thereby enabling more stable operation and higher reliability.

[0075] However, it is not possible to supply sufficient charge carriers to the first semiconductor layer 135, which includes the first transistor TR1, which is an oxide semiconductor. Figure 2 Show Figure 1 Part of the first transistor TR1.

[0076] refer to Figure 2 Materials that could serve as charge carriers for the first semiconductor layer 135 (such as H) can be blocked by the third gate insulating layer 143, thus preventing them from being supplied to the first semiconductor layer 135. Therefore, the on-state current of the first transistor TR1 can be reduced during reliability assessment.

[0077] However, the display device according to an exemplary embodiment of the present invention adds a first auxiliary layer 151 rich in charge carriers (such as fluorine) to supply charge carriers to the first semiconductor layer 135 and increase the conduction current of the first transistor TR1.

[0078] Figure 3 This illustrates the principle of supplying charge carriers to the first semiconductor layer 135 in a display device according to an exemplary embodiment of the present invention. (See reference...) Figure 3 In the display device according to this exemplary embodiment, F is released from the F-rich first auxiliary layer 151 and supplied to the first semiconductor layer 135. Figure 3 The example shows a F-rich layer, but in addition to F, the first auxiliary layer 151 may further include Cl, C, etc., and this material may also act as a charge carrier.

[0079] Figure 4 The diagram shows measurement results of the conduction current in a display device according to an exemplary embodiment of the present invention, with and without the first auxiliary layer 151 (Embodiment 1). Reference Figure 4 In the display device according to this exemplary embodiment of the present invention, when the first auxiliary layer 151 is included, the conduction current increases.

[0080] Figure 5 The measurements of fluorine concentration are shown when the first auxiliary layer 151 is included (Example 1) and when the first auxiliary layer 151 is not included (Example 2). Reference Figure 5It was confirmed that when the first auxiliary layer 151 is included at the interface between the light-blocking layer 115 and the first insulating layer 161 (Example 1), the fluorine concentration (e.g., intensity in counts per second (cps)) is high.

[0081] Figure 6 Show along Figure 3 The concentrations of Si, O, F, and C were measured using line AA′. (Reference) Figure 6 As can be seen, in the first auxiliary layer 151, which serves as the interface between the light-blocking layer 115 and the first insulating layer 161, the concentrations of F and C increase. The region of the first auxiliary layer 151 is shown as a dashed rectangle. Thus, the material, such as F or C, included in the first auxiliary layer 151 can be supplied to the first semiconductor layer 135 to act as charge carriers.

[0082] Figure 7 A cross-section of a display device according to an exemplary embodiment of the present invention is shown. (Reference) Figure 7 The display device and Figure 1 The difference in the display device of the exemplary embodiment of the present invention depicted is that the third gate insulating layer 143 is only disposed in the region overlapping with the first gate electrode GE1. Figure 7 As shown, even when the third gate insulating layer 143 is only disposed between the first gate electrode GE1 and the first semiconductor layer 135 (e.g., channel region 137), carriers can be supplied to the first semiconductor layer 135 through the first auxiliary layer 151 to increase the conduction current.

[0083] Figure 8 A cross-section of a display device according to an exemplary embodiment of the present invention is shown. (Reference) Figure 8 The display device and Figure 1 The display device of the exemplary embodiment of the present invention depicted herein is the same, except that it further includes a second auxiliary layer 152 disposed between the first gate electrode GE1 and the second insulating layer 162. The second auxiliary layer 152 may also be disposed across the upper surface of the third gate insulating layer 143.

[0084] The second auxiliary layer 152 may include fluorine. For example, the second auxiliary layer 152 may include fluorine-containing SiN. x SiO x And / or SiON. For example, the second auxiliary layer 152 may include SiN. x :F、SiO x :F and / or SiON:F. Additionally, the second auxiliary layer 152 may include Cl and / or C. For example, the second auxiliary layer 152 may include SiN. x Cl, SiN x C, SiO x Cl, SiO x:C, SiON:C, and / or SiON:Cl. The subscript x can be an integer between 1 and 4. The thickness of the second auxiliary layer 152 can be from 1 Å to 100 Å. In the following description, the second auxiliary layer 152 is the same as the first auxiliary layer 151.

[0085] As mentioned above, in Figure 8 In the display device according to an exemplary embodiment of the present invention depicted herein, since carriers are supplied from both the first auxiliary layer 151 and the second auxiliary layer 152, the conduction current of the first semiconductor layer 135 can be further increased.

[0086] Figure 9 A cross-section of a display device according to an exemplary embodiment of the present invention is shown. (Reference) Figure 9 The display device and Figure 8 The display device is the same as the exemplary embodiment of the present invention depicted in the figure, except that the third gate insulating layer 143 is disposed only in the region overlapping with the first gate electrode GE1. Figure 10 A cross-section of a display device according to an exemplary embodiment of the present invention is shown. (Reference) Figure 10 The display device and Figure 1 The display device of the exemplary embodiment of the present invention depicted herein is the same, except that it further includes a third auxiliary layer 153 disposed between the second gate lower electrode GE2-U and the second gate insulating layer 142 and between the second gate insulating layer 142 and the first gate insulating layer 141. The third auxiliary layer 153 may include fluorine. For example, the third auxiliary layer 153 may include fluorine-containing SiN. x SiO x And / or SiON. For example, the third auxiliary layer 153 may include SiN. x :F、SiO x :F and / or SiON:F. Additionally, the third auxiliary layer 153 may include Cl and / or C. For example, the third auxiliary layer 153 may include SiN. x Cl, SiN x C, SiO x Cl, SiO x :C, SiON:C, and / or SiON:Cl. The subscript x can be an integer between 1 and 4. The thickness of the third auxiliary layer 153 can be from 1 Å to 100 Å. In the following description, the third auxiliary layer 153 is the same as the first auxiliary layer 151.

[0087] According to Figure 10 In the exemplary embodiment of the display device, since carriers are supplied from both the first auxiliary layer 151 and the third auxiliary layer 153, the conduction current of the first semiconductor layer 135 can be further increased.

[0088] Figure 11 A cross-section of a display device according to an exemplary embodiment of the present invention is shown. (Reference) Figure 11 The display device and Figure 10 The display device is the same as the exemplary embodiment of the present invention depicted in the figure, except that the third gate insulating layer 143 is disposed only in the region overlapping with the first gate electrode GE1.

[0089] Figure 12 A cross-section of a display device according to an exemplary embodiment of the present invention is shown. (Reference) Figure 12 The display device and Figure 1 The display device of the exemplary embodiment of the present invention described herein is the same, except that it further includes a second auxiliary layer 152 disposed between the first gate electrode GE1 and the second insulating layer 162 and a third auxiliary layer 153 disposed between the second gate lower electrode GE2-U and the second gate insulating layer 142.

[0090] Figure 13 A cross-section of a display device according to an exemplary embodiment of the present invention is shown. (Reference) Figure 13 The display device and Figure 12 The display device of the exemplary embodiment of the present invention depicted herein is the same, except that the third gate insulating layer 143 is disposed only in the region overlapping with the first gate electrode GE1. For example, the third gate insulating layer 143 may be disposed between the first gate electrode GE1 and the first semiconductor layer 135. Circuit diagrams of a display device according to an exemplary embodiment of the present invention will be described below. Figure 14 A circuit diagram of a display device according to an exemplary embodiment of the present invention is shown.

[0091] refer to Figure 14 The pixel circuit includes a second transistor T2 for controlling a light-emitting diode (LED) (e.g., an organic light-emitting diode OLED), a first transistor T1 for switching the second transistor T2, and a capacitor Cst connected to a first power line ELVDD.

[0092] exist Figure 14 In this configuration, the first transistor T1 can be a switching transistor, and the second transistor T2 can be a driving transistor. Figure 14 The first transistor T1 can correspond to Figures 1 to 13 The first transistor TR1, and the second transistor T2 can correspond to Figures 1 to 13 The second transistor TR2.

[0093] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first transistor T1 may be connected to the i-th scan line Sn(i), and the source electrode may be connected to the j-th data line Dj. The drain electrode of the first transistor T1 may be connected to the gate electrode of the second transistor T2. The first transistor T1 may transmit the data signal applied to the j-th data line Dj to the second transistor T2 according to the scan signal applied to the i-th scan line Sn(i).

[0094] The second transistor T2 may include a gate electrode, a source electrode, and a drain electrode. In the second transistor T2, the gate electrode may be connected to the first transistor T1, the source electrode may be connected to the first power line ELVDD, and the drain electrode may be connected to the organic light-emitting diode (OLED).

[0095] An organic light-emitting diode (OLED) may include an emitting layer, and an anode and a cathode electrode facing each other, with the emitting layer between the anode and cathode electrodes. The anode electrode may be connected to the drain electrode of a second transistor T2. The cathode electrode may be connected to a second power line ELVSS to apply a common voltage. Depending on the output signal of the second transistor T2, the emitting layer may display an image by emitting light or not emitting light.

[0096] Here, the light emitted from the emitting layer can vary depending on the material of the emitting layer, and can be colored light or white light.

[0097] A capacitor Cst can be connected between the gate electrode and the source electrode of the second transistor T2 to charge and retain the data signal input to the gate electrode of the second transistor T2.

[0098] Although Figure 14 The illustrated pixel circuit includes two transistors T1 and T2 and a capacitor Cst, but the invention is not limited thereto, and may include a thin-film transistor and a capacitor, or three or more transistors and two or more capacitors. For example, as Figure 15 As shown, the pixel circuit may include first to seventh transistors T1 to T7 and capacitor Cst.

[0099] Figure 15 A circuit diagram of a display device according to an exemplary embodiment of the present invention is shown. (Reference) Figure 15 The pixel PX of the emission display device includes multiple transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst and light-emitting diodes (LEDs) connected to various signal lines.

[0100] The transmitting display device includes a display area in which an image is displayed, and such pixels PX are arranged in various shapes in the display area.

[0101] Transistors T1, T2, T3, T4, T5, T6, and T7 include a driving transistor T1 (hereinafter also referred to as the first transistor T1), a switching transistor connected to the scan line Sn (i.e., the second transistor T2 and the third transistor T3), and other transistors (hereinafter referred to as compensation transistors) for performing the operations required to operate the light-emitting diode (LED). These compensation transistors T4, T5, T6, and T7 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0102] Multiple signal lines include a scan line Sn, a pre-amplifier scan line Sn-1, an optical emission control line EM, a bypass control line GB, a data line Dm, a drive voltage line ELVDD, an initialization voltage line Vint, and a common voltage line ELVSS. The bypass control line GB can be part of the pre-amplifier scan line Sn-1, or can be electrically connected to the pre-amplifier scan line Sn-1. Alternatively, the bypass control line GB can be part of the scan line Sn, or can be electrically connected to the scan line Sn.

[0103] Scan line Sn is connected to the gate driver to transmit the scan signal to the second transistor T2 and the third transistor T3. Front-stage scan line Sn-1 is connected to the gate driver to transmit the front-stage scan signal applied to the pixel PX located at the front stage to the fourth transistor T4. Light emission control line EM is connected to the emission controller to transmit the emission control signal used to control the timing of LED emission to the fifth transistor T5 and the sixth transistor T6. Bypass control line GB transmits the bypass signal to the seventh transistor T7.

[0104] The data line Dm is used to transmit the data voltage generated by the data driver, and the brightness of the LED changes according to the data voltage. The drive voltage line ELVDD applies the drive voltage. The initialization voltage line Vint transmits the initialization voltage used to initialize the drive transistor T1. The common voltage line ELVSS applies a common voltage. Constant voltages can be applied to the drive voltage line ELVDD, the initialization voltage line Vint, and the common voltage line ELVSS separately.

[0105] The transistor will be described below.

[0106] The driving transistor T1 is a transistor that adjusts the current output according to the applied data voltage. The output driving current Id is applied to the light-emitting diode (LED) to adjust the brightness of the LED according to the data voltage. For this purpose, the first electrode S1 of the driving transistor T1 is configured to receive the driving voltage. The first electrode S1 is connected to the driving voltage line ELVDD via the fifth transistor T5. Additionally, the first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2, thereby also applying a data voltage to it. The second electrode D1 (output electrode) of the driving transistor T1 is configured to output current to the LED. The second electrode D1 of the driving transistor T1 is connected to the anode of the LED via the sixth transistor T6. The gate electrode G1 is connected to the electrode (second storage electrode E2) of the storage capacitor Cst. Therefore, the voltage at the gate electrode G1 varies according to the voltage stored in the storage capacitor Cst, and thus the driving current Id output by the driving transistor T1 varies.

[0107] The second transistor T2 is the transistor that receives the data voltage in pixel PX. Its gate electrode G2 is connected to scan line Sn, and its first electrode S2 is connected to data line Dm. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal transmitted through scan line Sn, the data voltage transmitted through data line Dm is transmitted to the first electrode S1 of the driving transistor T1.

[0108] The third transistor T3 is used to allow the compensation voltage (Dm+Vth) obtained while the data voltage is changed by the driving transistor T1 to be transmitted to the second storage electrode E2 of the storage capacitor Cst. Its gate electrode G3 is connected to the scan line Sn, and its first electrode S3 is connected to the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. The third transistor T3 connects the gate electrode G1 and the second electrode D1 of the driving electrode T1 according to the scan signal received through the scan line Sn, and it also connects the second electrode D1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst.

[0109] The fourth transistor T4 is used to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 is connected to the preceding scan line Sn-1, and the first electrode S4 is connected to the initialization voltage line Vint. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the preceding scan signal transmitted via the preceding scan line Sn-1. Therefore, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage can be a low voltage value that turns on the driving transistor T1.

[0110] The fifth transistor T5 is used to transmit the driving voltage to the driving transistor T1. Its gate electrode G5 is connected to the light emission control line EM, and its first electrode S5 is connected to the driving voltage line ELVDD. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0111] The sixth transistor T6 is used to transfer the drive current Id output from the driving transistor T1 to the light-emitting diode (LED). Its gate electrode G6 is connected to the light emission control line EM, and its first electrode S6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the LED.

[0112] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on by the emission control signal received from the light emission control line EM. When a driving voltage is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs a driving current Id according to the voltage of its gate electrode G1 (i.e., the voltage of the second storage electrode E2 of the storage capacitor Cst). The output driving current Id is transmitted to the light-emitting diode LED through the sixth transistor T6. The light-emitting diode LED operates under the current Id. led It emits light as it flows through.

[0113] The seventh transistor T7 is used to initialize the anode of the light-emitting diode (LED). Its gate electrode G7 is connected to the bypass control line GB, its first electrode S7 is connected to the anode of the LED, and its second electrode D7 is connected to the initialization voltage line Vint. The bypass control line GB can be connected to the preceding scan line Sn-1, and the bypass signal is the same timing signal as the preceding scan signal. Alternatively, the bypass control line GB can be disconnected from the preceding scan line Sn-1 and can transmit a signal separate from the preceding scan signal. When the seventh transistor T7 is turned on by the bypass signal, the initialization voltage is applied to the anode of the LED to initialize it.

[0114] The first storage electrode E1 of the storage capacitor Cst is connected to the drive voltage line ELVDD, and the second storage electrode E2 is connected to the gate electrode G1 of the drive transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. As a result, the second storage electrode E2 determines the voltage of the gate electrode G1 of the drive transistor T1, and it receives the data voltage through the second electrode D3 of the third transistor T3, or the initialization voltage through the second electrode D4 of the fourth transistor T4.

[0115] On the other hand, the anode of the light-emitting diode (LED) is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7, and its cathode is connected to the common voltage line ELVSS for transmitting the common voltage.

[0116] exist Figure 15 In the exemplary embodiment of the invention depicted herein, the pixel circuit includes seven transistors T1 to T7 and a capacitor Cst. However, the invention is not limited thereto, and the number of transistors and capacitors and the connections between them may be modified differently.

[0117] As Figure 15 The first transistor T1 of the driving transistor can be used as Figures 1 to 13 The second transistor TR2 is the driving transistor. Additionally, as... Figure 15 The second transistor T2 or the third transistor T3 of the switching transistor can be used as... Figures 1 to 13 The first transistor TR1 is the switching transistor.

[0118] Although exemplary embodiments of the invention have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display device, the display device comprising: substrate; A second semiconductor layer disposed on the substrate, the second semiconductor layer comprising Si; Second gate The lower gate electrode overlaps with the channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second gate lower electrode; The second gate electrode and the light-blocking layer are disposed on the second gate insulating layer; A first auxiliary layer is disposed on the second gate electrode and the light-blocking layer; A first semiconductor layer overlapping the light-blocking layer, the first semiconductor layer comprising an oxide semiconductor; and The first gate electrode overlaps with the channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer includes a material selected from SiN. x SiO x and at least one compound of SiON, wherein the subscript x is an integer between 1 and 4, and The content of at least one material selected from F, Cl and C included in the first auxiliary layer is three times or more than the content of at least one material selected from F, Cl and C included in the second gate insulating layer.

2. The display device as claimed in claim 1, wherein: The thickness of the first auxiliary layer is in the range of 1 Å to 100 Å.

3. The display device as claimed in claim 1, wherein: The second gate electrode and the light-blocking layer are made of the same material.

4. The display device as claimed in claim 1, wherein: The light-blocking layer overlaps with the first semiconductor layer and has a region similar to that of the first semiconductor layer.

5. The display device as claimed in claim 1, further comprising: A second auxiliary layer is disposed on the first gate electrode. The second auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer includes a material selected from SiN. x SiO x and at least one compound of SiON, wherein the subscript x is an integer between 1 and 4, and The content of at least one material selected from F, Cl and C included in the second auxiliary layer is three or more times that of at least one material selected from F, Cl and C included in the second gate insulating layer.

6. The display device of claim 1, further comprising: A third auxiliary layer is disposed between the second gate lower electrode and the second gate insulating layer. The third auxiliary layer comprises an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer comprises a material selected from SiN. x SiO x and at least one compound of SiON, wherein the subscript x is an integer between 1 and 4, and The content of at least one material selected from F, Cl, and C included in the third auxiliary layer is three times or more than the content of at least one material selected from F, Cl, and C included in the second gate insulating layer.

7. The display device of claim 1, further comprising: A second auxiliary layer is disposed on the first gate electrode; And a third auxiliary layer, wherein the third auxiliary layer is disposed between the second gate lower electrode and the second gate insulating layer. Each of the second auxiliary layer and the third auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C, wherein the insulating layer includes materials selected from SiN. x SiO x and at least one compound of SiON, wherein the subscript x is an integer between 1 and 4, and The content of at least one material selected from F, Cl and C included in the second auxiliary layer and the third auxiliary layer is three times or more than that of at least one material selected from F, Cl and C included in the second gate insulating layer.

8. A display device, the display device comprising: substrate; as well as The first transistor and the second transistor are disposed on the substrate; The first transistor includes a first semiconductor layer, which comprises an oxide semiconductor and a first gate electrode. The second transistor includes a second semiconductor layer, which comprises a Si semiconductor, a second lower gate electrode, and a second upper gate electrode. The second gate insulating layer is disposed on the second gate lower electrode. The first auxiliary layer is disposed between the second gate electrode and the first semiconductor layer, and The first auxiliary layer includes an insulating layer and at least one material selected from F, Cl, and C. The content of at least one material selected from F, Cl and C included in the first auxiliary layer is three times or more than the content of at least one material selected from F, Cl and C included in the second gate insulating layer.

9. The display device as claimed in claim 8, wherein: The light-blocking layer and the second gate electrode are disposed on the same layer, and The first auxiliary layer is disposed on the second gate electrode and the light-blocking layer.

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