Display device

Abstract

A display device is provided including a display region and a non-display region. The display region includes a display element, and the non-display region includes a pad portion. A first thin film transistor (TFT) is arranged in the display region. The first TFT includes silicon and a first gate electrode. A second TFT is arranged on a first insulating layer covering the first gate electrode, and includes an oxide and a second gate electrode. A first voltage line extends in a first direction. A data line is spaced apart from the first voltage line. A connection wiring is provided in the display region, and connects the data line to the pad portion. The connection wiring includes a first portion extending in the first direction and a second portion extending in a second direction intersecting the first direction, and the first portion overlaps the first voltage line.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0110194, filed with the Korean Intellectual Property Office on September 5, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to display devices, and more particularly, to display devices comprising thin-film transistors comprising silicon semiconductors and thin-film transistors comprising oxide semiconductors. Background Technology

[0004] A display device is an output device used to present information in a visual form. Generally, a display device includes a display element and a driving circuit for controlling the electrical signals applied to the display element. The driving circuit may include thin-film transistors (TFTs), storage capacitors, and multiple wirings.

[0005] To precisely control the light emission and its intensity originating from the display element, the number of TFTs electrically connected to a single display element has increased. Therefore, technologies are being actively implemented to reduce the power consumption of highly integrated display devices.

[0006] In addition, the display device includes a display area for displaying images and a non-display area surrounding the display area. Recently, the non-display area has been reduced in size, allowing the size of the display area to be increased. Summary of the Invention

[0007] According to an exemplary embodiment of the present invention, a display device is provided, including a display area and a non-display area. The display area includes a display element, and the non-display area includes a pad portion. A first thin-film transistor (TFT) is disposed in the display area. The first TFT includes a first semiconductor layer comprising silicon and a first gate electrode. A first insulating layer covers the first gate electrode. A second TFT is disposed on the first insulating layer and includes a second semiconductor layer comprising oxide and a second gate electrode. A second insulating layer covers the second gate electrode. A first voltage line extends in a first direction on the second insulating layer. A data line is spaced apart from the first voltage line. A connection wiring is disposed in the display area and connects the data line to the pad portion. The connection wiring includes a first portion extending in the first direction and a second portion extending in a second direction intersecting the first direction, and the first portion overlaps with the first voltage line.

[0008] According to an exemplary embodiment of the present invention, the display element includes a pixel electrode and a counter electrode, and is arranged on a connection wiring. The pixel electrode overlaps with the first portion.

[0009] According to an exemplary embodiment of the present invention, the second voltage line overlaps with the second portion and extends in the second direction.

[0010] According to an exemplary embodiment of the present invention, the second voltage line is arranged on the first insulating layer.

[0011] According to an exemplary embodiment of the present invention, the display device further includes a scan line that overlaps with the second portion and extends in a second direction.

[0012] According to an exemplary embodiment of the present invention, the first portion includes a first protrusion that protrudes in a second direction and overlaps with the second voltage line.

[0013] According to an exemplary embodiment of the present invention, the display device further includes a node connection line disposed on a second insulating layer and connected to a first gate electrode through a contact hole. A first planarization layer covers the node connection line. A shielding electrode overlaps with the node connection line and is connected to a second voltage line.

[0014] According to an exemplary embodiment of the present invention, the connecting wiring and the shielding electrode are arranged on the same layer.

[0015] According to an exemplary embodiment of the present invention, the second thin-film transistor further includes a third gate electrode disposed under the second semiconductor layer to overlap with the second semiconductor layer.

[0016] According to an exemplary embodiment of the present invention, the second voltage line and the third gate electrode are arranged on the same layer.

[0017] According to an exemplary embodiment of the present invention, the second part includes a second protrusion that protrudes in a first direction and overlaps with the first voltage line.

[0018] According to an exemplary embodiment of the present invention, the display device further includes a first planarization layer between the first voltage line and the connection wiring.

[0019] According to an exemplary embodiment of the present invention, the display device further includes a first planarization layer between the second gate electrode and the first voltage line. A second planarization layer is disposed between the first voltage line and the connection wiring.

[0020] According to an exemplary embodiment of the present invention, the display device further includes a boost capacitor comprising a lower electrode disposed on the same layer as the first gate electrode and an upper electrode disposed on the same layer as the second semiconductor layer.

[0021] According to an exemplary embodiment of the present invention, the connection wiring includes a third portion extending in a first direction and connected to the pad portion. The data line is connected to the first portion in a non-display area.

[0022] According to an exemplary embodiment of the present invention, a display device including a substrate is provided. The substrate includes a display area and a non-display area. The non-display area includes a pad portion outside the display area. A first thin-film transistor is disposed in the display area and includes: a first semiconductor layer including a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer. A first insulating layer covers the first gate electrode. A second thin-film transistor is disposed on the first insulating layer and includes: a second semiconductor layer including an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer. A second insulating layer covers the second gate electrode. A first voltage line is disposed on the second insulating layer and extends in a first direction. A first wiring extends in the first direction adjacent to the first voltage line. A first signal line extends in a second direction intersecting the first direction, wherein the first signal line and the first gate electrode are disposed on the same layer. A second wiring overlaps with the first signal line and extends in the second direction. The first wiring is connected to the second wiring through a contact hole in the display area.

[0023] According to an exemplary embodiment of the present invention, the second wiring is disposed between the first insulating layer and the second insulating layer.

[0024] According to an exemplary embodiment of the present invention, the display device further includes a first connection electrode disposed on a first insulating layer and a second connection electrode connected to the first connection electrode through a first contact hole and disposed on a second insulating layer. A first gate electrode is connected to the first connection electrode through a second contact hole. The second connection electrode is connected to a second semiconductor layer through a third contact hole.

[0025] According to an exemplary embodiment of the present invention, the display device further includes a data line extending in a first direction. The data line is connected to a pad portion via a first wiring and a second wiring.

[0026] According to an exemplary embodiment of the present invention, a display device including a substrate is provided. The substrate includes: a display area including display elements and a non-display area including pad portions outside the display area. A first thin-film transistor is disposed in the display area and includes: a first semiconductor layer including silicon semiconductor or oxide semiconductor and a first gate electrode insulated from the first semiconductor layer. A first voltage line extends on the substrate in a first direction. A second voltage line extends on the substrate in a second direction. A bent connection wiring is disposed in the display area, the bent connection wiring connecting data lines to the pad portions. The bent connection wiring includes a portion extending in the first direction. This portion of the bent connection wiring overlaps with the first voltage line, and this portion of the bent connection wiring includes a first protrusion protruding in the second direction and overlapping with the second voltage line. Attached Figure Description

[0027] The above and other features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a schematic plan view of an example of a display device according to an exemplary embodiment of the present invention;

[0029] Figure 2 This is according to an exemplary embodiment of the present invention. Figure 1 An enlarged schematic plan view of region A;

[0030] Figure 3 This is according to an exemplary embodiment of the present invention. Figure 2 A partially enlarged plan view of region A';

[0031] Figure 4 This is according to an exemplary embodiment of the present invention. Figure 3 An enlarged plan view of part of region B;

[0032] Figure 5 This is an equivalent circuit diagram including a pixel in a display device according to an exemplary embodiment of the present invention;

[0033] Figure 6 This is a schematic layout diagram of the positions of a plurality of thin-film transistors and capacitors arranged in a pixel circuit of a display device according to an exemplary embodiment of the present invention;

[0034] Figure 7 It is along the exemplary embodiment of the present invention Figure 6 A schematic cross-sectional view of line I-I';

[0035] Figure 8 It is along the exemplary embodiment of the present invention Figure 6 A schematic cross-sectional view taken from line II-II';

[0036] Figure 9 It is along the exemplary embodiment of the present invention Figure 6 A schematic cross-sectional view of a pixel circuit taken from line I-I';

[0037] Figure 10 It is along the exemplary embodiment of the present invention Figure 6 A schematic cross-sectional view of a pixel circuit taken from line I-I';

[0038] Figure 11A This is a schematic layout diagram of the positions of a plurality of thin-film transistors and capacitors arranged in a first pixel circuit and a second pixel circuit of a display device according to an exemplary embodiment of the present invention.

[0039] Figure 11B This is a layout diagram of some of the wiring in a display device according to an exemplary embodiment of the present invention;

[0040] Figure 12 It is along the exemplary embodiment of the present invention Figure 11A A schematic cross-sectional view taken from line III-III'; and

[0041] Figure 13 It is along the exemplary embodiment of the present invention Figure 11A A schematic cross-sectional view taken from line IV-IV'. Detailed Implementation

[0042] The display device described herein is an apparatus for displaying images and may include liquid crystal displays, electrophoretic displays, organic light-emitting displays, inorganic electroluminescent (EL) displays, field emission displays, surface conduction electron emission displays, quantum dot displays, plasma displays, or cathode ray displays. Although organic light-emitting display devices are described as examples of display devices, the invention can be applied to various types of display devices in the following description.

[0043] Figure 1 This is a schematic plan view of an example of a display device 1 according to an exemplary embodiment of the present invention. Figure 2 yes Figure 1 An enlarged schematic plan view of region A, and Figure 3 yes Figure 2 A magnified plan view of part of region A'.

[0044] refer to Figure 1 The substrate 110 of the display device 1 may include a display area DA in which pixels PX, including display elements, are disposed, and a non-display area NDA including a pad portion PADA disposed outside the display area DA. For example, a first side of the display device 1 extending in a second direction (e.g., DR2 direction) may include a protruding portion of the non-display area NDA extending in a first direction (e.g., DR1 direction), the protruding portion including the pad portion PADA disposed therein.

[0045] The edges of the display area DA can have a shape similar to a rectangle or a square. However, the invention is not limited to this. In the display area DA, the first corner CN1 at the edge of the display area DA can have a rounded shape. For example, the display area DA may include a first edge E1 and a second edge E2 facing each other (e.g., arranged to extend parallel in a first direction (e.g., DR1 direction), and a third edge E3 and a fourth edge E4 located between the first edge E1 and the second edge E2 and facing each other (e.g., arranged to extend parallel in a second direction (e.g., DR2 direction)). The pad portion PADA is adjacent to the fourth edge E4 of the first edge E1 to the fourth edge E4. The first corner CN1 with a rounded shape connects the first edge E1 and the fourth edge E4. In the display area DA, in addition to the first corner CN1, the second corner CN2 at the edge of the display area DA can also have a rounded shape. The second corner CN2 connects the second edge E2 and the fourth edge E4. In addition, other portions of the edges in the display area DA may also have rounded shapes.

[0046] Each pixel PX emits light, such as red, green, blue, or white, and may include, for example, an organic light-emitting diode (OLED). Additionally, each pixel PX may further include devices such as thin-film transistors (TFTs) and storage capacitors.

[0047] According to an exemplary embodiment of the present invention, a pixel PX may refer to a sub-pixel that emits red, green, blue or white light.

[0048] The signal lines that can apply electrical signals to multiple pixels PX may include multiple scan lines SL or multiple data lines DL, etc. Each of the multiple data lines DL may extend in a first direction (e.g., DR1 direction), and each of the multiple scan lines SL may extend in a second direction (e.g., DR2 direction). The multiple scan lines SL may be arranged, for example, in multiple rows to transmit scan signals to the pixels PX, and the multiple data lines DL may be arranged, for example, in multiple columns to transmit data signals to the pixels PX. Each of the multiple pixels PX may be connected to at least one corresponding scan line SL and a corresponding data line DL of the multiple data lines DL.

[0049] The connection route FL can connect signal lines in the display area DA to the pad portion PADA in the non-display area NDA. The connection route FL can also connect to the fan-out route FOL in the non-display area NDA, and the fan-out route FOL can be connected to the pad portion PADA. For example, the first end of the fan-out route FOL can be connected to the pad portion PADA, and the second end of the fan-out route FOL can be connected to the connection route FL.

[0050] The connecting wiring FL can be arranged in the display area DA.

[0051] In an exemplary embodiment of the present invention, the virtual center line CL may divide the display device 1 into two equal parts. For example, the virtual center line CL may extend in a first direction (e.g., the DR1 direction). The connecting wiring FL arranged to the left of the virtual center line CL in the display area DA and the connecting wiring FL arranged to the right of the virtual center line CL in the display area DA may be substantially symmetrical with respect to the virtual center line CL.

[0052] Each of the connection routes FL may include a first portion FL1 and a third portion FL3 extending in a first direction (e.g., DR1 direction), and a second portion FL2 extending in a second direction (e.g., DR2 direction). The second portion FL2 may connect the first portion FL1 and the third portion FL3. The first portion FL1, the second portion FL2, and the third portion FL3 may be formed integrally. The third portion FL3 may be located at or adjacent to the virtual center line CL, and the first portion FL1 may be located at corners CN1 and CN2. The first portion FL1 may extend away from the fourth edge E4 in the first direction (e.g., DR1 direction). The second portion FL2 may bend from the first portion FL1 and extend towards the virtual center line CL from either the first edge E1 or the second edge E2 in the second direction (e.g., DR2 direction). The third portion FL3 may extend from the second portion FL2 in the first direction (e.g., DR1 direction) to the fourth edge E4 facing the pad portion PADA. The overall shape of the connection route FL around each side of the virtual center line CL may be an upside-down straight U-shape. The downward-flipped side of each inverted straight U-shape can contact the boundary of the fourth edge E4. For example, the connecting wiring FL, which includes the overall structure, can have nested U-shapes, each U-shape having an edge parallel to the adjacent connecting wiring FL and having different height and width characteristics.

[0053] Depending on where the connecting cabling FL is located, the display area DA can be divided into multiple areas. For example, the display area DA may include a first area SR1 in which the connecting cabling FL is located and a second area SR2 which is the remaining area excluding the first area SR1. The second area SR2 may be an area where no connecting cabling FL is located.

[0054] Depending on the extension direction of the connecting cabling FL, the first region SR1 can be divided into multiple sub-regions. For example, the first region SR1 may include a first sub-region SS1 in which the first part FL1 of the connecting cabling FL is arranged, a second sub-region SS2 in which the second part FL2 is arranged, and a third sub-region SS3 in which the third part FL3 is arranged. The first sub-regions SS1, SS2, and SS3 located to the right of the virtual center line CL can be substantially symmetrical to the first sub-regions SS1, SS2, and SS3 located to the left of the virtual center line CL, respectively.

[0055] The non-display area NDA may at least partially surround the display area DA. The non-display area NDA is the area where no pixels PX are disposed, and may include pad portions PADA, which are areas in which various electronic devices or printed circuit boards are electrically attached, and voltage lines for supplying power to drive display elements may be located in the non-display area NDA. The pad portions PADA may include multiple pads, and the multiple pads may be electrically connected to a data driver. In an exemplary embodiment of the present invention, a data driver for supplying data signals may be disposed on a film of pads electrically connected to the pad portions PADA using a chip-on-film (COF) method. According to an exemplary embodiment of the present invention, the data driver may be directly disposed on the substrate 110 using a chip-on-glass (COG) method or a chip-on-plastic (COP) method.

[0056] Fan-out routing (FOL) can be arranged in the non-display area NDA. Fan-out routing (FOL) can be connected to the signal lines of the display area DA to transmit signals from the pad portion PADA. In an exemplary embodiment of the invention, at least some of the fan-out routing (FOL) can be connected to connection routing (FL).

[0057] Figure 1 This is a plan view of the unbent substrate 110. In electronic devices such as the final display device or a smartphone that includes a display device, a portion of the substrate 110 may be bent to minimize the area of ​​the non-display area NDA that is identifiable by the user.

[0058] refer to Figure 2 The non-display area NDA may include a curved area BA, and the curved area BA may be located between the pad portion PADA and the display area DA. In this case, the substrate 110 may be bent in the curved area BA such that at least a portion of the pad portion PADA can be positioned to overlap with the display area DA. The pad portion PADA does not cover the display area DA, and the bending direction is set such that the pad portion PADA is located behind the display area DA. Accordingly, the user may consider that the display area DA occupies most of the viewing surface of the display device.

[0059] Figure 3 A portion of the first corner CN1 is illustrated. According to this exemplary embodiment of the invention, when observed by a user in a normal usage environment, the display device 1 or an electronic device including the display device 1 is perceived as having a rounded corner shape, i.e., a curved shape. In other words, from the user's perspective, the overall shape of the first corner CN1 can appear as a rounded corner shape. However, in environments where wiring with widths of several micrometers or tens of micrometers can be observed by magnifying the first corner CN1, such as… Figure 3 As illustrated, the first corner CN1 can be represented as a straight line shape with multiple bends in a first direction (e.g., DR1 direction) and a second direction (e.g., DR2 direction). For example, the first corner CN1 can have a stepped shape with consecutive steps spaced apart in the first direction (e.g., DR1 direction) and an extension length extending in the second direction (e.g., DR2 direction). The lowest step adjacent to the pad portion PADA can have the longest width among the steps of the stepped shape (e.g., the maximum extension length extending in the second direction (e.g., DR2 direction)). Although as Figure 3 As illustrated, the first corner CN1 appears as a straight line with multiple bends when magnified, but it can also be recognized as having a rounded shape, i.e., a curved shape, under normal use. Therefore, when the first corner CN1 and the second corner CN2 have rounded shapes, this can include cases where the shape is essentially rounded and cases where the shape is a straight line with multiple bends.

[0060] refer to Figure 3 The data line DL may include a first data line DL1 and a second data line DL2. The first data line DL1 may be a data line connected to the connection wiring FL via a node indicated by a circle. The second data line DL2 may be a data line other than the first data line DL1.

[0061] Furthermore, the fan-out wiring FOL may include a first fan-out wiring 203 and a second fan-out wiring 205. The first fan-out wiring 203 may be a fan-out wiring connected to the connection wiring FL. The second fan-out wiring 205 may be a fan-out wiring other than the first fan-out wiring 203. For example, the second fan-out wiring 205 in the fan-out wiring FOL may be connected to the second data line DL2.

[0062] In the display area DA, the connection wiring FL can be arranged to transmit electrical signals supplied from the pad portion PADA to signal lines connected to the pixel PX. For example, the connection wiring FL can be connected to the first data line DL1 and configured to transmit data signals supplied from the pads of the pad portion PADA to the first data line DL1. Each of the connection wiring FLs can be located on a different layer than the layer on which the scan line SL and data line DL of the pixel PX are arranged. However, the invention is not limited thereto.

[0063] The first portion FL1 of each of the connecting routes FL can be parallel to the first data line DL1 and can be arranged to partially overlap or be adjacent to the first data line DL1. The first portion FL1 of each of the connecting routes FL can extend parallel to the first data line DL1 in one of a plurality of columns. The second portion FL2 of each of the connecting routes FL can be parallel to the scan line SL and can be arranged to partially overlap or be adjacent to the scan line SL. The second portion FL2 of each of the connecting routes FL can extend parallel to the scan line SL in one of a plurality of rows. The third portion FL3 of each of the connecting routes FL can be parallel to the first data line DL1 and / or the second data line DL2 and can be arranged to partially overlap or be adjacent to the second data line DL2. The third portion FL3 of each of the connecting routes FL can extend parallel to the second data line DL2 in one of a plurality of columns.

[0064] In each of the connecting wires FL, the first part FL1 and the third part FL3 may be separated by at least one column. The first parts FL1 of a pair of adjacent connecting wires FL may be separated by at least one column. The third parts FL3 of a pair of adjacent connecting wires FL may be separated by at least one column. The second parts FL2 of a pair of adjacent connecting wires FL may be separated by at least one row.

[0065] One end of each of the connecting wires FL can be (e.g., at the first side flipped down) connected to the first data line DL1, and the other end of each of the connecting wires FL (e.g., at the second side flipped down) can be connected to the first fan-out wire 203. One end of the first fan-out wire 203 (e.g., the first end) can be connected to the other end of the connecting wire FL (e.g., the second side flipped down), and the other end of the first fan-out wire 203 (e.g., the second end) can be connected to the pad of the pad portion PADA. Additionally, the first portion FL1 of the connecting wire FL can be electrically connected to the first data line DL1 at the contact portion CNT of the non-display area NDA. In an exemplary embodiment of the invention, the first fan-out wire 203 can be a portion of the third portion FL3 extending into the non-display area NDA. In an exemplary embodiment of the invention, the first fan-out wire 203 is a separate wire arranged on a different layer than the layer on which the connecting wire FL (e.g., the first portion FL1) is arranged, and can be electrically connected to the third portion FL3 of the connecting wire FL in the non-display area NDA.

[0066] One end (e.g., the first end) of the second fan-out wiring 205 can be connected to the second data line DL2, and the other end (e.g., the second end) of the second fan-out wiring 205 can be connected to the pads of the pad portion PADA. In an exemplary embodiment of the present invention, the second fan-out wiring 205 may be a portion of the second data line DL2 extending into the non-display area NDA. In an exemplary embodiment of the present invention, the second fan-out wiring 205 is a separate wiring arranged on a different layer than the layer on which the second data line DL2 is arranged, and may be electrically connected to the second data line DL2 in the non-display area NDA.

[0067] As described above, arranging the connection wiring FL within the display area DA can reduce the area of ​​the non-display area NDA surrounding the first corner CN1 or the second corner CN2. When the connection wiring FL is not arranged within the display area DA as described above, the signal lines of the display area DA can extend in the direction of the first corner CN1 or the second corner CN2 within the display area DA to connect to the fan-out wiring FOL. In this case, the area occupied by the fan-out wiring FOL can increase, and the area of ​​the non-display area NDA can increase. In this exemplary embodiment of the invention, since the connection wiring FL connecting to the signal lines passes through the display area DA, the area of ​​the fan-out wiring FOL can be minimized. Therefore, the area of ​​the non-display area NDA can be reduced.

[0068] Figure 4 It is achieved through partial magnification. Figure 3 A plan view of region B. Figure 4 In, with Figure 3In the accompanying drawings, the same reference numerals indicate the same components, and redundant descriptions will be omitted.

[0069] Figure 4 An exemplary illustration shows the connection wiring FL positioned to the left of the virtual center line CL. Figure 4 This can be equally applied to the connection wiring FL located to the right of the virtual center line CL. Figure 4 In the diagram, pixel PX is arranged within a pixel region CA, which is divided by a dashed line. Figure 4 The diagram illustrates the connecting wiring FL arranged in the pixel regions CA of the adjacent first row PXRi and second row PXRi+1 and the adjacent first to fourth columns PXCj, PXCj+1, PXCj+2 and PXCj+3.

[0070] Figure 4 The diagram illustrates the first portion FL1 and the second portion FL2 of the connecting wiring FL, which are respectively arranged in the first sub-region SS1 and the second sub-region SS2. This can also be symmetrically applied to the second portion FL2 and the third portion FL3 of the connecting wiring FL, which are arranged in the second sub-region SS2 and the third sub-region SS3.

[0071] refer to Figure 4 In the first sub-region SS1, the first portion FL1 of the connecting wiring FL can extend in a first direction (e.g., the DR1 direction).

[0072] In exemplary embodiments of the present invention, such as Figure 4 As shown, the first portion FL1 may overlap with the drive voltage line PL. However, the invention is not limited thereto. For example, in an exemplary embodiment of the invention, the first portion FL1 may be spaced apart from the drive voltage line PL. Each drive voltage line PL may extend in a first direction (e.g., the DR1 direction) and may be spaced apart by at least one column. In an exemplary embodiment of the invention, the width of the drive voltage line PL may be greater than the width of the first portion FL1, and the drive voltage line PL may have a width that completely covers the width of the first portion FL1.

[0073] The first portion FL1 may include a first protrusion FLB1 projecting in a second direction (e.g., the DR2 direction) that is substantially orthogonal to the first direction (e.g., the DR1 direction). For example, each first portion FL1 may have a first protrusion FLB1 extending in the opposite direction of the axis represented by the DR2 direction from a line parallel to (e.g., on opposite sides) of the respective first portion FL1. The two protrusions FLB1 may be aligned in the second direction (e.g., the DR2 direction).

[0074] The first protrusion FLB1 may protrude from the first portion FL1 relative to the first portion FL1 of the connecting wiring FL. In other words, the first protrusion FLB1 may protrude from the first portion FL1 extending in a first direction (e.g., DR1 direction) of the connecting wiring FL along a second direction (e.g., DR2 direction) toward at least one of its sides. Furthermore, a pair of first protrusions FLB1 protruding from two adjacent first portions FL1 arranged side-by-side in the first sub-region SS1 and protruding toward each other may be arranged on the same line. For example, first protrusions FLB1 extending from adjacent sides of different first portions FL1 toward each other may be aligned with each other on an axis represented by the second direction (e.g., DR2 direction). To prevent short circuits between the connecting wiring FLs, the ends of the first protrusions FLB1 extending from two adjacent first portions FL1 toward each other are spaced apart, thus forming a gap between them. In the first sub-region SS1, the first portions FL1 and the first protrusions FLB1 may be arranged in a specific pattern in the pixel region CA.

[0075] The first protrusion FLB1 may extend in a second direction (e.g., the DR2 direction). The first protrusion FLB1 may overlap with the initialization voltage line VIL. The width of the initialization voltage line VIL may be greater than the width of the first protrusion FLB1, and may have a width that completely covers the width of the first protrusion FLB1.

[0076] In the second sub-region SS2, the second portion FL2 of the connecting wiring FL may extend in a second direction (e.g., the DR2 direction). In an exemplary embodiment of the invention, the second portion FL2 may extend in the second direction (e.g., the DR2 direction) overlapping with the initialization voltage line VIL. In an exemplary embodiment of the invention, the width of the initialization voltage line VIL is greater than the width of the second portion FL2, and may have a width that completely covers the width of the second portion FL2.

[0077] The second part FL2 may include a second protrusion FLB2 that protrudes in a first direction (e.g., the DR1 direction).

[0078] The second protrusion FLB2 may protrude from the second portion FL2 relative to the second portion FL2. The second protrusion FLB2 may also protrude from the parallel side of the corresponding second portion FL2 in the direction opposite to the axis represented by the DR1 direction. In other words, the second protrusion FLB2 may protrude from the second portion FL2 extending in a second direction (e.g., the DR2 direction) of the connecting wiring FL along at least one of the two sides in a first direction (e.g., the DR1 direction). Furthermore, a pair of second protrusions FLB2 protruding from two adjacent second portions FL2 in the second sub-region SS2 towards each other may be arranged on the same line. To prevent short circuits between the connecting wiring FLs, the ends of the second protrusions FLB2 extending from two adjacent second portions FL2 towards each other are spaced apart, thus forming a gap between them. In the second sub-region SS2, the second portion FL2 and the second protrusion FLB2 may be arranged in a specific pattern in the pixel region CA.

[0079] In an exemplary embodiment of the present invention, the second protrusion FLB2 may extend in a first direction (e.g., the DR1 direction) and overlap with the drive voltage line PL. In an exemplary embodiment of the present invention, the width of the drive voltage line PL may be greater than the width of the second protrusion FLB2, and may have a width that completely covers the width of the second protrusion FLB2.

[0080] In an exemplary embodiment of the present invention, the shielding electrode 173 and the upper connecting electrode 177 may be further arranged in the pixel region CA. The shielding electrode 173 and the upper connecting electrode 177 may be arranged on the same layer as the connecting wiring FL. Although Figure 4 The shielding electrode 173 and the upper connecting electrode 177 are illustrated, but the invention is not limited thereto. For example, according to exemplary embodiments of the invention, electrodes of various numbers and shapes can be arranged in the pixel region CA. The shielding electrode 173 and the upper connecting electrode 177 can prevent signal interference between the circuit portion and the connecting wiring FL, and can provide improved efficiency in the manufacturing process by ensuring pattern density.

[0081] Composed of the first sub-region SS1, the second sub-region SS2, and the third sub-region SS3 (see...) Figure 1 Composed of, already Figure 4 The first region SR1 described in [the document] can also be applied to the second region SR2 (see [the document]). Figure 1 Therefore, since the connecting wiring FL is also arranged in the second region SR2, the light reflection (or scattering) characteristics are similar, and thus the first region SR1 and the second region SR2 can be identified without distinguishing them from each other.

[0082] Figure 5This is an equivalent circuit diagram of a pixel PX in a display device 1 according to an exemplary embodiment of the present invention.

[0083] refer to Figure 5 Pixel PX includes a storage capacitor Cst, a boost capacitor Cbt, an initialization voltage line VIL, a driving voltage line PL, an organic light-emitting diode (OLED) as a display element, signal lines SL1, SL2, SLp, SLn, EM, and DL, and a plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7 connected to the signal lines SL1, SL2, SLp, SLn, EM, and DL. In an exemplary embodiment of the present invention, at least one of the signal lines SL1, SL2, SLp, SLn, EM, and DL, such as the initialization voltage line VIL and / or the driving voltage line PL, can be shared by adjacent pixels PX.

[0084] Thin-film transistors T1, T2, T3, T4, T5, T6, and T7 may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensating thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, a light emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0085] Some of the thin-film transistors T1, T2, T3, T4, T5, T6 and T7 can be provided as n-channel MOSFETs (NMOS), while the others can be provided as p-channel MOSFETs (PMOS).

[0086] In an exemplary embodiment of the present invention, the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 among the plurality of thin-film transistors T1, T2, T3, T4, T5, T6 and T7 can be provided as NMOS, while the other thin-film transistors can be provided as PMOS.

[0087] In an exemplary embodiment of the present invention, the compensation thin-film transistor T3, the first initialization thin-film transistor T4, and the second initialization thin-film transistor T7 among the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can be provided as NMOS, while the other thin-film transistors can be provided as PMOS. Alternatively, only one of the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can be provided as NMOS, while the other thin-film transistors can be provided as PMOS. Alternatively, all of the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can be provided as NMOS.

[0088] The signal lines may include a first scan line SL1 for transmitting a first scan signal Sn, a second scan line SL2 for transmitting a second scan signal Sn', a previous scan line SLp for transmitting a previous scan signal Sn-1 to a first initialization thin-film transistor T4, a light emission control line EM for transmitting a light emission control signal En to an operation control thin-film transistor T5 and a light emission control thin-film transistor T6, a next scan line SLn for transmitting a next scan signal Sn+1 to a second initialization thin-film transistor T7, and a data line DL that intersects the first scan line SL1 and is configured to transmit a data signal Dm.

[0089] The drive voltage line PL is configured to transmit the drive voltage ELVDD to the drive thin-film transistor T1, and the initialization voltage line VIL is configured to transmit the initialization voltage Vint used to initialize the drive thin-film transistor T1 and the pixel electrode.

[0090] The driving gate electrode of driving thin-film transistor T1 is connected to the storage capacitor Cst. The driving source electrode of driving thin-film transistor T1 is connected to the driving voltage line PL via the operation control thin-film transistor T5. The driving drain electrode of driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the light-emitting control thin-film transistor T6. Driving thin-film transistor T1 receives the data signal Dm according to the switching operation of switching thin-film transistor T2 and drives the driving current I... OLED It is supplied to organic light-emitting diodes (OLEDs).

[0091] The switching gate electrode of the switching thin-film transistor T2 is connected to the first scan line SL1, the switching source electrode of the switching thin-film transistor T2 is connected to the data line DL, and the switching drain electrode of the switching thin-film transistor T2 is connected to the driving source electrode of the driving thin-film transistor T1, and is connected to the driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 is turned on according to the first scan signal Sn received through the first scan line SL1, and performs a switching operation to transmit the data signal Dm transmitted to the data line DL to the driving source electrode of the driving thin-film transistor T1.

[0092] The compensation gate electrode of the compensation thin-film transistor T3 is connected to the second scan line SL2. The compensation drain electrode of the compensation thin-film transistor T3 is connected to the driving drain electrode of the driving thin-film transistor T1, and is connected to the pixel electrode of the organic light-emitting diode (OLED) via the light-emitting control thin-film transistor T6. The compensation source electrode of the compensation thin-film transistor T3 is connected to the first electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving thin-film transistor T1 via node connection line 166. Furthermore, the compensation source electrode of the compensation thin-film transistor T3 is connected to the first initialization drain electrode of the first initialization thin-film transistor T4.

[0093] The compensation thin-film transistor T3 is turned on according to the second scan signal Sn' received through the second scan line SL2, and electrically connects the driving gate electrode and the driving drain electrode of the driving thin-film transistor T1, thereby connecting the driving thin-film transistor T1 as a diode.

[0094] The first initialization gate electrode of the first initialization thin-film transistor T4 is connected to the previous scan line SLp. The first initialization source electrode of the first initialization thin-film transistor T4 is connected to the second initialization source electrode of the second initialization thin-film transistor T7 and the initialization voltage line VIL. The first initialization drain electrode of the first initialization thin-film transistor T4 is connected to the first electrode CE1 of the storage capacitor Cst, the compensation source electrode of the compensation thin-film transistor T3, and the driving gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on according to the previous scan signal Sn-1 received through the previous scan line SLp, and transmits the initialization voltage Vint to the driving gate electrode of the driving thin-film transistor T1 to perform an initialization operation for initializing the voltage of the driving gate electrode of the driving thin-film transistor T1.

[0095] The operation control gate electrode of the operation control thin film transistor T5 is connected to the light emission control line EM, the operation control source electrode of the operation control thin film transistor T5 is connected to the drive voltage line PL, and the operation control drain electrode of the operation control thin film transistor T5 is connected to the drive source electrode of the drive thin film transistor T1 and the switch drain electrode of the switch thin film transistor T2.

[0096] The light-emitting control gate electrode of the light-emitting control thin-film transistor T6 is connected to the light-emitting control line EM, the light-emitting control source electrode of the light-emitting control thin-film transistor T6 is connected to the driving drain electrode of the driving thin-film transistor T1 and the compensation drain electrode of the compensation thin-film transistor T3, and the light-emitting control drain electrode of the light-emitting control thin-film transistor T6 is electrically connected to the second initialization drain electrode of the second initialization thin-film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0097] The operation control thin-film transistor T5 and the light emission control thin-film transistor T6 are simultaneously turned on according to the light emission control signal En received through the light emission control line EM, and the driving voltage ELVDD is transmitted to the OLED, causing the driving current I... OLED It flows through an organic light-emitting diode (OLED).

[0098] The second initialization gate electrode G7 of the second initialization thin-film transistor T7 is connected to the next scan line SLn. The second initialization drain electrode of the second initialization thin-film transistor T7 is connected to the light-emitting control drain electrode of the light-emitting control thin-film transistor T6 and the pixel electrode of the organic light-emitting diode (OLED). The second initialization source electrode of the second initialization thin-film transistor T7 is connected to the first initialization source electrode of the first initialization thin-film transistor T4 and the initialization voltage line VIL. The second initialization thin-film transistor T7 is turned on according to the next scan signal Sn+1 received through the next scan line SLn to initialize the pixel electrode of the organic light-emitting diode (OLED).

[0099] like Figure 5 As illustrated, the second initialization thin-film transistor T7 can be connected to the next scan line SLn. In another embodiment, the second initialization thin-film transistor T7 can be connected to the light emission control line EM and driven according to the light emission control signal En. Figure 5 The positions of the source and drain electrodes can be changed depending on the type of transistor (p-type or n-type).

[0100] The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst is connected to the driving gate electrode of the driving thin-film transistor T1, and the second electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst can store a charge corresponding to the difference between the voltage of the driving gate electrode of the driving thin-film transistor T1 and the driving voltage ELVDD.

[0101] The boost capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 can be connected to the switching gate electrode of the switching thin-film transistor T2 and the first scan line SL1, and the fourth electrode CE4 can be connected to the compensation source electrode of the compensation thin-film transistor T3 and the node connection line 166. When the first scan signal Sn supplied to the first scan line SL1 is turned off, the boost capacitor Cbt can increase the voltage of the first node N1. As described above, when the voltage of the first node N1 increases, the black grayscale can be clearly expressed.

[0102] The first node N1 can be the region where the driving gate electrode of the driving thin-film transistor T1, the compensation source electrode of the compensation thin-film transistor T3, the first initialization drain electrode of the first initialization thin-film transistor T4, and the fourth electrode CE4 of the boost capacitor Cbt are connected.

[0103] The detailed operation of each pixel PX according to an exemplary embodiment of the present invention is as follows.

[0104] During the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line SLp, the first initialization thin-film transistor T4 turns on in response to the previous scan signal Sn-1 and drives the thin-film transistor T1 to be initialized by the initialization voltage Vint supplied from the initialization voltage line VIL.

[0105] During the data programming period, when the first scan signal Sn and the second scan signal Sn' are supplied through the first scan line SL1 and the second scan line SL2, respectively, the switching thin-film transistor T2 and the compensation thin-film transistor T3 are turned on in response to the first scan signal Sn and the second scan signal Sn', respectively. In this paper, the driving thin-film transistor T1 is connected to the turned-on compensation thin-film transistor T3 by a diode and is forward biased.

[0106] Then, a compensation voltage Dm+Vth (Vth being negative) obtained by subtracting the threshold voltage Vth of the driving thin-film transistor T1 from the data signal Dm supplied from the data line DL is applied to the driving gate electrode G1 of the driving thin-film transistor T1 (see example). Figure 6 ).

[0107] The driving voltage ELVDD and the compensation voltage Dm+Vth are applied to the corresponding terminals of the storage capacitor Cst, and the charge corresponding to the voltage difference between the two terminals is stored in the storage capacitor Cst.

[0108] During the light-emitting period, the operation control thin-film transistor T5 and the light-emitting control thin-film transistor T6 are turned on by the light-emitting control signal En supplied from the light-emitting control line EM. The drive current I is determined based on the voltage difference between the voltage at the drive gate electrode G1 of the driving thin-film transistor T1 and the drive voltage ELVDD. OLED It is generated and drives current I. OLED The light-emitting thin-film transistor T6 is supplied to the organic light-emitting diode (OLED).

[0109] In an exemplary embodiment of the present invention, at least one of the plurality of thin-film transistors T1, T2, T3, T4, T5, T6 and T7 includes a semiconductor layer comprising an oxide, and the other thin-film transistors include a semiconductor layer comprising silicon.

[0110] For example, the driving thin-film transistor T1, which directly affects the brightness of the display device 1, is configured to include a semiconductor layer formed of polycrystalline silicon with high reliability, and thus a high-resolution display device can be realized.

[0111] Because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is small even during long drive times. In other words, the color change of the image due to voltage drop is small even during low-frequency drive, thus enabling low-frequency drive.

[0112] As described above, because oxide semiconductors have low leakage current, at least one of the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 connected to the drive gate electrode G1 of the drive thin film transistor T1 is configured to include oxide semiconductors, and thus leakage current that may flow to the drive gate electrode G1 can be prevented and power consumption can be reduced.

[0113] Figure 6 This is a schematic layout diagram showing the positions of a plurality of thin-film transistors and capacitors arranged in a pixel circuit of a display device 1 according to an exemplary embodiment of the present invention. Specifically, Figure 6 yes Figure 4 A magnified view of region C. Figure 7 It is along Figure 6 A schematic cross-sectional view taken from line I-I', and Figure 8 It is along Figure 6 A schematic cross-sectional view taken from line II-II'.

[0114] refer to Figure 6 The pixel circuit of the display device 1 according to an exemplary embodiment of the present invention includes a data line DL and a driving voltage line PL extending along a first direction (e.g., DR1 direction), and includes a first scan line SL1, a second scan line SL2, a previous scan line SLp, a next scan line SLn, a light emission control line EM, and an initialization voltage line VIL extending along a second direction (e.g., DR2 direction) intersecting the first direction (e.g., DR1 direction). Furthermore, a connection wiring FL for connecting the data line DL to the pad portion PADA can be provided in the display area DA.

[0115] The pixel circuit may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, a light emission control thin-film transistor T6, a second initialization thin-film transistor T7, a storage capacitor Cst, and a boost capacitor Cbt.

[0116] In an exemplary embodiment of the present invention, the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the light emission control thin-film transistor T6, and the second initialization thin-film transistor T7 can be provided as thin-film transistors comprising silicon semiconductors.

[0117] Furthermore, the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 can be provided as thin-film transistors including oxide semiconductors.

[0118] The semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the light-emitting control thin-film transistor T6, and the second initialization thin-film transistor T7 are arranged on the same layer and comprise the same material. For example, the semiconductor layer may be formed of polycrystalline silicon.

[0119] The semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the light-emitting control thin-film transistor T6, and the second initialization thin-film transistor T7 can be disposed on a buffer layer 111 disposed on the substrate 110 (see [reference]). Figure 7 )superior.

[0120] The semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the light emission control thin-film transistor T6, and the second initialization thin-film transistor T7 can be connected to each other and can be bent into various shapes.

[0121] The semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the light-emitting control thin-film transistor T6, and the second initialization thin-film transistor T7 may each include a channel region and source and drain regions located on opposite sides of the channel region. For example, the source and drain regions may be doped with impurities, and the impurities may include N-type or P-type impurities. The source and drain regions correspond to the source electrode and drain electrode, respectively. Hereinafter, the terms source region and drain region are used instead of the terms source electrode and drain electrode.

[0122] The driving thin-film transistor T1 includes a driving semiconductor layer and a driving gate electrode G1. The driving semiconductor layer includes a driving channel region A1 and driving source regions S1 and driving drain regions D1 on opposite sides of the driving channel region A1 (e.g., parallel sides spaced apart in a first direction (e.g., DR1 direction)). The driving semiconductor layer has a curved shape, and therefore the driving channel region A1 can be longer than the other channel regions A2 to A7. For example, the driving semiconductor layer has a multiple-bend shape such as Omega or the letter "S", and therefore a long channel can be formed in a narrow space. Because the driving channel region A1 is formed long, the driving range of the gate voltage applied to the driving gate electrode G1 is expanded, making it possible to more precisely control the grayscale of the light emitted from the organic light-emitting diode OLED and improve display quality. The driving gate electrode G1 is island-shaped and overlaps with the driving channel region A1, and a first gate insulating layer 112 (see [reference]) is provided between the driving gate electrode G1 and the driving channel region A1. Figure 7 ).

[0123] The storage capacitor Cst can be arranged to overlap with the driving thin-film transistor T1. The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. The driving gate electrode G1 can be used as the gate electrode of the driving thin-film transistor T1 and the first electrode CE1 of the storage capacitor Cst. In other words, it can be understood that the driving gate electrode G1 and the first electrode CE1 are integrally formed. The second electrode CE2 of the storage capacitor Cst at least partially overlaps with the first electrode CE1, and a second gate insulating layer 113 (see [reference]) is provided between the second electrode CE2 and the first electrode CE1. Figure 7 In this paper, the second gate insulating layer 113 can be used as the dielectric layer of the storage capacitor Cst.

[0124] The second electrode CE2 may include a storage opening SOP. The storage opening SOP can be formed by removing a portion of the second electrode CE2 and can have a closed shape. Node connection line 166 can be connected to the first electrode CE1 through a first contact hole CNT1 arranged in the storage opening SOP. The second electrode CE2 can be connected to the drive voltage line PL through a seventh contact hole CNT7. The second electrode CE2 can extend in a second direction (e.g., the DR2 direction) to transmit the drive voltage ELVDD in the second direction (e.g., the DR2 direction). Therefore, multiple drive voltage lines PL and multiple second electrodes CE2 can form a grid structure in the display area DA.

[0125] The switching thin-film transistor T2 includes a switching semiconductor layer and a switching gate electrode G2. The switching semiconductor layer includes a switching channel region A2 and a switching source region S2 and a switching drain region D2 located on opposite sides of the switching channel region A2 (e.g., parallel sides spaced apart in a first direction, e.g., the DR1 direction). The switching source region S2 is connected to a data line DL via a contact hole and a connection electrode, and the switching drain region D2 is connected to a drive source region S1. In an exemplary embodiment of the invention, the switching gate electrode G2 can be provided as part of a first scan line SL1 by protruding in a second direction (e.g., the DR2 direction).

[0126] The operation control thin-film transistor T5 includes an operation control semiconductor layer and an operation control gate electrode G5. The operation control semiconductor layer includes an operation control channel region A5 and operation control source regions S5 and D5 located on opposite sides of the operation control channel region A5 (e.g., parallel sides spaced apart in a first direction (e.g., DR1 direction)). The operation control source region S5 can be connected to the drive voltage line PL through an eighth contact hole CNT8, and the operation control drain region D5 can be connected to the drive source region S1. The operation control gate electrode G5 is provided as part of the light emission control line EM.

[0127] The light-emitting control thin-film transistor T6 includes a light-emitting control semiconductor layer and a light-emitting control gate electrode G6. The light-emitting control semiconductor layer includes a light-emitting control channel region A6 and a light-emitting control source region S6 and a light-emitting control drain region D6 located on opposite sides of the light-emitting control channel region A6 (e.g., parallel sides spaced apart in a first direction (e.g., DR1 direction)). The light-emitting control source region S6 can be connected to the driving drain region D1, and the light-emitting control drain region D6 can be connected to the first connection electrode 167 through a sixth contact hole CNT6. The first connection electrode 167 can be connected to the pixel electrode 310 of the organic light-emitting diode OLED (see above) through an upper connection electrode 177 disposed on another layer. Figure 8 The light-emitting control gate electrode G6 is provided as part of the light-emitting control line EM.

[0128] The second initialization thin-film transistor T7 includes a second initialization semiconductor layer and a second initialization gate electrode G7. The second initialization semiconductor layer includes a second initialization channel region A7 and a second initialization source region S7 and a second initialization drain region D7 located on the opposite side of the second initialization channel region A7. The second initialization source region S7 can be connected to the initialization voltage line VIL via a third connection electrode 169, and the second initialization drain region D7 can be connected to the light-emitting control drain region D6. The second initialization gate electrode G7 is provided as part of the next scan line SLn.

[0129] First interlayer insulation layer 114 (see...) Figure 7 The thin-film transistors T1, T2, T5, T6 and T7, which include silicon semiconductors, can be arranged on thin-film transistors T3 and T4, which include oxide semiconductors, and can be arranged on the first interlayer insulating layer 114.

[0130] The semiconductor layers of the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 are arranged on the same layer and comprise the same material. For example, the semiconductor layer may be formed of oxide semiconductor.

[0131] Each of the semiconductor layers may include a channel region and source and drain regions located on opposite sides of the channel region (e.g., parallel sides spaced apart in a first direction (e.g., DR1 direction)). For example, the source and drain regions may be regions with increased carrier concentration obtained through plasma treatment. The source and drain regions correspond to the source electrode and drain electrode, respectively. In the following text, the terms "source region" and "drain region" may also be used in place of the source electrode and drain electrode.

[0132] The compensation thin-film transistor T3 includes a compensation semiconductor layer comprising an oxide semiconductor and a compensation gate electrode G3. The compensation semiconductor layer includes a compensation channel region A3 and compensation source regions S3 and D3 located on opposite sides of the compensation channel region A3 (e.g., parallel sides spaced apart in a first direction (e.g., DR1 direction)). The compensation source region S3 can be bridged to the driving gate electrode G1 via a node connection line 166. One end (e.g., a first end) of the node connection line 166 can be connected to the compensation source region S3 via a second contact hole CNT2, and the other end (e.g., a second end) of the node connection line 166 can be connected to the driving gate electrode G1 via a first contact hole CNT1. Furthermore, the compensation source region S3 can be connected to a first initialization drain region D4 disposed on the same layer. The compensation drain region D3 can be connected via a second connection electrode 168 to the driving semiconductor layer of the driving thin-film transistor T1 and the light-emitting control semiconductor layer of the light-emitting control thin-film transistor T6. The compensation gate electrode G3 is provided as part of a second scan line SL2.

[0133] The first initialization thin-film transistor T4 includes a first initialization semiconductor layer comprising an oxide semiconductor and a first initialization gate electrode G4. The first initialization semiconductor layer includes a first initialization channel region A4 and a first initialization source region S4 and a first initialization drain region D4 located on opposite sides of the first initialization channel region A4 (e.g., parallel sides spaced apart in a first direction (e.g., DR1 direction)). The first initialization source region S4 can be connected to a third connection electrode 169 via a ninth contact hole CNT9, and the third connection electrode 169 can be connected to an initialization voltage line VIL via a contact hole. The first initialization drain region D4 can be bridged to the drive gate electrode G1 via a node connection line 166. The first initialization gate electrode G4 is provided as part of the previous scan line SLp.

[0134] Third gate insulation layer 115 (see Figure 7 The first initialization semiconductor layer and the first initialization gate electrode G4 are arranged between the compensation semiconductor layer and the compensation gate electrode G3, and between the first initialization semiconductor layer and the first initialization gate electrode G4, to correspond to the respective channel regions.

[0135] The third electrode CE3, one electrode of the boost capacitor Cbt, is provided as part of the first scan line SL1 and connected to the switch gate electrode G2. The fourth electrode CE4 of the boost capacitor Cbt can be arranged to overlap with the third electrode CE3 and can be provided as an oxide semiconductor. The fourth electrode CE4 can be disposed on the same layer as the compensation semiconductor layer of the compensation thin-film transistor T3 and the semiconductor layer of the first initialization thin-film transistor T4, and can be provided in the region between the compensation semiconductor layer and the first initialization semiconductor layer. Alternatively, the fourth electrode CE4 can extend from the first initialization semiconductor layer. Alternatively, the fourth electrode CE4 can extend from the compensation semiconductor layer.

[0136] Second interlayer insulation layer 116 (see Figure 7 The driving voltage line PL, node connection line 166, and connection electrodes 167, 168, and 169 can be arranged on the second interlayer insulating layer 116.

[0137] In an exemplary embodiment of the present invention, the first planarization layer 118 (see Figure 7 The shielding electrode 173 can be arranged to cover the drive voltage line PL and the data line DL, and the shielding electrode 173 can be arranged on the first planarization layer 118.

[0138] The shielding electrode 173 can be arranged on the node connection line 166 spanning both the portion connected to the driving gate electrode G1 and the portion connected to the fourth electrode CE4. When the shielding electrode 173 is not arranged in this way, the node connection line 166 can connect to the pixel electrode 310 of the display element disposed thereon (see...). Figure 7 This creates a coupling capacitance. Consequently, the thin-film transistor connected to node connection line 166 may be affected.

[0139] In this exemplary embodiment of the invention, a shielding electrode 173 is arranged on the node connection line 166, and a constant voltage is applied to the shielding electrode 173 to minimize the effect of coupling capacitance. In an embodiment, the shielding electrode 173 can be connected to a third connection electrode 169 via a third contact hole CNT3. The third connection electrode 169 can be connected to the initialization voltage line VIL via a contact hole. Accordingly, an initialization voltage Vint can be applied to the shielding electrode 173. In some exemplary embodiments of the inventive concept, the shielding electrode 173 can be connected to the drive voltage line PL via a contact hole. Accordingly, a drive voltage ELVDD can be applied to the shielding electrode 173.

[0140] In some exemplary embodiments of the present invention, the shielding electrode 173 may be formed to cover the entire node connection line 166. In some exemplary embodiments of the present invention, the shielding electrode 173 may be arranged to overlap with at least a portion of the driving thin-film transistor T1, the compensation thin-film transistor T3, and / or the first initialization thin-film transistor T4.

[0141] In an exemplary embodiment of the present invention, the first scan line SL1, the next scan line SLn, and the light emission control line EM can be formed of the same material as the driving gate electrode G1 and formed on the same layer as the driving gate electrode G1.

[0142] In exemplary embodiments of the present invention, although Figure 6The illustration shows a first scan line SL1 extending in a first direction (e.g., DR1 direction) to include the third electrode CE3 of the boost capacitor Cbt, but the third electrode CE3 of the boost capacitor Cbt may be included as part of the first scan line SL1. In this case, the first scan line SL1 may extend in a second direction (e.g., DR2 direction) relative to the third electrode CE3 of the boost capacitor Cbt.

[0143] In an exemplary embodiment of the invention, some of the wiring may be provided as two conductive layers disposed on different layers. For example, the second scan line SL2 may include a lower scan line 143 and an upper scan line 153 disposed on different layers. The lower scan line 143 may be formed of the same material as the second electrode CE2 of the storage capacitor Cst and is formed on the same layer as the second electrode CE2 of the storage capacitor Cst, and the upper scan line 153 may be disposed on the third gate insulating layer 115 (see...). Figure 7 The lower scan line 143 can be arranged to at least partially overlap with the upper scan line 153. The lower scan line 143 and the upper scan line 153 correspond to a portion of the compensation gate electrode G3 of the compensation thin film transistor T3, and therefore the compensation thin film transistor T3 can have a dual-gate structure in which the gate electrode is arranged on and under the semiconductor layer, respectively.

[0144] Furthermore, in an exemplary embodiment of the present invention, the previous scan line SLp may include a lower previous scan line 141 and an upper previous scan line 151 disposed on different layers. The lower previous scan line 141 may be formed of the same material as the second electrode CE2 of the storage capacitor Cst and is formed on the same layer as the second electrode CE2 of the storage capacitor Cst, and the upper previous scan line 151 may be disposed on the third gate insulating layer 115 (see [link to documentation]). Figure 7 The lower preceding scan line 141 can be arranged to at least partially overlap with the upper preceding scan line 151. The lower preceding scan line 141 and the upper preceding scan line 151 correspond to a portion of the first initialization gate electrode G4 of the first initialization thin-film transistor T4, and therefore the first initialization thin-film transistor T4 can have a dual-gate structure in which the gate electrode is arranged on and below the semiconductor layer, respectively. In another exemplary embodiment of the invention, the first initialization thin-film transistor T4 may include a gate electrode and may at least partially overlap with the semiconductor layer. In this case, the first initialization thin-film transistor T4 may have a single-gate structure.

[0145] In an exemplary embodiment of the present invention, the initialization voltage line VIL can be arranged in a first interlayer insulating layer 114 covering the scan line 143 (see [reference]). Figure 7Above. For example, the initialization voltage line VIL can be arranged on the same layer as the previous scan line SLp. In this case, the initialization voltage line VIL can be arranged to overlap with the first scan line SL1. Accordingly, the area of ​​the third electrode CE3 and the fourth electrode CE4 of the boost capacitor Cbt increases, and therefore the capacitance of the boost capacitor Cbt can increase. In another exemplary embodiment of the invention, the initialization voltage line VIL can be arranged on the same layer as the lower scan line 143. In this case, the initialization voltage line VIL can be spaced apart from the first scan line SL1 and may not overlap with the first scan line SL1.

[0146] The connecting wiring FL may include a first portion FL1 and a third portion extending in a first direction (e.g., DR1 direction) and a second portion FL2 extending in a second direction (e.g., DR2 direction), and the first portion FL1, the second portion FL2 and the third portion of the connecting wiring FL may include protrusions.

[0147] In an exemplary embodiment of the present invention, the first portion FL1 may overlap with the drive voltage line PL. For example, the first portion FL1 may extend in a first direction (e.g., the DR1 direction) to continuously overlap with the drive voltage line PL. In another exemplary embodiment of the present invention, the first portion FL1 may be spaced apart from the drive voltage line PL.

[0148] The second portion FL2 can overlap with the initialization voltage line VIL. For example, the second portion FL2 can extend in a second direction (e.g., the DR2 direction) to continuously overlap with the initialization voltage line VIL. In this case, the initialization voltage line VIL can be arranged between the first scan line SL1 and the second portion FL2. Accordingly, data signals transmitted to the second portion FL2 can be prevented from being distorted due to scan signals transmitted to the first scan line SL1.

[0149] In an exemplary embodiment of the present invention, the connection wiring FL may be arranged on the same layer as the shielding electrode 173. In another exemplary embodiment of the present invention, the connection wiring FL may be arranged on the shielding electrode 173.

[0150] In an exemplary embodiment of the present invention, the pixel electrode 310 may overlap with a first portion FL1 or a second portion FL2 of the connecting wiring FL. For example, the pixel electrode 310 may overlap with a second protrusion of the first portion FL1 and / or the second portion FL2 extending in a first direction (e.g., the DR1 direction).

[0151] The second portion FL2 of the connection wiring FL is parallel to the scan line, and therefore, distortion of the data signal transmitted to the connection wiring FL may occur due to the scan signal transmitted to the scan line, and diagonal patterns may occur. According to an exemplary embodiment of the invention, the connection wiring FL may overlap with the initialization voltage line VIL or the drive voltage line PL. Accordingly, the drive voltage line PL or the initialization voltage line VIL serves as a shield to block signal interference between the connection wiring FL and the scan line, thereby minimizing or preventing parasitic capacitance. Therefore, distortion of the data signal in the connection wiring FL can be minimized or prevented.

[0152] In the following text, reference will be made to Figure 7 and Figure 8 The structure of the display device 1 according to an exemplary embodiment of the present invention will be described in detail. Figure 7 and Figure 8 The diagram illustrates the structure of the driving thin-film transistor T1, the compensation thin-film transistor T3, the first initialization thin-film transistor T4, the light-emitting control thin-film transistor T6, the storage capacitor Cst, and the boost capacitor Cbt.

[0153] refer to Figure 7 and Figure 8 According to an exemplary embodiment of the present invention, a display device 1 includes a substrate 110, a first thin-film transistor including a silicon semiconductor, a second thin-film transistor including an oxide semiconductor, a driving voltage line PL extending in a display region DA in a first direction (e.g., DR1 direction), a data line DL spaced apart from the driving voltage line PL, and a connection wiring FL connecting the data line DL to a pad portion PADA. The connection wiring FL may include a first portion FL1 extending in the first direction (e.g., DR1 direction) and a second portion FL2 extending in a second direction (e.g., DR2 direction), and the first portion FL1 may overlap with the driving voltage line PL.

[0154] Furthermore, the display device 1 may further include various insulating layers such as a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, a third gate insulating layer 115, a first interlayer insulating layer 114, a second interlayer insulating layer 116, a first planarization layer 118, and a second planarization layer 119.

[0155] The substrate 110 may comprise glass, ceramic, metallic, and / or flexible or bendable materials. When the substrate 110 possesses flexible or bendable properties, it may comprise polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate. The substrate 110 may have a single-layer or multi-layer structure of the above materials, and in the case of a multi-layer structure, it may further include an inorganic layer. In some exemplary embodiments of the present invention, the substrate 110 may have an organic / inorganic / organic stacked structure.

[0156] The buffer layer 111 can increase the flatness of the upper surface of the substrate 110, and the buffer layer 111 can be made of materials such as silicon oxide (SiO2). x oxide layers and / or such as silicon nitride (SiN) x The nitride layer and / or silicon oxynitride (SiON) are formed.

[0157] A barrier layer may be further included between the substrate 110 and the buffer layer 111. The barrier layer can prevent or minimize the penetration of impurities from the substrate 110 into the silicon semiconductor layer. The barrier layer may include inorganic and / or organic materials such as oxides or nitrides, and may have a single-layer or multi-layer structure of inorganic and organic materials.

[0158] The driving semiconductor layer AS1 of the driving thin film transistor T1, which includes a silicon semiconductor semiconductor layer, and the light-emitting control semiconductor layer AS6 of the light-emitting control thin film transistor T6 can be arranged on the buffer layer 111.

[0159] The driving semiconductor layer AS1 may include a doped, conductive driving source region S1 and a driving drain region D1 spaced apart from each other, as well as a driving channel region A1 disposed between the driving source region S1 and the driving drain region D1. The driving source region S1 and the driving drain region D1 may correspond to the source electrode and the drain electrode of the driving thin film transistor T1, respectively, and the driving source region S1 and the driving drain region D1 may be interchanged in position.

[0160] The light-emitting control semiconductor layer AS6 may include a doped, conductive light-emitting control source region S6 and a light-emitting control drain region D6 spaced apart from each other, as well as a light-emitting control channel region A6 disposed between the light-emitting control source region S6 and the light-emitting control drain region D6. The light-emitting control source region S6 and the light-emitting control drain region D6 may correspond to the source electrode and drain electrode of the light-emitting control thin-film transistor T6, respectively, and the light-emitting control source region S6 and the light-emitting control drain region D6 may be interchanged in position.

[0161] A driving gate electrode G1 is disposed on a driving semiconductor layer AS1, and a light-emitting control gate electrode G6 is disposed on a light-emitting control semiconductor layer AS6. A first gate insulating layer 112 may be disposed between the driving semiconductor layer AS1 and the driving gate electrode G1, and between the light-emitting control semiconductor layer AS6 and the light-emitting control gate electrode G6. Furthermore, a first scan line SL1 and / or a light-emitting control line EM may be disposed on the same layer as the driving gate electrode G1 and / or the light-emitting control gate electrode G6. For example, the first scan line SL1 and / or the light-emitting control line EM and the driving gate electrode G1 may be disposed on a first gate insulating layer 112 covered by a second gate insulating layer 113.

[0162] The first gate insulating layer 112 may include an inorganic material comprising oxides or nitrides. For example, the first gate insulating layer 112 may include silicon oxide (SiO2) or silicon nitride (SiN). x The materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2). The driving gate electrode G1 can be arranged to overlap with the driving channel region A1 and can be formed from a single layer or multiple layers including Mo, Cu, or Ti.

[0163] A storage capacitor Cst can be formed on the driving gate electrode G1 to overlap with it. The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2. A second gate insulating layer 113 can be disposed between the first electrode CE1 and the second electrode CE2. In this document, the driving gate electrode G1 can be used as both the gate electrode of the driving thin-film transistor T1 and the first electrode CE1 of the storage capacitor Cst. In other words, it can be understood that the driving gate electrode G1 and the first electrode CE1 are formed integrally.

[0164] The second gate insulating layer 113 may include an inorganic material comprising oxides or nitrides. For example, the second gate insulating layer 113 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2).

[0165] The second electrode CE2 may be disposed on the second gate insulating layer 113 to overlap with the first electrode CE1. The second electrode CE2 may include a storage opening SOP. The storage opening SOP is formed by removing a portion of the second electrode CE2, and may have a closed line shape. A first contact hole CNT1 defined in the second gate insulating layer 113 may be disposed in the storage opening SOP. The driving gate electrode G1 and the node connection line 166 may be connected through the first contact hole CNT1. The second electrode CE2 may include molybdenum (Mo), copper (Cu), titanium (Ti), or the like, and may be formed as a single layer or multiple layers. The lower voltage line UPL (shown in Figure 6 or Figure 8 ) may be disposed on the same layer as the second electrode CE2. For example, the lower voltage line UPL and the second electrode CE2 may be disposed on the second gate insulating layer 113 and covered by the first interlayer insulating layer 114.

[0166] The first interlayer insulating layer 114 may be disposed on the second electrode CE2. The first interlayer insulating layer 114 may include an inorganic material including an oxide and / or a nitride. For example, the first interlayer insulating layer 114 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2).

[0167] The compensation semiconductor layer AO3 included in the compensation thin film transistor T3 and the first initialization semiconductor layer AO4 included in the first initialization thin film transistor T4, both of which include an oxide semiconductor, may be disposed on the first interlayer insulating layer 114. The compensation semiconductor layer AO3 may include a compensation source region S3 and a compensation drain region D3 that have conductivity and are spaced apart from each other, and a compensation channel region A3 disposed between the compensation source region S3 and the compensation drain region D3.

[0168] The first initialization semiconductor layer AO4 may include a first initialization source region S4 and a first initialization drain region D4 that have conductivity and are spaced apart from each other, and a first initialization channel region A4 disposed between the first initialization source region S4 and the first initialization drain region D4.

[0169] The compensation semiconductor layer AO3 and the first initialization semiconductor layer AO4 can be formed from Zn oxide-based materials such as Zn oxide, In-Zn oxide, and / or Ga-In-Zn oxide. In some exemplary embodiments of the present invention, the compensation semiconductor layer AO3 and the first initialization semiconductor layer AO4 may include IGZO (In-Ga-Zn-O) semiconductors, ITZO (In-Sn-Zn-O) semiconductors, and / or IGTZO (In-Ga-Sn-Zn-O) semiconductors comprising ZnO having metals such as indium (In), gallium (Ga), and / or tin (Sn).

[0170] The compensated source region S3, compensated drain region D3, first initialization source region S4, and first initialization drain region D4 can be formed by adjusting the carrier concentration of the oxide semiconductor and making the oxide semiconductor conductive. For example, the compensated source region S3 and compensated drain region D3, and the first initialization source region S4 and first initialization drain region D4 can be formed by increasing the carrier concentration of the oxide semiconductor through plasma treatment using hydrogen (H)-based gas, fluorine (F)-based gas, or a combination thereof.

[0171] The first lower gate electrode G3a can be disposed below the compensation semiconductor layer AO3, and the first upper gate electrode G3b can be disposed above the compensation semiconductor layer AO3. In other words, the compensation thin-film transistor T3 can include a dual-gate electrode structure.

[0172] The second lower gate electrode G4a can be disposed below the first initialization semiconductor layer AO4, and the second upper gate electrode G4b can be disposed above the first initialization semiconductor layer AO4. In other words, the first initialization thin-film transistor T4 may include a dual-gate electrode structure.

[0173] The first interlayer insulating layer 114 can be disposed between the first lower gate electrode G3a and the compensation semiconductor layer AO3, and between the second lower gate electrode G4a and the first initialization semiconductor layer AO4. The first lower gate electrode G3a and the second lower gate electrode G4a can be formed of the same material as the second electrode CE2 of the storage capacitor Cst, and are formed on the same layer as the second electrode CE2 of the storage capacitor Cst. For example, the first lower gate electrode G3a, the second lower gate electrode G4a, and the second electrode CE2 can be disposed on the second gate insulating layer 113.

[0174] The third gate insulating layer 115 can be disposed between the compensation semiconductor layer AO3 and the first upper gate electrode G3b, and between the first initialization semiconductor layer AO4 and the second upper gate electrode G4b, and its overall shape gradually tapers in the thickness direction. The first upper gate electrode G3b is disposed to overlap with the compensation channel region A3 and is insulated from the compensation semiconductor layer AO3 by the third gate insulating layer 115. The second upper gate electrode G4b is disposed to overlap with the first initialization channel region A4 and is insulated from the first initialization semiconductor layer AO4 by the third gate insulating layer 115.

[0175] The third gate insulating layer 115 can be formed with the first upper gate electrode G3b and the second upper gate electrode G4b through the same mask process, and in this case, the third gate insulating layer 115 can be formed to have the same shape as the first upper gate electrode G3b and the second upper gate electrode G4b.

[0176] The third gate insulating layer 115 may include an inorganic material comprising oxides and / or nitrides. For example, the third gate insulating layer 115 may include silicon oxide (SiO2), silicon nitride (SiN2), etc. x The materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2). The first upper gate electrode G3b and the second upper gate electrode G4b can be arranged on the third gate insulating layer 115, and can include molybdenum (Mo), copper (Cu), or titanium (Ti), and can be formed by a single layer or multiple layers.

[0177] The boost capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 can be disposed on the first gate insulating layer 112, i.e., on the same layer as the driving gate electrode G1. The fourth electrode CE4 can extend from the first initialization semiconductor layer AO4 or the compensation semiconductor layer AO3. In other words, the fourth electrode CE4 can be provided as an oxide semiconductor and can be disposed on the first interlayer insulating layer 114. A second gate insulating layer 113 and a first interlayer insulating layer 114 can be disposed between the third electrode CE3 and the fourth electrode CE4, and the second gate insulating layer 113 and the first interlayer insulating layer 114 can serve as the dielectric layer of the boost capacitor Cbt.

[0178] The fourth electrode CE4 of the boost capacitor Cbt can be connected to the node connection line 166 through the second contact hole CNT2, and electrically connected to the drive gate electrode G1 through the first contact hole CNT1. Accordingly, when the first scan signal Sn supplied to the first scan line SL1 is turned off, the boost capacitor Cbt can raise the first node N1 (see...). Figure 5 The voltage of the voltage makes it possible to clearly express black grayscale.

[0179] The second interlayer insulating layer 116 can be arranged to cover thin-film transistors formed of oxide semiconductors, such as compensation thin-film transistor T3 and first initialization thin-film transistor T4. The second interlayer insulating layer 116 can be arranged on the first upper gate electrode G3b and the second upper gate electrode G4b, and the data line DL, the drive voltage line PL, the node connection line 166, and the connection electrodes 167, 168 and 169 can be arranged on the second interlayer insulating layer 116.

[0180] The second interlayer insulating layer 116 may comprise an inorganic material containing oxides and / or nitrides. For example, the second interlayer insulating layer 116 may comprise silicon oxide (SiO2), silicon nitride (SiN2), etc. x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2).

[0181] The data line DL, drive voltage line PL, node connection line 166, and connection electrodes 167, 168, and 169 can be formed of highly conductive materials such as metals and / or conductive oxides. For example, the data line DL, drive voltage line PL, node connection line 166, and connection electrodes 167, 168, and 169 can be formed of a single layer or multiple layers including aluminum (Al), copper (Cu), or titanium (Ti). In some exemplary embodiments of the present invention, the data line DL, drive voltage line PL, node connection line 166, and connection electrodes 167, 168, and 169 can be formed of a three-layer structure in which titanium, aluminum, and titanium (Ti / Al / Ti) are arranged sequentially.

[0182] One end of the node connection line 166 can be connected to the drive gate electrode G1 through the first contact hole CNT1. The first contact hole CNT1 can pass through the second interlayer insulating layer 116, the first interlayer insulating layer 114, and the second gate insulating layer 113, and can expose the drive gate electrode G1. A portion of the node connection line 166 can be inserted into the first contact hole CNT1 to be electrically connected to the drive gate electrode G1.

[0183] The first contact hole CNT1 can be spaced apart from the edge of the storage opening SOP in the storage opening SOP of the second electrode CE2, and therefore the node connection line 166 inserted into the first contact hole CNT1 can be insulated from the closed line shape of the defining opening SOP of the second electrode CE2.

[0184] The other end of the node connection line 166 can be connected to, for example, the fourth electrode CE4 of the boost capacitor Cbt or the oxide semiconductor layer of the first initialization semiconductor layer AO4 through the second contact hole CNT2. The second contact hole CNT2 can be connected to the oxide semiconductor layer through the second interlayer insulating layer 116.

[0185] In an exemplary embodiment of the invention, the third connection electrode 169 may be connected to the initialization voltage line VIL via a contact hole passing through the second interlayer insulation layer 116. The third connection electrode 169 is also connected to the shielding electrode 173 via a third contact hole CNT3, and thus the initialization voltage Vint may be provided to the shielding electrode 173.

[0186] refer to Figure 8 The first connection electrode 167 can be connected to the light-emitting control semiconductor layer AS6 through the sixth contact hole CNT6. The sixth contact hole CNT6 can pass through the second interlayer insulating layer 116, the first interlayer insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112, and can expose a portion of the light-emitting control semiconductor layer AS6. A portion of the first connection electrode 167 can be inserted into the sixth contact hole CNT6 to be electrically connected to the light-emitting control semiconductor layer AS6. The first connection electrode 167 can be connected to the pixel electrode 310 to transmit the signal applied by the light-emitting control thin-film transistor T6 to the pixel electrode 310.

[0187] One end (e.g., the first end) of the second connection electrode 168 can be connected to the light-emitting control semiconductor layer AS6 through the fourth contact hole CNT4. The other end (e.g., the second end) of the second connection electrode 168 can be connected to the compensation semiconductor layer AO3 through the fifth contact hole CNT5.

[0188] A first planarization layer 118 is disposed on the data line DL, node connection line 166, drive voltage line PL, and connection electrodes 167, 168, and 169. The first planarization layer 118 may comprise organic materials such as acrylic, benzocyclobutene (BCB), polyimide, and / or hexamethyldisiloxane (HMDSO). Alternatively, the first planarization layer 118 may comprise inorganic materials. The first planarization layer 118 serves as a protective layer covering the thin-film transistors T1 to T7, and the upper portion of the first planarization layer 118 is planarized. The first planarization layer 118 may be formed of a single layer or multiple layers.

[0189] The first portion FL1 and the second portion FL2 of the connecting wiring FL, the shielding electrode 173, and the upper connecting electrode 177 can be disposed on the first planarization layer 118. The first portion FL1 can be disposed to overlap with the driving voltage line PL in the thickness direction. The second portion FL2 can be disposed to overlap with the initialization voltage line VIL in the thickness direction.

[0190] A shielding electrode 173 is arranged on the node connection line 166 to overlap with the node connection line 166. In an exemplary embodiment of the invention, the shielding electrode 173 can be connected to a third connection electrode 169 through a third contact hole CNT3. The third connection electrode 169 can be connected to the initialization voltage line VIL through a contact hole provided in the second interlayer insulation layer 116. Accordingly, an initialization voltage Vint can be applied to the shielding electrode 173.

[0191] The upper connecting electrode 177 can be connected to the first connecting electrode 167 through a contact hole defined in the first planarization layer 118.

[0192] The first portion FL1 and the second portion FL2 of the connecting wiring FL, the shielding electrode 173, and the upper connecting electrode 177 can be formed of a conductive material such as metal. For example, the first portion FL1 and the second portion FL2 of the connecting wiring FL, the shielding electrode 173, and the upper connecting electrode 177 can include aluminum (Al), copper (Cu), and / or titanium (Ti), and can be formed of a single layer or multiple layers.

[0193] The second planarization layer 119 can be arranged to cover the first portion FL1, the second portion FL2, the shielding electrode 173, and the upper connecting electrode 177. The second planarization layer 119 may include organic materials such as acrylic, benzocyclobutene (BCB), polyimide, and / or hexamethyldisiloxane (HMDSO). Alternatively, the second planarization layer 119 may include inorganic materials. The upper portion of the second planarization layer 119 may be planarized, and the second planarization layer 119 may be formed of a single layer or multiple layers.

[0194] An organic light-emitting diode (OLED) including a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 between the pixel electrode 310 and the counter electrode 330 and including a light-emitting layer can be located on the second planarization layer 119.

[0195] The pixel electrode 310 can be connected to the upper connection electrode 177 through a contact hole defined in the second planarization layer 119, and can be connected to the light emission control drain region D6 of the light emission control thin film transistor T6 through the upper connection electrode 177 and the first connection electrode 167.

[0196] In an exemplary embodiment of the present invention, the pixel electrode 310 may overlap with the first portion FL1 or the second portion FL2 of the connecting wiring FL.

[0197] A pixel defining layer 120 may be disposed on the second planarization layer 119. The pixel defining layer 120 defines a pixel PX by having an opening corresponding to each sub-pixel (e.g., an opening that at least exposes the central portion of the pixel electrode 310). Additionally, the pixel defining layer 120 may increase the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310, and thus prevent arcing at the edge of the pixel electrode 310. The pixel defining layer 120 may be formed of an organic material such as polyimide and / or hexamethyldisiloxane (HMDSO).

[0198] The intermediate layer 320 of an organic light-emitting diode (OLED) can include low-molecular-weight materials or high-molecular-weight materials. When low-molecular-weight materials are included, the intermediate layer 320 can have a structure in which hole injection layer (HIL), hole transport layer (HTL), emitter layer (EML), electron transport layer (ETL), electron injection layer (EIL), etc., are stacked in single or composite structures, and can include various organic materials such as copper phthalocyanine (CuPc), N,N-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine (NPB), and / or aluminum tri-8-hydroxyquinoline (Alq3). These layers can be formed by vacuum deposition.

[0199] When the interlayer 320 comprises a high molecular weight material, the interlayer 320 can typically have a structure including an HTL and an EML. In this case, the HTL can comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML can comprise a high molecular weight material such as a polystyrene-based material (PPV) and / or a polyfluorene-based material. The interlayer 320 can be formed by means of screen printing, inkjet printing, laser-induced thermal imaging (LITI), etc.

[0200] However, the intermediate layer 320 is not limited to this and can also have various structures. In addition, the intermediate layer 320 may include a layer integrally formed over the plurality of pixel electrodes 310, or may include a layer patterned to correspond to each of the plurality of pixel electrodes 310.

[0201] The counter electrode 330 can be integrally formed with respect to multiple organic light-emitting diodes (OLEDs) to correspond to multiple pixel electrodes 310.

[0202] Because organic light-emitting diodes (OLEDs) are susceptible to damage from externally introduced moisture or oxygen, a thin-film encapsulation layer or sealing substrate can be disposed on the OLED to cover and protect it. The thin-film encapsulation layer can cover the display area DA and extend beyond it. The thin-film encapsulation layer can include an inorganic encapsulation layer containing at least one inorganic material and an organic encapsulation layer containing at least one organic material. In some exemplary embodiments of the invention, the thin-film encapsulation layer can have a structure in which a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer are stacked. The sealing substrate can be arranged facing the substrate 110 and can be used to seal the non-display area NDA (see [reference]) using sealing members such as sealants and / or glass frits. Figure 1 It is bonded to substrate 110 in the middle.

[0203] Furthermore, spacers to prevent the mask from being imprinted can be further arranged on the pixel defining layer 120. Various functional layers, such as polarizing layers for reducing external light reflection, black matrices, color filters, and / or touchscreen layers with touch electrodes, can be provided on the thin-film encapsulation layer.

[0204] In the display device 1 according to an exemplary embodiment of the present invention, there is a reference... Figure 6 Multiple pixel circuits with the same shape can be arranged along a first direction (e.g., DR1 direction) and a second direction (e.g., DR2 direction). In another exemplary embodiment of the invention, the pixel circuits included in the display device can be arranged in a symmetrical shape with adjacent pixel circuits. When the pixel circuits included in the display device have symmetrical shapes, vertical crosstalk between the data lines of the first pixel circuit and the scan lines of the second pixel circuit adjacent to the first pixel circuit can be prevented.

[0205] Figure 9 This is a cross-sectional view of a pixel circuit of a display device according to an exemplary embodiment of the present invention. Figure 9 In, with Figure 7 The same reference numerals in the accompanying drawings may refer to the same components, and therefore, their redundant descriptions will be omitted.

[0206] refer to Figure 9A display device according to an exemplary embodiment of the present invention includes a substrate 110, a first thin-film transistor (e.g., a driving thin-film transistor T1) including a silicon semiconductor (e.g., a driving semiconductor layer AS1), a second thin-film transistor (e.g., a first initialization thin-film transistor T4) including an oxide semiconductor (e.g., a first initialization semiconductor layer AO4), a driving voltage line PL extending in a first direction (e.g., the DR1 direction) in a display area DA, a data line DL spaced apart from the driving voltage line PL, and a connection wiring FL connecting the data line DL to a pad portion PADA. In this document, the connection wiring FL may include a first portion FL1 extending in the first direction (e.g., the DR1 direction) and a second portion FL2 extending in a second direction (e.g., the DR2 direction), and the first portion FL1 may overlap with the driving voltage line PL.

[0207] According to this exemplary embodiment of the present invention, the initialization voltage line VIL can be disposed on the second gate insulating layer 113. For example, the initialization voltage line VIL can be disposed between the second gate insulating layer 113 and the first interlayer insulating layer 114. For example, the second lower gate electrode G4a and the second electrode CE2 of the storage capacitor Cst can be disposed on the same layer. In addition, the contact hole connecting the initialization voltage line VIL to the third connection electrode 169 can penetrate the first interlayer insulating layer 114 and the second interlayer insulating layer 116.

[0208] In an exemplary embodiment of the present invention, the third electrode CE3 of the boost capacitor Cbt can be provided as part of the first scan line SL1 and can be connected to the switch gate electrode G2. Accordingly, the third electrode CE3 of the boost capacitor Cbt can be integrally formed with the first scan line SL1. In this case, the first scan line SL1 can be non-overlapping with the initialization voltage line VIL in the thickness direction.

[0209] Figure 10 This is a cross-sectional view of a pixel circuit of a display device according to an exemplary embodiment of the present invention. Figure 10 In, and reference Figure 9 The same reference numerals in the accompanying drawings may refer to the same components, and therefore, redundant descriptions will be omitted.

[0210] refer to Figure 10According to an exemplary embodiment of the present invention, a display device includes a substrate 110, a first thin-film transistor comprising a silicon semiconductor, a second thin-film transistor comprising an oxide semiconductor, a driving voltage line PL extending in a display region DA in a first direction (e.g., DR1 direction), a data line DL spaced apart from the driving voltage line PL, and a connection wiring FL connecting the data line DL to a pad portion PADA. In this document, the connection wiring FL may include a first portion FL1 extending in the first direction (e.g., DR1 direction) and a second portion FL2 extending in a second direction (e.g., DR2 direction), and the first portion FL1 may overlap with the driving voltage line PL.

[0211] In an exemplary embodiment of the present invention, the data line DL and the drive voltage line PL can be arranged on the first planarization layer 118. Accordingly, the data line DL and the drive voltage line PL can be arranged on the same layer as the shielding electrode 173. The second planarization layer 119 can be arranged to cover the data line DL, the drive voltage line PL, and the shielding electrode 173.

[0212] In an exemplary embodiment of the present invention, the first portion FL1 and / or the second portion FL2 of the connecting wiring FL can be arranged on the second planarization layer 119.

[0213] In an exemplary embodiment of the present invention, the third planarization layer 119-1 may be arranged to cover the first portion FL1 and / or the second portion FL2 of the connection wiring FL. The third planarization layer 119-1 may comprise organic materials such as acrylic, benzocyclobutene (BCB), polyimide, and / or hexamethyldisiloxane (HMDSO). Alternatively, the third planarization layer 119-1 may comprise inorganic materials. The upper portion of the third planarization layer 119-1 is planarized. The third planarization layer 119-1 may be formed of a single layer or multiple layers.

[0214] The display element, including the pixel electrode 310, can be arranged on the third planarization layer 119-1.

[0215] Figure 11A This is a schematic layout diagram of the positions of a plurality of thin-film transistors and capacitors arranged in the first pixel circuit and the second pixel circuit of a display device according to an exemplary embodiment of the present invention. Figure 11B This is a layout diagram of a portion of the wiring of a display device according to an exemplary embodiment of the present invention. Figure 12 It is along Figure 11A A schematic cross-sectional view taken from line III-III', and Figure 13 It is along Figure 11A A schematic cross-sectional view taken from line IV-IV'.

[0216] exist Figure 11A , Figure 11B , Figure 12 and Figure 13 In, and reference Figure 6 , Figure 7 and Figure 8 The same reference numerals in the accompanying drawings may refer to the same components, and therefore, redundant descriptions will be omitted.

[0217] refer to Figure 11A A display device according to an exemplary embodiment of the present invention may include a first pixel circuit PC1 and a second pixel circuit PC2. In this case, the first pixel circuit PC1 and the second pixel circuit PC2 may be arranged symmetrically about a first direction (e.g., the DR1 direction). Accordingly, vertical crosstalk between the data line DL of the first pixel circuit PC1 and the scan line of the second pixel circuit PC2 adjacent to the first pixel circuit PC1 can be prevented. The first pixel circuit PC1 and the second pixel circuit PC2 are arranged symmetrically, and therefore, the first pixel circuit PC1 will be described primarily, and the description of the second pixel circuit PC2 will be omitted.

[0218] The first pixel circuit PC1 of the display device according to an exemplary embodiment of the present invention includes a data line DL and a driving voltage line PL extending along a first direction (e.g., DR1 direction), and includes a first scan line SL1, a second scan line SL2, a previous scan line SLp, a next scan line, a light emission control line EM, and an initialization voltage line VIL extending along a second direction (e.g., DR2 direction) intersecting the first direction (e.g., DR1 direction). Furthermore, connection wiring FL for connecting the data line DL to the pad portion PADA can be provided in the display area DA.

[0219] The first pixel circuit PC1 may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, a light emission control thin-film transistor T6, a second initialization thin-film transistor T7, a storage capacitor Cst, and a boost capacitor Cbt.

[0220] In an exemplary embodiment of the present invention, the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the light emission control thin-film transistor T6, and the second initialization thin-film transistor T7 can be provided as thin-film transistors comprising silicon semiconductors.

[0221] Furthermore, the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 can be provided as thin-film transistors including oxide semiconductors.

[0222] The semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the light-emitting control thin-film transistor T6, and the second initialization thin-film transistor T7 are arranged on the same layer and comprise the same material. For example, the semiconductor layer may be formed of polycrystalline silicon.

[0223] refer to Figure 11A and Figure 12 The first electrode CE1 of the storage capacitor Cst may extend in a first direction (e.g., the DR1 direction). In this case, the second electrode CE2 may not include a storage opening. The first electrode CE1 can be connected to the first intermediate connection electrode 155 through the first connection contact hole CNT1-1.

[0224] The first intermediate connection electrode 155 can be connected to the first electrode CE1 through the first connection contact hole CNT1-1, and can be connected to the node connection line 166 through the second connection contact hole CNT1-2. The compensation source region S3 can be connected to the driving gate electrode G1 through the first intermediate connection electrode 155 and the node connection line 166. In addition, the node connection line 166 can be connected to the first initialization drain region D4 through the second contact hole CNT2.

[0225] In an exemplary embodiment of the present invention, the initialization voltage line VIL and the previous scan line SLp may overlap each other. In this case, the initialization voltage line VIL may be arranged on the same layer as the lower scan line 143 of the second scan line SL2. The initialization voltage line VIL may be spaced apart from the first scan line SL1.

[0226] refer to Figure 11A and Figure 11B The connecting wiring FL may include a first wiring FL1' extending in a first direction (e.g., DR1 direction) and a second wiring FL2' extending in a second direction (e.g., DR2 direction). The first wiring FL1' and the second wiring FL2' may include protrusions.

[0227] In an exemplary embodiment of the present invention, the first wiring FL1' may overlap with the third connection electrode 169. In this case, the first wiring FL1' may be continuously arranged in the extending direction of the third connection electrode 169. In an exemplary embodiment of the present invention, the first wiring FL1' may overlap with the driving voltage line PL. Furthermore, the first wiring FL1' may overlap with the pixel electrode 310.

[0228] The second wiring FL2' can extend in a second direction (e.g., the DR2 direction). For example, the second wiring FL2' can be arranged to continuously overlap with the light-emitting control line EM.

[0229] In this exemplary embodiment of the invention, the first wiring FL1' and the second wiring FL2' can be arranged on different layers. For example, the first wiring FL1' can be arranged on the same layer as the shielding electrode 173, while the second wiring FL2' can be arranged on the same layer as the upper scan line 153 of the second scan line SL2. For example, the second wiring FL2' can be arranged between the first interlayer insulating layer 114 and the second interlayer insulating layer 116.

[0230] refer to Figure 11A , Figure 11B and Figure 13 The first wiring FL1' and the second wiring FL2' can be connected via contact holes in the display area DA. For example, the first wiring FL1' can be connected to the second intermediate connection electrode 164 via the second intermediate contact hole CNTb. The second intermediate connection electrode 164 can be connected to the second wiring FL2' via the first intermediate contact hole CNTa. Accordingly, data signals can be transmitted from the second wiring FL2' to the first wiring FL1'. In this exemplary embodiment of the invention, the second wiring FL2' connecting the wiring FL can be arranged on the same layer as the upper scan line 153 to overlap with the light emission control line EM, so that space can be utilized. Furthermore, crosstalk with the scan lines can be prevented.

[0231] According to the exemplary embodiments of the present invention described above, a display device is provided in which the driving circuit for driving the display element includes a first thin-film transistor formed of silicon semiconductor and a second thin-film transistor formed of oxide semiconductor, thereby reducing power consumption and causing wiring arranged in the non-display area to be routed to the display area, thereby reducing the area of ​​the non-display area.

[0232] Although exemplary embodiments of the invention have been shown and described above, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: The substrate includes: a display area including display elements and a non-display area including pad portions outside the display area; A first thin-film transistor is disposed in the display area and includes: a first semiconductor layer comprising silicon semiconductor and a first gate electrode insulated from the first semiconductor layer; A first insulating layer covers the first gate electrode; The second thin-film transistor is disposed on the first insulating layer and includes: a second semiconductor layer comprising an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer; A second insulating layer covers the second gate electrode; A first voltage line extends in a first direction on the second insulating layer; The data line is spaced apart from the first voltage line; and The connection wiring in the display area connects the data line to the pad portion. The connecting wiring includes a first portion extending in the first direction and a second portion extending in a second direction intersecting the first direction. Wherein, the first portion overlaps with the first voltage line, and The display device further includes a second voltage line that overlaps with the second portion, extends in the second direction, and is disposed on the first insulating layer.

2. The display device according to claim 1, wherein, The first portion includes a first protrusion that protrudes in the second direction and overlaps with the second voltage line.

3. The display device according to claim 1, wherein, The second thin-film transistor further includes a third gate electrode, which is disposed under the second semiconductor layer to overlap with the second semiconductor layer.

4. The display device according to claim 3, wherein, The second voltage line and the third gate electrode are arranged on the same layer.

5. The display device according to claim 1, wherein, The second portion includes a second protrusion that protrudes in the first direction and overlaps with the first voltage line.

6. The display device according to claim 1, further comprising a first planarization layer between the first voltage line and the connection wiring.

7. A display device, comprising: A substrate includes a display area and a non-display area, wherein the non-display area includes pad portions outside the display area; A first thin-film transistor is disposed in the display area and includes: a first semiconductor layer comprising silicon semiconductor and a first gate electrode insulated from the first semiconductor layer; A first insulating layer covers the first gate electrode; The second thin-film transistor is disposed on the first insulating layer and includes: a second semiconductor layer comprising an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer; A second insulating layer covers the second gate electrode; A first voltage line extends in a first direction and is disposed on the second insulating layer; The first wiring extends in the first direction and is adjacent to the first voltage line; A first signal line extends in a second direction intersecting the first direction, wherein the first signal line and the first gate electrode are arranged on the same layer; A second wiring overlaps with the first signal line and extends in the second direction; and The data cable extends in the first direction. The first wiring is connected to the second wiring through a contact hole in the display area, and The data line is connected to the pad portion via the first wiring and the second wiring.

8. The display device according to claim 7, further comprising: The first connecting electrode is disposed on the first insulating layer; and The second connecting electrode is connected to the first connecting electrode through the first contact hole and is disposed on the second insulating layer. The first gate electrode is connected to the first connection electrode through the second contact hole, and The second connection electrode is connected to the second semiconductor layer through a third contact hole.

Images