Display device

Abstract

A display device is provided, including: a substrate including a display area and a transmission area surrounding the display area; a plurality of display elements located in the display area; a plurality of first horizontal lines and a plurality of second horizontal lines each extending in a first direction and spaced apart from each other, and the transmission area is located between the plurality of first horizontal lines and the plurality of second horizontal lines; a plurality of first vertical lines and a plurality of second vertical lines each extending in a second direction intersecting the first direction and spaced apart from each other, and the transmission area is located between the plurality of first vertical lines and the plurality of second vertical lines; and a first connection line connecting at least one of the plurality of first vertical lines to at least one of the plurality of second vertical lines and going around the transmission area, wherein the first connection line is located on the same layer as at least one of the plurality of first horizontal lines.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0104984, filed on August 27, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Some aspects of example embodiments relate to a display device. Background Technology

[0003] Recently, the use of display devices has become more diversified. As display devices have become thinner and lighter, their application range has gradually expanded.

[0004] Furthermore, with technological advancements, the area occupied by the display region of a display device can be continuously increased, and functions that can be combined with or associated with the display device can be added. In order to increase or maintain a relatively large display area while adding various functions, some example embodiments may include a display device having an area within the display region for adding various functions without displaying images.

[0005] The information disclosed in this background section is only for enhancing the understanding of the background, and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0006] Some aspects of example embodiments relate to a display device, for example, to a display device in which the display panel includes a transmissive region.

[0007] To increase functionality that can be combined or associated with a display device, one or more example embodiments include a display panel that includes a transmissive area in which a camera, sensor, etc., can be arranged, and a display device that includes the display panel.

[0008] One or more example embodiments include display panels and display devices that may have a relatively reduced area occupied by wiring arranged in rows around the transmissive region.

[0009] However, it should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for the purpose of limiting disclosure.

[0010] Other aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosed example embodiments given.

[0011] According to some example embodiments, a display device includes: a substrate including a transmissive region and a display region surrounding the transmissive region; a plurality of display elements disposed in the display region; a plurality of first horizontal lines and a plurality of second horizontal lines extending in a first direction and spaced apart from each other, with the transmissive region located between the plurality of first horizontal lines and the plurality of second horizontal lines; a plurality of first vertical lines and a plurality of second vertical lines extending in a second direction intersecting the first direction and spaced apart from each other, with the transmissive region located between the plurality of first vertical lines and the plurality of second vertical lines; and a first connecting line connecting at least one of the plurality of first vertical lines to at least one of the plurality of second vertical lines and circling around the transmissive region, wherein the first connecting line is disposed on a first layer having the same layer as the layer on which at least one of the plurality of first horizontal lines is disposed.

[0012] According to some example embodiments, the display device may further include: a second connecting line that connects at least one of a plurality of first vertical lines to at least one of a plurality of second vertical lines and runs around the transmissive region, wherein the second connecting line may be arranged on a second layer different from the first layer.

[0013] According to some example embodiments, the first connecting line and the second connecting line can be respectively configured as multiple first connecting lines and multiple second connecting lines, and the multiple first connecting lines and multiple second connecting lines can be alternately arranged around the transmission area.

[0014] According to some example embodiments, the first connecting line can be connected to at least one of a plurality of first vertical lines through a contact hole.

[0015] According to some example embodiments, the display device may further include: a bridging metal that connects the first connecting line to at least one of a plurality of first vertical lines, wherein the bridging metal can be connected to the first connecting line through a first contact hole, and the bridging metal can be connected to at least one of the plurality of first vertical lines through a second contact hole.

[0016] According to some example embodiments, the display device may further include: a third horizontal line extending from the display area in a first direction and circling around the transmissive area, wherein the third horizontal line may be arranged on a different layer than the first layer.

[0017] According to some example embodiments, at least one of the plurality of first horizontal lines can be connected to at least one of the plurality of second horizontal lines via a horizontal connecting line.

[0018] According to some example embodiments, the display device may further include: an electrode layer surrounding the transmissive region and superimposed with a first connection line; a horizontal driving voltage line extending in a first direction; and a vertical driving voltage line extending in a second direction, wherein the horizontal driving voltage line and the vertical driving voltage line may be connected to the electrode layer.

[0019] According to some example embodiments, the display device may further include: a second connecting line that connects at least one of a plurality of first vertical lines to at least one of a plurality of second vertical lines and runs around the transmissive region, wherein the electrode layer is at least partially superimposed on the first connecting line and the second connecting line.

[0020] According to some example embodiments, the display device may further include: a third connecting line that connects at least one of the plurality of first vertical lines to at least one of the plurality of second vertical lines and runs around the transmissive region, wherein the third connecting line may be arranged on a third layer on which the layer having at least one of the plurality of first vertical lines connected to the third connecting line is arranged is the same layer.

[0021] According to some example embodiments, the display device may further include: a fourth connecting line that connects at least one of a plurality of first vertical lines to at least one of a plurality of second vertical lines and runs around the transmissive region, wherein the fourth connecting line may be arranged on a fourth layer different from the third layer.

[0022] According to some example embodiments, the display device may further include: a horizontal connecting line extending in a first direction and circling around the transmissive region, wherein the horizontal connecting line can connect at least one of a plurality of first horizontal lines to at least one of a plurality of second horizontal lines.

[0023] According to some example embodiments, the display device may further include: a second connecting line that connects at least one of a plurality of first vertical lines to at least one of a plurality of second vertical lines and runs around the transmissive region, wherein at least one of the plurality of first horizontal lines connected to the horizontal connecting line may be arranged on a second layer different from the first layer, and the second connecting line may be arranged on the second layer.

[0024] According to some example embodiments, a display device includes: a substrate including a transmissive region, a display region surrounding the transmissive region, and a non-display region located between the transmissive region and the display region; a plurality of display elements arranged in the display region; a plurality of first horizontal lines and a plurality of second horizontal lines, all extending in a first direction and spaced apart from each other, with the transmissive region located between the plurality of first horizontal lines and the plurality of second horizontal lines; a plurality of first vertical lines and a plurality of second vertical lines, all extending in a second direction intersecting the first direction and spaced apart from each other, with the transmissive region located between the plurality of first vertical lines and the plurality of second vertical lines; and a plurality of connecting lines arranged in the non-display region such that at least one of the plurality of first vertical lines is connected to at least one of the plurality of second vertical lines, and including a first connecting line, a second connecting line, a third connecting line, and a fourth connecting line each arranged on different layers, wherein the first connecting line is arranged on a first layer that is the same layer as the layer on which at least one of the plurality of first horizontal lines is arranged.

[0025] According to some example embodiments, a thin-film transistor can be arranged in a display area, the thin-film transistor including a first semiconductor layer and a first gate electrode, and a first interconnect line can be arranged on the same layer as the layer on which the first gate electrode is arranged.

[0026] According to some example embodiments, a storage capacitor may be arranged in a display area. The storage capacitor includes a first electrode and a second electrode. The first electrode is arranged on the same layer as a layer on which a first gate electrode is arranged. The second electrode is arranged above the first electrode. A second connecting line may be arranged on the same layer as a layer on which a second electrode is arranged.

[0027] According to some example embodiments, the third connecting line can be arranged on a third layer that is the same layer as the layer on which at least one of the multiple first vertical lines is arranged.

[0028] According to some example embodiments, the third connecting line may have regions that overlap with a portion of the first connecting line and a portion of the second connecting line, respectively, and a region located between the first connecting line and the second connecting line in a plan view.

[0029] According to some example embodiments, the fourth connecting line may have regions that overlap with a portion of the first connecting line and a portion of the second connecting line, respectively, and a region located between the first connecting line and the second connecting line in a plan view.

[0030] According to some example embodiments, the plurality of connecting lines may further include a fifth connecting line, which is arranged on a different layer than the layer on which the first connecting line, the second connecting line, the third connecting line and the fourth connecting line are arranged. Attached Figure Description

[0031] The above and other aspects, features, and characteristics of certain embodiments disclosed will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 This is a perspective view of a display device according to some example embodiments;

[0033] Figures 2A to 2D This is a cross-sectional view of a display device according to some example embodiments;

[0034] Figures 3A to 3C This is a cross-sectional view of a display device according to some example embodiments;

[0035] Figure 4 This is a plan view of a display panel according to some example embodiments;

[0036] Figure 5A and Figure 5B This is an equivalent circuit diagram of a pixel of a display device according to some example embodiments;

[0037] Figures 6A to 6C It is along Figure 4 A cross-sectional view of the display device taken by line I-I';

[0038] Figure 7 It is a plan view of the wiring around the transmission area according to some example embodiments;

[0039] Figure 8A and Figure 8B It is along Figure 7 A cross-sectional view of the wiring cut off by line II-II';

[0040] Figure 9A This is a plan view of a portion of a display device according to some example embodiments;

[0041] Figure 9B This is a plan view of a portion of a display device according to some example embodiments;

[0042] Figure 10 This is a plan view of a portion of a display device according to some example embodiments;

[0043] Figure 11 It is along Figure 10 A sectional view taken from line III-III';

[0044] Figure 12 This is a plan view of a portion of a display device according to some example embodiments;

[0045] Figure 13 It is along Figure 12 A sectional view taken by line IV-IV';

[0046] Figure 14 A plan view of a portion of a display device according to some example embodiments; and

[0047] Figure 15 This is a plan view of a portion of a display device according to some example embodiments. Detailed Implementation

[0048] Reference will now be made in more detail to some exemplary embodiments illustrated in the accompanying drawings, in which the same reference numerals throughout refer to the same elements. In this respect, these exemplary embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, exemplary embodiments are described below only by reference to the accompanying drawings to explain aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] In the following, exemplary embodiments according to this disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are given to the same or corresponding elements, and repeated descriptions thereof are omitted.

[0050] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another.

[0051] As used herein, unless the context clearly indicates otherwise, the singular forms “a (kind)” and “the” are also intended to include the plural forms.

[0052] It will also be understood that the terms “comprising” and / or “including” as used herein indicate the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0053] It will be understood that when a layer, region, or component is referred to as being "formed" "on" another layer, region, or component, that layer, region, or component may be formed directly or indirectly on said other layer, region, or component. That is, for example, intermediate layers, regions, or components may exist. Furthermore, this application is not limited to this; for example, when described as being "on" a side, right side, or left side, it may mean being on a side, right side, or left side, etc.

[0054] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0055] When an embodiment can be implemented differently, the specific process sequence may be performed differently than the order in which it is described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0056] It will be understood that when a layer, region, or component is referred to as being "connected to" another layer, region, or component, that layer, region, or component may be "directly connected" to said other layer, region, or component and / or may be "indirectly connected" to said other layer, region, or component, with an intermediate layer, region, or component situated between them. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected to" another layer, region, or component, that layer, region, or component may be "directly electrically connected" to said other layer, region, or component and / or may be "indirectly electrically connected" to said other layer, region, or component, with an intermediate layer, region, or component situated between them.

[0057] Figure 1 This is a perspective view of a display device 1 according to some example embodiments.

[0058] Reference Figure 1 The display device 1 includes a light-emitting display area DA and a non-light-emitting non-display area NDA. The display device 1 can display an image by utilizing light emitted from a plurality of pixels arranged in the display area DA.

[0059] Display device 1 includes a transmissive region TA. The transmissive region TA may be completely or partially surrounded by the display region DA. That is, according to some example embodiments, the transmissive region TA may be completely surrounded by the display region DA and located within the display region DA. According to some embodiments, the transmissive region TA may be only partially surrounded by the display region DA, such that the transmissive region TA is adjacent to the display region DA in a portion and is partially located outside the display region DA. The transmissive region TA corresponds to an area that can transmit (or receive) light and / or sound output from electronic components to the outside (e.g., external electronic components) or propagating from the outside toward electronic components. According to some example embodiments, when light passes through the transmissive region TA, the transmittance may be 50% or more, 70% or more, 75% or more, 80% or more, 85% or more, or 90% or more.

[0060] The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 is disposed between the transmissive area TA and the display area DA. The first non-display area NDA1 may surround the transmissive area TA. According to some example embodiments, the pixels for displaying the image are not arranged in the first non-display area NDA1, but the wiring for transmitting electrical signals to the pixels may be arranged in the first non-display area NDA1, with the pixels spaced apart from each other and the transmissive area TA located between the pixels.

[0061] The second non-display area NDA2 extends along the edge of the display device 1 and surrounds the display area DA. The pixels of the displayed image are not arranged in the second non-display area NDA2, but various types of wiring, built-in circuit units, etc., can be arranged in the second non-display area NDA2.

[0062] Each pixel provided to the display device 1 may include a light-emitting diode (LED) as a display element capable of emitting light of a set color or a predetermined color. The LED may include an organic LED containing an organic material as an emission layer. Optionally, the LED may include an inorganic LED. Optionally, the LED may include a quantum dot as an emission layer. According to some example embodiments, the display device 1 may include a liquid crystal display device.

[0063] In the following description, for ease of description, the display device 1 is described as an example of an organic light-emitting display device that includes organic light-emitting diodes.

[0064] According to some example embodiments, such as Figure 1 As shown, the transmissive region TA can be arranged in the central portion of the display area DA in the width direction of the display device 1, and in the top of the display area DA in the longitudinal direction of the display device 1. According to some example embodiments, the transmissive region TA can be arranged in the central portion of the display area DA in the longitudinal direction of the display device 1, or offset at the bottom of the display area DA. Optionally, the transmissive region TA can be offset on the left or right side in the width direction of the display device 1.

[0065] The shape of the display area DA can be circular, elliptical, or polygonal (such as triangular or pentagonal). The size, shape, number, and position of the transmission area TA can be varied.

[0066] Figures 2A to 2D It is based on some example embodiments along Figure 1 The cross-sectional view of display device 1 taken by line A-A'.

[0067] Reference Figure 2AThe display device 1 may include a display panel 10 and a component 20. The display panel 10 includes display elements, and the component 20 corresponds to the transmission area TA.

[0068] The display panel 10 may include a substrate 100, an encapsulation substrate 300, and a display element layer 200 disposed between the substrate 100 and the encapsulation substrate 300, the encapsulation substrate 300 being an encapsulation member facing the substrate 100. A sealing material 350 (sealant) may be disposed between the substrate 100 and the encapsulation substrate 300, the sealing material 350 covering the lateral sides of the display element layer 200. Although in Figure 2A The diagram shows the sealing material 350 arranged on two opposite sides of the transmission region TA, but it should be understood that when viewed in a direction perpendicular to the main surface of the substrate 100, the transmission region TA can be completely surrounded by the sealing material 350.

[0069] Substrate 100 may include glass or polymer resin. The polymer resin may include polymer resins such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Substrate 100 comprising polymer resin may be flexible, rollable, or bendable. Substrate 100 may have a multilayer structure including an organic layer and an inorganic layer, the organic layer comprising the polymer resin. Encapsulation substrate 300 may include glass or polymer resin.

[0070] Display element layer 200 may include a circuit layer, an organic light-emitting diode (OLED), and an insulating layer IL located between the circuit layer and the OLED. The circuit layer includes a thin-film transistor (TFT), and the OLED is a display element connected to the TFT. The TFT and the OLED connected thereto may be arranged in a display area DA, and some wirings WL of the display element layer 200 may be located in a first non-display area NDA1. The wirings WL can provide signals or voltages (e.g., set or predetermined signals or voltages) to pixels spaced apart from each other, and a transmissive area TA is located between the pixels spaced apart from each other. Although in Figure 2A The diagram shows that the wiring WL is not superimposed on the sealing material 350 in the first non-display area NDA1, but according to some example embodiments, some of the sealing material 350 may be arranged on the wiring WL.

[0071] The display panel 10 may include through holes 10H corresponding to the transmissive region TA. For example, the substrate 100 and the encapsulation substrate 300 may each include through holes 100H and 300H, respectively, both corresponding to the transmissive region TA. The display element layer 200 may also include through holes corresponding to the transmissive region TA.

[0072] According to some example embodiments, the input sensing element, the anti-reflective element, and the transmissive window may also be arranged on the display panel 10. The input sensing element senses touch input, and the anti-reflective element includes a polarizer and a delay element or a color filter and a black matrix.

[0073] Component 20 may be located in the transmission region TA. Component 20 may include electronic components that use light or sound. For example, component 20 may be a sensor (such as an infrared sensor that emits and / or receives light), a camera that receives light and captures images, a sensor that outputs and senses light or sound to measure distance or identify fingerprints, a small light that outputs light, or a speaker that outputs sound. Electronic components that use light can use light of various wavelengths, such as visible light, infrared light, and ultraviolet light. Figure 2A When the display panel 10 includes a through hole 10H corresponding to the transmission area TA, light or sound output from electronic components or light or sound received by electronic components can be utilized more effectively.

[0074] and Figure 2A Unlike the display panel 10 which includes a through hole 10H corresponding to the transmission region TA, some components of the display panel 10 may not include through holes. For example, Figure 2B As shown, the packaging substrate 300 includes a through-hole 300H corresponding to the transmission region TA, but the substrate 100 may not include a through-hole. Optionally, as... Figure 2C and Figure 2D As shown, neither the substrate 100 nor the encapsulation substrate 300 may have a through hole corresponding to the transmission region TA. Even as Figures 2B to 2D The substrate 100 shown does not include the through hole 100H, and the portion of the display element layer 200 corresponding to the transmissive region TA can also be removed, thus ensuring the light transmittance of the electronic components. Therefore, in the display device 1 including Figures 2B to 2D In the case of the display panel 10 shown, light-utilizing electronic components can be appropriately used as electronic components.

[0075] like Figure 2D As shown, the display panel 10 may not include the sealing material 350 around the transmissive area TA. Because Figure 2D The display panel 10 does not include through holes corresponding to the transmission region TA in the substrate 100 and the encapsulation substrate 300, so external air will not penetrate into the transmission region TA.

[0076] exist Figures 2A to 2D The component 20 shown can be located inside the through hole 10H so as to overlap with the lateral side of the through hole 10H defining the display panel 10. For example, when viewed in a plan view, the component 20 can be located inside the through hole 10H.

[0077] Component 20 may be another component besides electronic components. According to some example embodiments, when the display device 1 is used as a smartwatch or as an instrument panel for a car, component 20 may be a component such as a clock hand or pointer indicating setting information or predetermined information (e.g., vehicle speed). Optionally, component 20 may include components such as accessories that enhance the aesthetics of the display panel 10.

[0078] Figures 3A to 3C It is based on some example embodiments along Figure 1 The cross-sectional view of display device 1 taken by line A-A'.

[0079] Reference Figure 3A , and reference Figure 2A Similar to the described display device 1, the display device 1 may include a display panel 10 and components 20. Furthermore, according to some example embodiments, the display device 1 may also include an input sensing element for sensing touch input, an anti-reflective element, a window, etc., arranged on the display panel 10.

[0080] Reference above Figure 2A The display panel 10 described below, which includes a sealing material 350 and an encapsulation substrate 300 as an encapsulation member, differs from the display panel 10 described in this embodiment. The display panel 10 may include a thin-film encapsulation layer 300' as an encapsulation member. In this case, the flexibility of the display panel 10 can be further improved. Hereinafter, for ease of description, the differences will be primarily described.

[0081] The thin-film encapsulation layer 300' may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Regarding this, Figure 3A The diagram shows a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0082] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include silicon oxide (SiO2) and silicon nitride (SiN). x The organic encapsulation layer 320 may include at least one inorganic insulating material selected from silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc peroxide (ZnO2). The organic encapsulation layer 320 may include a polymeric material. The polymeric material may include acrylic resins, epoxy resins, polyimide, and polyethylene.

[0083] The display panel 10 may include through holes 10H corresponding to the transmissive region TA. For example, the substrate 100 and the thin-film encapsulation layer 300' may each include through holes 100H and 300H' corresponding to the transmissive region TA, respectively. The first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330, and the organic encapsulation layer 320 may each include holes corresponding to the transmissive region TA. The size of the holes in the organic encapsulation layer 320 may be larger than the size of the holes in the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, so the first inorganic encapsulation layer 310 may contact the second inorganic encapsulation layer 330 around the transmissive region TA.

[0084] With including Figure 3A The display panel 10 corresponding to the through hole 10H in the transmission area TA is different; the display panel 10 may not include the through hole. For example... Figure 3B As shown, the thin-film encapsulation layer 300' includes a through-hole 300H' corresponding to the transmission region TA, but the substrate 100 may not include the through-hole. Optionally, as... Figure 3C As shown, neither the substrate 100 nor the thin-film encapsulation layer 300' may include a through-hole corresponding to the transmission region TA. Even as Figure 3B and Figure 3C The substrate 100 shown does not include the through hole 100H, and the portion of the display element layer 200 corresponding to the transmission region TA can also be removed, thus ensuring the light transmittance of the electronic element as component 20 as described above.

[0085] like Figure 3C As shown, when the thin-film encapsulation layer 300' does not include through holes, at least one inorganic encapsulation layer and at least one organic encapsulation layer can both cover portions of the substrate 100 in the transmissive region TA. In this case, the portion of the display element layer 200 corresponding to the transmissive region TA between the substrate 100 and the thin-film encapsulation layer 300' can be removed. Although in Figure 3A The diagram shows that the entire insulating layer IL corresponding to the transmission region TA has been removed, but some layers in the multilayer insulating layer IL can be removed.

[0086] Component 20 can be located inside the through hole 10H, for example, it can be as follows: Figure 3A The through-hole 100H shown is located inside the through-hole 200H of the substrate 100 and the display element layer 200, or it can be as follows: Figure 3B The through hole 200H shown is located inside the display element layer 200 so as to overlap with the lateral side of the defining through hole 10H of the display panel 10.

[0087] Although Figures 2A to 2D The diagram shows that the display panel 10 includes only the encapsulation substrate 300 as an encapsulation component and... Figures 3A to 3CThe diagram shows a display panel 10 comprising only a thin-film encapsulation layer 300' as an encapsulation component; however, according to some example embodiments, the display panel 10 may employ both an encapsulation substrate 300 and a thin-film encapsulation layer 300'. For example, the display panel 10 may include... Figures 2A to 2D One of the packaging substrates 300 shown in the figure and Figures 3A to 3C One of the two thin-film encapsulation layers 300' shown in the figure.

[0088] Figure 4 This is a plan view of the display panel 10 according to some example embodiments.

[0089] Reference Figure 4 The display panel 10 includes a plurality of pixels P arranged in a display area DA. Each of the pixels P may include a display element such as an organic light-emitting diode (OLED). Each pixel P may emit, for example, red, green, blue, or white light through the OLED. In this specification, pixel P may be a sub-pixel that emits red, green, blue, or white light as described above. The display area DA may be referred to... Figures 2A to 3C The encapsulated components described are covered and protected from external contamination such as air or moisture.

[0090] The transmissive region TA can be arranged at the center of the display region DA in the width direction (first direction (X direction)) and partially surrounded by the display region DA. Therefore, a plurality of pixels P can be arranged around the transmissive region TA. The plurality of pixels P can surround at least a portion of the transmissive region TA. A first non-display region NDA1, where no pixels P are arranged, is located between the transmissive region TA and the display region DA. Wiring can be arranged around the first non-display region NDA1, and the wiring applies signals or power (e.g., set or predetermined signals or power) to the pixels P separated from each other around the transmissive region TA. Furthermore, some wiring can be disconnected even with the transmissive region TA in between.

[0091] Each pixel P can be electrically connected to a built-in circuit arranged in the second non-display area NDA2. The first scan drive circuit 110, the second scan drive circuit 120, the terminal unit 140, the data drive circuit 150, the first power line 160, and the second power line 170 can be arranged in the second non-display area NDA2.

[0092] The first scan driving circuit 110 can supply a scan signal to each pixel P via a scan line SL. The first scan driving circuit 110 can also provide an emission control signal to each pixel P via an emission control line EL. The second scan driving circuit 120 can be parallel to the first scan driving circuit 110, with a display area DA located between them. Some of the pixels P arranged in the display area DA can be electrically connected to the first scan driving circuit 110, and the remaining pixels of the pixels P can be connected to the second scan driving circuit 120.

[0093] The first scan drive circuit 110 can be connected to the second scan drive circuit 120 via driver lines DRL. Multiple driver lines DRL can be configured. Each driver line can transmit gate drive high voltage, gate drive low voltage, start signal, etc. Here, the gate drive high voltage and gate drive low voltage can be voltages used to drive the first scan drive circuit 110 and the second scan drive circuit 120. Because the first scan drive circuit 110 is connected to the second scan drive circuit 120 via driver lines DRL, the brightness deviation of the display device 1 can be minimized or reduced.

[0094] Terminal unit 140 may be disposed on one side of substrate 100. Terminal unit 140 may be exposed without being covered by an insulating layer and electrically connected to printed circuit board PCB. Terminal PCB-P of printed circuit board PCB may be electrically connected to terminal unit 140 of display panel 10. Printed circuit board PCB transmits power or controller signals to display panel 10. Control signals generated by controller may be transmitted through printed circuit board PCB to first scan drive circuit 110 and second scan drive circuit 120. Controller may provide drive voltage ELVDD (also referred to as first power voltage) and common voltage ELVSS (see below) through first line 161 and second line 171, respectively. Figure 5A and Figure 5B ).

[0095] A driving voltage ELVDD can be provided to each pixel P through a driving voltage line PL connected to the first power line 160, and a common voltage ELVSS can be provided to the counter electrode of pixel P connected to the second power line 170. The second power line 170 has a loop shape with an open side and can partially surround the display area DA.

[0096] The data drive circuit 150 is electrically connected to the data line DL. The data signal from the data drive circuit 150 can be provided to each pixel P via the connection line 151 connected to the terminal unit 140 and the data line DL connected to the connection line 151. Although in Figure 4The diagram shows the data driver circuit 150 arranged on a printed circuit board (PCB), but according to some example embodiments, the data driver circuit 150 may be arranged on the substrate 100. For example, the data driver circuit 150 may be arranged between the terminal unit 140 and the first power line 160.

[0097] The first power line 160 can be connected to the first line 161 and can receive the drive voltage ELVDD from the controller connected to the terminal unit 140. The first power line 160 can be arranged to correspond to all pixels P arranged in the first direction and can transmit the drive voltage ELVDD to each column of pixels P.

[0098] According to some example embodiments, a first scan line SLa on the left side of the transmission region TA may be spaced apart from a second scan line SLb collinear with the first scan line SLa on the right side of the transmission region TA, and the transmission region TA is located between the first scan line SLa and the second scan line SLb. Furthermore, a first emission control line ELa on the left side of the transmission region TA may be spaced apart from a second emission control line ELb collinear with the first emission control line ELa on the right side of the transmission region TA, and the transmission region TA is located between the first emission control line ELa and the second emission control line ELb.

[0099] In this scenario, the lengths of the first scan line SLa and the second scan line SLb arranged on the same line (e.g., collinear) can be substantially the same, and the lengths of the first emission control line ELa and the second emission control line ELb arranged on the same line can also be substantially the same. Because the lengths of the first scan line SLa and the second scan line SLb are substantially the same, the brightness of the pixels P arranged on the left and right sides of the transmission region TA can be relatively uniform. Therefore, the first scan line SLa may not be connected to the second scan line SLb. Similarly, the first emission control line ELa may not be connected to the second emission control line ELb.

[0100] The first scan line SLa and the first emission control line ELa can be connected to the first scan drive circuit 110 and can extend in the (+) first direction (X direction). The second scan line SLb and the second emission control line ELb can be connected to the second scan drive circuit 120 and can extend in the (-) first direction ((-)X direction).

[0101] Figure 5A and Figure 5B This is an equivalent circuit diagram of a pixel P of a display device 1 according to some example embodiments.

[0102] Reference Figure 5AEach pixel P includes a pixel circuit PC and an organic light-emitting diode OLED. The pixel circuit PC is connected to the scan line SL and the data line DL, and the organic light-emitting diode OLED is connected to the pixel circuit PC.

[0103] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and in response to the scan signal Sn input through the scan line SL, it transmits the data signal Dm input through the data line DL to the driving thin-film transistor T1.

[0104] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and stores the voltage corresponding to the difference between the voltage transmitted from the switching thin-film transistor T2 and the first power voltage (or drive voltage) ELVDD supplied to the drive voltage line PL.

[0105] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the organic light-emitting diode (OLED) in response to the voltage stored in the storage capacitor Cst. The OLED can emit light (e.g., with a set or predetermined brightness) by using the driving current.

[0106] Although Figure 5A The image shows a pixel circuit PC comprising two thin-film transistors and a storage capacitor, but according to some example embodiments, the number of thin-film transistors and the number of storage capacitors may vary.

[0107] For example, such as Figure 5B As shown, the pixel circuit PC may include seven thin-film transistors and a storage capacitor.

[0108] Reference Figure 5B Pixel P includes pixel circuitry PC and an organic light-emitting diode (OLED) connected to the pixel circuitry PC. Pixel circuitry PC may include a storage capacitor and multiple thin-film transistors. The thin-film transistors and storage capacitors may be connected to signal lines SL, SL-1, EL, and DL, initialization voltage line VL, and drive voltage line PL.

[0109] Although Figure 5B The diagram illustrates that each pixel P is connected to signal lines SL, SL-1, EL, and DL, initialization voltage line VL, and drive voltage line PL; however, the embodiments are not limited thereto. According to some example embodiments, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, or the drive voltage line PL may be shared by adjacent pixels P.

[0110] The multiple thin-film transistors may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0111] The signal lines include a scan line SL, a previous scan line SL-1, an emission control line EL, and a data line DL. The scan line SL transmits the scan signal Sn. The previous scan line SL-1 transmits the previous scan signal Sn-1 to the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7. The emission control line EL transmits the emission control signal En to the operation control thin-film transistor T5 and the emission control thin-film transistor T6. The data line DL intersects with the scan line SL and transmits the data signal Dm. The drive voltage line PL transmits the drive voltage ELVDD to the drive thin-film transistor T1. The initialization voltage line VL transmits the initialization voltage Vint that initializes the drive thin-film transistor T1 and the pixel electrodes of the organic light-emitting diode (OLED).

[0112] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the first electrode CE1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin-film transistor T1 is connected to the driving voltage line PL through the operation control thin-film transistor T5. The driving drain electrode D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode (or anode) of the organic light-emitting diode (OLED) through the emission control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm based on the switching operation of the switching thin-film transistor T2 (which is turned on or off according to the scan signal Sn supplied by the scan line SL) and drives the driving current I. OLED Supply to organic light-emitting diodes (OLEDs).

[0113] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL, the switching source electrode S2 of the switching thin-film transistor T2 is connected to the data line DL, and the switching drain electrode D2 of the switching thin-film transistor T2 is connected to the driving source electrode S1 of the driving thin-film transistor T1 and simultaneously (or concurrently) connected to the driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 is turned on in response to the scan signal Sn transmitted through the scan line SL and performs a switching operation to transmit the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin-film transistor T1.

[0114] The compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL. The compensation source electrode S3 of the compensation thin-film transistor T3 is connected to the driving drain electrode D1 of the driving thin-film transistor T1 and simultaneously (or concurrently) connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The compensation drain electrode D3 of the compensation thin-film transistor T3 is connected to the first electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and the driving thin-film transistor T1 is diode-connected by electrically connecting the driving gate electrode G1 of the driving thin-film transistor T1 to the driving drain electrode D1.

[0115] The first initialization gate electrode G4 of the first initialization thin-film transistor T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization thin-film transistor T4 is connected to the second initialization drain electrode D7 and the initialization voltage line VL of the second initialization thin-film transistor T7. The first initialization drain electrode D4 of the first initialization thin-film transistor T4 is connected to the first electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin-film transistor T3, and the driving gate electrode G1 of the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and performs an initialization operation that transmits the initialization voltage Vint to the driving gate electrode G1 of the driving thin-film transistor T1, thereby initializing the voltage of the driving gate electrode G1 of the driving thin-film transistor T1.

[0116] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emitter control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the drive voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the drive source electrode S1 of the driving thin film transistor T1 and the switch drain electrode D2 of the switching thin film transistor T2.

[0117] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3. The emission control drain electrode D6 of the emission control thin film transistor T6 is connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0118] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 are simultaneously (or concurrently) turned on in response to the emission control signal En transmitted through the emission control line EL, so as to allow the drive voltage ELVDD to be transmitted to the organic light-emitting diode OLED, and therefore the drive current I OLED It flows through an organic light-emitting diode (OLED).

[0119] The second initialization gate electrode G7 of the second initialization thin-film transistor T7 is connected to the previous scan line SL-1. The second initialization source electrode S7 of the second initialization thin-film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin-film transistor T6 and the pixel electrode of the organic light-emitting diode (OLED). The second initialization drain electrode D7 of the second initialization thin-film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin-film transistor T4 and the initialization voltage line VL. The second initialization thin-film transistor T7 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, thus initializing the pixel electrode of the OLED.

[0120] Although Figure 5B The illustration shows a case where the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are connected to the previous scan line SL-1, but the embodiment is not limited thereto. According to some example embodiments, the first initialization thin-film transistor T4 may be connected to the previous scan line SL-1 and driven in response to the previous scan signal Sn-1, and the second initialization thin-film transistor T7 may be connected to a separate signal line (e.g., the next scan line) and driven in response to a signal transmitted through the separate signal line.

[0121] The second electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light-emitting diode (OLED) is connected to the common voltage ELVSS. Therefore, the OLED can receive a driving current I from the driving thin-film transistor T1. OLED It emits light, thus displaying an image.

[0122] Although Figure 5B The diagram shows that both the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 have dual gate electrodes, but both the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 may have a single gate electrode.

[0123] Figures 6A to 6C This is a cross-sectional view of a portion of the stacked structure of a display device 1 according to some example embodiments.

[0124] Reference Figure 6AThe display device 1 may include a substrate 100, a first thin-film transistor TFT1 and a second thin-film transistor TFT2 disposed on the substrate 100, a storage capacitor Cst, an organic light-emitting diode OLED, and a first wiring WL1, a second wiring WL2 and a third wiring WL3.

[0125] A buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 can reduce or block the penetration of foreign matter or contaminants, such as moisture or outside air, from beneath the substrate 100 and provides a flat surface on the substrate 100. The buffer layer 111 may comprise inorganic materials, organic materials, or organic / inorganic composite materials, such as oxides or nitrides, and may include a single-layer or multi-layer structure comprising inorganic and organic materials. A barrier layer may be further disposed between the substrate 100 and the buffer layer 111, the barrier layer blocking the penetration of outside air.

[0126] The first thin-film transistor (TFT1) may include a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The second thin-film transistor (TFT2) may include a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The first TFT1 can be connected to an organic light-emitting diode (OLED) and can be used as a driving TFT for the OLED. The second TFT2 can be connected to a data line DL and can be used as a switching TFT. Although two TFTs are shown in the figures, the embodiment is not limited to this. The number of TFTs can be 2 to 7. Different modifications can be made.

[0127] The first semiconductor layer A1 and the second semiconductor layer A2 may comprise amorphous silicon or polycrystalline silicon. According to some example embodiments, the first semiconductor layer A1 and the second semiconductor layer A2 may comprise an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). Each of the first semiconductor layer A1 and the second semiconductor layer A2 may comprise a channel region, a source region, and a drain region, the source region and the drain region being doped with impurities.

[0128] The first gate electrode G1 and the second gate electrode G2 can be disposed on the first semiconductor layer A1 and the second semiconductor layer A2, respectively, and the first gate insulating layer 112 is disposed between the first semiconductor layer A1 and the first gate electrode G1, and between the second semiconductor layer A2 and the second gate electrode G2. The first gate electrode G1 and the second gate electrode G2 can include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti) and can be a single layer or multiple layers. For example, each of the first gate electrode G1 and the second gate electrode G2 can be a single layer of Mo.

[0129] The first gate insulating layer 112 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2 or ZnO2.

[0130] A second gate insulating layer 113 may be provided to cover the first gate electrode G1 and the second gate electrode G2. The second gate insulating layer 113 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2 or ZnO2.

[0131] The first electrode CE1 of the storage capacitor Cst can be stacked with the first thin-film transistor TFT1. For example, the first gate electrode G1 of the first thin-film transistor TFT1 can be used as the first electrode CE1 of the storage capacitor Cst.

[0132] The second electrode CE2 of the storage capacitor Cst is stacked with the first electrode CE1, and the second gate insulating layer 113 is located between the second electrode CE2 and the first electrode CE1. In this case, the second gate insulating layer 113 can serve as the dielectric layer of the storage capacitor Cst. The second electrode CE2 may include a conductive material comprising Mo, Al, Cu, and Ti, and may comprise a single layer or multiple layers comprising the above materials. For example, the second electrode CE2 may include a single layer of Mo or a multilayer of Mo / Al / Mo.

[0133] The first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 can be disposed on the interlayer insulating layer 114. The first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 can comprise conductive materials containing Mo, Al, Cu, and Ti, and can comprise a single layer or multiple layers containing the above materials. For example, the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 can have a Ti / Al / Ti multilayer structure.

[0134] The first planarization layer 116 can be located on the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2. The organic light-emitting diode (OLED) can be located on the first planarization layer 116.

[0135] The first planarization layer 116 may have a flat top surface, allowing the pixel electrode 210 to be formed flat. The first planarization layer 116 may comprise a single layer or multiple layers containing organic materials. The first planarization layer 116 may comprise general polymers (such as benzocyclobutene (BCB), polyimide, polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0136] An organic light-emitting diode (OLED) is disposed on a first planarization layer 116. The OLED includes a pixel electrode 210, an intermediate layer 220, and a counter electrode 230, wherein the intermediate layer 220 includes an organic emitting layer.

[0137] A via is disposed in the first planarization layer 116, exposing one of the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TFT1. The pixel electrode 210 can pass through the via and be electrically connected to the first thin-film transistor TFT1 by contacting the first source electrode S1 or the first drain electrode D1.

[0138] Pixel electrode 210 may include a transparent electrode or a reflective electrode. According to some example embodiments, pixel electrode 210 may include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer. The reflective layer may include at least one of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and mixtures thereof. The transparent or semi-transparent electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), and zinc aluminum oxide (AZO).

[0139] A pixel defining layer 119 may be disposed on the first planarization layer 116. The pixel defining layer 119 may define the emission region of pixel P by including an opening 119OP corresponding to each sub-pixel (i.e., an opening 119OP that at least exposes the central portion of pixel electrode 210). Furthermore, the pixel defining layer 119 may prevent arcing or the like at the edges of pixel electrode 210 by increasing the distance between the edge of pixel electrode 210 and the counter electrode 230 above pixel electrode 210. The pixel defining layer 119 may comprise at least one organic insulating material such as polyimide, polyamide, acrylic resin, BCB, and phenolic resin. The pixel defining layer 119 may be formed by a method such as spin coating.

[0140] Spacer SPCs may be disposed on pixel defining layer 119. Spacer SPCs may be disposed between multiple display elements and may protrude in a direction away from substrate 100. According to some example embodiments, spacer SPCs may be elements used to prevent chopping during masking processes. According to some example embodiments, spacer SPCs may alter the light path. Spacer SPCs may comprise at least one organic insulating material such as polyimide, polyamide, acrylic resin, BCB, and phenolic resin. Spacer SPCs may be formed by methods such as spin coating. According to some example embodiments, during processes using halftone masks, spacer SPCs may be formed simultaneously (e.g., concurrently) with pixel defining layer 119 using the same material as pixel defining layer 119.

[0141] The intermediate layer 220 of an organic light-emitting diode (OLED) may include an organic emitting layer. The organic emitting layer may include an organic material comprising a fluorescent or phosphorescent material emitting red, green, blue, or white light. The organic emitting layer may include a low molecular weight organic material or a polymeric organic material. Functional layers may optionally be further disposed below and on the organic emitting layer, and the functional layers may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL). According to some example embodiments, the intermediate layer 220 may correspond to each of the plurality of pixel electrodes 210. According to some example embodiments, the intermediate layer 220 may include a layer that extends across the plurality of pixel electrodes 210 as a whole. For example, the organic emitting layer may correspond to each of the plurality of pixel electrodes 210, and the functional layers on and / or below the organic emitting layer may be configured to extend across the plurality of pixels 210 as a whole. According to some example embodiments, the intermediate layer 220 may be configured to extend across the plurality of pixel electrodes 210 as a whole.

[0142] The counter electrode 230 may include a transparent electrode or a reflective electrode. According to some example embodiments, the counter electrode 230 may include a transparent electrode or a semi-transparent electrode, and may include a thin metal layer having a low work function and comprising at least one of lithium (Li), calcium (Ca), lithium fluoride (LiF) / Ca, LiF / Al, Al, Ag, Mg, and mixtures thereof. Furthermore, a transparent conductive oxide (TCO) layer comprising ITO, IZO, ZnO, or In2O3 may be further disposed on the thin metal layer. The counter electrode 230 may be configured as an integral part of a plurality of organic light-emitting diodes (OLEDs) and may correspond to a plurality of pixel electrodes 210.

[0143] A capping layer and / or a protective layer can be further disposed on the counter electrode 230. The capping layer improves light extraction efficiency, and the protective layer protects the organic light-emitting diode (OLED) in subsequent processes.

[0144] The first wiring WL1, the second wiring WL2, and the third wiring WL3 can transmit electrical signals and / or constant voltages to the first thin-film transistor TFT1 and the second thin-film transistor TFT2 of the pixel circuit PC.

[0145] The first wiring WL1 can be disposed on the first gate insulating layer 112. The first gate insulating layer 112 and the layer on which the first gate electrode G1 and the second gate electrode G2 are disposed are the same layer. The first wiring WL1 can be used as scan lines SL and SL-1 (see) to transmit the scan signal Sn to the pixel circuit PC. Figure 5B Optionally, the first wiring WL1 can be used as the transmit control line EL (see...). Figure 5B ).

[0146] The second wiring WL2 can be disposed on the second gate insulating layer 113, which is the same layer as the second electrode CE2 on which the storage capacitor Cst is disposed, and the second wiring WL2 can be used as a scan line SL and / or an emission control line EL.

[0147] The third wiring WL3 can be disposed on the interlayer insulating layer 114 and can be used as a data line DL to transmit the data signal Dm to the pixel circuit PC. Alternatively, the third wiring WL3 can be used as a drive voltage line PL to transmit the drive voltage ELVDD to the pixel circuit PC (see...). Figure 5A and Figure 5B ).

[0148] Figure 6B This is a cross-sectional view of a portion of the display device 1 applicable to the embodiment. Figure 6B In, because of Figure 6A The same reference numerals in the accompanying drawings indicate the same components, so some repetitive descriptions can be omitted.

[0149] Reference Figure 6B The display device 1 may also include a second planarization layer 117 on the first planarization layer 116. Therefore, the fourth wiring WL4 may be arranged between the first planarization layer 116 and the second planarization layer 117.

[0150] The second planarization layer 117 may have a flat top surface, allowing the pixel electrode 210 to be formed flat. The second planarization layer 117 may comprise a single layer or multiple layers containing organic materials. The second planarization layer 117 may comprise general polymers (such as benzocyclobutene (BCB), polyimide, polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0151] Organic light-emitting diodes (OLEDs) are disposed on the second planarization layer 117. The pixel electrodes 210 of the OLEDs can be connected to the first thin-film transistor (TFT) 1 via connection electrodes CM disposed on the first planarization layer 116.

[0152] The fourth wiring WL4 can be disposed on the first planarization layer 116. According to some example embodiments, the fourth wiring WL4 can be used as a drive voltage line PL to transmit the drive voltage ELVDD to the pixel circuit PC. According to some example embodiments, the fourth wiring WL4 can be used as a data line DL to transmit the data signal Dm to the pixel circuit PC.

[0153] Figure 6C This is a cross-sectional view of a portion of a display device 1 according to some example embodiments. Figure 6C In, because of Figure 6B The same reference numerals in the accompanying drawings indicate the same components, so some repetitive descriptions can be omitted.

[0154] Reference Figure 6C According to some example embodiments, the display device 1 may further include a third thin-film transistor TFT3, wherein the third semiconductor layer A3 is disposed on a layer different from the first semiconductor layer A1 on which the first thin-film transistor TFT1 is disposed. Furthermore, according to some example embodiments, the interlayer insulating layer 114 may include a first interlayer insulating layer 114a and a second interlayer insulating layer 114b. Additionally, the third planarization layer 118 may be further disposed on the second planarization layer 117.

[0155] The third thin-film transistor TFT3 may include a third semiconductor layer A3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3. The third semiconductor layer A3 may be disposed on the first interlayer insulating layer 114a. That is, the third semiconductor layer A3 may be disposed on a layer different from the layer on which the first semiconductor layer A1 is disposed. The third semiconductor layer A3 may include a channel region, a source region, and a drain region, with the source and drain regions located on two opposite sides of the channel region. According to some example embodiments, the third semiconductor layer A3 may include an oxide semiconductor. For example, the third semiconductor layer A3 may include Zn oxide, In-Zn oxide, and Ga-In-Zn oxide as Zn oxide-based materials. Optionally, the third semiconductor layer A3 may include IGZO (In-Ga-Zn-O) semiconductor, ITZO (In-Sn-Zn-O) semiconductor, or IGTZO (In-Ga-Sn-Zn-O) semiconductor, which include ZnO containing metals such as indium (In), gallium (Ga), and tin (Sn).

[0156] The source and drain regions of the third semiconductor layer A3 can be formed by adjusting the carrier concentration of the oxide semiconductor and making the oxide semiconductor conductive. For example, the source and drain regions of the third semiconductor layer A3 can be formed by performing a plasma process on the oxide semiconductor using hydrogen (H)-based gas, fluorine (F)-based gas, or a combination thereof and increasing the carrier concentration.

[0157] The third gate electrode G3 can be stacked with the channel region of the third semiconductor layer A3, and the third gate insulating layer 115 can be disposed between the third semiconductor layer A3 and the third gate electrode G3. That is, the third gate electrode G3 can be insulated from the third semiconductor layer A3 through the third gate insulating layer 115. The third gate insulating layer 115 can be patterned according to the shape of the third gate electrode G3.

[0158] The third gate insulating layer 115 may include an inorganic material comprising oxides or nitrides. For example, the third gate insulating layer 115 may include SiO2, SiN x The third gate electrode G3 may be disposed on the third gate insulating layer 115 and may include a single layer or multiple layers comprising at least one of Mo, Cu and Ti.

[0159] The second interlayer insulating layer 114b can cover the third gate electrode G3 of the third thin-film transistor TFT3 and can be disposed throughout the top surface of the substrate 100. The third source electrode S3 and the third drain electrode D3 can be disposed on the second interlayer insulating layer 114b.

[0160] The third source electrode S3 and the third drain electrode D3 can contact the source and drain regions of the third semiconductor layer A3, respectively, through contact holes passing through the second interlayer insulating layer 114b. The third source electrode S3 and the third drain electrode D3 can include conductive materials comprising Mo, Al, Cu, and Ti, and can include a single layer or multiple layers comprising the above materials. The third source electrode S3 and the third drain electrode D3 can be disposed on the same layer as the layer on which the third wiring WL3 is disposed.

[0161] A third gate insulating layer 115 may be disposed on a first interlayer insulating layer 114a, and a fifth wiring WL5 may be disposed on the third gate insulating layer 115. The third gate insulating layer 115 may be patterned along the shape of the fifth wiring WL5. According to some example embodiments, the fifth wiring WL5 may be used as a scan line SL for transmitting a scan signal Sn to a pixel circuit PC. According to some example embodiments, the fifth wiring WL5 may be used as an emittance control line EL for transmitting an emittance control signal En to a pixel circuit PC.

[0162] The third planarization layer 118 can be arranged between the second planarization layer 117 and the pixel electrode 210.

[0163] The third planarization layer 118 may have a flat top surface, allowing the pixel electrode 210 to be formed flat. The third planarization layer 118 may comprise a single layer or multiple layers containing organic materials. The third planarization layer 118 may comprise general polymers (such as benzocyclobutene (BCB), polyimide, polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0164] The organic light-emitting diode (OLED) is disposed on the third planarization layer 118. The pixel electrode 210 of the OLED can be connected to the first thin-film transistor (TFT) 1 through an additional connection electrode CM' disposed on the second planarization layer 117 and a connection electrode CM disposed on the first planarization layer 116.

[0165] The sixth wiring WL6 can be disposed on the second planarization layer 117. According to some example embodiments, the sixth wiring WL6 can be used as a drive voltage line PL to transmit the drive voltage ELVDD to the pixel circuit PC. According to some example embodiments, the sixth wiring WL6 can be used as a data line DL to transmit the data signal Dm to the pixel circuit PC.

[0166] Figure 7 This is an enlarged plan view of the wiring WL around the transmissive region TA of the display device 1, according to some example embodiments. Figure 8A and Figure 8B It is along Figure 7 A cross-sectional view of wiring WL taken from line II-II'.

[0167] Reference Figure 7 The first non-display area NDA1 is arranged around the transmissive area TA, and the display area DA surrounds the transmissive area TA and the first non-display area NDA1.

[0168] Multiple pixels P and multiple signal lines can be arranged in the display area DA, with the signal lines providing electrical signals to the multiple pixels P. The first scan line SLa and the second scan line SLb, as well as the first emission control line ELa and the second emission control line ELb, can extend in a first direction, and the data line DL can extend in a second direction (Y direction) that intersects the first direction (X direction).

[0169] According to some example embodiments, a wiring WL extending in the first direction and arranged on the left side of the transmission region TA is referred to as a first horizontal line HLa, and a wiring WL extending in the first direction and arranged on the right side of the transmission region TA is referred to as a second horizontal line HLb. Furthermore, a wiring WL extending in the second direction and arranged above the transmission region TA is referred to as a first vertical line VLa, and a wiring WL extending in the second direction and arranged below the transmission region TA is referred to as a second vertical line VLb.

[0170] The first horizontal line HLa may include a first scan line SLa and a first emission control line ELa. Furthermore, although not shown, the first horizontal line HLa may also include a reference... Figure 5B The line described in the preceding scan line SL-1 and / or the next scan line that is on the left side of the transmission region TA.

[0171] The second horizontal line HLb may include a second scan line SLb and a second emission control line ELb. Furthermore, the second horizontal line HLb may also include a reference line. Figure 5B The line described in the preceding scan line SL-1 and / or the next scan line that is on the right side of the transmission region TA.

[0172] The first vertical line VLa may include the first data line DLa, and the second vertical line VLb may include the second data line DLb.

[0173] The first scan line SLa on the left side of the transmission region TA can be separated from the second scan line SLb on the right side of the transmission region TA, and the transmission region TA is located between the first scan line SLa and the second scan line SLb. Furthermore, the first emission control line ELa on the left side of the transmission region TA can be separated from the second emission control line ELb on the right side of the transmission region TA, and the transmission region TA is located between the first emission control line ELa and the second emission control line ELb.

[0174] According to some example embodiments, the lengths of the first scan line SLa and the second scan line SLb arranged on the same line can be substantially the same, and the lengths of the first transmit control line ELa and the second transmit control line ELb arranged on the same line can be substantially the same.

[0175] According to some example embodiments, the number of pixels P connected to the first scan line SLa can be the same as the number of pixels P connected to the second scan line SLb.

[0176] According to some example embodiments, the load applied to the first scan line SLa can be substantially the same as the load applied to the second scan line SLb.

[0177] According to some example embodiments, even if the first scan line SLa is not connected to the second scan line SLb, no delay in the scan signal may occur between the pixel P on the left side of the transmission region TA and the pixel P on the right side of the transmission region TA.

[0178] In other words, according to some example embodiments, a high-quality image can be displayed on the display area DA even if the first scan line SLa on the left side of the transmission region TA is not connected to the second scan line SLb on the right side of the transmission region TA. Similarly, the first emission control line ELa may not be connected to the second emission control line ELb.

[0179] When the scan lines around the transmission region TA are not broken around the transmission region TA and are arranged to circle the transmission region TA, the number of lines arranged in the first non-display region NDA1 increases, and therefore the area of ​​the first non-display region NDA1 increases. In contrast, according to some example embodiments, since at least some of the signal lines on the left side of the transmission region TA may not be connected to at least some of the signal lines on the right side of the transmission region TA, the area of ​​the first non-display region NDA1 can be reduced.

[0180] Furthermore, the first data line DLa above the transmission region TA can be separated from the second data line DLb below the transmission region TA, and the transmission region TA is located between the first data line DLa and the second data line DLb. The first data line DLa can be connected to the second data line DLb on the same line in the second direction via a connecting line CL.

[0181] The connecting line CL can be arranged in a first non-display area NDA surrounding the transmissive area TA. The connecting line CL can extend in a second direction (Y direction) to connect the first data line DLa to the second data line DLb, and can be routed around the edge of the transmissive area TA in the first non-display area NDA1.

[0182] For example, when the transmission region TA is arranged in a circular shape, the connecting line CL can be curved along the edge of the transmission region TA. Although the connecting line CL is shown as an arc curve in the figure, the bypass portion can be arranged as a zigzag bend.

[0183] The first data line DLa can be separated from the second data line DLb around the transmission region TA in order to protect the pixel P from electrostatic discharge (ESD) that may occur in the vicinity of the transmission region TA.

[0184] Static charges can accumulate around a transmission region TA, which may include at least one opening, and there is a high probability of electrostatic discharge (ESD). When the wiring WL arranged around the transmission region TA continuously forms a conductive layer, a large voltage caused by ESD is directly applied to the pixel P.

[0185] In contrast, according to some example embodiments, since the first vertical line VLa and the second vertical line VLb arranged around the transmission region TA can be connected to each other by the connecting line CL, it is possible to prevent or reduce the direct application of large voltages due to electrostatic discharge to the pixel P.

[0186] The connecting line CL may include a first connecting line CL1 disposed on the same layer as at least one of the first horizontal lines HLa disposed thereon. For example, the first connecting line CL1 may be disposed on a reference layer. Figures 6A to 6C The first wiring WL1 described is disposed on the same layer. That is, the first connection line CL1 can be disposed on the same layer as the layer on which the first gate electrode G1 of the first thin film transistor TFT1 is disposed.

[0187] According to some example embodiments, the connecting line CL may further include a second connecting line CL2 disposed on a different layer than the layer on which the first connecting line CL1 is disposed. For example, the second connecting line CL2 may be disposed on a layer with a reference layer. Figures 6A to 6C The second wiring WL2 described is arranged on the same layer. That is, the second connection line CL2 can be arranged on the same layer as the second electrode CE2 on which the storage capacitor Cst is arranged.

[0188] According to some example embodiments, the first connecting line CL1 may be arranged on the same layer as the layer on which one of the second wiring WL2 to the sixth wiring WL6 is arranged, and the second connecting line CL2 may be arranged on the same layer as the layer on which the wiring of the first wiring WL1 to the sixth wiring WL6 is arranged, with the wiring arranged on a different layer than the layer on which the first connecting line CL1 is arranged.

[0189] The second connecting line CL2 can be arranged on the same layer as at least one of the first horizontal lines HLa. That is, some of the first horizontal lines HLa can be arranged on the same layer as the layer on which the first connecting line CL1 is arranged, and the others of the first horizontal lines HLa can be arranged on the same layer as the layer on which the second connecting line CL2 is arranged.

[0190] According to some example embodiments, the first scan line SLa can be disposed on the same layer as the layer on which the first connecting line CL1 is disposed, and the first transmit control line ELa can be disposed on the same layer as the layer on which the second connecting line CL2 is disposed. According to some example embodiments, some of the first scan lines SLa can be disposed on the same layer as the layer on which the first connecting line CL1 is disposed, and others of the first scan lines SLa can be disposed on the same layer as the layer on which the second connecting line CL2 is disposed.

[0191] The first connecting line CL1 and the second connecting line CL2 can be alternately arranged in the first non-display area NDA1. Because the first connecting line CL1 is arranged on a different layer than the layer on which the second connecting line CL2 is arranged, the interval between the first connecting line CL1 and the second connecting line CL2 can be narrowed, thereby reducing the area of ​​the first non-display area NDA1.

[0192] Figure 8A and Figure 8B It is along Figure 7 A cross-sectional view of the wiring cut off by line II-II'. Figure 8A and Figure 8B In, because of Figure 6A The same reference numerals in the accompanying drawings indicate the same components, so some repetitive descriptions can be omitted.

[0193] Reference Figure 8A The first connection line CL1 can be disposed on the first gate insulating layer 112, and the second connection line CL2 can be disposed on the second gate insulating layer 113. That is, the second gate insulating layer 113 can be disposed between the first connection line CL1 and the second connection line CL2. The first connection line CL1 and the second connection line CL2 can be disposed alternately in the first non-display area NDA1. Although the first connection line CL1 is shown in the figures not to overlap with the second connection line CL2, according to some example embodiments, the first connection line CL1 can overlap with the second connection line CL2.

[0194] The first data line DLa, which serves as the first vertical line VLa, can be arranged on the interlayer insulation layer 114. In this case, the first data line DLa can be connected to the connecting line CL through the contact hole CNT passing through the interlayer insulation layer 114.

[0195] According to some example embodiments, the first data line DLa can be connected to the connecting line CL via a bridging metal BM arranged on different layers.

[0196] For example, such as Figure 8BAs shown, the bridging metal BM can be disposed on the first planarization layer 116 and connected to the connecting line CL through a first contact hole CNT1 passing through the first planarization layer 116 and the interlayer insulation layer 114. Furthermore, the bridging metal BM can be connected to the first data line DLa through a second contact hole CNT2 passing through the first planarization layer 116. According to some example embodiments, the connecting line CL may not overlap with the first data line DLa.

[0197] Figure 9A and Figure 9B This is a plan view of a portion of a display device 1 according to some example embodiments. For example, the surrounding environment of the transmissive region TA is shown. Figure 9A and Figure 9B In, because of Figure 7 The same reference numerals in the accompanying drawings indicate the same components, so some repetitive descriptions can be omitted.

[0198] Reference Figure 9A The display device 1 may further include a third horizontal line HLc extending from the display area DA in a first direction and surrounding the transmission area TA. The third horizontal line HLc may be a scan line SL for transmitting scan signals Sn or an emission control line EL for transmitting emission control signals En.

[0199] The third horizontal line HLc can be placed on a different layer than the layer on which the connecting line CL is placed.

[0200] According to some example embodiments, the third horizontal line HLc may have a reference arranged thereon. Figures 6A to 6C The first wiring WL1 described is arranged on the same layer as the layer on which the connecting line CL is arranged, and the second wiring WL2 is arranged on the same layer as the connecting line CL. According to some example embodiments, the third horizontal line HLc can be arranged on the same layer as the connecting line CL. Figures 6A to 6C The second wiring WL2 described is arranged on the same layer, and the connecting line CL can be arranged on the same layer as the layer on which the first wiring WL1 is arranged.

[0201] According to some example embodiments, the connecting lines CL may include connecting lines CL arranged on different layers. For example, when the third horizontal line HLc is arranged on the same layer as the layer on which the first wiring WL1 is arranged, some of the connecting lines CL may be arranged on the same layer as the layer on which the second wiring WL2 is arranged, and others of the connecting lines CL may be arranged on the same layer as the layer on which the third wiring WL3 is arranged.

[0202] Reference Figure 9B The display device 1 may further include a horizontal connecting line HCL that connects at least one of the first horizontal lines SLa to at least one of the second horizontal lines SLb.

[0203] The line connected by the horizontal connection line HCL can be the scan line SL that transmits the scan signal Sn. Alternatively, the line connected by the horizontal connection line HCL can be the transmit control line EL that transmits the transmit control signal En.

[0204] According to some example embodiments, the horizontal connecting line HCL can be arranged on a different layer than the layer on which the first horizontal line HLa and the second horizontal line HLb are arranged, and can be connected to the first horizontal line HLa and the second horizontal line HLb through contact holes.

[0205] According to some example embodiments, the horizontal connecting line HCL can be connected to the first horizontal line HLa and the second horizontal line HLb via a bridging metal. In this case, the horizontal connecting line HCL can be disposed on the same layer as the layer on which the first horizontal line HLa is disposed.

[0206] According to some example embodiments, the horizontal connecting line HCL can be arranged with reference to it. Figures 6A to 6C The first wiring WL1 or the second wiring WL2 described are arranged on the same layer.

[0207] Figure 10 This is a plan view of a portion of a display device 1 according to some example embodiments. Figure 11 Is with Figure 10 The sectional view corresponding to line III-III'. Figure 10 and Figure 11 In, because of Figure 7 , Figure 8A as well as Figure 8B The same reference numerals in the accompanying drawings indicate the same components, so some repetitive descriptions can be omitted.

[0208] Reference Figure 10 and Figure 11 The display device 1 may further include an electrode layer PML surrounding the transmissive region TA. The electrode layer PML may be connected to a horizontal driving voltage line PLA extending in a first direction. Furthermore, the electrode layer PML may be connected to a vertical driving voltage line PLb extending in a second direction.

[0209] Horizontal drive voltage line PLA and / or vertical drive voltage line PLb can transmit the drive voltage ELVDD to multiple pixels P. Horizontal drive voltage line PLA can extend from the second electrode CE2 of the storage capacitor Cst. Vertical drive voltage line PLb can extend from the first power line 160 outside the display area DA (see...). Figure 4 (Extension) Horizontal drive voltage lines PLA and vertical drive voltage lines PLb can be arranged on different layers and connected to each other through contact holes. Multiple horizontal drive voltage lines PLA and multiple vertical drive voltage lines PLb can form a grid structure.

[0210] The electrode layer PML can be at least partially superimposed on multiple interconnect lines CL. Therefore, the area of ​​the first non-display area NDA1 can be reduced. According to some example embodiments, as shown in the figures, the electrode layer PML can be disposed on the first planarization layer 116. According to some example embodiments, the electrode layer PML can be disposed on the interlayer insulating layer 114.

[0211] The electrode layer PML can be arranged in a shape that surrounds the transmission region TA. Because the driving voltage lines (i.e., the horizontal driving voltage line PLA and the vertical driving voltage line PLb on the left and right sides of the transmission region TA and above and below the transmission region TA) can be connected to each other through the electrode layer PML, the driving voltage ELVDD can be provided uniformly around the transmission region TA.

[0212] Figure 12 This is a plan view of a portion of a display device 1 according to some example embodiments. For example, the surrounding environment of the transmissive region TA is shown. Figure 13 It is along Figure 12 A sectional view taken along line IV-IV'. Figure 12 In, because of Figure 7 The same reference numerals in the accompanying drawings indicate the same components, so some repetitive descriptions can be omitted.

[0213] Reference Figure 12 Multiple connecting lines CL may include a first connecting line CL1, a second connecting line CL2, a third connecting line CL3, and a fourth connecting line CL4, all of which are arranged on different layers.

[0214] In this case, the first connecting line CL1 can be disposed on the same layer as at least one of a plurality of first horizontal lines HLa disposed thereon. For example, the first connecting line CL1 can be disposed on a layer with a reference line disposed thereon. Figures 6A to 6C The first wiring WL1 described is disposed on the same layer. That is, the first connection line CL1 can be disposed on the same layer as the layer on which the first gate electrode G1 of the first thin film transistor TFT1 is disposed.

[0215] The second connecting line CL2 can be disposed on a different layer than the layer on which the first connecting line CL1 is disposed, and can be disposed on the same layer as a layer on which at least one of multiple first horizontal lines HLa is disposed. For example, the second connecting line CL2 can be disposed on a layer with a reference line HLa. Figures 6A to 6C The second wiring WL2 described is arranged on the same layer. That is, the second connection line CL2 can be arranged on the same layer as the second electrode CE2 on which the storage capacitor Cst is arranged.

[0216] The third connecting line CL3 can be disposed on the same layer as at least one of the multiple first vertical lines VLa disposed thereon. For example, the third connecting line CL3 can be disposed on a layer with a reference line. Figures 6A to 6C The third wiring WL3 described is on the same layer. That is, the third connecting line CL3 can be on the same layer as the layer on which the data line DL is located.

[0217] The fourth connecting line CL4 can be placed on a different layer than the layer on which the first connecting line CL1, the second connecting line CL2, and the third connecting line CL3 are placed. For example, the fourth connecting line CL4 can be placed on a reference layer. Figure 6B and Figure 6C The fourth wiring, WL4, is described as being arranged on the same layer.

[0218] The positions of the first connecting line CL1, the second connecting line CL2, the third connecting line CL3, and the fourth connecting line CL4 can be changed differently. For example, the positions of the first connecting line CL1, the second connecting line CL2, the third connecting line CL3, and the fourth connecting line CL4 can be changed from a reference. Figure 6C Choose appropriately from the first wiring WL1, the second wiring WL2, the third wiring WL3, the fourth wiring WL4, the fifth wiring WL5, and the sixth wiring WL6 described.

[0219] The first connecting line CL1, the second connecting line CL2, the third connecting line CL3, and the fourth connecting line CL4 can be arranged in the direction from the transmission area TA to the display area DA, and the first connecting line CL1, the fourth connecting line CL4, the second connecting line CL2, and the third connecting line CL3 are arranged in sequence and repeated.

[0220] The connecting line CL can be arranged in a first non-display area NDA1 surrounding the transmissive area TA. The connecting line CL can extend in a second direction (Y direction) to connect the first data line DLa to the second data line DLb, and can travel around the edge of the transmissive area TA in the first non-display area NDA1.

[0221] For example, when the transmission region TA is arranged in a circular shape, the connecting line CL can be curved along the edge of the transmission region TA. In this case, the connecting line CL near the transmission region TA can be curved with a large curvature along the edge of the transmission region TA, and the curvature of the connecting line CL away from the transmission region TA can decrease. Although the connecting line CL is shown as an arc curve in the figure, the bypass portion can be arranged as a zigzag line.

[0222] Multiple connection lines (CLs) can include areas that overlap each other.

[0223] Reference Figure 13The third connecting line CL3 can be arranged between the first connecting line CL1 and the second connecting line CL2. In this case, the third connecting line CL3 may include regions that overlap with a portion of the first connecting line CL1 and a portion of the second connecting line CL2, respectively.

[0224] The fourth connecting line CL4 can be arranged between the first connecting line CL1 and the second connecting line CL2. In this case, the fourth connecting line CL4 may include regions that overlap with a portion of the first connecting line CL1 and a portion of the second connecting line CL2, respectively.

[0225] For example, the first connecting line CL1 may have a first overlap length OL1 with respect to the third connecting line CL3. The first overlap length OL1 may be about 15% to about 35% of the width Wt1 of the first connecting line CL1. According to some example embodiments, the width Wt1 of the first connecting line CL1 may be about 1.5 μm to about 3 μm, and the first overlap length OL1 may be about 0.5 μm to about 1 μm.

[0226] The first connecting line CL1 may have a second overlap length OL2 with respect to the fourth connecting line CL4. The second overlap length OL2 may have a length of about 15% to about 35% of the width Wt1 of the first connecting line CL1. According to some example embodiments, the width Wt1 of the first connecting line CL1 may be about 1.5 μm to about 3 μm, and the second overlap length OL2 may be about 0.5 μm to about 1 μm.

[0227] The second connecting line CL2 may have a third overlap length OL3 with respect to the fourth connecting line CL4. The third overlap length OL3 may be approximately 15% to approximately 35% of the width Wt2 of the second connecting line CL2. According to some example embodiments, the width Wt2 of the second connecting line CL2 may be approximately 1.5 μm to approximately 3 μm, and the third overlap length OL3 may be approximately 0.5 μm to approximately 1 μm.

[0228] The second connecting line CL2 may have a fourth overlap length OL4 with respect to the third connecting line CL3. The fourth overlap length OL4 may be approximately 15% to approximately 35% of the width Wt2 of the second connecting line CL2. According to some example embodiments, the width Wt2 of the second connecting line CL2 may be approximately 1.5 μm to approximately 3 μm, and the fourth overlap length OL4 may be approximately 0.5 μm to approximately 1 μm.

[0229] According to some example embodiments, the separation distance between the first connecting line CL1 and the second connecting line CL2 along the top surface of the substrate 100 may be about 0.5 μm to about 1 μm.

[0230] According to some example embodiments, the separation distance between the third connecting line CL3 and the fourth connecting line CL4 along the top surface of the substrate 100 can be about 0.5 μm to about 1 μm.

[0231] Because multiple connecting lines CL include areas that overlap with each other, the area of ​​the first non-display area NDA1 can be reduced.

[0232] Figure 14 and Figure 15 This is a plan view of a portion of the display device 1 according to an embodiment. For example, the surrounding environment of the transmissive region TA is shown. Figure 14 and Figure 15 In, because of Figure 12 The same reference numerals in the accompanying drawings indicate the same components, so some repetitive descriptions can be omitted.

[0233] Reference Figure 14 At least one of the first horizontal lines HLa can be connected to at least one of the second horizontal lines HLb via a horizontal connector HCL. The horizontal connector HCL can be disposed on the same layer as the layer on which the first wiring WL1 is disposed. In this case, the multiple connectors CL can include connectors disposed on layers different from the layer on which the horizontal connectors HCL are disposed. For example, the multiple connectors CL can include a first connector CL1, a second connector CL2, a third connector CL3, and a fourth connector CL4.

[0234] In addition, the display device 1 may also include a third horizontal line HLc extending from the display area DA and surrounding the transmission area TA (see Figure 9A ).

[0235] Reference Figure 15 Multiple connecting lines CL may include a first connecting line CL1, a second connecting line CL2, a third connecting line CL3, a fourth connecting line CL4, a fifth connecting line CL5, and a sixth connecting line CL6.

[0236] The fifth connecting line CL5 and the sixth connecting line CL6 can be arranged on a different layer than the layer on which the first connecting line CL1, the second connecting line CL2, the third connecting line CL3, and the fourth connecting line CL4 are arranged. For example, the fifth connecting line CL5 can be arranged on a layer with a reference layer. Figure 6C The fifth cabling, WL5, is described as being laid out on the same layer. The sixth connecting cable, CL6, can be placed on a reference layer. Figure 6C The sixth wiring, WL6, described is arranged on the same layer.

[0237] As mentioned above, because multiple connection lines CL are arranged on each layer, the area of ​​the first non-display area NDA1 can be reduced.

[0238] At least one of the first horizontal lines HLa can be connected to at least one of the second horizontal lines HLb. Furthermore, the display device 1 may also include a third horizontal line HLc (see [reference needed]) extending from the display area DA and surrounding the transmission area TA. Figure 9A ).

[0239] The display device according to an embodiment may have a reduced non-display area around the transmissive area. Furthermore, because the wiring around the transmissive area is connected by connecting lines, the display device can be protected against damage caused by electrostatic discharge. This effect is provided as an example, but the scope of this disclosure is not limited to this effect.

[0240] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims and their equivalents.

Claims

1. A display device, the display device comprising: The substrate includes a transmissive region and a display region surrounding the transmissive region; Multiple display elements are located in the display area; Multiple first horizontal lines and multiple second horizontal lines extend in a first direction and are spaced apart from each other, such that the transmission area is located between the multiple first horizontal lines and the multiple second horizontal lines; Multiple first vertical lines and multiple second vertical lines extend in a second direction that intersects the first direction, and are spaced apart from each other, such that the transmission area is located between the multiple first vertical lines and the multiple second vertical lines; as well as A first connecting line connects at least one of the plurality of first vertical lines to at least one of the plurality of second vertical lines and runs around the perimeter of the transmission region. The first connecting line is located on a first layer that shares the same layer as at least one of the plurality of first horizontal lines arranged on it. The display device further includes: A bridging metal is disposed on a different layer from the first connecting line and at least one of the plurality of first vertical lines, thereby connecting the first connecting line to at least one of the plurality of first vertical lines. The bridging metal is connected to the first connecting line through a first contact hole, and the bridging metal is connected to at least one of the plurality of first vertical lines through a second contact hole. Wherein, the first connecting line does not overlap with at least one of the plurality of first vertical lines in a direction perpendicular to the surface of the substrate.

2. The display device according to claim 1, further comprising: A second connecting line connects at least one of the plurality of first vertical lines to at least one of the plurality of second vertical lines and runs around the perimeter of the transmission region. The second connecting line is located on a second layer, which is different from the first layer.

3. The display device according to claim 2, wherein, The first connecting line and the second connecting line are respectively configured as multiple first connecting lines and multiple second connecting lines, and The plurality of first connecting lines and the plurality of second connecting lines are alternately arranged around the transmission area.

4. The display device according to claim 1, wherein, The first connecting line is connected to at least one of the plurality of first vertical lines through a contact hole.

5. The display device according to claim 1, wherein, The plurality of first horizontal lines and the plurality of second horizontal lines include scan lines and emission control lines, and the plurality of first vertical lines and the plurality of second vertical lines include data lines.

6. The display device according to claim 1, further comprising: A third horizontal line extends from the display area in the first direction and circles around the transmissive area. The third horizontal line is located on a different layer than the first layer.

7. The display device according to claim 1, wherein, At least one of the plurality of first horizontal lines is connected to at least one of the plurality of second horizontal lines via a horizontal connecting line.

8. The display device according to claim 1, further comprising: An electrode layer surrounds the transmission region and is stacked with the first connection line; A horizontal driving voltage line extends in the first direction; as well as The vertical driving voltage line extends in the second direction. The horizontal driving voltage line and the vertical driving voltage line are connected to the electrode layer.

9. The display device according to claim 8, further comprising: A second connecting line connects at least one of the plurality of first vertical lines to at least one of the plurality of second vertical lines and runs around the perimeter of the transmission region. The electrode layer is at least partially superimposed on the first connecting line and the second connecting line.

10. The display device according to claim 1, further comprising: A third connecting line connects at least one of the plurality of first vertical lines to at least one of the plurality of second vertical lines and runs around the perimeter of the transmission region. The third connecting line is located on a third layer that is the same layer as at least one of the plurality of first vertical lines that are connected to the third connecting line.

11. The display device according to claim 10, further comprising: A fourth connecting line connects at least one of the plurality of first vertical lines to at least one of the plurality of second vertical lines and runs around the transmission region. The fourth connecting line is located on a fourth layer, which is different from the third layer.

12. The display device according to claim 11, further comprising: A horizontal connecting line extends in the first direction and runs around the perimeter of the transmission region. The horizontal connecting line connects at least one of the plurality of first horizontal lines to at least one of the plurality of second horizontal lines.

13. The display device according to claim 12, further comprising: A second connecting line connects at least one of the plurality of first vertical lines to at least one of the plurality of second vertical lines and runs around the periphery of the transmission region. Wherein, at least one of the plurality of first horizontal lines connected to the horizontal connecting line is located on a second layer different from the first layer, and The second connecting line is located on the second layer.

14. A display device, the display device comprising: The substrate includes a transmissive region, a display region surrounding the transmissive region, and a non-display region located between the transmissive region and the display region; Multiple display elements are located in the display area; Multiple first horizontal lines and multiple second horizontal lines extend in a first direction and are spaced apart from each other, such that the transmission area is located between the multiple first horizontal lines and the multiple second horizontal lines; Multiple first vertical lines and multiple second vertical lines extend in a second direction that intersects the first direction, and are spaced apart from each other, such that the transmission area is located between the multiple first vertical lines and the multiple second vertical lines; as well as Multiple connecting lines, located in the non-display area, connect at least one of the multiple first vertical lines to at least one of the multiple second vertical lines, and include first connecting lines, second connecting lines, third connecting lines, and fourth connecting lines, each arranged on a different layer from the others. The first connecting line is located on the same layer as at least one of the plurality of first horizontal lines. The display device further includes: Multiple bridging metals are arranged on a different layer than the multiple connecting lines and the multiple first vertical lines, and the multiple connecting lines are respectively connected to the multiple first vertical lines. Each of the bridging metals is connected to a corresponding connecting line among the plurality of connecting lines through a first contact hole, and each of the bridging metals is connected to a corresponding first vertical line among the plurality of first vertical lines through a second contact hole. Wherein, the corresponding connecting line does not overlap with the corresponding first vertical line in the direction perpendicular to the surface of the substrate.

15. The display device according to claim 14, further comprising: A thin-film transistor is located in the display area. The thin-film transistor includes a first semiconductor layer and a first gate electrode, and the first connection line is located on the same layer as the first gate electrode.

16. The display device according to claim 15, further comprising: A storage capacitor, located in the display area, includes a first electrode and a second electrode. The first electrode and the first gate electrode are located on the same layer, and the second electrode is located above the first electrode. The second connecting line is located on the same layer as the second electrode.

17. The display device according to claim 14, wherein, The third connecting line is located on a third layer that is on the same layer as at least one of the plurality of first vertical lines.

18. The display device according to claim 14, wherein, The third connecting line has regions that overlap with portions of the first connecting line and the second connecting line, respectively, and a region located between the first connecting line and the second connecting line in a plan view.

19. The display device according to claim 14, wherein, The fourth connecting line has regions that overlap with portions of the first connecting line and the second connecting line, respectively, and a region located between the first connecting line and the second connecting line in a plan view.

20. The display device according to claim 14, wherein, The plurality of connecting lines also includes a fifth connecting line, which is located on a different layer than the layer on which the first connecting line is arranged, the layer on which the second connecting line is arranged, the layer on which the third connecting line is arranged, and the layer on which the fourth connecting line is arranged.

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