Display device

Abstract

A display device is provided. The display device includes first, second, and third front signal lines arranged on a first portion and electrically connected to light emitting elements, a connection line overlapping with a second portion, and first, second, and third back signal lines arranged on a third portion. The first, second, and third front signal lines are arranged on different layers. The first front signal line and the first back signal line are arranged on the same layer. The second front signal line and the second back signal line are arranged on the same layer. The third front signal line and the third back signal line are arranged on the same layer. The connection line electrically connects and selectively connects the front signal lines and the back signal lines.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display apparatus having a narrow bezel. BACKGROUND

[0002] A display apparatus can display various images on a display screen to provide information to a user. Generally, the information can be displayed in an allocated screen.

[0003] The display apparatus can include a display area displaying information and a non-display area which can surround the display area.

[0004] In recent years, as the resolution of the display apparatus increases, the number of signal lines which can be arranged in the non-display area has increased. Accordingly, the width of the non-display area (or the width of the bezel area) can increase, and thus, the aesthetic quality of the display apparatus can decrease.

[0005] As the display apparatus increases in size, a difference in length can occur between data signal lines which can transmit data signals to pixels of the display apparatus. Accordingly, the resistance value of each of the plurality of data signal lines can be non-uniform, which can result in a decrease in the display quality of the display apparatus.

[0006] It will be appreciated that this Background of the Technology section of the Specification is provided merely for purposes of summarizing information and is not intended to limit the scope of the subject matter disclosed herein. However, the Background of the Technology section of the Specification can include ideas, concepts or realizations that, alone or in combination, can not be considered prior art by those skilled in the art. SUMMARY

[0007] The disclosure provides a display apparatus having a narrow bezel and excellent display quality.

[0008] An embodiment may provide a display device that may include a base layer, wherein the base layer includes a first portion, a second portion extending from the first portion, and a third portion extending from the second portion. The display device may include a plurality of light-emitting elements, wherein the plurality of light-emitting elements includes a first light-emitting element, a second light-emitting element, and a third light-emitting element, the plurality of light-emitting elements being disposed on the first portion. The display device may include a first front signal line, a second front signal line, and a third front signal line, wherein the first front signal line is disposed on the first portion and electrically connected to the first light-emitting element, the second front signal line is disposed on the first portion and electrically connected to the second light-emitting element, wherein the first and second front signal lines may be disposed on different layers, and the third front signal line is electrically connected to the third light-emitting element, wherein the first, second, and third front signal lines may be disposed on different layers. The display device may include a first rear signal line, a second rear signal line, and a third rear signal line, wherein the first rear signal line is arranged on a third portion, and the first rear signal line and the first front signal line may be arranged on the same layer; the second rear signal line is arranged on the third portion, and the second rear signal line and the second front signal line may be arranged on the same layer; the third rear signal line is arranged on the third portion, and the third rear signal line and the third front signal line may be arranged on the same layer. The display device may include a plurality of connecting lines, wherein the plurality of connecting lines overlap with a second portion, and wherein at least one of the plurality of connecting lines is electrically connected to the first front signal line and the third rear signal line.

[0009] The second part of the base layer can be bent.

[0010] The display device may further include a data driving circuit, wherein the data driving circuit is disposed on a third portion of the base layer, and wherein the data driving circuit is electrically connected to a first rear signal line, a second rear signal line, and a third rear signal line.

[0011] Each of the first front signal line, the second front signal line, the third front signal line, the first rear signal line, the second rear signal line, and the third rear signal line may include a first metallic material, and each of the plurality of connecting lines may include a second metallic material different from the first metallic material.

[0012] The first metallic material may have a resistivity greater than that of the second metallic material.

[0013] The first metallic material may include molybdenum, and the second metallic material may include aluminum.

[0014] The multiple connecting lines may include a first connecting line, a second connecting line, and a third connecting line, wherein the first connecting line is electrically connected to a first front signal line and a third rear signal line, the second connecting line is electrically connected to a second front signal line and a second rear signal line, and the third connecting line is electrically connected to a third front signal line and a first rear signal line.

[0015] Each of the first front signal line, the second front signal line, and the third front signal line may be configured as multiple, and some of the first front signal lines, the second front signal lines, and the third front signal lines arranged on the outer side have a width greater than the width of some of the first front signal lines, the second front signal lines, and the third front signal lines arranged on the inner side.

[0016] Some front signal lines located on the outer side may have a greater thickness than some front signal lines located on the inner side.

[0017] Each of the first, second, and third rear signal lines can be configured as multiple, and some of the rear signal lines arranged on the outer side among the multiple first, second, and third rear signal lines have a width greater than the width of some of the rear signal lines arranged on the inner side among the multiple first, second, and third rear signal lines.

[0018] Some of the rear signal lines located on the outer side have a greater thickness than some of the rear signal lines located on the inner side.

[0019] Some of the connecting lines located on the outer side of a plurality of connecting lines may have a wider width than some of the connecting lines located on the inner side of a plurality of connecting lines.

[0020] Some connecting lines located on the outer side may have a greater thickness than some connecting lines located on the inner side.

[0021] The display device may also include a plurality of transistors and power lines, wherein the plurality of transistors are arranged on a first portion of the base layer and electrically connected to a plurality of light-emitting elements, and the power lines provide an initialization voltage to the plurality of transistors, wherein the power lines and a third front signal line may be arranged on the same layer.

[0022] The display device may further include a first insulating layer, wherein the first insulating layer covers the first front signal line and the first rear signal line, and is disposed below the second front signal line and the second rear signal line. The display device may further include a second insulating layer, wherein the second insulating layer covers the second front signal line and the second rear signal line, and is disposed below the third front signal line and the third rear signal line. The display device may further include a third insulating layer, wherein the third insulating layer covers the third front signal line and the third rear signal line, and may be disposed below the connecting line.

[0023] The display device may further include a plurality of contact holes, wherein the plurality of contact holes are defined to pass through a first insulating layer, a second insulating layer and a third insulating layer, wherein a first front signal line, a second front signal line, a third front signal line, a first rear signal line, a second rear signal line and a third rear signal line can be electrically connected to a plurality of connecting lines through the plurality of contact holes.

[0024] One embodiment may provide a display device that may include a base layer, wherein the base layer includes a first portion, a second portion extending from the first portion, and a third portion extending from the second portion. The display device may include a plurality of light-emitting elements, a plurality of first front signal lines, and a plurality of second front signal lines, wherein the plurality of light-emitting elements are disposed on the first portion, the plurality of first front signal lines are electrically connected to at least one of the plurality of light-emitting elements and disposed on the first portion, and the plurality of second front signal lines are electrically connected to at least one of the plurality of light-emitting elements and disposed on the first portion, wherein the plurality of first front signal lines may be disposed on a different layer than the layer on which the plurality of second front signal lines may be disposed. The display device may include a plurality of third front signal lines, a plurality of second rear signal lines, a plurality of third rear signal lines, and a plurality of connecting lines. The plurality of third front signal lines are electrically connected to at least one of a plurality of light-emitting elements and are arranged on a layer different from the layer on which the plurality of first front signal lines are arranged and the layer on which the plurality of second front signal lines are arranged. The plurality of second rear signal lines are arranged on a third portion and on the same layer as the layer on which the plurality of second front signal lines are arranged. The plurality of third rear signal lines are arranged on a third portion and on the same layer as the layer on which the plurality of third front signal lines are arranged. The plurality of connecting lines electrically connect the plurality of first front signal lines to the plurality of second rear signal lines and electrically connect the plurality of second front signal lines and the plurality of third front signal lines to the plurality of third rear signal lines.

[0025] The second part of the base layer can be bent.

[0026] The display device may also include a data driving circuit, wherein the data driving circuit is disposed on a third portion of the base layer and is electrically connected to a plurality of second rear signal lines and a plurality of third rear signal lines.

[0027] Each of the plurality of first front signal lines, plurality of second front signal lines, plurality of third front signal lines, plurality of second rear signal lines, and plurality of third rear signal lines may include a first metal material, and each of the plurality of connecting lines may include a second metal material different from the first metal material.

[0028] The first metallic material may have a resistivity greater than that of the second metallic material.

[0029] The first metallic material may include molybdenum, and the second metallic material may include aluminum.

[0030] Among the plurality of first front signal lines, plurality of second front signal lines, and plurality of third front signal lines, some of the front signal lines arranged on the outer side may have a width greater than the width of some of the front signal lines arranged on the inner side; or some of the front signal lines arranged on the outer side may have a thickness greater than the thickness of some of the front signal lines arranged on the inner side.

[0031] Some of the rear signal lines arranged on the outer side among the plurality of second and third rear signal lines may have a width greater than the width of some of the rear signal lines arranged on the inner side among the plurality of second and third rear signal lines; or some of the rear signal lines arranged on the outer side among the plurality of second and third rear signal lines may have a thickness greater than the thickness of some of the rear signal lines arranged on the inner side among the plurality of second and third rear signal lines.

[0032] Some of the connecting lines located on the outer side may have a wider width than some of the connecting lines located on the inner side; or some of the connecting lines located on the outer side may have a thicker thickness than some of the connecting lines located on the inner side.

[0033] The display device may also include a plurality of transistors and power lines, wherein the plurality of transistors are arranged on a first portion of the base layer and electrically connected to a plurality of light-emitting elements, and the power lines provide an initialization voltage to the plurality of transistors, wherein the power lines and a plurality of third front signal lines may be arranged on the same layer.

[0034] The display device further includes a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first insulating layer covers a plurality of first front signal lines and is disposed below a plurality of second front signal lines and a plurality of second rear signal lines, the second insulating layer covers a plurality of second front signal lines and a plurality of second rear signal lines and is disposed below a plurality of third front signal lines and a plurality of third rear signal lines, and the third insulating layer covers a plurality of third front signal lines and a plurality of third rear signal lines and is disposed below a plurality of connecting lines.

[0035] The display device may further include a plurality of contact holes, wherein the contact holes are defined to pass through a first insulating layer, a second insulating layer and a third insulating layer, wherein a plurality of first front signal lines, a plurality of second front signal lines, a plurality of third front signal lines, a plurality of second rear signal lines and a plurality of third rear signal lines can be electrically connected to a plurality of connecting lines through the plurality of contact holes.

[0036] Based on the above, since the signal lines transmitting data signals can be stacked into layers, the display device can have a narrow bezel, thus improving its aesthetic quality. Because the color deviation between pixels can be small, the display device can achieve excellent display quality. Attached Figure Description

[0037] The above and other advantages of this disclosure will readily become apparent when considered in conjunction with the accompanying drawings, and by referring to the following detailed description, in which:

[0038] Figure 1A This is a schematic perspective view showing a display device according to an embodiment of the present disclosure;

[0039] Figure 1B This is an exploded schematic perspective view showing a display device according to an embodiment of the present disclosure;

[0040] Figure 2 This is a schematic plan view showing a display module according to an embodiment of the present disclosure;

[0041] Figure 3 It is shown schematically. Figure 2 The display module can show a view of the shape bent relative to the bent area;

[0042] Figure 4A It is shown Figure 2 A schematic circuit diagram of the pixels;

[0043] Figure 4B It shows that it is applied to Figure 4A A schematic timing diagram of the driving signals for the pixels;

[0044] Figure 5A It is shown that... Figure 4A A schematic diagram of the pixel layout corresponding to the schematic circuit diagram;

[0045] Figure 5B This is a schematic plan view showing a conductive pattern included in a third conductive layer according to an embodiment of the present disclosure;

[0046] Figure 6A and Figure 6B This is a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure;

[0047] Figure 7A It is shown Figure 2 A magnified schematic view of area AA;

[0048] Figure 7B It is along Figure 7A A schematic cross-sectional view taken by line I-I';

[0049] Figure 7C It is along Figure 7A A schematic cross-sectional view taken from line II-II';

[0050] Figure 7D It is along Figure 7A A schematic cross-sectional view taken from line II-II';

[0051] Figure 8A , Figure 8B , Figure 8C and Figure 8D It is illustrated schematically according to layers. Figure 7A The view of the lines shown;

[0052] Figure 9 It is shown schematically. Figure 2 A magnified view of region AA;

[0053] Figure 10A , Figure 10B , Figure 10C and Figure 10D It is illustrated schematically according to layers. Figure 9 The view of the lines shown; and

[0054] Figure 11 It is shown schematically. Figure 2 A magnified view of area BB. Detailed Implementation

[0055] In the following description, embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings. It will be understood that when an element or layer is referred to as being "on," "connected to," or "attached to" another element or layer, the element or layer may be directly on the other element or layer, or connected to or attached to the other element, or there may be intermediate elements or layers present.

[0056] Throughout this specification, similar reference numerals refer to similar elements. In the drawings, for the effective description of the technical content, the thickness, scale, and dimensions of parts may be exaggerated. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms "and" and "or" may be used in combination or separately and are to be understood as equivalent to "and / or".

[0057] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms as well.

[0058] Spatial relative terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used in this document for the convenience of description to describe the relationship between one element or feature and another element or feature as shown in the figure.

[0059] It will also be understood that the terms “having” and / or “comprising”, when used in this specification, indicate the presence of the stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or clusters thereof.

[0060] The term "overlap" may include layering, stacking, facing or opposite, extending above, covering or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. The expression "non-overlap" may include "separated from," "set beside," or "offset from," or any other suitable equivalent that will be understood and appreciated by one of ordinary skill in the art.

[0061] For the purposes of its meaning and interpretation, the phrase “at least one” is intended to include “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms, such as those defined in common dictionaries, should be interpreted as having the same meaning as they have in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0063] In the following text, embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings.

[0064] Figure 1A This is a schematic perspective view showing a display device DD according to an embodiment of the present disclosure.Figure 1B This is an exploded schematic perspective view showing a display device DD according to an embodiment of the present disclosure.

[0065] Figure 1A The display device DD, implemented as a smartphone, is shown as a representative example; however, the display device DD is not limited to smartphones. For example, the display device DD can be implemented as a large-sized electronic product such as a television or monitor, or a small to medium-sized electronic product such as a mobile phone, tablet computer, car navigation unit, gaming unit, or smartwatch.

[0066] The display device DD may include a display area DA and a non-display area NDA. The display area DA and the non-display area NDA may be arranged within the display device DD; however, the implementation should not be limited thereto or thereby restricted. For example, other areas may also be defined within the display device DD. The display area DA may be a pressure-sensing area for an input sensor SP, described later, capable of sensing external input. The display area DA may display an image IM and may sense user input, such as touch events.

[0067] The display area DA may be substantially parallel to the surface defined by the first direction axis DR1 and the second direction axis DR2. The third direction axis DR3 may indicate the normal direction of the display area DA, that is, the thickness direction of the display device DD. The front (or upper) surface and the rear (or lower) surface of each component of the display device DD may be distinguished from each other by the third direction axis DR3. However, the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are relative to each other and may be changed to other directions. In the following, the first direction, the second direction, and the third direction may be the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, respectively, and are assigned the same reference numerals.

[0068] Figure 1A The shape of the display area DA shown is merely exemplary and can be changed without limitation as needed. The non-display area NDA can be arranged adjacent to the display area DA, and the image IM may not be displayed in the non-display area NDA. The border area of ​​the display device DD may correspond to the non-display area NDA. The non-display area NDA may surround the display area DA; however, the shapes of the display area DA and the non-display area NDA should not be limited thereto or thereby restricted, and can be changed.

[0069] Reference Figure 1B The display device DD may include a window member WM, a display module DM, and a setting member ST. The window member WM may include a transmissive area TA and a frame area BZA therein. However, the window member WM should not be limited to this or thus restricted, and according to embodiments, other areas may also be arranged in the window member WM.

[0070] The transmission region TA can be a region through which incident light can pass. For example, an image IM generated by the display module DM can be perceived by the user after passing through the transmission region TA. The transmission region TA can correspond to the display region DA.

[0071] The border area BZA can be arranged adjacent to the transmissive area TA. For example, the border area BZA can surround the transmissive area TA. The border area BZA can have a predetermined color. The border area BZA can overlap with the non-display area NDA.

[0072] The display module DM can be positioned below the window member WM. The window member WM protects the display module DM from external impacts.

[0073] The display module DM may include a valid region ACA and a non-valid region NACA that may be defined therein. The valid region ACA may correspond to... Figure 1A The display area DA can display the image IM and can sense user input.

[0074] The non-active region NACA may correspond to the non-display region NDA, and lines may be arranged in the non-active region NACA to apply electrical signals to or receive electrical signals from the active region ACA.

[0075] At least a portion of the component ST can be positioned below the display module DM. The component ST can accommodate the window component WM and the display module DM.

[0076] Figure 2 This is a schematic plan view showing a display module DM according to an embodiment of the present disclosure. Figure 3 It is shown schematically. Figure 2 The display module DM can display a view of the shape of the bend relative to the bend area BA.

[0077] The display module DM may include a display panel DP, an input sensor SP, a data drive circuit DIC, pads PD, a printed circuit board PCB, an input sensing drive circuit TIC, and a control drive circuit CIC.

[0078] The display panel DP may include a base layer BL, a circuit layer CL, a light-emitting element layer ELL, and a packaging layer TFE. The base layer BL may include polyimide PI; however, embodiments should not be limited thereto or thereby restricted. The base layer BL may include a first portion PT1, a second portion PT2 extending from the first portion PT1, and a third portion PT3 extending from the second portion PT2. The first portion PT1, the second portion PT2, and the third portion PT3 may be integrally formed with each other to form the base layer BL.

[0079] The second portion PT2 can be a region that substantially forms a curvature. In the case of a bend in the display module DM, the third portion PT3 can be spaced apart from the first portion PT1 on the third directional axis DR3. The second portion PT2 of the base layer BL can be defined as a bend region BA. The length of the second portion PT2 of the base layer BL, measurable on the second directional axis DR2, can be varied as needed. The circuit layer CL can be arranged on the base layer BL and may include pixel driving circuitry and signal lines. For example, the circuit layer CL may include multiple transistors T1 to T7 (see...). Figure 4A ), capacitor CP (see Figure 4A ) and multiple lines SLi-1, SLi, SLi+1, DL, VL and PL (see Figure 4A ).

[0080] The circuit layer CL may overlap with the first portion PT1, the second portion PT2, and the third portion PT3 of the base layer BL. However, the configurations of the circuit layer CL corresponding to the first portion PT1, the second portion PT2, and the third portion PT3 may differ from each other. The circuit layer CL may include pixel driving circuitry arranged corresponding to the active area ACA of the first portion PT1 and signal lines arranged corresponding to the inactive area NACA of the first portion PT1. The circuit layer CL may also include signal lines arranged on different layers to correspond to the second portion PT2 and the third portion PT3.

[0081] The light-emitting element layer ELL can be disposed on the circuit layer CL and can overlap with the first portion PT1 of the base layer BL. The light-emitting element layer ELL may include electrical connections to a plurality of transistors T1 to T7 (see [link to documentation]). Figure 4A ) light-emitting element LD (see Figure 4A ).

[0082] The encapsulation layer TFE can be disposed on the light-emitting element layer ELL and can encapsulate the light-emitting element layer ELL. A portion of the encapsulation layer TFE can overlap with the non-active region NACA. Although not shown separately, other insulating layers may also be disposed between the light-emitting element layer ELL and the encapsulation layer TFE, or between the encapsulation layer TFE and the input sensor SP, to improve optical performance.

[0083] The input sensor SP can be arranged on the encapsulation layer TFE and can overlap with the first portion PT1 of the base layer BL. Figure 3 In one embodiment, the input sensor SP can be directly disposed on the encapsulation layer TFE; however, according to another embodiment, the input sensor SP can be attached to the encapsulation layer TFE via an adhesive member.

[0084] The input sensor SP may include a first sensor IE1 and a second sensor IE2. Each of the first sensor IE1 and the second sensor IE2 may include electrodes comprising a metallic material. Each of the first sensor IE1 and the second sensor IE2 may have a grid shape.

[0085] The first sensor IE1 can form a capacitance with the second sensor IE2. When a user touches the effective area ACA, the capacitance between the first sensor IE1 and the second sensor IE2 can change. The input sensing drive circuit TIC can sense the change in capacitance of the input sensor SP and determine which point of the effective area ACA the user has touched.

[0086] The configuration of the input sensor SP should not be subject to any particular restrictions. The display module DM may include a mutual capacitance driven input sensor with two sensors or a self-capacitance driven input sensor with one sensor. Input sensors that are not capacitive sensors may be used in the display module DM.

[0087] The data driver circuit DIC may overlap with the third portion PT3 of the base layer BL. For example, the data driver circuit DIC may be arranged (e.g., mounted) on the third portion PT3 of the base layer BL.

[0088] The data drive circuit DIC can be electrically connected to the pixel PX in the effective area ACA to provide data signals to the pixel PX.

[0089] The pad PD may include a first pad PD1 and a second pad PD2.

[0090] The first pad PD1 can transmit electrical signals to the pixel PX via the data drive circuit DIC. The first pad PD1 can be electrically connected to multiple transistors T1 to T7 of the pixel PX (see...). Figure 4A At least one of them.

[0091] The second pad PD2 can be electrically connected to the input sensor SP. Each of the plurality of second pads PD2 can be electrically connected to one of the first sensor IE1 and the second sensor IE2.

[0092] The printed circuit board (PCB) can be electrically connected to the pads (PD). The input sensing drive circuit (TIC) and the control drive circuit (CIC) can be mounted on the PCB.

[0093] The input sensing drive circuit TIC can use the second pad PD2 to sense changes in the capacitance of the input sensor SP. Accordingly, the input sensing drive circuit TIC can sense user touches applied to the effective area ACA and pressure applied to it from the outside.

[0094] The control drive circuit CIC can be a circuit used to control at least one of the data drive circuit DIC and the input sensing drive circuit TIC.

[0095] The portion of the display module DM corresponding to the second part PT2 (or the bending area BA) of the base layer BL can be bent.

[0096] Although not shown separately, the anti-reflective component can be arranged between the display module DM and the window component WM. The anti-reflective component can be a polarizing film or a polarizing plate.

[0097] Although not shown separately, the display module DM may also include a synthetic resin layer or synthetic resin film arranged to correspond to the bending region BA of the display module DM. The synthetic resin layer or synthetic resin film can reduce the stress on the signal lines arranged in the bending region BA.

[0098] Figure 4A This is a schematic circuit diagram illustrating a pixel PX according to an embodiment of the present disclosure. Figure 4B It shows that it is applied to Figure 4A A schematic timing diagram of the driving signals for pixel PX. Figure 4A A representative example is shown which pixel PX is electrically connected to the i-th scan line SLi, the (i+1)-th scan line SLi+1, and the i-th emission control line ECLi.

[0099] A pixel PX may include a light-emitting element (LD) and a pixel circuit CC. The pixel circuit CC may include multiple transistors T1 to T7 and a capacitor CP. The pixel circuit CC may control the amount of current flowing through the light-emitting element LD in response to a data signal.

[0100] The light-emitting element (LD) can emit light at a predetermined brightness, which corresponds to the amount of current supplied from the pixel circuit (CC). For this purpose, the potential of the first power supply voltage ELVDD can be set higher than the potential of the second power supply voltage ELVSS. The first power supply voltage ELVDD can be applied to the first power supply line PL.

[0101] Each of the plurality of transistors T1 to T7 may include a source, a drain, and a gate. The source, drain, and gate may be implemented in the form of electrodes, or may be implemented in a portion of a semiconductor pattern. Electrode-type source, drain, and gate may include metal patterns. Semiconductor-type source, drain, and gate may include conductive semiconductor regions, as they may have a high doping concentration. Regions that may be undoped or have a relatively low doping concentration may correspond to the active region of the transistor.

[0102] In this disclosure, for ease of explanation, one of the source and drain will be referred to as the "first electrode," and the other of the source and drain will be referred to as the "second electrode." The gate will be referred to as the "control electrode."

[0103] The first electrode of the first transistor T1 can be electrically connected to the first power supply line PL via the fifth transistor T5, and the second electrode of the first transistor T1 can be electrically connected to the anode of the light-emitting element LD via the sixth transistor T6. In this disclosure, the first transistor T1 may be referred to as a "driving transistor". The first transistor T1 can control the amount of current flowing through the light-emitting element LD in response to the voltage applied to its control electrode.

[0104] The second transistor T2 can be electrically connected between the data line DL and the first electrode of the first transistor T1. The control electrode of the second transistor T2 can be electrically connected to the i-th scan line SLi. When the i-th scan signal Si can be applied to the i-th scan line SLi, the second transistor T2 can be turned on to electrically connect the data line DL and the first electrode of the first transistor T1.

[0105] The third transistor T3 can be electrically connected between the second electrode and the control electrode of the first transistor T1. The control electrode of the third transistor T3 can be electrically connected to the i-th scan line SLi. When the i-th scan signal Si can be applied to the i-th scan line SLi, the third transistor T3 can be turned on to electrically connect the second electrode and the control electrode of the first transistor T1. Therefore, when the third transistor T3 can be turned on, the first transistor T1 can be electrically connected in a diode configuration.

[0106] The fourth transistor T4 can be electrically connected between the control node ND and the second power supply line VL. The control electrode of the fourth transistor T4 can be electrically connected to the (i-1)th scan line SLi-1. When the (i-1)th scan signal Si-1 can be applied to the (i-1)th scan line SLi-1, the fourth transistor T4 can be turned on to apply the initialization voltage Vint to the control node ND.

[0107] The fifth transistor T5 can be electrically connected between the first power supply line PL and the first electrode of the first transistor T1. The control electrode of the fifth transistor T5 can be electrically connected to the i-th light emission control line ECLi.

[0108] The sixth transistor T6 can be electrically connected between the second electrode of the first transistor T1 and the anode of the light-emitting element LD. The control electrode of the sixth transistor T6 can be electrically connected to the i-th light-emitting control line ECLi.

[0109] The seventh transistor T7 can be electrically connected between the second power line VL and the anode of the light-emitting element LD. The control electrode of the seventh transistor T7 can be electrically connected to the (i+1)th scan line SLi+1. When the (i+1)th scan signal Si+1 can be applied to the (i+1)th scan line SLi+1, the seventh transistor T7 can be turned on to apply the initialization voltage Vint to the anode of the light-emitting element LD.

[0110] Capacitor CP can be electrically connected between the first power line PL and the control node ND. Capacitor CP can be charged with a voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 can be turned on, the amount of current flowing through the first transistor T1 can be determined based on the charging voltage in capacitor CP.

[0111] Reference Figure 4B The light emission control signal Ei can have a high level E-HIGH or a low level E-LOW. Each of the multiple scan signals Si-1, Si, and Si+1 can have a high level S-HIGH or a low level S-LOW.

[0112] When the light emission control signal Ei has a high level (E-HIGH), the fifth transistor T5 and the sixth transistor T6 can be turned off. When the fifth transistor T5 is turned off, the first power supply line PL and the first electrode of the first transistor T1 can be electrically disconnected from each other. When the sixth transistor T6 is turned off, the second electrode of the first transistor T1 and the anode of the light-emitting element LD can be electrically disconnected from each other. Therefore, during the period when the light emission control signal Ei with a high level (E-HIGH) is applied to the i-th light emission control line ECLi, the light-emitting element LD may not emit light.

[0113] When the (i-1)th scan signal Si-1 applied to the (i-1)th scan line SLi-1 has a low level S-LOW, the fourth transistor T4 can be turned on. When the fourth transistor T4 can be turned on, the initialization voltage Vint can be applied to the control node ND.

[0114] When the i-th scan signal Si applied to the i-th scan line SLi has a low level S-LOW, the second transistor T2 and the third transistor T3 can be turned on. When the (i+1)-th scan signal Si+1 applied to the (i+1)-th scan line SLi+1 has a low level S-LOW, the seventh transistor T7 can be turned on.

[0115] With the second transistor T2 turned on, a data signal can be applied to the first electrode of the first transistor T1. Since the control node ND can be initialized to the initialization voltage Vint, the first transistor T1 can be turned on. With the first transistor T1 turned on, a voltage corresponding to the data signal can be applied to the control node ND. The capacitor CP can be charged with the voltage corresponding to the data signal.

[0116] With the seventh transistor T7 turned on, the initialization voltage Vint can be applied to the anode of the light-emitting element LD, and thus the parasitic capacitance of the light-emitting element LD can be released.

[0117] When the light emission control signal Ei applied to the i-th light emission control line ECLi is at a low level (E-LOW), the fifth transistor T5 and the sixth transistor T6 can be turned on. When the fifth transistor T5 is turned on, the first power supply voltage ELVDD can be supplied to the first electrode of the first transistor T1. When the sixth transistor T6 is turned on, the second electrode of the first transistor T1 and the anode of the light-emitting element LD can be electrically connected to each other. The light-emitting element LD can generate light with a predetermined brightness corresponding to the amount of current supplied to it.

[0118] Figure 4A A pixel PX implemented using a PMOS transistor is shown as a representative example; however, the implementation should not be limited thereto or thereby restricted. According to another embodiment of this disclosure, the pixel PX may be implemented using an NMOS transistor. According to yet another embodiment of this disclosure, the pixel PX may be implemented using a combination of NMOS and PMOS transistors.

[0119] In this disclosure, the structure of the pixel PX should not be limited to Figure 4A The structure shown is illustrated. According to another embodiment of this disclosure, the pixel PX can be implemented in various ways to allow the light-emitting element LD to emit light. In embodiments of this disclosure, the light-emitting element LD can be an organic light-emitting element, a micro LED, or a light-emitting element using quantum dots.

[0120] Figure 5A It is shown that... Figure 4A A schematic diagram of the layout of pixels PX corresponding to the schematic circuit diagram. Figure 5B This is a schematic plan view showing the conductive pattern included in the third conductive layer GMP3. Figure 6A and Figure 6B This is a schematic cross-sectional view showing a display panel DP according to an embodiment of the present disclosure. Figure 6A and Figure 6B Each part includes the effective region ACA and the ineffective region NACA. Figure 6B A cross-section overlapping the signal line in the bending region BA is shown, and Figure 6A A cross-section is shown that does not overlap with the signal line in the bending region BA.

[0121] Reference Figure 5A The diagram shows the first transistor T1 to the seventh transistor T7 of pixel PX. It also shows multiple scan lines SLi-1, SLi and SLi+1, the i-th light emission control line ECLi, the first power line PL, and the second power line VL. Figure 5A It shows the process from the base layer BL to... Figure 6A The stacked structure of the fifth conductive layer DMP2.

[0122] Reference Figure 6AThe circuit layer CL may include a first buffer layer BFL1, a second buffer layer BFL2, a first insulating layer GI1, a second insulating layer GI2, a third insulating layer ILD1, a fourth insulating layer ILD2, a fifth insulating layer VIA1, a sixth insulating layer VIA2, a patterned semiconductor layer ACP, a patterned first conductive layer GMP1, a patterned second conductive layer GMP2, a patterned third conductive layer GMP3, a patterned fourth conductive layer DMP1, and a patterned fifth conductive layer DMP2.

[0123] The first transistors T1 to the seventh transistor T7 of pixel PX, multiple scan lines SLi-1, SLi and SLi+1, the i-th light-emitting control line ECLi, the first power line PL and the second power line VL can be formed by conductive patterns of the first conductive layer GMP1, the second conductive layer GMP2, the third conductive layer GMP3, the fourth conductive layer DMP1 and the fifth conductive layer DMP2 forming the circuit layer CL, and the semiconductor pattern of the semiconductor layer ACP. Figure 5A As a representative example, a pixel PX is shown, comprising two fourth transistors T4 electrically connected in series with each other.

[0124] Figure 5B A second power line VL is shown included in the third conductive layer GMP3. The third conductive layer GMP3 may also include another conductive pattern. The second power line VL corresponds to a conductive pattern included in the third conductive layer GMP3, and since the conductive pattern with a line shape receives the initialization voltage Vint, this conductive pattern can be named the second power line VL.

[0125] In embodiments of this disclosure, the line pattern that does not receive the initialization voltage Vint can be arranged in the same form as the second power line VL. The line pattern can overlap with some transistors (e.g., the fourth transistor T4 and the seventh transistor T7) to block external light from entering the transistors. Accordingly, the voltage-current characteristics of the transistors can be prevented from being altered by external light.

[0126] The first insulating layer GI1 can be a first gate insulating layer, the second insulating layer GI2 can be a second gate insulating layer, the third insulating layer ILD1 can be a first interlayer insulating layer, the fourth insulating layer ILD2 can be a second interlayer insulating layer, the fifth insulating layer VIA1 can be a first through layer, the sixth insulating layer VIA2 can be a second through layer, the first conductive layer GMP1 can be a first gate metal pattern, the second conductive layer GMP2 can be a second gate metal pattern, the third conductive layer GMP3 can be a third gate metal pattern, the fourth conductive layer DMP1 can be a first data metal pattern, and the fifth conductive layer DMP2 can be a second data metal pattern. However, the implementation should not be limited to this or thereby restricted.

[0127] In embodiments of this disclosure, each of the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2 may include an organic layer and / or an inorganic layer. In embodiments of this disclosure, each of the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2 may include multiple inorganic thin layers. The multiple inorganic thin layers may include a silicon nitride layer and a silicon oxide layer.

[0128] In embodiments of this disclosure, each of the first through layer VIA1 and the second through layer VIA2 may include an organic material. In embodiments of this disclosure, each of the first gate metal pattern GMP1, the second gate metal pattern GMP2, and the third gate metal pattern GMP3 may include molybdenum (Mo); however, embodiments should not be limited thereto or thereby restricted.

[0129] In embodiments of this disclosure, each of the first data metal pattern DMP1 and the second data metal pattern DMP2 may include at least one of aluminum (Al) and titanium (Ti); however, embodiments should not be limited thereto or thereby restricted. In embodiments of this disclosure, each of the first data metal pattern DMP1 and the second data metal pattern DMP2 may have a stacked structure in which titanium, aluminum, and titanium may be stacked (e.g., stacked sequentially).

[0130] A first buffer layer BFL1 may be disposed on a base layer BL. A second buffer layer BFL2 may be disposed on the first buffer layer BFL1. Each of the first buffer layer BFL1 and the second buffer layer BFL2 prevents impurities present in the base layer BL from entering the pixel PX. In particular, each of the first buffer layer BFL1 and the second buffer layer BFL2 prevents impurities from diffusing to the semiconductor layers ACP of the plurality of transistors T1 to T7 of the pixel PX.

[0131] Impurities can be introduced from the outside or caused by the thermal decomposition of the base layer BL. Impurities can be sodium or gas emitted from the base layer BL. Each of the first buffer layer BFL1 and the second buffer layer BFL2 prevents moisture from entering the pixel PX. According to another embodiment of this disclosure, at least one of the first buffer layer BFL1 and the second buffer layer BFL2 may be omitted.

[0132] The semiconductor layer ACP may be disposed on the second buffer layer BFL2. The semiconductor layer ACP may form each of a plurality of transistors T1 to T7. The semiconductor layer ACP may comprise polycrystalline silicon, amorphous silicon, metal-oxide-semiconductor, or combinations thereof. Figure 6ASemiconductor patterns for forming the source S1, active region A1, and drain D1 of a first transistor T1 are shown, as well as semiconductor patterns for forming the source S2, active region A2, and drain D2 of a second transistor T2. Figure 6B In the diagram, two semiconductor patterns are shown as spaced apart from each other; however, as... Figure 5A As shown, the two semiconductor patterns may have an integral shape in a plan view. A first gate insulating layer GI1 may be disposed on the second buffer layer BFL2 and may cover the semiconductor layer ACP. A first gate metal pattern GMP1 may be disposed on the first gate insulating layer GI1. The gate G1 of the first transistor T1 and the gate G2 of the second transistor T2 are shown as the first gate metal pattern GMP1. Although not shown separately, the first gate metal pattern GMP1 may include one of the two electrodes of the capacitor CP forming the pixel PX.

[0133] A second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1 and may cover the first gate metal pattern GMP1. A second gate metal pattern GMP2 may be disposed on the second gate insulating layer GI2. The second gate metal pattern GMP2 may be the other electrode of the two electrodes forming the capacitor CP. The upper electrode UE is shown as the second gate metal pattern GMP2. The opening UE-OP may be defined by the upper electrode UE.

[0134] A first interlayer insulating layer ILD1 may be disposed on the second gate insulating layer GI2 and may cover the second gate metal pattern GMP2. A third gate metal pattern GMP3 may be disposed on the first interlayer insulating layer ILD1. As a representative example, two connection electrodes CNE-G3 are shown as the third gate metal pattern GMP3. One connection electrode CNE-G3 may be electrically connected to the gate G1 of the first transistor T1 through a contact hole CH10 defined by the second gate insulating layer GI2 and the first interlayer insulating layer ILD1. The contact hole CH10 may pass through the opening UE-OP. The other connection electrode CNE-G3 may be electrically connected to the source S2 of the second transistor T2 through a contact hole CH20 defined by the first gate insulating layer GI1, the second gate insulating layer GI2, and the first interlayer insulating layer ILD1. Although not shown in Figure 6AAs shown, however, the third gate metal pattern GMP3 may include a second power line VL. A second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1 and may cover the third gate metal pattern GMP3. A first data metal pattern DMP1 may be disposed on the second interlayer insulating layer ILD2. Two connection electrodes CNE-D1 are shown as the first data metal pattern DMP1. The two connection electrodes CNE-D1 may be electrically connected to the two connection electrodes CNE-G3 respectively through a plurality of contact holes CH11 and CH21 defined through the second interlayer insulating layer ILD2. The connection electrode CNE-G3 of the third gate metal pattern GMP3 may be omitted, and in this case, the two connection electrodes CNE-D1 of the first data metal pattern DMP1 may be connected to the gate G1 of the first transistor T1 and the source S2 of the second transistor T2 respectively.

[0135] A first through-layer VIA1 may be disposed on a second interlayer insulating layer ILD2 and may cover a first data metal pattern DMP1. A second data metal pattern DMP2 may be disposed on the first through-layer VIA1. As a representative example, a connection electrode CNE-D2 is shown as the second data metal pattern DMP2. The connection electrode CNE-D2 may be connected to the connection electrode CNE-D1 through a contact hole CH22 defined by the first through-layer VIA1.

[0136] The second through layer VIA2 may be disposed on the first through layer VIA1 and may cover the second data metal pattern DMP2. The light-emitting element layer ELL may include a light-emitting element LD and a pixel defining layer PDL. The light-emitting element LD may include an anode AE, a light-emitting layer EML, and a cathode CE.

[0137] An anode AE ​​may be disposed on a second through layer VIA2. The anode AE ​​may be electrically connected to a second data metal pattern DMP2 via contact holes. A pixel defining layer PDL may be disposed on the second through layer VIA2 and may expose at least a portion of the anode AE. A light-emitting layer EML may be disposed on the anode AE. A cathode CE may be disposed on the light-emitting layer EML.

[0138] When the light-emitting element LD is an organic light-emitting diode (OLED), the light-emitting layer EML may include organic materials. According to another embodiment of this disclosure, when the light-emitting element LD is a micro-LED, the light-emitting layer EML may include inorganic materials. An encapsulation layer TFE may encapsulate the light-emitting element layer ELL to protect it from external oxygen or moisture. The encapsulation layer TFE may be a layer obtained by stacking organic and inorganic layers.

[0139] Reference Figure 6A and Figure 6BIn the non-effective NACA region, the signal line LNC can be arranged according to the region. The signal line LNC can be the second data metal pattern DMP2.

[0140] The first buffer layer BFL1, the second buffer layer BFL2, the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2 may not be arranged in the portion corresponding to the bending region BA. Figure 6A and Figure 6B In this design, the opening OP can be formed from the first buffer layer BFL1 to the second interlayer insulating layer ILD2. The opening OP can overlap with or correspond to the bending region BA. An opening OP defined by two stepped portions is shown. When the opening OP is defined by two stepped portions, the inclined surface defining the opening OP can be stepped.

[0141] Since only the first through layer VIA1 and the second through layer VIA2 can be arranged in the portion corresponding to the bending region BA, the flexibility of the bending region BA can be improved.

[0142] Figure 7A It is shown Figure 2 A magnified schematic view of area AA. Figure 7B It is along Figure 7A A schematic cross-sectional view taken by line I-I'. Figure 7C and Figure 7D It is along Figure 7A A schematic cross-sectional view taken from line II-II'. Figure 8A , Figure 8B , Figure 8C and Figure 8D It is illustrated schematically through each layer. Figure 7A The view shows multiple lines STF, LNC, and STR.

[0143] Multiple front signal lines (STFs) can be arranged on the first portion (PT1) of the base layer (BL). These STFs can be electrically connected to multiple pixels (PXs). The STFs may include a first front signal line (STF1), a second front signal line (STF2), and a third front signal line (STF3). These STFs can be arranged on different layers. The portion containing the STFs may be referred to as the spider web section. Multiple rear signal lines (STRs) can be arranged on the third portion (PT3) of the base layer (BL). These STRs can be electrically connected to the data drive circuit (DIC). These STRs may include a first rear signal line (STR1), a second rear signal line (STR2), and a third rear signal line (STR3). These STRs can be arranged on different layers. Multiple connection lines (LNCs) (or connection signal lines) can be arranged on the second portion (PT2) of the base layer (BL) to electrically connect the STFs and STRs. Multiple connection lines LNC may include a first connection line LNC1, a second connection line LNC2, and a third connection line LNC3.

[0144] Multiple front signal lines (STF) and multiple rear signal lines (STR) may comprise a first metallic material, and multiple connection lines (LNC) may comprise a second metallic material. The first metallic material may have a resistivity greater than that of the second metallic material. The first metallic material may comprise molybdenum (Mo). The second metallic material may comprise at least one of aluminum (Al) and titanium (Ti).

[0145] Reference Figure 7B and Figure 8A The first front signal line STF1 and the first rear signal line STR1 can be arranged on the same layer. The first front signal line STF1 and the first rear signal line STR1 can be arranged on the same layer as the first gate metal pattern GMP1.

[0146] The first front signal line STF1 may include a line portion LNF1 and a pad portion PDF1. The first rear signal line STR1 may include a line portion LNR1 and a pad portion PDR1.

[0147] Reference Figure 7B and Figure 8B The second front signal line STF2 and the second rear signal line STR2 can be arranged on the same layer. The second front signal line STF2 and the second rear signal line STR2 can be arranged on the same layer as the second gate metal pattern GMP2.

[0148] The second front signal line STF2 may include a line portion LNF2 and a pad portion PDF2. The second rear signal line STR2 may include a line portion LNR2 and a pad portion PDR2.

[0149] ReferenceFigure 7B and Figure 8C The third front signal line STF3 and the third rear signal line STR3 can be arranged on the same layer. The third front signal line STF3 and the third rear signal line STR3 can be arranged on the same layer as the third gate metal pattern GMP3.

[0150] Each of the plurality of third front signal lines STF3 may include a line portion LNF3 and a pad portion PDF3. Each of the plurality of third rear signal lines STR3 may include a line portion LNR3 and a pad portion PDR3.

[0151] Reference Figure 8D Multiple connection lines LNC can be arranged on the same layer as the second data metal pattern DMP2; however, the implementation should not be limited thereto or thereby restricted. According to another embodiment of this disclosure, multiple connection lines LNC can be arranged on the same layer as the first data metal pattern DMP1.

[0152] like Figure 7A and Figure 7C As shown, the first connecting line LNC1 can be connected to the first front signal line STF1 through contact hole CTH, and can also be electrically connected to the third rear signal line STR3 through contact hole CTH. Figure 7C As shown, the first connection line LNC1 can be connected to the contact hole CTH of the first front signal line STF1, which penetrates from the second gate insulating layer GI2 to the first through layer VIA1. The first connection line LNC1 can be connected to the contact hole CTH of the third rear signal line STR3, which penetrates from the second interlayer insulating layer ILD2 to the first through layer VIA1. The second connection line LNC2 can be electrically connected to the second front signal line STF2 and the second rear signal line STR2 through the contact hole CTH. The third connection line LNC3 can be electrically connected to the third front signal line STF3 and the first rear signal line STR1 through the contact hole CTH.

[0153] like Figure 7DAs shown, the first connection line LNC1 can be connected to the first front signal line STF1 via the connection electrode CNE-D1, and can also be connected to the third rear signal line STR3 via the connection electrode CNE-D1. One connection electrode CNE-D1 can be connected to the first front signal line STF1 via a contact hole CH30 defined from the second gate insulating layer GI2 to the second interlayer insulating layer ILD2, while the other connection electrode CNE-D1 can be connected to the third rear signal line STR3 via a contact hole CH40 defined through the second interlayer insulating layer ILD2. The first connection line LNC1 can be connected to the two connection electrodes CNE-D1 via a plurality of contact holes CH31 and CH41 defined through the first through layer VIA1. The number of the plurality of contact holes CH30, CH31, CH40 and CH41 should not be particularly limited, and each of the plurality of contact holes CH30, CH31, CH40 and CH41 can be set to an odd number or a plural number.

[0154] Multiple front signal lines (STFs) may have different widths and / or different thicknesses. For example, in a direction substantially parallel to the first direction axis DR1, some signal lines arranged on the outer side of the multiple front signal lines (STFs) may have a larger width or a larger thickness than some signal lines arranged on the inner side of the multiple front signal lines (STFs).

[0155] Multiple rear signal lines STR may have different widths and / or different thicknesses. For example, in a direction substantially parallel to the first direction axis DR1, some signal lines arranged on the outer side of the multiple rear signal lines STR may have a larger width or a larger thickness than some signal lines arranged on the inner side of the multiple rear signal lines STR.

[0156] Multiple connection lines (LNCs) may have different widths and / or different thicknesses. For example, in a direction substantially parallel to the first direction axis DR1, the signal lines arranged on the outer side of the multiple connection lines (LNCs) may have a larger width or a larger thickness than the signal lines arranged on the inner side of the multiple connection lines (LNCs).

[0157] Since the signal lines placed on the outer side are longer than those placed on the inner side, the resistance difference between multiple signal lines can be reduced by allowing the signal lines placed on the outer side to have a larger width and thickness than those placed on the inner side.

[0158] Figure 9 It is shown schematically. Figure 2 A magnified view of region AA. Figure 10A , Figure 10B , Figure 10C and Figure 10D It is illustrated schematically through each layer. Figure 9The view shows the multiple lines STF-1, LNC-1 and STR-1.

[0159] Multiple front signal lines STF-1 can be arranged on the first part PT1 of the base layer BL. The multiple front signal lines STF-1 may include a first front signal line STF1-1, a second front signal line STF2-1, and a third front signal line STF3-1. The first front signal line STF1-1, the second front signal line STF2-1, and the third front signal line STF3-1 can be arranged on different layers.

[0160] Multiple front signal lines STF-1 can be electrically connected to multiple pixel PXs.

[0161] Multiple rear signal lines STR-1 may be arranged on the third part PT3 of the base layer BL. The multiple rear signal lines STR-1 may include a second rear signal line STR2-1 and multiple third rear signal lines STR3-1 and STR3-2. The multiple third rear signal lines STR3-1 and STR3-2 may include a first group of lines STR3-1 and a second group of lines STR3-2.

[0162] The second rear signal line STR2-1 and multiple third rear signal lines STR3-1 and STR3-2 can be arranged on different layers.

[0163] Multiple rear signal lines STR-1 can be electrically connected to the data drive circuit DIC.

[0164] Multiple connection lines LNC-1 can be arranged on the second part PT2 of the base layer BL to electrically connect multiple front signal lines STF-1 and multiple rear signal lines STR-1. The multiple connection lines LNC-1 may include a first connection line LNC1-1, a second connection line LNC2-1, and a third connection line LNC3-1.

[0165] Reference Figure 10A The first front signal line STF1-1 can be arranged on the same layer as the first gate metal pattern GMP1.

[0166] Each of the plurality of first front signal lines STF1-1 may include a line portion LNF1-1 and a pad portion PDF1-1.

[0167] Reference Figure 10B The second front signal line STF2-1 and the second rear signal line STR2-1 can be arranged on the same layer as each other. The second front signal line STF2-1 and the second rear signal line STR2-1 can be arranged on the same layer as the second gate metal pattern GMP2.

[0168] The second front signal line STF2-1 may include a line portion LNF2-1 and a pad portion PDF2-1. The second rear signal line STR2-1 may include a line portion LNR2-1 and a pad portion PDR2-1.

[0169] Reference Figure 10C The third front signal line STF3-1 and multiple third rear signal lines STR3-1 and STR3-2 can be arranged on the same layer as each other. The third front signal line STF3-1 and multiple third rear signal lines STR3-1 and STR3-2 can be arranged on the same layer as the third gate metal pattern GMP3.

[0170] The third front signal line STF3-1 may include a line portion LNF3-1 and a pad portion PDF3-1. The first group of lines STR3-1 may include a line portion LNR3-1 and a pad portion PDR3-1. The second group of lines STR3-2 may include a line portion LNR3-2 and a pad portion PDR3-2.

[0171] Reference Figure 10D The connecting line LNC-1 may be arranged on the same layer as the second data metal pattern DMP2; however, the implementation should not be limited thereto or thereby restricted. According to another embodiment of this disclosure, the connecting line LNC-1 may be arranged on the same layer as the first data metal pattern DMP1.

[0172] The first connecting line LNC1-1 can be electrically connected to the first front signal line STF1-1 and the second rear signal line STR2-1 through the contact hole CTH. For example, the first connecting line LNC1-1 can be electrically connected to the first front signal line STF1-1 and the second rear signal line STR2-1.

[0173] The second connecting line LNC2-1 can be electrically connected to the second front signal line STF2-1 and the first group of lines STR3-1 through the contact hole CTH. For example, the second connecting line LNC2-1 can be electrically connected to the second front signal line STF2-1 and the first group of lines STR3-1.

[0174] The third connecting line LNC3-1 can be electrically connected to the third front signal line STF3-1 and the second group line STR3-2 via the contact hole CTH. For example, the third connecting line LNC3-1 can be electrically connected to the third front signal line STF3-1 and the second group line STR3-2.

[0175] Figure 11 It is shown schematically. Figure 2 A magnified view of area BB.

[0176] Multiple subsequent signal lines STR may include multiple resistance control units RCP. The resistance control unit RCP may be a signal line with a sawtooth shape.

[0177] The density of the serrated pattern of the resistor control unit RCP arranged on the outer side among the multiple resistor control units RCP can be less than the density of the serrated pattern of the resistor control unit RCP arranged on the inner side among the multiple resistor control units RCP.

[0178] Since the signal lines arranged on the outer side can be longer than the signal lines arranged on the inner side, the resistance difference between multiple signal lines can be reduced by allowing the density of the sawtooth pattern of the resistance control section of the signal lines arranged on the outer side to be relatively low.

[0179] While embodiments of this disclosure have been described, it is understood that this disclosure should not be limited to these embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of this disclosure as claimed below. Therefore, the subject matter disclosed should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined by the appended claims, which include any equivalents.

Claims

1. A display device, comprising: A base layer, the base layer comprising a first portion, a second portion extending from the first portion, and a third portion extending from the second portion; A plurality of light-emitting elements, including a first light-emitting element, a second light-emitting element, and a third light-emitting element, wherein the plurality of light-emitting elements are arranged on the first portion; A first front signal line is arranged on the first portion and electrically connected to the first light-emitting element; The second front signal line is arranged on the first portion and electrically connected to the second light-emitting element, wherein the first front signal line and the second front signal line are arranged on different layers; The third front signal line is electrically connected to the third light-emitting element, wherein the first front signal line, the second front signal line and the third front signal line are arranged on different layers; The first rear signal line is arranged on the third part, wherein the first rear signal line and the first front signal line are arranged on the same layer; The second rear signal line is arranged on the third part, wherein the second rear signal line and the second front signal line are arranged on the same layer; A third rear signal line, the third rear signal line being arranged on the third portion, wherein the third rear signal line and the third front signal line are arranged on the same layer; and Multiple connecting lines, which overlap with the second portion. The plurality of connecting lines include: The first connecting line is electrically connected to the first front signal line and the third rear signal line; A second connecting line, the second connecting line being electrically connected to the second front signal line and the second rear signal line; and The third connecting line is electrically connected to the third front signal line and the first rear signal line.

2. The display device as claimed in claim 1, wherein, The second part of the base layer is bent.

3. The display device as claimed in claim 2, further comprising: A data driving circuit is disposed on the third portion of the base layer, wherein the data driving circuit is electrically connected to the first rear signal line, the second rear signal line and the third rear signal line.

4. The display device as claimed in claim 2, wherein, Each of the first front signal line, the second front signal line, the third front signal line, the first rear signal line, the second rear signal line, and the third rear signal line comprises a first metallic material, and Each of the plurality of connecting lines includes a second metal material that is different from the first metal material.

5. The display device as claimed in claim 4, wherein, The first metallic material has a resistivity that is greater than that of the second metallic material.

6. The display device as claimed in claim 4, wherein, The first metallic material includes molybdenum, and the second metallic material includes aluminum.

7. The display device as claimed in claim 2, wherein, Each of the first front signal line, the second front signal line, and the third front signal line is configured as multiple, and Some of the first front signal lines, the second front signal lines, and the third front signal lines arranged on the outer side have a width greater than that of some of the first front signal lines, the second front signal lines, and the third front signal lines arranged on the inner side.

8. The display device as claimed in claim 7, wherein, The front signal lines arranged on the outer side have a greater thickness than the front signal lines arranged on the inner side.

9. The display device as claimed in claim 2, wherein, Each of the first, second, and third rear signal lines is configured as multiple, and Some of the first, second, and third rear signal lines arranged on the outer side have a width greater than that of some of the first, second, and third rear signal lines arranged on the inner side.

10. The display device as claimed in claim 9, wherein, The rear signal lines arranged on the outer side have a greater thickness than the rear signal lines arranged on the inner side.

11. The display device as claimed in claim 2, wherein, Some of the connecting lines located on the outer side have a width greater than that of some of the connecting lines located on the inner side.

12. The display device as claimed in claim 11, wherein, The connecting lines arranged on the outer side have a greater thickness than the connecting lines arranged on the inner side.

13. The display device as claimed in claim 1, further comprising: A plurality of transistors are arranged on the first portion of the base layer and electrically connected to the plurality of light-emitting elements; as well as A power line that provides an initialization voltage to the plurality of transistors, wherein the power line and the third front signal line are arranged on the same layer.

14. The display device as claimed in claim 1, further comprising: A first insulating layer covers the first front signal line and the first rear signal line, and the first insulating layer is disposed below the second front signal line and the second rear signal line; A second insulating layer covers the second front signal line and the second rear signal line, and the second insulating layer is disposed below the third front signal line and the third rear signal line; as well as A third insulating layer covers the third front signal line and the third rear signal line, and the third insulating layer is disposed below the connecting line.

15. The display device of claim 14, further comprising: Multiple contact holes, wherein the multiple contact holes are defined to pass through the first insulating layer, the second insulating layer, and the third insulating layer. The first front signal line, the second front signal line, the third front signal line, the first rear signal line, the second rear signal line, and the third rear signal line are electrically connected to the plurality of connecting lines through the plurality of contact holes.

16. A display device, comprising: A base layer, the base layer comprising a first portion, a second portion extending from the first portion, and a third portion extending from the second portion; Multiple light-emitting elements are arranged on the first portion; A plurality of first front signal lines, the plurality of first front signal lines being electrically connected to at least one of the plurality of light-emitting elements and arranged on the first portion; A plurality of second front signal lines, the plurality of second front signal lines being electrically connected to at least one of the plurality of light-emitting elements and arranged on the first portion, wherein the plurality of first front signal lines are arranged on a different layer than the layer on which the plurality of second front signal lines are arranged; A plurality of third front signal lines, the plurality of third front signal lines being electrically connected to at least one of the plurality of light-emitting elements and being arranged on a different layer from the layer on which the plurality of first front signal lines are arranged and the layer on which the plurality of second front signal lines are arranged; A plurality of second rear signal lines are arranged on the third portion and on the same layer as the layer on which the plurality of second front signal lines are arranged. A plurality of third rear signal lines, the plurality of third rear signal lines being arranged on the third portion and on the same layer as the layer on which the plurality of third front signal lines are arranged; and Multiple connecting lines electrically connect the multiple first front signal lines to the multiple second rear signal lines, and electrically connect the multiple second front signal lines and the multiple third front signal lines to the multiple third rear signal lines.

17. The display device as claimed in claim 16, wherein, The second part of the base layer is bent.

18. The display device of claim 17, further comprising: A data driving circuit is disposed on the third portion of the base layer, wherein the data driving circuit is electrically connected to the plurality of second rear signal lines and the plurality of third rear signal lines.

19. The display device as claimed in claim 17, wherein, Each of the plurality of first front signal lines, the plurality of second front signal lines, the plurality of third front signal lines, the plurality of second rear signal lines, and the plurality of third rear signal lines includes a first metallic material, and Each of the plurality of connecting lines includes a second metal material that is different from the first metal material.

20. The display device as claimed in claim 19, wherein, The first metallic material has a resistivity that is greater than that of the second metallic material.

21. The display device as claimed in claim 19, wherein, The first metallic material includes molybdenum, and the second metallic material includes aluminum.

22. The display device as claimed in claim 17, wherein, Some of the plurality of first front signal lines, the plurality of second front signal lines, and the plurality of third front signal lines arranged on the outer side have a width greater than the width of some of the plurality of first front signal lines, the plurality of second front signal lines, and the plurality of third front signal lines arranged on the inner side; or Some of the first front signal lines, the second front signal lines, and the third front signal lines arranged on the outer side have a thickness greater than that of some of the first front signal lines, the second front signal lines, and the third front signal lines arranged on the inner side.

23. The display device as claimed in claim 17, wherein, Some of the second and third rear signal lines arranged on the outer side have a width greater than that of some of the second and third rear signal lines arranged on the inner side. or Some of the second and third rear signal lines arranged on the outer side have a thickness greater than that of some of the second and third rear signal lines arranged on the inner side.

24. The display device as claimed in claim 17, wherein, Some of the connecting lines located on the outer side have a width greater than that of some of the connecting lines located on the inner side. or Some of the connecting lines located on the outer side have a greater thickness than some of the connecting lines located on the inner side.

25. The display device of claim 16, further comprising: A plurality of transistors are arranged on the first portion of the base layer and electrically connected to the plurality of light-emitting elements; as well as A power line that provides an initialization voltage to the plurality of transistors, wherein the power line and the plurality of third front signal lines are arranged on the same layer.

26. The display device of claim 16, further comprising: A first insulating layer covers the plurality of first front signal lines and is disposed below the plurality of second front signal lines and the plurality of second rear signal lines; A second insulating layer covers the plurality of second front signal lines and the plurality of second rear signal lines, and the second insulating layer is disposed below the plurality of third front signal lines and the plurality of third rear signal lines; as well as A third insulating layer covers the plurality of third front signal lines and the plurality of third rear signal lines, and the third insulating layer is disposed below the plurality of connecting lines.

27. The display device of claim 26, further comprising: Multiple contact holes, wherein the multiple contact holes are defined to pass through the first insulating layer, the second insulating layer, and the third insulating layer. The plurality of first front signal lines, the plurality of second front signal lines, the plurality of third front signal lines, the plurality of second rear signal lines, and the plurality of third rear signal lines are electrically connected to the plurality of connecting lines through the plurality of contact holes.

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