Display device

Abstract

A display device includes a first substrate, an insulating layer, a plurality of display elements, a plurality of first spacers, and a second substrate. The first substrate includes a transmission region, a display region surrounding at least a portion of the transmission region, and a first non-display region placed between the transmission region and the display region. The insulating layer is arranged on the first substrate in the display region and the first non-display region. The plurality of display elements is provided on the insulating layer in the display region. The plurality of first spacers each has an island shape and is spaced apart from each other on the insulating layer in the first non-display region. The second substrate faces the first substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0108939, filed on September 3, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of this disclosure relate to display devices, and more specifically, to display devices including a transmissive region. Background Technology

[0004] The applications of display devices have recently become more diversified. Furthermore, as display devices become thinner and lighter, their uses have expanded to a wide range of electronic products. Simultaneously, as the display area of ​​a display device increases, various applications or functions associated with the display device can be added. To increase the display area and add various functions, display devices with areas within the display area for adding various functions other than image display have been researched. Summary of the Invention

[0005] Exemplary embodiments of this disclosure include a high-quality display device that includes a transmissive area within the display area capable of transmitting light, serving as an area for adding various functions. However, these exemplary embodiments are merely examples, and the scope of this disclosure is not limited thereto.

[0006] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the exemplary embodiments presented in this disclosure.

[0007] According to an exemplary embodiment of this disclosure, a display device includes a first substrate, an insulating layer, a plurality of display elements, a plurality of first spacers, and a second substrate. The first substrate includes a transmissive region, a display region surrounding at least a portion of the transmissive region, and a first non-display region disposed between the transmissive region and the display region. An insulating layer is disposed on the first substrate in the display region and the first non-display region. The plurality of display elements are disposed on the insulating layer in the display region. The plurality of first spacers each have an island shape and are spaced apart from each other on the insulating layer in the first non-display region. The second substrate faces the first substrate.

[0008] The insulating layer may include at least one inorganic insulating layer and at least one organic insulating layer, and the at least one organic insulating layer may be on at least one inorganic insulating layer.

[0009] Each of the plurality of display elements may include a first electrode, a second electrode facing the first electrode, and an emission layer disposed between the first electrode and the second electrode, and a pixel defining layer disposed between the first electrodes of the plurality of display elements may be arranged on at least one organic insulating layer.

[0010] Multiple first spacers may be arranged on a pixel-defining layer in a first non-display area.

[0011] The second electrode may cover the pixel-defining layer and multiple first spacers.

[0012] Multiple first spacers may include organic insulating materials.

[0013] The display device may further include a second spacer disposed on an insulating layer in the first non-display area and having a ring shape surrounding the transmissive area.

[0014] The second spacer may be placed adjacent to the transmission area, and a plurality of first spacers may be arranged around the second spacer.

[0015] The second spacer may include organic insulating material.

[0016] The display device may further include a plurality of third spacers placed on an insulating layer in the display area, each having an island shape and arranged between a plurality of display elements.

[0017] The display device may further include a sealant that connects the first substrate to the second substrate and is disposed on the first substrate in a second non-display area surrounding the display area.

[0018] The display device may further include a metal layer provided on a second substrate and overlapping with a plurality of first spacers.

[0019] The second substrate may have a groove positioned to correspond to the transmission region, and the groove is formed as a recessed region of the second substrate on the surface facing the first substrate.

[0020] According to an exemplary embodiment of this disclosure, a display device includes a first substrate, a first electrode, an insulating layer, a plurality of first spacers, an emissive layer, and a second electrode. The first substrate includes a transmissive region, a display region surrounding at least a portion of the transmissive region, and a first non-display region disposed between the transmissive region and the display region. The first electrode is disposed in the display region on the first substrate. The insulating layer is disposed in the display region and the first non-display region on the first substrate, and includes an opening exposing a portion of the first electrode in the display region and a through-hole corresponding to the transmissive region. The plurality of first spacers are disposed on the insulating layer in the first non-display region, each having an island shape, and are arranged around the through-hole along its circumference. The emissive layer is disposed within an opening in the insulating layer. The second electrode faces the first electrode in the display region and covers the plurality of first spacers in the first non-display region.

[0021] Multiple first spacers may include organic insulating materials.

[0022] The display device may further include a second spacer disposed on an insulating layer in a first non-display area and having a ring shape surrounding a transmissive area, wherein the second spacer may be between a through-hole and a plurality of first spacers.

[0023] The second spacer may include organic insulating material.

[0024] The display device may further include a second substrate facing the first substrate.

[0025] The display device may further include a metal layer provided on a second substrate and overlapping with a plurality of first spacers.

[0026] The second substrate may have grooves on its surface facing the first substrate, which are positioned to correspond to the transmission region.

[0027] According to an exemplary embodiment of this disclosure, a display device includes a first substrate, a first electrode, an insulating layer, a plurality of bypass wirings, a plurality of first spacers, a second electrode, and a metal layer. The first substrate includes a transmissive region, a display region surrounding at least a portion of the transmissive region, and a first non-display region disposed between the transmissive region and the display region. An insulating layer is formed on the first substrate and disposed in the display region and the first non-display region. A plurality of bypass wirings are disposed in the insulating layer in the first non-display region. A plurality of first spacers, each having an island shape, are spaced apart from each other on the insulating layer in the first non-display region. A second substrate faces the first substrate. A metal layer is provided on the second substrate and overlaps with the plurality of first spacers and the plurality of bypass wirings, the metal layer being configured to prevent external light incident through the transmissive region from reaching the plurality of bypass wirings.

[0028] The display device may further include a groove formed on the surface facing the first substrate as a recessed area of ​​the second substrate, wherein the groove is positioned to correspond to the transmissive area and does not overlap with the plurality of first spacers. Attached Figure Description

[0029] The above and other aspects and features of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0030] Figure 1A and Figure 1B A schematic perspective view of a display device according to an exemplary embodiment of the present disclosure;

[0031] Figure 2A and Figure 2B A schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0032] Figure 3A This is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure, and Figure 3B For along Figure 3A A cross-sectional view taken from line II-II';

[0033] Figure 4 This is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure, and Figure 5 A schematic equivalent circuit diagram for one pixel of a display panel;

[0034] Figure 6A and Figure 6B A schematic plan view of a portion of a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 7 A portion of a display panel according to an exemplary embodiment of the present disclosure is illustrated schematically;

[0036] Figure 8 For along Figure 7 A cross-sectional view of this portion of the display panel, taken by line III-III';

[0037] Figure 9A and Figure 9B They are respectively Figure 7 Enlarged views of sections A2 (section A) and A3 (section B) of the second and third regions;

[0038] Figure 10 For along Figure 9A A cross-sectional view of the second region A2 intercepted by line IV-IV';

[0039] Figures 11 to 13 They show the following along Figure 7 Other sections intercepted by line III-III';

[0040] Figure 14 A schematic plan view of an input sensing layer on a display panel according to an exemplary embodiment of the present disclosure;

[0041] Figure 15 A cross-sectional view of a stacked structure of an input sensing layer according to an exemplary embodiment of the present disclosure;

[0042] Figure 16 A plan view of a portion of a display device according to an exemplary embodiment of the present disclosure;

[0043] Figure 17 For exemplary embodiments according to this disclosure along Figure 16 A cross-sectional view of this part of the display device taken by line V-V';

[0044] Figure 18 A schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0045] Figure 19 A portion of a display panel according to an exemplary embodiment of the present disclosure is illustrated schematically; and

[0046] Figure 20 For including along Figure 19 A cross-sectional view of the display device taken from the section of line VI-VI'.

[0047] because Figures 1A to 20 The accompanying drawings are for illustrative purposes, so the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0048] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein like reference numerals denote like elements throughout. In this regard, the exemplary embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, with reference to the figures, the following description is merely of exemplary embodiments to explain aspects of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated enumerated items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0050] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0051] It will be further understood that the terms “comprises” and / or “comprising” as used herein indicate the presence of the stated features or elements, but do not exclude the presence or addition of one or more other features or elements.

[0052] It will be understood that when a layer, region, or element is referred to as being “formed” on another layer, region, or element, it can be formed directly or indirectly on that other layer, region, or element. That is, for example, intermediate layers, regions, or elements may exist.

[0053] In this specification, “A and / or B” means A or B, or A and B. The expression “at least one of A and B” indicates only a, only b, both a and b, or variations thereof.

[0054] In the following exemplary embodiments, the meaning of wiring extending in the first or second direction includes not only extending in a straight line but also extending in a zigzag or curved manner in the first or second direction.

[0055] In the following exemplary embodiments, when "plane" is referred to, it means when the target is viewed from above, and when "section" is referred to, it means when the section formed by vertically cutting the target is viewed from the side. In the following exemplary embodiments, when "overlap" is referred to, it encompasses both "plane" overlap and / or "section" overlap. However, in general, the term "overlap" means overlap in a direction perpendicular to the top surface of the substrate.

[0056] Figure 1A and Figure 1B This is a schematic perspective view of a display device 1 according to an exemplary embodiment of the present disclosure.

[0057] refer to Figure 1A The display device 1 may include a first region A1 and a second region A2 surrounding at least a portion of the first region A1. In the second region A2, a plurality of pixels, such as an array of pixels, may be arranged, and an image may be displayed via the array of pixels. According to an exemplary embodiment of this disclosure, the plurality of pixels may be arranged in a matrix shape, but this disclosure is not limited thereto. For example, the plurality of pixels may be arranged in a pentile matrix shape or a rhomboid shape. The second region A2 may correspond to a display area capable of displaying an image. At least a portion of the first region A1 may be surrounded by the second region A2. Figure 1A As shown, a portion of the first region A1 is not surrounded by the second region A2. According to an exemplary embodiment of this disclosure, as... Figure 1BAs shown, the first area A1 can be completely surrounded by the second area A2. In the first area A1, components can be arranged as electronic elements capable of providing various functions to the display device 1. The first area A1 can be a transmissive area capable of transmitting light and / or sound emitted from the component to the outside or traveling from the outside toward the component. For example, when the component includes a light-using sensor or camera, the first area A1 can be a transmissive area capable of transmitting light from the sensor or light traveling toward the camera.

[0058] The third area A3 can be located between the first area A1 and the second area A2. The third area A3 can be a non-display area without any pixels. Similar to the third area A3, the fourth area A4 surrounding the second area A2 can also be a non-display area without any pixels. Various types of wiring and circuits can be arranged in the fourth area A4. For example... Figure 1A The diagram shows that zone A3 can be connected to zone A4. For example... Figure 1B As shown, zone A3 can be an independent zone that is not connected to zone A4. For example, as... Figure 1B The diagram shows that zone A3 can be completely surrounded by zone A2, zone A2 can be completely surrounded by zone A4, and zone A1 can be completely surrounded by zone A3.

[0059] Each of the plurality of pixels included in the display device 1 may include a light-emitting diode (LED) as a display element capable of emitting light of a certain color. The LED may include an organic light-emitting diode (OLED) comprising an organic material as an emission layer. Alternatively, the LED may include an inorganic LED. Alternatively, the LED may include quantum dots and / or quantum rods as an emission layer. For ease of explanation, the case where the LED comprises an organic LED will now be described.

[0060] Despite Figure 1A and Figure 1B In this embodiment, the first region A1 is arranged at the center of the second region A2 in the width direction (e.g., the x-direction) of the display device 1, but this disclosure is not limited thereto. Here, the x-direction includes both the positive and negative directions, and not just the negative direction. Figure 1A and Figure 1B The arrow pointing to the x direction is shown in the image. According to an exemplary embodiment of this disclosure, the first region A1 may be arranged offset to the left or right in the width direction (e.g., the x-direction) of the display device 1. The first region A1 may be arranged in various positions, such as on the upper side, center, or lower side in the length direction (e.g., the y-direction) of the display device 1. Here, the y-direction includes both positive and negative directions, not just the positive direction. Figure 1A and Figure 1B The arrow pointing to the direction of y is shown in the image.

[0061] exist Figure 1A and Figure 1BIn the present disclosure, the display device 1 includes a single first region A1. However, according to an exemplary embodiment of the present disclosure, the display device 1 may include multiple first regions A1. The shape, size, and position of the first region A1 can be changed. For example, according to an exemplary embodiment of the present disclosure, the shape of the first region A1 can be modified in various ways, such as, for example, a circular shape, an elliptical shape, a polygonal shape, a star shape, or a rhombus shape. When two or more first regions A1 are provided, the first regions A1 may have the same shape or different shapes, and may have the same size or different sizes.

[0062] Figure 2A and Figure 2B This is a schematic cross-sectional view of a display device 1 according to an exemplary embodiment of the present disclosure, and each can correspond to along... Figure 1A and Figure 1B The cross section intercepted by line I-I'.

[0063] refer to Figure 2A The display device 1 may include a display panel 10, an input sensing layer 40 and an optical functional layer 50 sequentially arranged on the display panel 10. The display panel 10, the input sensing layer 40 and the optical functional layer 50 may be covered by a window 60. The window 60 may be attached to components below the window 60, such as the optical functional layer 50, via an adhesive layer (e.g., optically clear adhesive OCA). The display device 1 may be included in any various electronic devices, such as mobile phones, tablet PCs, laptop computers and smartwatches.

[0064] Display panel 10 can display images and may include a plurality of light-emitting diodes arranged in the second region A2. Input sensing layer 40 can obtain coordinate information based on external input (e.g., touch event). Input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes, and may be arranged on display panel 10. Input sensing layer 40 can sense external input according to mutual capacitance method or self-capacitance method. For example, input sensing layer 40 can obtain information about external input by the change in capacitance between two sensing electrodes.

[0065] The input sensing layer 40 can be formed directly on the display panel 10. Alternatively, the input sensing layer 40 can be formed separately and then bonded to the display panel 10 via an adhesive layer (e.g., optically clear adhesive OCA). According to exemplary embodiments of this disclosure, such as... Figure 2A As shown, the input sensing layer 40 can be formed directly on the display panel 10, and in this case, an adhesive layer may not be provided between the input sensing layer 40 and the display panel 10. For example, the input sensing layer 40 and the display panel 10 can be integrated into a single substrate within the display device 1. Therefore, the thickness of the display device 1 can be reduced. Although... Figure 2AAs shown, the input sensing layer 40 is placed between the display panel 10 and the optical functional layer 50, but this disclosure is not limited thereto. For example, according to an exemplary embodiment of this disclosure, the input sensing layer 40 may be placed on top of the optical functional layer 50.

[0066] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer reduces the reflectivity of light (external light) incident from an external source toward the display panel 10 through the window 60, and may include a phase retarder and a polarizer. The phase retarder may be film-type or liquid-coated type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be film-type or liquid-coated type. A film-type polarizer may include a stretchable synthetic resin film, and a liquid-coated polarizer may include liquid crystal arranged in a predetermined configuration. For example, when both the polarizer and the phase retarder are film-type, a λ / 4 phase retarder film (or a λ / 2 phase retarder film) may be bonded and laminated to one surface of the polarizer using an optically transparent adhesive OCA layer. The phase retarder and polarizer may further include transparent protective films, respectively.

[0067] According to an exemplary embodiment of this disclosure, the antireflective layer may include, for example, a structure of a black matrix and color filters. Color filters can be arranged taking into account the color of the light beams emitted through the pixels of the display panel 10. Therefore, a desired color can be achieved by filtering the light emitted through each pixel using color filters. According to an exemplary embodiment of this disclosure, the antireflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, can destructively interfere with each other, and thus reduce the reflectivity of external light.

[0068] The optical functional layer 50 may include a lens layer. The lens layer may enhance the emission efficiency of light emitted from the display panel 10 or reduce color deviation of light emitted from the display panel 10. The lens layer may include a layer having a concave lens shape or a convex lens shape, and / or may include multiple layers, each with a different refractive index. According to an exemplary embodiment of this disclosure, an array of lenses in the lens layer may cover an array of pixels, wherein at least one of the lenses may cover at least one of the pixels. The optical functional layer 50 may include both an anti-reflective layer and a lens layer, or may include one of an anti-reflective layer and a lens layer.

[0069] The input sensing layer 40 and the optical functional layer 50 may each include a hole corresponding to the first region A1. For example, the input sensing layer 40 may include a first hole 40H that completely penetrates the input sensing layer 40, and the optical functional layer 50 may include a second hole 50H that completely penetrates the optical functional layer 50. The first hole 40H and the second hole 50H may be arranged in the first region A1 and may overlap each other. Alternatively, according to an exemplary embodiment of this disclosure, one or both of the input sensing layer 40 and the optical functional layer 50 may not have a hole corresponding to the first region A1. When the adhesive layer disposed between the window 60 and the optical functional layer 50 comprises an optically clear adhesive OCA, the adhesive layer may not include a hole corresponding to the first region A1, such as... Figure 2A As shown in the figure. According to exemplary embodiments of this disclosure, such as Figure 2B As shown, the optically transparent adhesive OCA may include a third hole OCAH corresponding to the first region A1.

[0070] Component 20 may be placed in the first region A1. Component 20 may include electronic components. For example, component 20 may be an electronic component that uses light or sound. For example, the electronic component may include a sensor that receives and outputs light, such as an infrared sensor, a camera that receives light and captures images, a sensor that outputs and senses light or sound to measure distance or identify fingerprints, a small light that outputs light, or a speaker that outputs sound. The electronic component that uses light may use light in various wavelength bands, such as visible light, infrared light, and ultraviolet light. According to an exemplary embodiment of this disclosure, the first region A1 may be a transmissive region capable of transmitting light that is output from component 20 to the outside or travels from the outside toward component 20. For example, component 20 may include at least one of a camera, a speaker, a light, a light detection sensor, and a thermal detection sensor. Component 20 may detect external targets received through the first region A1, or may provide sound signals (such as voice) to the outside through the first region A1. In addition, component 20 may include multiple configurations and is not limited to any one of the exemplary embodiments.

[0071] According to an exemplary embodiment of this disclosure, when the display device 1 is used as a smartwatch or as a dashboard for a car, component 20 may be, for example, a clock hand or a component indicating predetermined information (e.g., vehicle speed). When the display device 1 includes clock hands or is used as a dashboard for a car, component 20 may be exposed to the outside through window 60, and window 60 may include an opening corresponding to the first area A1.

[0072] As described above, component 20 may include one or more elements capable of adding functionality to display device 1, or may include accessories such as enhancing the aesthetics of display panel 10. Component 20 may be disposed in the first region A1 to overlap with the first hole 40H and the second hole 50H. Accordingly, because component 20 is assembled to overlap with the first hole 40H and the second hole 50H in the plan view, it can easily communicate with the outside through the first hole 40H and the second hole 50H.

[0073] Figure 3A This is a schematic plan view of a display panel 10 according to an exemplary embodiment of the present disclosure, and Figure 3B For along Figure 3A The cross-sectional view taken from line II-II'.

[0074] refer to Figure 3A and Figure 3B The display panel 10 includes a display layer 200 disposed on a substrate 100. The substrate 100 may include a glass material and / or a polymer resin, and may have a single-layer structure or a multi-layer structure. For example, the substrate 100 may include a glass material primarily containing silicon oxide (SiO2), and / or a polymer resin, such as a reinforced plastic. According to an exemplary embodiment of this disclosure, the substrate 100 may have a multi-layer structure and may include one or more base layers and one or more barrier layers. The polymer resin may be transparent and may be provided such that at least a portion of the display panel 10 can be easily bent. Alternatively, the substrate 100 may be provided in a rigid state.

[0075] Display layer 200 may be positioned corresponding to second region A2 and may include a plurality of pixels P. Each of the plurality of pixels P included in display layer 200 may include pixel circuitry and a display element electrically connected to the pixel circuitry. The pixel circuitry may include transistors and storage capacitors, and the display element may include light-emitting diodes, such as organic light-emitting diodes (OLEDs) (see [link to OLED model]). Figure 5 ).

[0076] The display layer 200 may be covered by the encapsulation member 300. The encapsulation member 300 may be an encapsulation substrate comprising a glass material and / or a polymer resin. For example, the encapsulation member 300 may comprise a glass material primarily containing silicon oxide (SiO2) and / or a polymer resin, such as a reinforced plastic. When the substrate 100 comprises a polymer resin and the encapsulation member 300 comprises a polymer resin, the flexibility of the display panel 10 may be enhanced. The encapsulation member 300 may be arranged facing the substrate 100, and a sealant ST may be disposed between the substrate 100 and the encapsulation member 300. The encapsulation member 300 may be spaced apart from the display layer 200 and / or the substrate 100 by a predetermined gap, and the gap may be maintained by the sealant ST. The sealant ST may be placed in a fourth region A4 and may be continuously arranged along the substrate 100 between the substrate 100 and the encapsulation member 300, and may completely surround the display layer 200. When viewed from a direction perpendicular to the upper surface of the substrate 100 (or in a plan view), the second region A2 may be completely surrounded by the sealant ST. The sealant ST connects the substrate 100 to the encapsulation member 300, and can therefore be used to prevent, for example, oxygen or moisture from entering the display layer 200, and can also be used to increase the strength of the instrument.

[0077] The sealant ST can be an inorganic material, such as a frit. The sealant ST can be formed by coating using a dispensing method or a screen printing method. The frit may include a crystalline (fully crystalline and / or partially crystalline) substrate glass or parent glass. Frit generally refers to a powdered material used in the manufacture of glass, but can also refer to a paste-like material in which laser-absorbing or infrared-absorbing materials, organic binders, and fillers for reducing the coefficient of thermal expansion are added to a host material (such as silicon oxide (SiO2)). The paste-like frit can be cured by a drying or firing process, as this removes the organic binder and moisture. The laser-absorbing or infrared-absorbing material may include transition metal compounds. A laser can be used as a heat source for curing the sealant ST to attach the substrate 100 to the encapsulation member 300.

[0078] A portion of the display layer 200 can be removed, for example, a portion corresponding to the first region A1. In this regard, Figure 3B The display layer 200 is shown to include a fourth hole 200H. In addition to the pixel circuits and display elements described above, the display layer 200 may further include an insulating layer disposed between wirings connected to each pixel circuit, between electrodes, and / or between electrodes of the display element. For example, the fourth hole 200H can be formed through corresponding holes of the overlapping insulating layers included in the display layer 200 (see...). Figure 8 , Figures 11 to 13 , Figure 18 and Figure 20The fourth hole 200H of the display layer 200 can be formed to completely penetrate the display layer 200, extending from the top surface to the bottom surface. However, as... Figure 3B As shown, the substrate 100 may not have a through-hole corresponding to the first region A1, and the encapsulation member 300 may not have a through-hole corresponding to the first region A1. The display layer 200 disposed in the third region A3 may not include pixel circuitry and may not include display elements.

[0079] Spacer SPCs may be disposed in the third region A3. Spacer SPCs may be disposed over at least one insulating layer extending from the second region A2 to the third region A3, and may include an organic material. Spacer SPCs may be disposed around the first region A1. According to an exemplary embodiment of this disclosure, the spacer SPC may include a first spacer SPC1 (see...) Figure 7 The first spacer SPC1 is a plurality of island-shaped insulating patterns spaced apart from each other. According to an exemplary embodiment of this disclosure, the spacer SPC may include a first spacer SPC1 (the first spacer SPC1 is a plurality of island-shaped insulating patterns spaced apart from each other) and a second spacer SPC2 (see...). Figure 19 (The second spacer SPC2 is an annular insulating pattern surrounding the first region A1). The spacer SPC can be used to maintain the gap between the substrate 100 and the encapsulation member 300, and to support the encapsulation member 300. It can also be used to separate the first region A1 from the second region A2 to prevent substances introduced through the first region A1, such as oxygen or moisture, from penetrating the display layer 200. For ease of illustration, Figure 3A and Figure 3B The spacer SPC is schematically shown, and it is shown that the spacer SPC is placed on the display layer 200. However, the spacer SPC may be part of the display layer 200.

[0080] A pad unit 140, comprising multiple pads, may be arranged on one side of the fourth region A4. The pad unit 140 may be exposed without being covered by an insulating layer and may be electrically connected to a printed circuit board (PCB). According to an exemplary embodiment of this disclosure, a flexible printed circuit board (FPCB) may be electrically connected to the pad unit 140 located on one side of a display panel 10 in the fourth region A4. The FPCB may be bent and electrically connected to the display panel 10. Accordingly, the FPCB may output signals to or receive signals from the display panel 10 via the pad unit 140. The pad unit 140 may be arranged outside a sealant ST. The sealant ST may be arranged above a plurality of connecting lines (which connect the wiring to the pixels of the second region A2 to the pad unit 140) and may overlap some of the connecting lines.

[0081] Figure 4This is a schematic plan view of a display panel 10 according to an exemplary embodiment of the present disclosure, and Figure 5 A schematic equivalent circuit diagram for a pixel P of the display panel 10.

[0082] The diagram of display panel 10 can be found in the above reference. Figure 3A and Figure 3B The diagram of the described display panel 10 is actually the same. For example, as shown... Figure 4 As shown in the figure, the display panel 10 may include a first area A1, a second area A2 surrounding the first area A1, a third area A3 placed between the first area A1 and the second area A2, and a fourth area A4 surrounding the second area A2.

[0083] Display panel 10 may include a plurality of pixels P arranged in the second area A2. For example... Figure 5 As shown, each of the pixels P may include a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC as a display element. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Cst. Each of the pixels P may emit, for example, red, green, or blue light, or may emit red, green, blue, or white light via the OLED. The first transistor T1 and the second transistor T2 may be implemented using thin-film transistors. The display panel 10 may display a predetermined image based on an electrical signal, using light emitted from the plurality of pixels P arranged in the second region A2.

[0084] A second transistor T2, acting as a switching transistor for controlling the on and off states of pixel P, can be connected to scan line SL and data line DL. Based on the switching voltage received via scan line SL, the data signal received via data line DL can be transmitted to the first transistor T1. A capacitor Cst can be connected to the second transistor T2 and drive voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the second transistor T2 and the first power supply voltage ELVDD supplied to drive voltage line PL.

[0085] A first transistor T1, acting as a driving transistor, can be connected to a driving voltage line PL and a capacitor Cst. The driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) can be controlled according to the voltage value stored in the capacitor Cst. Based on the driving current, the OLED can emit light with a specific brightness. The on-time of the first transistor T1 can be determined based on the amount of voltage stored in the capacitor Cst. The first transistor T1 can then supply a first power supply voltage ELVDD, transmitted through the driving voltage line PL, to the OLED during the on-time. The opposite electrode (e.g., the cathode) of the OLED can receive a second power supply voltage ELVSS.

[0086] although Figure 5 The illustration shows a pixel circuit PC comprising two transistors and one storage capacitor, but this disclosure is not limited thereto. The number of transistors and the number of storage capacitors can vary depending on the design of the pixel circuit PC. For example, the pixel circuit PC may include three, four, five, or more transistors instead of the two transistors shown above. Moreover, the pixel circuit PC may include more than one storage capacitor.

[0087] Return to reference Figure 4 A third region A3 may surround a first region A1. The third region A3 is a region in which no display element (e.g., an organic light-emitting diode, OLED) is disposed. Signal lines configured to provide signals to pixels P disposed around the first region A1 may cross the third region A3. In a fourth region A4, a first scan driver 1100 and a second scan driver 1200, each providing scan signals to each of the pixels P, a data driver 1300 providing data signals to each of the pixels P, and main power wiring for providing a first power supply voltage ELVDD and a second power supply voltage ELVSS, may be disposed. The first scan driver 1100 and the second scan driver 1200 may each be placed in the fourth region A4 and may be disposed on either side of a second region A2, which is located between the first scan driver 1100 and the second scan driver 1200. The first scan driver 1100, the second scan driver 1200, and the data driver 1300 may be disposed outside the sealant ST disposed in the fourth region A4.

[0088] exist Figure 4 In this embodiment, the data driver 1300 is placed on one edge of the substrate 100. However, according to an exemplary embodiment of this disclosure, the data driver 1300 may be placed on a flexible printed circuit board (FPCB) electrically connected to pads (e.g., pad units 140) arranged on one side of the display panel 10. Accordingly, the FPCB may output signals to or receive signals from the display panel 10.

[0089] Figure 6A and Figure 6B This is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure.

[0090] refer to Figure 6A Some of the pixels P formed in the second region A2 can be spaced apart from each other around the first region A1. For example, the first region A1 can be placed in a... Figure 6A Between two pixels P in the x-direction. Similarly, the first region A1 can be placed between the two pixels P arranged in the x-direction. Figure 6ABetween two pixels P in the y-direction. Since the third region A3 is a region in the planar diagram where no pixels P are placed, some pixels P can be placed above and below the third region A3 (y-direction), and some pixels P can be placed to the left and right of the third region A3 (x-direction).

[0091] Two pixels P arranged in the y-direction (with a first region A1 placed between them) can be electrically connected to the same data line DL, and the data line DL can be bent in a third region A3. For example, a portion of the data line DL can be bent and extend in the third region A3 along the edge of the first region A1 (e.g., along the arc of the first region A1). The data line DL may include a first portion DL-L1 and a second portion DL-L2 extending in the y-direction and across a second region A2 to apply data signals to the pixels P, and a third portion DL-D connected to the first portion DL-L1 and the second portion DL-L2 and extending in the third region A3 along the arc of the first region A1. According to an exemplary embodiment of this disclosure, the first portion DL-L1, the second portion DL-L2, and the third portion DL-D can be integrally formed as wiring on the same layer. According to an exemplary embodiment of this disclosure, the first part DL-L1 and the second part DL-L2 may be on the same layer and not connected to each other, and the third part DL-D may be arranged on a different layer than the layer on which the first part DL-L1 and the second part DL-L2 are arranged, and may be electrically connected to the first part DL-L1 and the second part DL-L2 via contact holes.

[0092] Two pixels P arranged in the x-direction (with the first region A1 placed between them) can be electrically connected to different scan lines SL. The scan line SL on the left side of the first region A1 can be electrically connected to the reference above. Figure 4 The first scan driver 1100 is described, and the scan line SL on the right side of the first region A1 is electrically connected to the reference above. Figure 4 The second scan driver 1200 is described. When as Figure 4 As shown in the figure, when the display panel 10 includes two scan drivers, the pixels P on both sides of the first area A1 can be electrically connected to scan lines SL spaced apart from each other.

[0093] According to exemplary embodiments of this disclosure, such as Figure 6BAs shown, when the second scan driver 1200 is omitted, two pixels P arranged in the x-direction (with the first region A1 placed between them) can be connected to the same scan line, and like the data line DL, the scan line can include a portion extending along the arc of the first region A1 within the third region A3. For example, the scan line SL can include a first portion SL-L1 and a second portion SL-L2 extending in the x-direction to apply a scan signal to the pixel P and crossing the second region A2, and a third portion SL-D connecting the first portion SL-L1 and the second portion SL-L2 and extending along the arc of the first region A1 within the third region A3. According to an exemplary embodiment of this disclosure, the first portion SL-L1, the second portion SL-L2, and the third portion SL-D can be integrally formed as wiring on the same layer. According to an exemplary embodiment of this disclosure, the first portion SL-L1 and the second portion SL-L2 may be on the same layer and not connected to each other, and the third portion SL-D may be arranged on a different layer than the layer on which the first portion SL-L1 and the second portion SL-L2 are arranged, and may be electrically connected to the first portion SL-L1 and the second portion SL-L2 via contact holes.

[0094] Figure 7 A portion of a display panel 10 according to an exemplary embodiment of the present disclosure is shown schematically. Figure 8 It shows along Figure 7 The section of the display panel cut by line III-III'. Figure 9A and Figure 9B They are respectively Figure 7 The enlarged view of the second region A2 (enlarged view of region A) and the enlarged view of the third region A3 (enlarged view of region B), and Figure 10 For along Figure 9A The cross-sectional view of the second region A2 intercepted by line IV-IV'. Figures 11 to 13 They show the following along Figure 7 Other sections intercepted by line III-III'.

[0095] Figure 7 A portion of a display panel 10, including a first zone A1 and a third zone A3 surrounding the first zone A1, is shown. Figure 7 The planar graph PV refers to the graph defined on the xy plane, and Figure 7 The cross-sectional diagram CSV refers to a diagram defined on the xz plane. Figure 7 The cross-sectional diagram CSV can correspond to along Figure 7 The cross section intercepted by line III-III' of the plan view PV.

[0096] refer to Figure 7A plurality of first spacers SPC1 may be arranged in the third region A3 of the display panel 10. The first spacers SPC1 may be arranged on a stack of at least one inorganic insulating layer IL and at least one organic insulating layer OL above the substrate 100. The first spacers SPC1 may be island-shaped insulating patterns. The first spacers SPC1 may be arranged at regular intervals in the third region A3. In other words, a plurality of first spacers SPC1, each having an island shape and spaced apart from each other, may be formed on an insulating layer in the third region A3, the insulating layer comprising at least one inorganic insulating layer IL and at least one organic insulating layer OL, wherein at least one organic insulating layer OL may be formed on at least one inorganic insulating layer IL and stacked between the plurality of first spacers SPC1 and at least one inorganic insulating layer IL. Some of the first spacers SPC1 may be arranged at the boundary between the second region A2 and the third region A3, and therefore may be arranged in both the second region A2 and the third region A3. In other words, each of the first spacers SPC1 includes at least a portion arranged in the third region A3.

[0097] In the second region A2 of the display panel 10, a plurality of third spacers SPC3 may be arranged. The third spacers SPC3 may be arranged on a stack of at least one inorganic insulating layer 1L and at least one organic insulating layer 1L above the substrate 100. The third spacers SPC3 may be island-shaped insulating patterns. The third spacers SPC3 may be arranged in the second region A2 at regular intervals. In other words, a plurality of third spacers SPC3 may be placed on the insulating layers in the second region A2, each having an island shape, and arranged between a plurality of display elements (see...). Figure 9A In this embodiment, at least one organic insulating layer OL may be formed on at least one inorganic insulating layer IL and stacked between a plurality of third spacers SPC1 and at least one inorganic insulating layer IL. The first spacers SPC1 and the third spacers SPC3 may be insulating patterns having the same shape. According to an exemplary embodiment of this disclosure, the first spacers SPC1 and the third spacers SPC3 may comprise the same material. According to an exemplary embodiment of this disclosure, the first spacers SPC1 and the third spacers SPC3 may comprise materials different from each other. The width Wa of each of the first spacers SPC1 in the x-direction may be equal to or different from the width Wc of each of the third spacers SPC3 in the x-direction.

[0098] At least one inorganic insulating layer IL and at least one organic insulating layer OL may be insulating layers extending from the second region A2 to the third region A3, respectively. For example, at least one inorganic insulating layer IL may include Figure 8 and Figure 10 At least one of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207. At least one organic insulating layer OL may include... Figure 8 and Figure 10 At least one of the first organic insulating layer 209, the second organic insulating layer 211, and the pixel defining layer 215. For example, as Figure 7 (CSV) Figure 8 and Figure 10 As shown, at least one organic insulating layer OL is formed on at least one inorganic insulating layer IL.

[0099] refer to Figure 8 and Figure 10 The pixel circuit PC can be disposed on the substrate 100, and the organic light-emitting diode (OLED) electrically connected to the pixel circuit PC can be disposed on the pixel circuit PC. (See above reference...) Figure 3A and Figure 3B The substrate 100 may comprise, for example, a glass material or a polymer resin. The substrate 100 may be a single layer or multiple layers. When the substrate 100 has multiple layers, it may include one or more base layers and one or more barrier layers.

[0100] The buffer layer 201 is used to prevent impurities from penetrating into the semiconductor layer Act of the thin-film transistor (TFT) and may be disposed on the substrate 100. The buffer layer 201 may include an inorganic insulating material, such as, for example, silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon oxide (SiO2), and may be a single layer or multiple layers including the inorganic insulating material.

[0101] Pixel circuitry PC may be disposed on buffer layer 201. Pixel circuitry PC may include thin-film transistors (TFTs) and capacitors Cst. TFTs may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. The gate electrode GE may overlap with the semiconductor layer Act. This portion of the semiconductor layer Act overlapping with the gate electrode GE may constitute the channel region of the thin-film transistor TFT. The source and drain regions of the thin-film transistor TFT may include portions of the semiconductor layer Act disposed on either side of the channel region. Figure 10 The thin-film transistor TFT can correspond to the above reference. Figure 5 One of the transistors described, for example, the driving transistor ( Figure 5 The first transistor T1). According to this exemplary embodiment, the thin-film transistor TFT is a top-gate type, wherein the gate electrode GE is disposed on the semiconductor layer Act, and the gate insulating layer 203 is interposed between them. However, this disclosure is not limited thereto. For example, according to an exemplary embodiment of this disclosure, the thin-film transistor TFT may be a bottom-gate type.

[0102] The semiconductor layer Act may include polycrystalline silicon (poly-Si). Alternatively, the semiconductor layer Act may include, for example, amorphous silicon (a-Si), oxide semiconductor, or organic semiconductor. The gate electrode GE may include a low-resistance metallic material. The gate electrode GE may include a conductive material comprising, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), or alloys thereof, and may be formed as a multilayer or a single layer comprising the above materials.

[0103] The gate insulating layer 203 disposed between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material, such as, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), zirconium oxide (ZrO2), or hafnium oxide (HfO2). The gate insulating layer 203 may be a single layer or multiple layers comprising the above materials.

[0104] The source electrode SE and drain electrode DE, which serve as connection electrodes electrically connected to the semiconductor layer Act, can be placed with the data line DL (see...). Figure 6A and Figure 6B The source electrode SE and drain electrode DE are on the same layer as the data line DL, and may include the same material. The portion of the semiconductor layer Act connected to the source electrode SE or drain electrode DE may be doped with an n-type or p-type dopant. The source electrode SE and drain electrode DE may include highly conductive materials. Each of the source electrode SE and drain electrode DE may include a conductive material comprising, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), or alloys thereof, and may be a multilayer or a single layer comprising the aforementioned materials. According to an exemplary embodiment of this disclosure, each of the source electrode SE and drain electrode DE may be formed as a titanium / aluminum / titanium (Ti / Al / Ti) multilayer.

[0105] The capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 that overlap each other, with a first interlayer insulating layer 205 disposed between the lower electrode CE1 and the upper electrode CE2. The capacitor Cst and the thin-film transistor (TFT) may overlap each other. In this regard, Figure 10 The illustration shows a case where the gate electrode GE of the thin-film transistor TFT is the lower electrode CE1 of the capacitor Cst. According to an exemplary embodiment of this disclosure, the capacitor Cst and the thin-film transistor TFT may not overlap. The capacitor Cst may be covered by a second interlayer insulating layer 207. The upper electrode CE2 of the capacitor Cst may comprise a conductive material including, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), or alloys thereof, and may be a multilayer or a single layer comprising the aforementioned materials.

[0106] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may each comprise an inorganic insulating material, such as, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), or hafnium oxide (HfO2). Each of the first interlayer insulating layer 205 and the second interlayer insulating layer 207 may be a single layer or multiple layers comprising the aforementioned materials.

[0107] The pixel circuit PC, including a thin-film transistor (TFT) and a capacitor (Cst), may be covered by a first organic insulating layer 209. The first organic insulating layer 209 is a planarized insulating layer, and its upper surface may include an approximately flat surface. The first organic insulating layer 209 may include an organic insulating (insulating) material, such as, for example, a commercially available polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylyl polymers, vinyl alcohol polymers, or blends thereof. According to an exemplary embodiment of this disclosure, the first organic insulating layer 209 may include polyimide (PI).

[0108] The connecting metal electrode CM may be located on the first organic insulating layer 209. The connecting metal electrode CM may contact the thin-film transistor TFT (e.g., the drain electrode DE of the thin-film transistor TFT) through contact holes formed in the first organic insulating layer 209, and the pixel electrode 221 may contact the connecting metal electrode CM through contact holes formed in the second organic insulating layer 211. The connecting metal electrode CM may comprise a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or alloys thereof, and may be formed as a multilayer or a single layer comprising the aforementioned materials. The connecting metal electrode CM may comprise the same material as that included in the source electrode SE or drain electrode DE of the thin-film transistor TFT. For example, the connecting metal electrode CM may be formed as a multilayer of titanium / aluminum / titanium (Ti / Al / Ti).

[0109] A second organic insulating layer 211 may be disposed on the connecting metal electrode CM. The upper surface of the second organic insulating layer 211 may include an approximately flat surface. The second organic insulating layer 211 may include an organic insulating material, such as, for example, a commercial polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylyl polymers, vinyl alcohol polymers, or blends thereof. According to an exemplary embodiment of this disclosure, the second organic insulating layer 211 may include polyimide (PI). According to an exemplary embodiment of this disclosure, each of the first organic insulating layer 209 and the second organic insulating layer 211 may be formed by spin coating. An inorganic insulating layer may be further disposed between the first organic insulating layer 209 and the second organic insulating layer 211.

[0110] Pixel electrode 221 may be disposed on the second organic insulating layer 211. Pixel electrode 221 may include a conductive oxide, such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). According to an exemplary embodiment of this disclosure, pixel electrode 221 may include a reflective layer comprising, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds of these materials. According to an exemplary embodiment of this disclosure, pixel electrode 221 may further include a film formed of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) above / below the aforementioned reflective layer. Pixel electrode 221 may be electrically connected to a thin-film transistor (TFT) of pixel circuit PC via a connecting metal electrode CM.

[0111] A pixel defining layer 215 may be disposed on a pixel electrode 221. The pixel defining layer 215 may include an opening OP (through which a portion of the upper surface of the pixel electrode 221 is exposed) and may cover the edge of the pixel electrode 221. The opening OP of the pixel defining layer 215 may define a light emitting region EA. The pixel defining layer 215 may be disposed between a plurality of pixel electrodes 221 and may include an organic insulating material. Alternatively, the pixel defining layer 215 may include an inorganic insulating material, such as, for example, silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon oxide (SiO2). Alternatively, the pixel defining layer 215 may include both organic and inorganic insulating materials.

[0112] An intermediate layer 222 disposed between pixel electrode 221 and opposing electrode 223 may include an emitting layer 222b. The emitting layer 222b may include, for example, an organic material. The emitting layer 222b may include a low-molecular-weight organic material or a high-molecular-weight organic material that emits light of a particular color. The intermediate layer 222 may include a first functional layer 222a disposed below the emitting layer 222b, and / or a second functional layer 222c disposed above the emitting layer 222b. According to an exemplary embodiment of this disclosure, the emitting layer 222b may include at least one material that emits red, green, and blue light, and may include a fluorescent or phosphorescent material.

[0113] The first functional layer 222a may be a single layer or multiple layers. For example, when the first functional layer 222a comprises a high molecular weight organic material, the first functional layer 222a is a hole transport layer (HTL) with a single-layer structure, and may include, for example, poly(3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). When the first functional layer 222a comprises a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0114] The second functional layer 222c may be optional. For example, the second functional layer 222c may be formed when the first functional layer 222a and the emitter layer 222b comprise high molecular weight materials. The second functional layer 222c may be a single layer or multiple layers. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). For example, the intermediate layer 222 may include at least one of a hole transport layer (HTL), a hole injection layer (HIL), an electron injection layer (EIL), and an electron transport layer (ETL).

[0115] The emitting layer 222b of the intermediate layer 222 can be disposed in each pixel in the second region A2. The emitting layer 222b can be disposed to overlap with the opening OP of the pixel defining layer 215 and / or a portion of the pixel electrode 221. Each of the first functional layer 222a and the second functional layer 222c of the intermediate layer 222 is a continuous layer as a single entity, and accordingly can be formed not only in the second region A2 but also in the third region A3, while the emitting layer 222b is formed only in the second region A2.

[0116] The counter electrode 223 may comprise a conductive material having a low work function. For example, the counter electrode 223 may comprise a (semi-)transparent layer comprising, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys of these materials. Alternatively, the counter electrode 223 may further comprise a layer formed of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) on a (semi-)transparent layer comprising any of the aforementioned materials. The counter electrode 223, as a continuous layer of a single entity, may be formed in a second region A2 to cover a plurality of pixel electrodes 221, and may also be formed in a third region A3. The intermediate layer 222 and the counter electrode 223 may be formed by thermal deposition.

[0117] A capping layer 230 may be placed on the opposing electrode 223. The capping layer 230 may include lithium fluoride (LiF), inorganic materials, and / or organic materials. According to an exemplary embodiment of this disclosure, the capping layer 230 may be omitted.

[0118] like Figure 9A and Figure 10 As shown, a third spacer SPC3 may be formed on the pixel defining layer 215 in the second region A2. The third spacer SPC3 may include an organic insulating material, such as polyimide (PI). Alternatively, the third spacer SPC3 may include an inorganic insulating material, such as, for example, silicon nitride (Si3N4) or silicon oxide (SiO2), or may include both inorganic and organic insulating materials. The third spacer SPC3 may include a material different from that included in the pixel defining layer 215. Alternatively, the third spacer SPC3 may include the same material included in the pixel defining layer 215. In this case, the pixel defining layer 215 and the third spacer SPC3 may be formed together using a halftone mask or similar photolithography process. According to an exemplary embodiment of this disclosure, the pixel defining layer 215 and the third spacer SPC3 may include polyimide (PI).

[0119] Multiple third spacers (SPC3) can be arranged at regular intervals within the non-light-emitting region (NEA), which is positioned between the light-emitting regions (EA). Display elements (such as organic light-emitting diodes, OLEDs) can be formed within the light-emitting regions (EA). The light-emitting regions (EA) may include a first light-emitting region (EA1) emitting light of a first color, a second light-emitting region (EA2) emitting light of a second color, and a third light-emitting region (EA3) emitting light of a third color. The light-emitting regions (EA) may emit, for example, red, green, blue, or white light. Figure 9AIn the present invention, the light emitting regions EA are arranged in a honeycomb pattern. However, according to an exemplary embodiment of the present disclosure, the light emitting regions EA can be arranged in various layouts (e.g., stripe arrangement and / or mosaic arrangement). Each first light emitting region EA1 may overlap with a portion of a first pixel electrode 221a exposed through an opening OP of the pixel defining layer 215. Each second light emitting region EA2 may overlap with a portion of a second pixel electrode 221b exposed through an opening OP of the pixel defining layer 215. Each third light emitting region EA3 may overlap with a portion of a third pixel electrode 221c exposed through an opening OP of the pixel defining layer 215.

[0120] The third spacer SPC3 can be arranged between the second pixel electrodes 221b arranged in the x-direction, and / or between the first pixel electrodes 221a and the third pixel electrodes 221c that alternate with each other in the y-direction. In other words, the third spacer SPC3 can be arranged between the second light-emitting regions EA2 arranged in the x-direction and / or in the portion of the non-light-emitting region NEA between the first light-emitting regions EA1 and the third light-emitting region EA3 that alternate with each other in the y-direction. For example, the third spacer SPC3 can be arranged in the portion of the non-light-emitting region NEA between multiple display elements (such as organic light-emitting diodes, OLEDs) that can emit, for example, red, green, or blue light, or red, green, blue, or white light. Figure 9A In this example, each of the third spacers SPC3 is rectangular and larger than each of the second light-emitting regions EA2. However, this is only an example. The position, shape, and size of each of the third spacers SPC3 may depend on the layout, shape, and size of each of the light-emitting regions EA2. For example, the third spacers SPC3 may be arranged between the second light-emitting regions EA2 arranged in the y-direction and / or in the portion of the non-light-emitting region NEA between the first light-emitting regions EA1 and the third light-emitting regions EA3 alternating with each other in the x-direction. Each of the third spacers SPC3 may be polygonal and / or circular, such as, for example, square, circular, triangular, or elliptical, and may each have a size smaller than or the same as the size of the second light-emitting region EA2.

[0121] like Figure 8 As shown, a first region A1 may exist between pixels. Each pixel includes, for example, a light-emitting diode (LED) serving as a display element. Each LED includes a stack of a pixel electrode 221, an emitting layer 222b, and a counter electrode 223. The counter electrode 223 faces the pixel electrode 221, and the emitting layer 222b is disposed between the pixel electrode 221 and the counter electrode 223. The display layer 200 may include a fourth aperture 200H disposed in the first region A1.

[0122] A fourth hole 200H can be formed while the vias formed in the insulating layers of the display layer 200 overlap each other. The insulating layers of the display layer 200, such as the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, the second interlayer insulating layer 207, the first organic insulating layer 209, the second organic insulating layer 211, and the pixel defining layer 215, may each include vias placed in the first region A1. The size of the fourth hole 200H can be defined by the insulating layer in the insulating layer of the display layer 200 that defines the minimum hole size. According to an exemplary embodiment of this disclosure, Figure 8 The fourth hole 200H is shown to be defined by the size of the through hole in the buffer layer 201.

[0123] Furthermore, a fifth hole 5H can be formed by overlapping the through-holes formed in the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 corresponding to the first region A1, respectively, and the size of the fifth hole 5H can be defined by the smallest through-hole size of these layers. According to an exemplary embodiment of this disclosure, Figure 8 The fifth hole 5H is shown to be defined by the size of the through hole in the first functional layer 222a. In this case, the width W2 (diameter) of the fifth hole 5H can be greater than the width W1 (diameter) of the fourth hole 200H.

[0124] Multiple scan lines SL arranged in the third zone A3 (see Figure 6A and Figure 6B The corresponding third part SL-D can be placed between the gate insulating layer 203 and the first interlayer insulating layer 205. Multiple data lines DL arranged in the third region A3 (see...) Figure 6A and Figure 6B The corresponding third portion DL-D of the scan lines SL can be placed between the second interlayer insulating layer 207 and the first organic insulating layer 209. According to an exemplary embodiment of the present disclosure, the corresponding third portions SL-D of multiple scan lines SL and / or the corresponding third portions DL-D of multiple data lines DL can be placed between the first interlayer insulating layer 205 and the second interlayer insulating layer 207.

[0125] The first spacer SPC1 may surround the first region A1 and may be arranged at regular intervals in the third region A3. For example, the first spacer SPC1 may be placed on the insulating layer or pixel defining layer 215 in the third region A3, each having an island shape, and arranged around the fourth hole 200H (or through holes formed in the insulating layer of the display layer 200) along the circumference of the fourth hole 200H. Figure 9B As shown, the first spacer SPC1 can be arranged at regular intervals in the x and / or y directions. Although Figure 9BA first spacer SPC1, each having a rectangular shape, is shown, but this is merely an example. For example, each of the first spacer SPC1 may be a polygon and / or a circle, such as, for example, a square, circle, triangle, or ellipse. According to an exemplary embodiment of this disclosure, the layout orientation of the first spacer SPC1 and the shape and size of each of the first spacer SPC1 may be the same as those of the third spacer SPC3. According to an exemplary embodiment of this disclosure, at least one of the layout orientation of the first spacer SPC1 and the shape and size of each of the first spacer SPC1 may differ from at least one of the layout orientation of the third spacer SPC3 and the shape and size of each of the third spacer SPC3. The spacing between the first spacer SPC1 in the x and y directions may be the same as or different from the spacing between the third spacer SPC3 in the x and y directions. For example, the spacing between the first spacer SPC1 in the x and y directions may be smaller than the spacing between the third spacer SPC3 in the x and y directions.

[0126] The first spacer SPC1 may include an organic insulating material, such as polyimide (PI). Alternatively, the first spacer SPC1 may include an inorganic insulating material, such as silicon nitride (Si3N4) or silicon oxide (SiO2), or may include both inorganic and organic insulating materials. The first spacer SPC1 may include a material different from that included in the pixel defining layer 215. Alternatively, the first spacer SPC1 may include the same material as that included in the pixel defining layer 215. In this case, the pixel defining layer 215 and the first spacer SPC1 may be formed together using a halftone mask or the like via a photolithography process. According to an exemplary embodiment of this disclosure, the pixel defining layer 215 and the first spacer SPC1 may include polyimide (PI). The first spacer SPC1 may include a material different from that included in the third spacer SPC3. Alternatively, the first spacer SPC1 may include the same material as that included in the third spacer SPC3. In this case, the first spacer SPC1 and the third spacer SPC3 may be formed simultaneously in the same process.

[0127] The first functional layer 222a, the second functional layer 222c, the opposing electrode 223, and the capping layer 230 can cover the first spacer SPC1, the gap between the first spacers SPC1, the third spacer SPC3, and the gap between the third spacers SPC3. For example, the first functional layer 222a, the second functional layer 222c, the opposing electrode 223, and the capping layer 230 can extend from the second region A2 to the third region A3 to cover both the third spacer SPC3 and the first spacer SPC1. Therefore, when the pixel electrode 221 is referred to as the first electrode and the opposing electrode 223 is referred to as the second electrode, the second electrode can face the first electrode in the display area (e.g., the second region A2) and can cover the pixel defining layer 215 and the plurality of first spacers SPC1 in the non-display area (e.g., the third region A3).

[0128] The first spacer SPC1 and the third spacer SPC3 may have the same height and may maintain the gap between the substrate 100 and the encapsulation member 300 in each of the second region A2 and the third region A3. For example, the first spacer SPC1 and the third spacer SPC3 may be used to maintain the gap between the substrate 100 and the encapsulation member 300 and at the same time support the encapsulation member 300.

[0129] The encapsulation member 300 is arranged facing the substrate 100. In the first region A1, the material included in the display layer 200 is not disposed between the lower surface of the encapsulation member 300 and the upper surface of the substrate 100. In other words, in the first region A1, the upper surface of the substrate 100 can directly face the lower surface of the encapsulation member 300. The encapsulation member 300 may include the same material as the substrate 100 and may have the same refractive index as the substrate 100. For example, each of the substrate 100 and the encapsulation member 300 may have a refractive index of about 1.3 to about 1.7, for example, about 1.5. For example, the encapsulation member 300 may be an encapsulation substrate facing the substrate 100. Therefore, when the substrate 100 is referred to as the first substrate, the encapsulation member 300 may be referred to as the second substrate. An air gap may be formed in the first region A1 by the substrate 100 and the encapsulation member 300.

[0130] like Figure 11As shown, the encapsulation member 300 may include a trench TR formed on a first surface 300a facing the substrate 100. The trench TR may be recessed from the first surface 300a of the encapsulation member 300 in a direction away from the substrate 100. The trench TR may be positioned to at least correspond to a first region A1 and may have a width W3 greater than the width W1 of the first region A1. The trench TR of the encapsulation member 300 may have a width W3 that does not overlap with the first spacer SPC1. For example, the encapsulation member 300 in the recessed region (trench TR) does not overlap with the first spacer SPC1. In other words, the width W3 of the trench TR may be less than the width W2 of the fifth hole 5H. Because the encapsulation member 300 includes a trench TR corresponding to a position in the first region A1, the transmittance of the first region A1 may be enhanced. For example, when the encapsulation member 300 is thinner, the light transmittance may be higher.

[0131] exist Figure 8 In this case, the upper surface of the capping layer 230 directly contacts the encapsulation member 300. However, according to an exemplary embodiment of this disclosure, such as Figure 12 As shown, the upper surface of the cover layer 230 may not contact the encapsulation member 300 and may be spaced apart from each other by a certain distance. In this case, the encapsulation member 300 may be spaced apart from the display layer 200 and / or the substrate 100 by a predetermined gap, and the gap may be maintained primarily by the sealant ST.

[0132] like Figure 13 As shown, the dummy layer DM can be further arranged in the third region A3. The dummy layer DM can be arranged in the gap between the first spacers SPC1 and may include a luminescent material. The dummy layer DM can be placed between the first functional layer 222a and the second functional layer 222c, which respectively extend from the second region A2 to the third region A3.

[0133] Figure 14 This is a schematic plan view of an input sensing layer 40 on a display panel according to an exemplary embodiment of the present disclosure.

[0134] refer to Figure 14 The input sensing layer 40 may include a first sensing electrode 410, first traces 415-1 to 415-4 connected to the first sensing electrode 410, a second sensing electrode 420, and second traces 425-1 to 425-5 connected to the second sensing electrode 420. The first sensing electrode 410 and the second sensing electrode 420 may be arranged in a second region A2, and the first traces 415-1 to 415-4 and the second traces 425-1 to 425-5 may be arranged in a fourth region A4.

[0135] A first sensing electrode 410 may be arranged in the y-direction, and a second sensing electrode 420 may be arranged in the x-direction intersecting the y-direction. The first sensing electrodes 410 arranged in the y-direction may be connected to each other via a first connecting electrode 411 disposed therebetween, forming first sensing lines 410C1 to 410C4 extending in the y-direction. The second sensing electrodes 420 arranged in the x-direction may be connected to each other via a second connecting electrode 421 disposed therebetween, forming second sensing lines 420R1 to 420R5 extending in the x-direction. The first sensing lines 410C1 to 410C4 and the second sensing lines 420R1 to 420R5 may intersect each other. For example, the first sensing lines 410C1 to 410C4 may be perpendicular to the second sensing lines 420R1 to 420R5. Figure 14 As shown in the figure, for example, the first sensing lines 410C1 to 410C4 are longer than the second sensing lines 420R1 to 420R5.

[0136] The first sensing lines 410C1 to 410C4 can be connected to the pads of the sensing signal pad unit 440 via first traces 415-1 to 415-4 provided in the fourth region A4. For example, the first traces 415-1 to 415-4 may have a double-routing structure, wherein they are connected to the top and bottom of each of the first sensing lines 410C1 to 410C4. The first traces 415-1 to 415-4 connected to the top and bottom of the first sensing lines 410C1 to 410C4 can be connected to the corresponding pads, respectively. For example, the first traces 415-1 to 415-4 are respectively connected to the two ends of the first sensing lines 410C1 to 410C4.

[0137] The second sensing lines 420R1 to 420R5 can be connected to the pads of the sensing signal pad unit 440 via the second traces 425-1 to 425-5 provided in the fourth region A4. For example, the second traces 425-1 to 425-5 can be connected to the corresponding pads respectively. For example, the second traces 425-1 to 425-5 can be connected to one end of the second sensing lines 420R1 to 420R5 respectively.

[0138] As referenced above Figure 2A and Figure 2B The first region A1 is the region in which components can be arranged. Therefore, no sensing electrodes are arranged in the first region A1. A metal layer 450 may be arranged near the first region A1, for example, in a third region A3, which will be described later.

[0139] Figure 14A dual-path structure is shown, wherein first traces 415-1 to 415-4 are connected to the top and bottom of each of the first sensing lines 410C1 to 410C4. This dual-path structure can increase sensing sensitivity. Because the first sensing lines 410C1 to 410C4 are longer than the second sensing lines 420R1 to 420R5, a voltage drop occurs in the detection signal (or transmission signal), and therefore the sensing sensitivity can be reduced. According to this exemplary embodiment, by providing the detection signal (or transmission signal) through the first traces 415-1 to 415-4 connected to the two opposite ends of the first sensing lines 410C1 to 410C4, the voltage drop in the detection signal (or transmission signal) can be prevented, and therefore the reduction in sensing sensitivity can be prevented. According to an exemplary embodiment of this disclosure, the first traces 415-1 to 415-4 may have a single-path structure, wherein they are connected to the top or bottom of the first sensing lines 410C1 to 410C4.

[0140] Figure 15 This is a cross-sectional view of the stacked structure of the input sensing layer 40 according to an exemplary embodiment of the present disclosure.

[0141] refer to Figure 15 The input sensing layer 40 may include a first conductive layer CML1 and a second conductive layer CML2. A first insulating layer 43 may be provided between the first conductive layer CML1 and the second conductive layer CML2, and a second insulating layer 45 may be provided on the second conductive layer CML2.

[0142] The first conductive layer CML1 and the second conductive layer CML2 may include, for example, a metal layer and / or a transparent conductive layer. The metal layer may include, for example, molybdenum (Mo), menthium (Md), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), or alloys thereof. The transparent conductive layer may include a transparent conductive oxide, such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). Alternatively, the transparent conductive layer may include a conductive polymer (e.g., poly(3,4-ethylenedioxythiophene) (PEDOT)), metal nanowires, or graphene, etc.

[0143] The first conductive layer CML1 and the second conductive layer CML2 can be a single layer or multiple layers. When the first conductive layer CML1 and the second conductive layer CML2 are single layers, they may each include a metal layer or a transparent conductive layer, and the materials of the metal layer and the transparent conductive layer may be as described above. The first conductive layer CML1 or the second conductive layer CML2 may include a single metal layer. The first conductive layer CML1 or the second conductive layer CML2 may include multiple metal layers. The multiple metal layers may include, for example, three layers of Ti / Al / Ti, or two layers of Mo / Md. Alternatively, the multiple metal layers may include metal layers and transparent conductive layers. The first conductive layer CML1 and the second conductive layer CML2 may have different stacking structures or may have the same stacking structure. For example, the first conductive layer CML1 may include a metal layer and the second conductive layer CML2 may include a transparent conductive layer. Alternatively, the first conductive layer CML1 and the second conductive layer CML2 may include the same metal layer.

[0144] The materials of the first conductive layer CML1 and the second conductive layer CML2, as well as the layout of the sensing electrodes included in the first conductive layer CML1 and the second conductive layer CML2, can be determined by considering sensing sensitivity. Resistive-capacitive (RC) delay can affect sensing sensitivity. Because sensing electrodes including a metal layer have a smaller resistance than those including a transparent conductive layer, the RC value can be reduced. Accordingly, the charging time of the capacitor defined between the sensing electrodes can be reduced. Compared to sensing electrodes including a metal layer, sensing electrodes including a transparent conductive layer are not visually visible to the user and can increase the input area, thereby increasing capacitance. To prevent sensing electrodes including a metal layer from being observed by the user, sensing electrodes including a metal layer can have a mesh shape. Mesh-shaped sensing electrodes can increase flexibility and reduce noise on the display panel.

[0145] Each of the first insulating layer 43 and the second insulating layer 45 may include an inorganic insulating material and / or an organic insulating material. The inorganic insulating material may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON), and the organic insulating material may include an organic polymer material.

[0146] The above reference Figure 14 The first sensing electrode 410, the first connecting electrode 411, the second sensing electrode 420, and the second connecting electrode 421 described may each be included in the first conductive layer CML1 or the second conductive layer CML2.

[0147] According to an exemplary embodiment of this disclosure, the first conductive layer CML1 may include a first connection electrode 411, and the second conductive layer CML2 may include a first sensing electrode 410, a second sensing electrode 420, and a second connection electrode 421. According to an exemplary embodiment of this disclosure, the first conductive layer CML1 may include a first sensing electrode 410, a second sensing electrode 420, and a second connection electrode 421, and the second conductive layer CML2 may include the first connection electrode 411. According to an exemplary embodiment of this disclosure, the first conductive layer CML1 may include a first sensing electrode 410 and a first connection electrode 411, and the second conductive layer CML2 may include a second sensing electrode 420 and a second connection electrode 421. In this case, the first sensing electrode 410 and the first connection electrode 411 are included on the same layer and integrally formed with each other, and the second sensing electrode 420 and the second connection electrode 421 are also included on the same layer. Therefore, the insulating layer between the first conductive layer CML1 and the second conductive layer CML2 may not include contact holes. For example, while the second sensing electrode 420 and the second connecting electrode 421 intersect, the first sensing electrode 410 (which is connected to the first connecting electrode 411) is insulated from the second sensing electrode 420 (which is connected to the second connecting electrode 421 formed on the first insulating layer 43) (e.g., it does not contact the second sensing electrode 420).

[0148] Figure 15 The input sensing layer 40 is shown to include a first conductive layer CML1, a first insulating layer 43, a second conductive layer CML2, and a second insulating layer 45. However, according to an exemplary embodiment of this disclosure, a buffer layer comprising an inorganic or organic insulating material may be further disposed below the first conductive layer CML1.

[0149] Figure 16 This is a plan view of a portion of a display device according to an exemplary embodiment of the present disclosure.

[0150] refer to Figure 16 The first sensing electrode 410 may be arranged in the y-direction, and the second sensing electrode 420 may be arranged in the x-direction. Adjacent second sensing electrodes 420 may be connected to each other via a second connecting electrode 421 placed between them. Adjacent first sensing electrodes 410 may be connected to each other via a first connecting electrode 411. The first sensing electrode 410 and the second sensing electrode 420, as well as the first connecting electrode 411 and the second connecting electrode 421, may have a mesh (or grid or lattice) shape. When the first sensing electrode 410 and the second sensing electrode 420 include a metal layer, the first sensing electrode 410 and the second sensing electrode 420 may have a mesh shape to prevent visibility to the user and / or transmission of light emitted from the light-emitting diode of each pixel. Figure 16As shown in the enlarged view, the first sensing electrode 410 and the second sensing electrode 420 can be mesh-shaped metal layers including holes 410H and 420H, respectively. Holes 410H and 420H can be arranged to overlap with the light-emitting region EA of the pixel. In other words, the corresponding mesh lines ML of the first sensing electrode 410 and the second sensing electrode 420 can be positioned to correspond to the non-light-emitting region NEA. Figure 9A As shown, the light emitting region EA may include a first light emitting region EA1 that emits light of a first color, a second light emitting region EA2 that emits light of a second color, and a third light emitting region EA3 that emits light of a third color. The light emitting region EA may emit, for example, red light, green light, blue light, or white light. The first connecting electrode 411 and the second connecting electrode 421 may each include a mesh-shaped metal layer. Figure 16 In the diagram, holes 410H and 420H are shown to have the same shape. However, this disclosure is not limited thereto. For example, three types of mesh holes corresponding to three types of light emitting regions (such as the first light emitting region to the third light emitting region EA1, EA2 and EA3) can be formed.

[0151] The first connection electrode 411 may include an island portion 411b spaced apart from the first sensing electrode 410. The island portion 411b may be disposed within a hole formed in the second connection electrode 421 and may be spaced apart from the second connection electrode 421 to be electrically insulated from the second connection electrode 421.

[0152] One of adjacent first sensing electrodes 410 can be connected to island portion 411b via first bridge portion 411a, and the other first sensing electrode 410 can be connected to island portion 411b via second bridge portion 411c. In the first connecting electrode 411, the first bridge portion 411a, island portion 411b, and second bridge portion 411c can be connected to each other. According to an exemplary embodiment of this disclosure, island portion 411b can be arranged on the same layer as the layer on which the first sensing electrode 410, the second sensing electrode 420, and the second connecting electrode 421 are arranged. For example, Figure 15 The second conductive layer CML2 may include an island portion 411b, a first sensing electrode 410, a second sensing electrode 420, and a second connecting electrode 421. On the other hand, the first bridge portion 411a and the second bridge portion 411c may be disposed on a layer different from the layer on which the island portion 411b is disposed. For example, Figure 15 The first conductive layer CML1 may include a first bridge portion 411a and a second bridge portion 411c. Therefore, the first bridge portion 411a, the island portion 411b, and the second bridge portion 411c can be connected to each other through contact holes formed in the first insulating layer 43.

[0153] The dummy electrode 430 can be arranged between the first sensing electrode 410 and the second sensing electrode 420, which are adjacent to each other. For example, as Figure 16 As shown, the dummy electrode 430 may include a first dummy electrode 431 and a second dummy electrode 432, each extending along the edge of the first sensing electrode 410 or the second sensing electrode 420. For example, the first dummy electrode 431 and the second dummy electrode 432 may each extend in a zigzag shape. The dummy electrode 430 may be arranged to increase sensing sensitivity, and the dummy electrode 430 may be a floating electrode. The dummy electrode 430 or the floating electrode may be electrically separated from the first sensing electrode 410 and the second sensing electrode 420.

[0154] The first sensing electrode 410 and the second sensing electrode 420 disposed around the first region A1 may have different shapes than the other sensing electrodes. The first sensing electrode 410 and the second sensing electrode 420 disposed around the first region A1 may have smaller areas than the other sensing electrodes. For example, portions of the first sensing electrode 410 and the second sensing electrode 420 may be removed from the first region A1.

[0155] Each of the first sensing electrode 410 and the second sensing electrode 420 adjacent to the first region A1 may have a circular edge, and the arrangement of the respective circular edges of the first sensing electrode 410 and the second sensing electrode 420 may have a shape surrounding the first region A1.

[0156] A metal layer 450 may be disposed between the first region A1 and the first sensing electrode 410 and the second sensing electrode 420. The first sensing electrode 410 and the second sensing electrode 420 may be disposed in the second region A2, which is an active region, and the metal layer 450 may be disposed in the third region A3. The metal layer 450 may be used to cover the routing wiring disposed in the third region A3, for example, the third portion DL-D of the data line DL (see...). Figure 6B , Figure 8 and Figures 11 to 13 ) and the third part of the scan line SL, SL-D (see Figure 6B , Figure 8 and Figures 11 to 13 If the metal layer 450 is not arranged and the wiring is therefore exposed by not being covered, then external light incident through the first zone A1 can be... Figure 17 The bypass wiring DWL reflects light and can be visually identifiable, or may affect the characteristics of components that can be arranged in the first region A1. According to an exemplary embodiment of this disclosure, a metal layer 450 may be provided on a second substrate (e.g., encapsulation member 300) and may overlap with a plurality of first spacers SPC1 and a plurality of bypass wiring DWL disposed on a first substrate (e.g., substrate 100), the metal layer 450 being configured to prevent external light incident through the transmission region (e.g., first region A1) from reaching the plurality of bypass wiring DWL.

[0157] According to an exemplary embodiment of the present disclosure, a metal layer 450 disposed around a first region A1 (e.g., in a third region A3) can minimize the effect of reflected light by blocking obliquely traveling external light.

[0158] The metal layer 450 may surround the first region A1 and have a certain width, and may have an annular shape surrounding the first region A1 in a plan view. The metal layer 450 may include, for example, molybdenum (Mo), menthium (Md), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), or alloys thereof. The metal layer 450 may be in a floating state, wherein it is not electrically connected to surrounding elements, such as the first sensing electrode 410 and the second sensing electrode 420, and the dummy electrode 430. The metal layer 450 may overlap with the first spacer SPC1 of the third region A3. According to an exemplary embodiment of the present disclosure, the metal layer 450 may be disposed in at least one of the first insulating layer 43 and the second insulating layer 45.

[0159] Figure 17 For exemplary embodiments according to this disclosure along Figure 16 The cross-sectional view of this part of the display device is taken by line V-V'.

[0160] refer to Figure 17 A display layer 200 disposed on substrate 100 includes a plurality of pixels, such as an organic light-emitting diode (OLED), disposed in a second region A2. The display layer 200 includes a bypass wiring (DWL) disposed in a third region A3. First spacers SPC1 and third spacers SPC3 may be disposed on the display layer 200. First spacers SPC1 may be disposed in the third region A3, and third spacers SPC3 may be disposed in the non-light-emitting region (NEA) of the second region A2. Some of the first spacers SPC1 may be disposed at the boundary between the third region A3 and the second region A2. Although in Figure 17 In the display layer 200, the first spacer SPC1 and the third spacer SPC3 are arranged on the display layer 200, but the first spacer SPC1 and the third spacer SPC3 may be part of the display layer 200.

[0161] The encapsulation component 300 can be arranged to cover the display layer 200. The encapsulation component 300 encapsulates the display layer 200 and can be a rigid encapsulation substrate.

[0162] Metal layer 450 may be placed on package member 300 and may include a sixth hole 450H corresponding to the first region A1. Metal layer 450 may be disposed on the same layer on which the input sensing layer 40 is disposed. Metal layer 450 may be disposed below the first sensing electrode 410, a first insulating layer 43 of the input sensing layer 40 is disposed between metal layer 450 and the first sensing electrode 410, and the first sensing electrode 410 may be covered by a second insulating layer 45. Metal layer 450 may float from the input sensing layer 40 and is therefore electrically insulated from the input sensing layer 40. For example, metal layer 450 may be electrically insulated from the first sensing electrode 410 and the second sensing electrode 420. Metal layer 450 may be arranged to overlap with the bypass wiring DWL and the first spacer SPC1 disposed in the third region A3 of display layer 200.

[0163] Because region A1 is transmissive, components arranged in region A1 (such as sensors or cameras, CMRs) can emit and / or receive external light outwards. Since light travels in all directions, without the metal layer 450, as when... Figure 17 The dashed lines indicate that external light ETL incident at an angle toward the substrate 100 can travel toward the display layer 200. However, according to an exemplary embodiment of this disclosure, the metal layer 450 is arranged to surround the first region A1 and thus reflect the external light ETL incident at an angle, thereby preventing the external light ETL from traveling toward the display layer 200.

[0164] According to this exemplary embodiment, the edge of the sixth hole 450H may be closer to the first region A1 than the closest bypass wiring DWL to the first region A1. Therefore, it prevents external light ETL traveling at an angle from reaching the bypass wiring DWL. If external light ETL does reach the bypass wiring DWL, it can be reflected by the bypass wiring DWL and thus interfere with the performance of components (such as sensors or camera CMRs) arranged in the first region A1.

[0165] An optical functional layer 50 may be placed on the input sensing layer 40. The optical functional layer 50 may include a second aperture 50H corresponding to the first region A1. The optical functional layer 50 may include external light reflecting elements, such as a phase delayer and / or polarizer, to prevent reflection of external light ETL. Alternatively, the optical functional layer 50 may include external light reflecting elements, such as a combination of a color filter and a black matrix, or a destructive interference structure, to prevent reflection of external light ETL.

[0166] The width (diameter) W5 of the second aperture 50H of the optical functional layer 50 can be greater than the width (diameter) W4 of the sixth aperture 450H of the metal layer 450. Because the optical functional layer 50 prevents reflection of external light ETL, when the second aperture 50H of the optical functional layer 50 is formed to have a width substantially the same as the sixth aperture 450H of the metal layer 450, and when the camera CMR is used as a component, the optical functional layer 50 can limit the field of view of the camera CMR (e.g., a wide-angle camera). For example, in this case, only light incident at a small angle from the outside can reach the camera CMR, while light incident at a large angle from the outside can be blocked by the optical functional layer 50. In other words, the camera CMR may not be able to capture light from a wide range of incident angles. The limitation of the field of view can be more significant when the optical functional layer 50 includes external light reflecting components (such as a relatively thick polarizer). The limitation of the field of view can also be more significant due to process errors that may occur during the process of aligning the second aperture 50H of the optical functional layer 50 with the first region A1 during the manufacture of the display device.

[0167] According to an exemplary embodiment of this disclosure, the second hole 50H of the optical functional layer 50 is formed to have a width larger than that of the sixth hole 450H of the metal layer 450, thereby preventing the limitation of the field of view of the camera CMR and also preventing damage to the image captured by the camera CMR. The window 60 can be disposed on the optical functional layer 50 by means of an optically transparent adhesive OCA.

[0168] Figure 18 This is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure.

[0169] refer to Figure 18 A buffer layer 201, a gate insulating layer 203, a first interlayer insulating layer 205, a second interlayer insulating layer 207, a first organic insulating layer 209, and a second organic insulating layer 211 are disposed on the substrate 100. Each pixel circuit PC may include a thin-film transistor and a capacitor, and the semiconductor layer and electrodes of the thin-film transistor and the electrodes of the capacitor may be disposed on the substrate 100. Figure 8 and Figure 10 On the insulating layer described.

[0170] The pixel electrode 221 can be connected to the connecting metal electrode CM through the contact hole of the second organic insulating layer 211, and the connecting metal electrode CM can be connected to the thin-film transistor of the pixel circuit PC through the contact hole of the first organic insulating layer 209. According to an exemplary embodiment of this disclosure, the connecting metal electrode CM can be omitted, and the pixel electrode 221 can be connected to the thin-film transistor of the pixel circuit PC through the corresponding contact holes of the first organic insulating layer 209 and the second organic insulating layer 211.

[0171] A pixel defining layer 215 disposed on pixel electrode 221 may include an opening that overlaps with a portion of pixel electrode 221 and exposes a portion of pixel electrode 221, and the opening of pixel defining layer 215 may define a light emitting region EA. A first functional layer 222a, an emitting layer 222b, a second functional layer 222c, a counter electrode 223, and a capping layer 230 may be sequentially stacked on pixel defining layer 215. Emitting layer 222b may be arranged to overlap with the opening of pixel defining layer 215. The material and features of display layer 200 disposed on substrate 100 are the same as those referenced above. Figure 8 and Figure 10 The descriptions are the same.

[0172] The display layer 200 includes an insulating layer, a first functional layer 222a, a second functional layer 222c, a counter electrode 223, and a capping layer 230, which prevent the reflection of external light. Here, the insulating layer is as described above. Figure 8 and Figure 10 Description. The insulating layer, first functional layer 222a, second functional layer 222c, opposite electrode 223 and / or capping layer 230 included in the display layer 200 may be partially exposed without being completely covered by the metal layer 450.

[0173] The encapsulation member 300 may be arranged to face the substrate 100. In the first region A1, the material included in the display layer 200 is not disposed between the lower surface of the encapsulation member 300 and the upper surface of the substrate 100. For example, an air gap may be formed in the first region A1 between the substrate 100 and the encapsulation member 300. In other words, in the first region A1, the upper surface of the substrate 100 may directly face the lower surface of the encapsulation member 300.

[0174] The metal layer 450 may be arranged in the third zone A3 and may overlap with the bypass wiring DWL and the first spacer SPC1 arranged in the third zone A3.

[0175] The metal layer 450 can directly contact the upper surface of the package member 300 and can be formed in the process of forming the input sensing layer 40 (e.g., the process of forming the first trace 415 and the first connection electrode 411). Figure 18 A first trace 415 placed in the fourth region A4 and a metal layer 450 placed in the third region A3 are shown disposed directly on the upper surface of the encapsulation member 300. At least one of the traces placed in the fourth region A4, such as the first trace 415, may overlap with the sealant ST.

[0176] A first insulating layer 43, formed of, for example, silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON), may be disposed on the metal layer 450. A sensing electrode and a second insulating layer 45 may be sequentially disposed on the first insulating layer 43. The first insulating layer 43 and the second insulating layer 45 may each include a hole 43H and a hole 45H disposed in the first region A1.

[0177] The end of the first insulating layer 43 may cover the inner edge of the metal layer 450, and the end of the second insulating layer 45 may cover the end of the first insulating layer 43. The first insulating layer 43 and the second insulating layer 45 may comprise the same material or may comprise different materials from each other. Each of the first insulating layer 43 and the second insulating layer 45 may comprise an inorganic insulating material or an organic insulating material.

[0178] Figure 18 A metal layer 450 is shown below a first insulating layer 43. The first insulating layer 43 may be placed between the metal layer 450 and a first sensing electrode 410, the first sensing electrode 410 not overlapping with the metal layer 450, and the first sensing electrode 410 may be covered by a second insulating layer 45. However, this disclosure is not limited thereto. For example, according to an exemplary embodiment of this disclosure, a sensing electrode including the first sensing electrode 410 and a second connection electrode may be arranged below the first insulating layer 43, a trace may be arranged above the first insulating layer 43, and when the trace is formed, the metal layer 450 may be formed together with the trace, and therefore may be arranged above the first insulating layer 43.

[0179] The optical functional layer 50 may be arranged as part of the covering metal layer 450, and the optically clear adhesive OCA and window 60 may be arranged on the optical functional layer 50. Figure 2B As shown, by removing the portion corresponding to the first region A1 from the optically clear adhesive OCA, the optically clear adhesive OCA may include a third hole OCAH. A light-shielding unit 61 may be disposed on the rear surface of the window 60 to cover elements disposed in the fourth region A4, such as the first trace 415. The light-shielding unit 61 covering the dead zone may include a colored layer. For example, the light-shielding unit 61 may be one or more colored layers printed or deposited on the rear side of the window 60 in the fourth region A4. For example, the light-shielding unit 61 may include layers of various colors such as white, black, silver, gold, and pink. The light-shielding unit 61 may have the shape of a polygonal ring or frame surrounding the second region A2. For example, the light-shielding unit 61 may have the shape of an approximately quadrilateral ring or frame.

[0180] The second aperture 50H of the optical functional layer 50 may overlap with the sixth aperture 450H of the metal layer 450. For alignment errors during the assembly of the display device and / or the quality of the image captured by the camera due to the camera's field of view when component 20 is a camera, the width W4 of the sixth aperture 450H of the metal layer 450 may be smaller than the width W5 of the second aperture 50H of the optical functional layer 50. For example, the camera may be able to capture light incident at a relatively large angle.

[0181] Figure 19 A portion of a display panel according to an exemplary embodiment of the present disclosure is shown schematically. Figure 20 For including along Figure 19 A cross-sectional view of the display device taken from the section of line VI-VI'.

[0182] Figure 19 A portion of the display panel, including a first zone A1 and a third zone A3 surrounding the first zone A1, is shown. Figure 19 The cross-sectional diagram CSV can correspond to along Figure 19 The cross section intercepted by line VI-VI' of the plan view PV.

[0183] refer to Figure 19 The third region A3 may include a first sub-region A31 and a second sub-region A32. The second sub-region A32 may be adjacent to and surround the first region A1, and the first sub-region A31 may surround the second sub-region A32 and be adjacent to the second region A2. A plurality of first spacers SPC1 may be arranged in the first sub-region A31, and second spacers SPC2 may be arranged in the second sub-region A32. The first spacers SPC1 and the second spacers SPC2 may be arranged on a stack of at least one inorganic insulating layer IL and at least one organic insulating layer OL above the substrate 100. For example, as Figure 19 (CSV) and Figure 20 As shown, at least one organic insulating layer OL is formed on at least one inorganic insulating layer IL.

[0184] The first spacer SPC1 may be an island-shaped insulating pattern. The first spacer SPC1 may be arranged at regular intervals in the first sub-region A31. Some of the first spacer SPC1 may be arranged at the boundary between the second region A2 and the third region A3, and thus may be arranged in both the second region A2 and the third region A3. Within the second sub-region A32, the second spacer SPC2 may be arranged along the arc of the first region A1 to have a closed-loop shape, such as an annular or circular shape. Therefore, the second spacer SPC2 may be adjacent to the first region A1, and the first spacer SPC1 may be arranged around the second spacer SPC2. The second spacer SPC2 may include the same material as that included in the first spacer SPC1. According to an exemplary embodiment of this disclosure, the second spacer SPC2 may include a different material than that included in the first spacer SPC1. According to an exemplary embodiment of this disclosure, the second spacer SPC2 may include an organic insulating material. The width Wb of the second spacer SPC2 in the x-direction may be greater than the width Wa of each of the first spacer SPC1 in the x-direction. The first spacer SPC1, the second spacer SPC2, and the third spacer SPC3 can be used to maintain the gap between the substrate 100 and the encapsulation member 300 and to support the encapsulation member 300. The second spacer SPC2 can be used to separate the first region A1 from the second region A2 to prevent foreign substances introduced through the first region A1, such as oxygen or moisture, from penetrating into the display area (second region A2) and degrading the performance of the display element. The metal layer 450 can be placed on the encapsulation member 300 and can overlap with the bypass wiring DWL, the first spacer SPC1, and the second spacer SPC2 arranged in the third region A3.

[0185] Figure 19 and Figure 20 An example including a single second spacer SPC2 is shown. According to an exemplary embodiment of this disclosure, two or more second spacer SPC2s may be spaced apart from each other by a predetermined distance. Second spacer SPC2s farther from the first zone A1 may surround second spacer SPC2s closer to the first zone A1. Two or more second spacer SPC2s may have the same width or different widths. In this case, the number of second spacer SPC2s can be determined to prevent excessive increase in the size of the third zone A3, and the number of first spacer SPC1s arranged in the third zone A3 can be reduced.

[0186] according to Figure 19 and Figure 20 In an exemplary embodiment, the island-shaped spacer and the annular spacer are arranged together in the third region A3 to provide more uniform support for the encapsulation member 300 and thus effectively prevent sagging and / or breakage of the encapsulation member 300. Other components are the same as those referenced above. Figures 7 to 18The descriptions are the same, and therefore their descriptions will be omitted.

[0187] The accompanying drawings of the above exemplary embodiments illustrate an example in which a first organic insulating layer 209 and a second organic insulating layer 211 are arranged between the pixel circuit PC and the pixel electrode 221, but this disclosure is not limited thereto. For example, according to an exemplary embodiment of this disclosure, a single organic insulating layer corresponding to the first organic insulating layer 209 and / or the second organic insulating layer 211 may be arranged between the pixel circuit PC and the pixel electrode 221, and the connecting metal electrode CM may be omitted. In this case, the pixel electrode 221 may contact the thin-film transistor TFT of the pixel circuit PC (see [reference]) through a contact hole in the single organic insulating layer. Figure 10 ), and therefore can be electrically connected to it.

[0188] According to exemplary embodiments of the present disclosure, the transmissive area of ​​a display device that includes a transmissive area in the display area may not be visually identifiable, and damage to the display device may be prevented. These effects are merely examples, and the present disclosure is not limited thereto.

[0189] It should be understood that the exemplary embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments. Although specific exemplary embodiments have been described with reference to the figures, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, comprising: A first substrate, the first substrate including a transmissive region, a display region surrounding at least a portion of the transmissive region, and a first non-display region disposed between the transmissive region and the display region; An insulating layer is disposed on the first substrate in the display area and the first non-display area; A plurality of display elements, wherein the plurality of display elements are disposed on the insulating layer in the display area; A plurality of first spacers, each having an island shape in a plan view and spaced apart from each other on the insulating layer in the first non-display area, the plurality of first spacers being arranged at regular intervals in a first direction or a second direction; and A second substrate facing the first substrate.

2. The display device according to claim 1, wherein the insulating layer comprises at least one inorganic insulating layer and at least one organic insulating layer, and The at least one organic insulating layer is on the at least one inorganic insulating layer.

3. The display device according to claim 2, wherein each of the plurality of display elements includes a first electrode, a second electrode facing the first electrode, and an emission layer disposed between the first electrode and the second electrode, and A pixel defining layer, placed between the first electrodes of the plurality of display elements, is disposed on the at least one organic insulating layer.

4. The display device according to claim 3, wherein the plurality of first spacers are disposed on the pixel defining layer in the first non-display area.

5. The display device of claim 3, wherein the second electrode covers the pixel defining layer and the plurality of first spacers.

6. The display device according to claim 1, wherein the plurality of first spacers comprise an organic insulating material.

7. The display device according to claim 1, further comprising a second spacer disposed on an insulating layer in the first non-display area and having a ring shape surrounding the transmissive area.

8. The display device according to claim 7, wherein the second spacer is adjacent to the transmissive region, and The plurality of first spacers are arranged around the second spacer.

9. The display device according to claim 7, wherein the second spacer comprises an organic insulating material.

10. The display device according to claim 1, further comprising a plurality of third spacers disposed on the insulating layer in the display area, each having an island shape and arranged between the plurality of display elements.

11. The display device of claim 1, further comprising a sealant that binds the first substrate to the second substrate and is disposed on the first substrate in a second non-display area surrounding the display area.

12. The display device of claim 1, further comprising a metal layer provided on the second substrate and overlapping the plurality of first spacers.

13. The display device according to claim 1, wherein the second substrate has a groove positioned corresponding to the transmissive region, and The trench is formed on the surface facing the first substrate as a recessed area of ​​the second substrate.

14. A display device, comprising: A first substrate, the first substrate including a transmissive region, a display region surrounding at least a portion of the transmissive region, and a first non-display region disposed between the transmissive region and the display region; A first electrode is disposed on the display area on the first substrate; An insulating layer is disposed on the first substrate in the display area and the first non-display area, and includes an opening that exposes a portion of the first electrode in the display area and includes a through-hole corresponding to the transmission area; A plurality of first spacers are placed on the insulating layer in the first non-display area, each having an island shape in a plan view and arranged around the through hole along the circumference of the through hole, the plurality of first spacers being arranged at regular intervals in a first direction or a second direction. An emitting layer is disposed within the opening of the insulating layer; and The second electrode faces the first electrode in the display area and covers the plurality of first spacers in the first non-display area.

15. The display device of claim 14, wherein the plurality of first spacers comprise an organic insulating material.

16. The display device of claim 14, further comprising a second spacer disposed on the insulating layer in the first non-display area and having a ring shape surrounding the transmissive area. The second spacer is located between the through hole and the plurality of first spacers.

17. The display device of claim 16, wherein the second spacer comprises an organic insulating material.

18. The display device according to claim 14, further comprising a second substrate facing the first substrate.

19. The display device of claim 18, further comprising a metal layer provided on the second substrate and overlapping the plurality of first spacers.

20. The display device of claim 18, wherein the second substrate has a groove disposed corresponding to the transmissive region, the groove being on the surface of the second substrate facing the first substrate.

21. A display device, comprising: A first substrate, the first substrate including a transmissive region, a display region surrounding at least a portion of the transmissive region, and a first non-display region disposed between the transmissive region and the display region; An insulating layer is formed on the first substrate and disposed in the display area and the first non-display area; Multiple bypass wirings are disposed in the insulating layer in the first non-display area; A plurality of first spacers, each having an island shape in a plan view and spaced apart from each other on the insulating layer in the first non-display area, the plurality of first spacers being arranged at regular intervals in a first direction or a second direction; A second substrate facing the first substrate; and A metal layer is provided on the second substrate and overlaps with the plurality of first spacers and the plurality of winding wirings, the metal layer being configured to prevent external light incident through the transmission area from reaching the plurality of winding wirings.

22. The display device of claim 21, further comprising a trench formed on the surface facing the first substrate as a recessed region of the second substrate. The groove is positioned to correspond to the transmission area and does not overlap with the plurality of first spacers.

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