Semiconductor device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same, the device comprising a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer; the first semiconductor layer having a smaller bandgap than the second semiconductor layer; a first electrode and a third electrode formed on the first or second semiconductor layer, a second electrode formed on the second semiconductor layer, a third semiconductor layer below the second electrode, and the third semiconductor layer being a P-type third semiconductor layer. The solution of the present disclosure can at least help achieve one of the following effects: reduce gate leakage current, have high threshold voltage, high power, high reliability, can achieve low on-resistance and a normally-off state of the device, can provide a stable threshold voltage, so that the semiconductor device has good switching characteristics and is safer in use.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Group III nitride semiconductors are an important new type of semiconductor material, mainly including AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Due to the advantages of direct band gap, wide bandgap, high breakdown electric field strength, high saturation electron velocity, etc., Group III nitride semiconductors have broad application prospects in the fields of light-emitting devices, power electronics, radio frequency devices, etc.

[0003] It is desirable to utilize the advantages of the III-nitride semiconductors to develop high-performance semiconductor devices with high withstand voltage, high power, and low on-resistance through optimized design of device structure and process. Summary of the invention

[0004] A brief overview of the present disclosure will be given below in order to provide a basic understanding of certain aspects of the present disclosure. It should be understood that this overview is not an exhaustive overview of the present disclosure. It is not intended to identify key or important parts of the present disclosure, nor is it intended to limit the scope of the present disclosure. Its purpose is simply to give certain concepts in a simplified form as a prelude to a more detailed description discussed later.

[0005] According to one aspect of the present disclosure, there is provided a semiconductor device comprising

[0006] A substrate; a first semiconductor layer formed on the first surface of the substrate; a second semiconductor layer formed on the first surface of the first semiconductor layer; the first semiconductor layer has a smaller bandgap width than the second semiconductor layer; a first electrode and a third electrode formed on the first or second semiconductor layer, and a second electrode formed on the second semiconductor layer; a length range of the third semiconductor layer projected onto the substrate is within a length range of the second electrode projected onto the substrate, and the third semiconductor layer is a P-type semiconductor layer.

[0007] Furthermore, the substrate is sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3 or single crystal silicon.

[0008] Furthermore, the first semiconductor layer is an intrinsic nitride semiconductor layer or an unintentionally doped nitride semiconductor layer, and the epitaxial direction of the intrinsic nitride semiconductor layer or the unintentionally doped nitride semiconductor layer parallel to the substrate is a

[0001] direction.

[0009] Furthermore, a two-dimensional charge carrier gas is formed between the first semiconductor layer and the second semiconductor layer, and the third semiconductor layer depletes 95%-100% of the two-dimensional charge carrier gas in at least a partial area below the second electrode area, while basically does not deplete the two-dimensional charge carrier gas in other areas except the partial area.

[0010] Furthermore, a two-dimensional charge carrier gas is formed between the first semiconductor layer and the second semiconductor layer, and when the bias voltage of the second electrode is 0, the two-dimensional charge carrier gas corresponding to at least a portion of the second electrode is lower than 5E+11 / cm2.

[0011] Furthermore, the epitaxial direction of the third semiconductor layer parallel to the substrate is the

[0001] direction, and its lateral epitaxial direction is .

[0012] Furthermore, the first semiconductor layer has a second surface opposite to the first surface of the substrate and a first surface facing away from the first surface of the substrate, the third semiconductor layer has a second surface opposite to the first surface of the first semiconductor layer and a first surface facing away from the first surface of the second semiconductor layer, the third semiconductor layer also has a third surface connected to the first and second surfaces of the third semiconductor layer, and the third surface of the third semiconductor layer forms an angle greater than 30 degrees and less than or equal to 90 degrees with the second surface of the third semiconductor layer.

[0013] Furthermore, the third semiconductor layer has a length of 0.01-10 microns and a thickness of 0.01-10 microns.

[0014] Furthermore, the third semiconductor layer is a single-layer structure or a plurality of discrete layer structures whose number is greater than or equal to 2.

[0015] Further, the plurality of discrete layer structures are discrete layer structures in a direction perpendicular to the substrate or discrete layer structures in a direction parallel to the substrate.

[0016] Furthermore, the separate layer structures are in close contact with each other, or there is a certain interval between the separate layer structures.

[0017] Furthermore, the third semiconductor layer is a layer structure with a gradient doping concentration.

[0018] Furthermore, the doping concentration of the third semiconductor layer gradually changes from the center of the third semiconductor layer to both sides parallel to the substrate, or the doping concentration of the third semiconductor layer gradually changes from the center of the third semiconductor layer to both sides vertical to the substrate, or the doping concentration of the third semiconductor layer is unilaterally gradual.

[0019] Furthermore, the doping concentration range of the third semiconductor layer is 1E+17 / cm3-5E+19 / cm3.

[0020] Furthermore, the third semiconductor layer directly contacts the second semiconductor layer or is spaced apart from the third semiconductor layer by a certain thickness.

[0021] Furthermore, a fourth semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer.

[0022] Furthermore, the fifth and / or sixth semiconductor layer is provided between the first semiconductor layer and the substrate.

[0023] Furthermore, a second insulating layer having an opening is formed between the first semiconductor layer and the substrate, and a seed layer is formed in the opening, and the seed layer is located below the first electrode.

[0024] Furthermore, a first and / or third insulating layer is provided between the second semiconductor layer and the second electrode.

[0025] Furthermore, the first and third insulating layers are silicon dioxide, silicon nitride and / or Al2O3.

[0026] Furthermore, the third semiconductor layer is connected to a fourth electrode.

[0027] Further, the fourth electrode is an independent electrode, or the fourth electrode is a non-independent electrode.

[0028] Furthermore, the substrate has a second surface opposite to the first surface, and the fourth electrode connected to the third semiconductor layer is formed on the second surface of the substrate.

[0029] Furthermore, the third semiconductor layer extends along a direction perpendicular to the flow of the two-dimensional charge carrier gas, and a fourth electrode connected to the third semiconductor layer is formed at a position not covered by the projection of the second electrode.

[0030] Furthermore, a fourth electrode connected to the third semiconductor layer is formed at the first electrode of the semiconductor device.

[0031] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: providing a substrate; forming a first semiconductor layer on a first surface of the substrate; forming a third semiconductor layer in the first semiconductor layer; forming a second semiconductor layer on a first surface of the first semiconductor layer; the first semiconductor layer having a smaller bandgap width than the second semiconductor layer, thereby forming a two-dimensional charge carrier gas at an interface between the first semiconductor layer and the second semiconductor layer; forming a first electrode and a third electrode having ohmic contact with the two-dimensional charge carrier gas, and forming a second electrode located on the first surface side of the third semiconductor layer, wherein a length range of the third semiconductor layer projected to the substrate is within a length range of the second electrode projected to the substrate.

[0032] Furthermore, the third semiconductor layer is formed by lateral epitaxy or ion implantation, and the third semiconductor layer is prepared as a discrete structure or a structure with a gradient doping concentration.

[0033] Furthermore, a second insulating layer is deposited on the first surface of the substrate, the second insulating layer covers the entire surface of the substrate, at least a portion of the second insulating layer is removed to form an opening, and a seed crystal material is coplanarly deposited, the seed crystal layer serving as a growth core for the first semiconductor layer.

[0034] Furthermore, before step S200, a seed crystal material is fully deposited on the first surface of the substrate, a portion of the seed crystal material is removed, and then a second insulating layer is coplanarly deposited, and at least a portion of the second insulating layer is removed until a portion of the seed crystal layer is exposed, and the exposed portion of the seed crystal layer serves as the growth core of the first semiconductor layer.

[0035] Furthermore, removing at least a portion of the second insulating layer means removing at least a portion of the second insulating layer corresponding to a subsequent first electrode region; or a position of the exposed portion of the seed layer corresponds to the first electrode region.

[0036] Furthermore, the first and third semiconductor layers are manufactured by using a seed layer as a core selection / lateral epitaxial process.

[0037] Furthermore, the third semiconductor layer is a P-type doped nitride layer, and its lateral growth direction is a [11-20] crystal direction.

[0038] Furthermore, a first region of the first semiconductor layer comprising a low-doped or unintentionally doped nitride semiconductor is laterally epitaxially grown with the seed layer as the core, and the first region of the first semiconductor layer starts to grow from the position where the seed layer is located, and by controlling its growth rate, the growth of the first region is stopped when the first semiconductor layer does not completely cover the second insulating layer.

[0039] Furthermore, with the first region of the grown first semiconductor layer as the core, the P-type doped nitride layer is grown on the surface and side of the first region of the first semiconductor layer. After growing a certain thickness of the P-type doped nitride layer, the growth of a low-doped or unintentionally doped nitride semiconductor layer is continued. Then, by removing part of the low-doped or unintentionally doped nitride semiconductor layer and the P-type nitride semiconductor layer to expose the P-type nitride semiconductor layer and the first region of the first semiconductor layer, the steps of growing the P-type doped nitride layer and continuing to grow the low-doped or unintentionally doped nitride semiconductor layer can be repeated multiple times.

[0040] Furthermore, there is a step 410 between step 400 and step 500; in step 410, an insulating material is fully deposited on the first surface of the second semiconductor layer to form the first insulating layer, and / or a third insulating layer is formed by etching the insulating material at a position corresponding to the second electrode.

[0041] Furthermore, there is also step 600: in step 600, a through hole is formed by etching at a position corresponding to the third semiconductor layer on the second surface of the substrate, the through hole directly reaches the third semiconductor layer, and a fourth electrode is formed in the through hole, thereby controlling the electric potential of the third semiconductor layer.

[0042] Furthermore, there is a step 600: forming a through hole by etching on one side of the width of the third semiconductor layer not covered by the orthographic projection of the second electrode, and forming a fourth electrode connected to the third semiconductor layer in the through hole.

[0043] According to another aspect of the present disclosure, an electronic device is provided, which includes the semiconductor device described in the present disclosure.

[0044] According to another aspect of the present disclosure, the electronic device is a power supply device, a server, a charger, a mobile phone, or an amplifier.

[0045] The solution of the present disclosure can at least help achieve one of the following effects: the semiconductor device can reduce gate leakage current, has high threshold voltage, high power, and high reliability, can achieve low on-resistance and a normally-off state of the device, and can provide a stable threshold voltage, so that the semiconductor device has good switching characteristics and is safer in use. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The specific contents of the present disclosure are described below with reference to the accompanying drawings, which will help to more easily understand the above and other purposes, features and advantages of the present disclosure. The accompanying drawings are only for illustrating the principles of the present disclosure.

[0047] The sizes and relative positions of the elements in the drawings are not necessarily drawn to scale. In the drawings:

[0048] Figure 1 A schematic cross-sectional view showing a structure of a semiconductor device according to a first embodiment;

[0049] Figure 2 A schematic cross-sectional view showing a modification of the structure of the semiconductor device according to the first embodiment;

[0050] Figure 3 A schematic cross-sectional view showing a modification of the structure of the semiconductor device according to the first embodiment;

[0051] Figure 4 shows an energy band diagram of a semiconductor device in a first embodiment;

[0052] Figure 5 A schematic cross-sectional view showing a modification of the structure of the semiconductor device according to the first embodiment;

[0053] Figure 6 A schematic cross-sectional view showing a structure of a semiconductor device according to a second embodiment;

[0054] Figure 7 A schematic cross-sectional view showing a structure of a semiconductor device according to a third embodiment;

[0055] Figure 8 A schematic cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment;

[0056] Fig. 9 shows a schematic top view of a semiconductor device structure according to a fifth embodiment;

[0057] Fig.10 A perspective view showing a structure of a semiconductor device according to a fifth embodiment;

[0058] Fig.11 A schematic cross-sectional view showing a structure of a semiconductor device according to a sixth embodiment;

[0059] Figure 12-Figure 22 A schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a seventh embodiment;

[0060] Fig.23 A schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an eighth embodiment;

[0061] Fig.24 A schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a ninth embodiment;

[0062] Fig.25 A schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a tenth embodiment. DETAILED DESCRIPTION

[0063] Exemplary disclosures of the present disclosure are described below in conjunction with the accompanying drawings. For the sake of clarity and conciseness, not all features of the actual disclosure are described in the specification. However, it should be understood that many decisions specific to the disclosure may be made in the process of developing any such actual disclosure in order to achieve the specific goals of the developer, and these decisions may vary from one disclosure to another.

[0064] It should also be noted here that in order to avoid obscuring the contents of the present disclosure due to unnecessary details, only the device structure closely related to the scheme according to the contents of the present disclosure is shown in the drawings, while other details that are not closely related to the contents of the present disclosure are omitted.

[0065] It should be understood that the present disclosure is not limited to the described implementation forms due to the following description with reference to the accompanying drawings. Herein, where feasible, features between different embodiments may be replaced or borrowed, and one or more features may be omitted in one embodiment.

[0066] First embodiment

[0067] Reference Figure 1 A semiconductor device according to a first embodiment will be described.

[0068] Specifically, the semiconductor device of the first embodiment is a compound semiconductor device. Further, the compound semiconductor device is a compound semiconductor device containing a nitride semiconductor material, also referred to as a nitride semiconductor device. The nitride semiconductor device includes a field effect transistor in which a nitride semiconductor material is used. Further, the field effect transistor is a GaN field effect transistor containing a GaN semiconductor material. In particular, the GaN field effect transistor is a normally closed transistor GaN-HEMT.

[0069] like Figure 1As shown, in the first embodiment, the semiconductor device, exemplarily such as a normally closed transistor GaN-HEMT, includes a substrate 100. The material of the substrate 100 can be selected according to actual needs, and the specific form of the substrate 100 is not limited in this embodiment. Optionally, the substrate 100 can be sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3 or single crystal silicon, etc.; further, the substrate 100 can be Al2O3 with a (0001) plane; further, the substrate 100 can be a silicon substrate 100 with a (111) plane. A first semiconductor layer 102 is formed on the first surface of the substrate 100. Optionally, the first semiconductor layer 102 is a GaN layer. Further, the first semiconductor layer 102 is an i-GaN or non-intentionally doped GaN layer. The first semiconductor layer 102 has a second surface opposite to the first surface of the substrate 100 and a first surface facing away from the first surface of the substrate 100. The epitaxial direction of the GaN layer parallel to the substrate is the

[0001] direction.

[0070] A second semiconductor layer 103 is formed on the first surface of the first semiconductor layer 102. The first semiconductor layer 102 has a smaller bandgap than the second semiconductor layer 103, so that a two-dimensional charge carrier gas, such as 2DEG, is formed between the first semiconductor layer 102 and the second semiconductor layer 103. The second semiconductor layer 103 has a second surface opposite to the first surface of the first semiconductor layer 102 and a first surface facing away from the second surface of the first semiconductor layer 102. Optionally, the second semiconductor layer 103 is an AlN, AlGaN, InAlGaN, InAlN layer, etc. A first insulating layer 105 is formed on the first surface of the second semiconductor layer 103. Therefore, the first insulating layer 105 can be a passivation layer, and the optional passivation layer material is SiO2, SiN, Al2O3, etc.

[0071] A first electrode 106, a second electrode 108 and a third electrode 107 are formed, and the first and third electrodes can be formed on the first semiconductor layer 102 or on the second semiconductor layer 103. The first electrode 106 can be an ohmic contact formed by the source electrode and the two-dimensional charge carrier gas, the second electrode 108 can be a Schottky contact formed by the gate electrode and the second semiconductor layer, and the third electrode 107 is an ohmic contact formed by the drain electrode and the two-dimensional charge carrier gas. It can be clearly understood that the first electrode 106 and the third electrode 107 can also be the first doped region (source region) and the second doped region (drain region) corresponding to the device, illustratively, such as a region doped with Si.

[0072] There is a third semiconductor layer 104 below the second electrode 108, and the third semiconductor layer 104 is a P-type third semiconductor layer 104. Optionally, the P-type third semiconductor layer 104 is a P-type GaN. The P-GaN can directly contact the second semiconductor layer, or a certain thickness can be spaced between the two. Exemplarily, a certain first semiconductor material can be spaced between the two. Since the third semiconductor layer 104 has a lower Fermi level, the 2DEG located above it can be depleted, resulting in the device having a higher threshold voltage and a normally closed state of the device.

[0073] The configuration of the third semiconductor layer 104, such as its thickness, length, width, and the amount of P-type doping concentration, can be set by device parameters to satisfy the depletion of 95%-100% of the 2DEG above it. Correspondingly, the threshold voltage of the device is above 0 volts. Exemplarily, the doping concentration of P-type impurities can be 1E+17 / cm3-5E+19 / cm3, and typically, the doping concentration of P-type impurities can be 1E+18 / cm3-5E+19 / cm3. The doping of P-type impurities can be determined according to the concentration of the two-dimensional charge carrier gas. The higher the concentration of the two-dimensional charge carrier gas, the higher the doping concentration of the P-type impurities can be.

[0074] Furthermore, the length range of the positive projection of the third semiconductor layer 104 along the two-dimensional charge carrier gas flow direction is within the length range of the positive projection of the second electrode 108 along the direction (i.e., the gate length range), and the length range of the third semiconductor layer 104 can be set to be greater than 0 and less than the gate length. In other words, the length range of the third semiconductor layer 104 projected onto the substrate is within the length range of the second electrode 108 projected onto the substrate. Figure 1 As shown, the third semiconductor layer 104 disposed within the gate length range can avoid depletion of the two-dimensional electron gas in the non-gate stack region, thereby causing the device to have lower on-resistance and good switching characteristics.

[0075] Further, the third semiconductor layer 104 has a second surface opposite to the first surface of the first semiconductor layer 102, and has a first surface away from the first surface of the first semiconductor layer. The third semiconductor layer 104 also has a third surface (such as a side plane) connecting the first and second surfaces of the third semiconductor layer 104. The third surface of the third semiconductor layer 104 forms an angle C with the first surface of the third semiconductor layer 104. The angle C can be 30-90 degrees.

[0076] Optionally, the growth surface of the third semiconductor layer 104 is noodle.

[0077] Furthermore, the third semiconductor layer 104 may be a single-layer structure, or may be composed of more than 2 separate layers. Figure 2 The third semiconductor layer 104 may be a layer separated along a direction parallel to the substrate 100. The layers separated along a direction parallel to the substrate 100 may overlap or may not overlap in the orthographic projection. Figure 3 As shown, the device is composed of discrete layers in a direction perpendicular to the substrate 100. The discrete layers may be in close contact with each other, or there may be a certain distance between the discrete layers, so that the performance of the device can be improved and the electric field in the device can be reduced.

[0078] Furthermore, the third semiconductor layer 104 may have a structure with a gradual doping concentration. The doping concentration may gradually change from the center of the third semiconductor layer 104 to both sides parallel to the substrate 100 or the third semiconductor layer 104 may be a unilateral gradual change parallel to the substrate 100, or may gradually change from the center of the third semiconductor layer 104 to both sides perpendicular to the substrate 100 or the third semiconductor layer 104 may be a unilateral gradual change perpendicular to the substrate 100.

[0079] Furthermore, the threshold voltage of the device can be controlled by the doping elements, doping concentration, the distance between the third semiconductor layer 104 and the barrier layer, the width of the third semiconductor layer 104, the gate electrode material, and the composition and thickness of the second semiconductor layer. Preferably, the doping concentration of the third semiconductor layer 104 is about 1E+19cm3, the gate electrode material can be Au, the length of the third semiconductor layer 104 is 0.01-10 microns, and the thickness is 0.01-10 microns. The length of the third semiconductor layer along the two-dimensional charge carrier gas flow direction (corresponding to the gate length in the device) can be precisely controlled by the process parameters such as the epitaxial time during the lateral epitaxy, thereby achieving a very thin length dimension. Since the resistance of the depletion region is usually relatively high, reducing the length of this part can effectively reduce the on-state resistance of the device, and is also conducive to reducing the size of the device and improving the area utilization of the wafer.

[0080] Figure 4 is the energy band diagram of the semiconductor device, from Figure 4 It can be seen that in the present disclosure, when the third semiconductor layer is arranged below the second electrode, the depletion layer of the semiconductor device is narrower, the depletion of the two-dimensional carrier charge is fast, and the controllability of the depletion of the two-dimensional electron gas at the location corresponding to the second electrode (gate stack) in the semiconductor device can be effectively achieved; and when the third semiconductor layer is arranged away from the second electrode, the two-dimensional electron gas outside the location corresponding to the second electrode (gate stack) will be depleted and cannot be controlled by the second electrode, thereby causing the on-state resistance of the semiconductor device to increase significantly or even fail to turn on.

[0081] Further, such as Figure 5 As shown, a fourth semiconductor layer 120 may be provided between the first semiconductor layer 102 and the second semiconductor layer. Exemplarily, the fourth semiconductor layer 120 may be an AlN layer, which may reduce effects such as impurity scattering and improve the mobility of electrons in the channel.

[0082] Furthermore, a fifth and / or sixth semiconductor layer may be provided between the second semiconductor layer and the substrate 100. Exemplarily, the fifth semiconductor layer 112 may be a group III nitride buffer layer, and the sixth semiconductor layer may be a nitride semiconductor layer, such as an AlN layer. The fifth semiconductor layer may be above the sixth semiconductor layer.

[0083] Further, the third semiconductor layer may be formed in the fifth and / or sixth semiconductor layer, and the third semiconductor layer formed in the fifth and / or sixth semiconductor layer is denoted by 104 ′.

[0084] The semiconductor device structure, especially the structural design of the third semiconductor layer 104, 104', avoids the situation that after the first insulating layer 105 is formed on the first surface of the second semiconductor layer, when a semiconductor layer such as P-GaN is grown, the crystal quality and electrical performance of the P-GaN semiconductor layer are poor. The semiconductor device structure can obtain a high-quality P-GaN semiconductor layer during or before the channel is made, and thus can obtain a reliable normally-off device with a high threshold voltage and low gate leakage.

[0085] Second embodiment

[0086] Reference Figure 6 A semiconductor device according to a second embodiment will be described.

[0087] On the basis of the first embodiment, a second insulating layer 101 may be formed between the substrate 100 and the first semiconductor layer 102, a groove may be formed in the insulating layer below the first electrode 106, and a seed layer 111 may be formed in the groove. The seed layer 111 is helpful to form a nitride semiconductor layer with low roughness and low dislocation density, such as the first semiconductor layer 102 or the fifth semiconductor layer 112, and can be symmetrically epitaxial during lateral epitaxy, thereby improving the growth quality of the semiconductor layer and effectively utilizing the wafer area.

[0088] Third embodiment

[0089] Reference Figure 7 A semiconductor device according to a third embodiment will be described.

[0090] On the basis of the first embodiment, a third insulating layer 109 may be provided between the second semiconductor layer and the second electrode 108, and the third insulating layer 109 may be silicon dioxide, silicon nitride, Al2O3, etc. The provision of the third insulating layer 109 may further reduce the gate leakage current of the second electrode 108 (gate), and at the same time, the presence of the third insulating layer 109 may expand the voltage range of the gate and enhance the reliability of the device.

[0091] Fourth Implementation Method

[0092] Reference Figure 8 A semiconductor device according to a fourth embodiment will be described.

[0093] On the basis of the first embodiment, an opening 10 is formed at the second surface of the substrate 100, and a fourth electrode 110 connected to the third semiconductor layer 104 (e.g., P-GaN) is formed therein. Since the third semiconductor layer 104 is not connected to any electrode or potential, its potential is floating, which will cause the threshold voltage of the device to be unstable. When the third semiconductor layer 104 is connected to the fourth electrode 110, the potential of the third semiconductor layer 104 can be controlled by the fourth electrode 110, so that the device can provide a stable threshold voltage.

[0094] It is clear that the fourth embodiment can be combined with the second or third embodiment to obtain the aforementioned beneficial effects.

[0095] Fifth Implementation Method

[0096] Reference Figure 9-10 A semiconductor device according to a fifth embodiment will be described.

[0097] In the fifth embodiment, on the basis of the first embodiment, the third semiconductor layer 104 (e.g., P-GaN) can be extended along the direction perpendicular to the two-dimensional charge carrier gas flow, and a fourth electrode 110 connected to the third semiconductor layer 104 can be formed at a position not covered by the positive projection of the second electrode 108. Since when the third semiconductor layer 104 is not connected to any electrode or potential, its potential is floating, which will cause the threshold voltage of the device to be unstable. When the third semiconductor layer 104 is connected to the fourth electrode 110, the potential of the third semiconductor layer 104 can be controlled by the fourth electrode 110, so that the device can provide a stable threshold voltage.

[0098] It is clear that the fifth embodiment can be combined with the second or third embodiment to obtain the aforementioned beneficial effects.

[0099] Sixth Implementation Method

[0100] Reference Fig.11 A semiconductor device according to a sixth embodiment will be described.

[0101] In the sixth embodiment, on the basis of the first embodiment, a fourth electrode 110 connected to the third semiconductor layer 104 (e.g., P-GaN) can be formed at the first electrode 106 of the device. Exemplarily, the surface of the first electrode 106 in contact with the second semiconductor layer can extend downward to form an L-type ohmic contact, connected to the third semiconductor layer 104. Since the third semiconductor layer 104 is not connected to any electrode or potential, its potential is floating, which will cause the threshold voltage of the device to be unstable. When the third semiconductor layer 104 is connected to the fourth electrode 110, the potential of the third semiconductor layer 104 can be controlled by the fourth electrode 110, so that the semiconductor device can provide a stable threshold voltage.

[0102] It is clear that the sixth embodiment can be combined with the second or third embodiment to obtain the aforementioned beneficial effects.

[0103] Seventh Implementation Plan

[0104] Now refer to Figure 12-22 A manufacturing method for manufacturing the semiconductor device of the first and second embodiments will be exemplarily described.

[0105] Step 100 , providing a substrate 100 . The selection of the material of the substrate 100 refers to the description in the first embodiment and will not be repeated here.

[0106] Step 110, depositing and forming the second insulating layer 101 on the first surface of the substrate 100, wherein the second insulating layer 101 covers the entire surface of the substrate 100. At least a portion of the second insulating layer 101 is removed, preferably at least a portion of the second insulating layer 101 corresponding to the region where the first electrode (source) is subsequently formed is removed, an opening is formed to expose a portion of the substrate 100, and then a seed layer is coplanarly deposited on the second insulating layer through a deposition process. The seed layer 111 and the second insulating layer each have a second surface opposite to the first surface of the substrate 100, and a first surface opposite to the first surface of the substrate 100. There is no restriction on the material of the second insulating layer 101. The material of the seed layer can be selected as a material that can serve as the growth core of the first semiconductor layer 102.

[0107] Alternatively, in step 110', a seed crystal material is deposited on the first surface of the substrate 100, and a portion of the seed crystal material is removed by photolithography, so that the remaining seed crystal layer serves as the growth core of the first semiconductor layer 102. Preferably, the region of the remaining seed crystal layer corresponds to the region where the first electrode (source) region is subsequently formed. Then, an insulating material is deposited on the first surface of the substrate 100 to fully cover the substrate 100 and the seed crystal layer, and a portion of the insulating material is removed to form a second insulating layer until the seed crystal layer is exposed. The seed crystal layer and the second insulating layer each have a second surface opposite to the first surface of the substrate 100, and a first surface opposite to the first surface of the substrate 100.

[0108] Step 120 , forming the first semiconductor layer 102 by selectively growing / laterally epitaxially with the seed layer as the center on the second insulating layer and the first surface of the seed layer.

[0109] It is understood that in the first embodiment, the above steps 110, 111 and step 120 are not necessary. The first semiconductor layer 102 (e.g., GaN) can be formed directly after step 100. There is no particular limitation on the growth method of the first semiconductor layer 102, and metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE) or other techniques can be used.

[0110] The method for forming the first semiconductor layer 100 by epitaxially laterally with the seed layer as the center is referred to as Figure 14-19 The specific instructions are as follows:

[0111] Step 121, selecting / laterally epitaxially growing a first region of the first semiconductor layer 102 comprising a low-doped or unintentionally doped nitride semiconductor with the seed crystal layer as the center, wherein the first region of the first semiconductor layer 102 starts to grow from the location of the seed crystal layer, and stops growing the first region when the first semiconductor layer 102 does not completely cover the second insulating layer 101 by controlling its growth rate.

[0112] Step 122, taking the first region of the grown first semiconductor layer 102 as the core, continue to grow a P-type doped nitride layer on the surface and side of the first region of the first semiconductor layer 102. After growing a certain thickness of the P-type doped nitride layer, part of the upper surface of the P-type nitride semiconductor layer 104 can be removed, or part of the upper surface of the P-type nitride semiconductor layer 104 and part of the first region of the first semiconductor layer 102 can be removed to expose the P-type nitride semiconductor layer 104 and the first region of the first semiconductor layer 102. Preferably, the length range of the projection of the P-type nitride semiconductor layer is within the length of the projection area of ​​the second electrode 108 to be formed subsequently, and the width of the P-type nitride semiconductor layer can exceed the width of the second electrode. Thereby completing the manufacture of the third semiconductor layer 104. More specifically, the lateral growth direction of the P-type doped nitride layer, such as P-GaN, is Crystal orientation, the growth plane can be vertical For example, its specific dimensions may be about 0.01-10 microns in length and about 0.01-10 microns in height. Crystal orientation, whose stable growth surface is inclined In the case of the surface, when the lateral growth direction is When the crystal direction is right, its lateral growth rate is faster and the performance of the device is better.

[0113] Step 123, taking the third semiconductor layer 104 and the first region of the first semiconductor layer 102 as nucleation centers, continue to grow the second region of the first semiconductor layer 102 including a low-doped or unintentionally doped nitride semiconductor until the second region of the first semiconductor 102 completely covers the substrate 100 / the first insulating layer 105. The P-type nitride semiconductor layer and the first region of the first semiconductor layer may be exposed and the surfaces of the two may be flush by removing a portion of the low-doped or unintentionally doped nitride semiconductor layer and the P-type nitride semiconductor layer, as shown in FIG. Fig.16 Or the first surface of the first semiconductor layer 102 away from the substrate 100 is higher than the first surface of the third semiconductor layer 104 away from the substrate 100 .

[0114] It is understandable that the steps 121 to 123 may be repeated several times to prepare Fig.19 The discrete third semiconductor layer 104 described in .

[0115] It is clear that in the process of growing the P-type doped nitride layer in step 122, the P-type doping concentration can be controlled during the process to achieve the third semiconductor layer 104 with single-sided or double-sided gradient doping as described in Embodiment 1. The specific form of P-type doping is not specifically limited here.

[0116] Alternatively, the third semiconductor layer 104 may be formed by performing ion implantation in the first semiconductor layer 102 to form the discrete or gradient third semiconductor layer 104 as described in the first or second embodiment.

[0117] Step 130, depositing a second semiconductor layer 103 on the first semiconductor layer 102. It is clear that before forming the second semiconductor layer 103, a fourth semiconductor layer 120 may be deposited on the first semiconductor layer 102. Thus, a two-dimensional charge carrier gas is formed at the interface between the second semiconductor layer 103 and the fourth semiconductor layer 120, or the first semiconductor layer 102 and the second semiconductor layer 103. The second semiconductor layer 103 may be in direct contact with the fourth semiconductor layer 120, or the second semiconductor layer 103 may be in direct contact with the first semiconductor layer 102.

[0118] It can be clearly stated that the fourth semiconductor layer 120 may be a nitride channel layer, and the second semiconductor layer 103 may be a nitride barrier layer; or the second semiconductor layer 103 may be a nitride barrier layer, and the first semiconductor layer 102 may be a nitride channel layer.

[0119] Step 140, forming a first electrode 106 (source electrode) and a third electrode 107 (drain electrode) having ohmic contact with the two-dimensional charge carrier gas, and a second electrode 108 (gate electrode) located above the first surface of the third semiconductor layer 104. The positions of the first electrode 106 and the third electrode 107 are not limited, and can be directly formed on the second semiconductor layer or directly deep into the channel layer. Exemplary structures are as follows: Fig.21 shown.

[0120] It is understandable that, in step 120, on the first surface of the second insulating layer and the seed layer, Fig. 22 The fifth semiconductor layer 112 is formed by epitaxy with the seed layer as the center. The method of forming the fifth semiconductor layer 112 and the third semiconductor layer 104' by selectively selecting / epitaxy with the seed layer as the center is the same as the method of forming the first semiconductor layer 102 and the third semiconductor layer 104, which will not be described here. Then, the first semiconductor layer 102, the second semiconductor layer 103 and other structures can be formed in sequence by well-known methods. The exemplary structure of protecting the fifth semiconductor layer is as follows: Fig. 22 shown.

[0121] Eighth Implementation Method

[0122] Now refer to Fig.23 A method for manufacturing the semiconductor device of the third embodiment will be exemplarily described.

[0123] In the seventh embodiment, between step 130 and step 140, an insulating material may be deposited on the first surface of the second semiconductor layer to form a first insulating layer 105, or a third insulating layer 109 may be formed at a position corresponding to the second electrode 108 by a related process, for example, an etching process, and the insulating material may be silicon dioxide, silicon nitride, Al2O3, etc. The second semiconductor layer may have the first and third insulating layers simultaneously or selectively.

[0124] Ninth Implementation Plan

[0125] Now refer to Fig.24 A method for manufacturing the semiconductor device of the fourth embodiment will be exemplarily described.

[0126] The seventh embodiment may further include step 150. In step 150, an etching process is performed at the second surface of the substrate 100 at a position corresponding to the formation of the third semiconductor layer 104 to form a through hole 10. The through hole directly reaches the third semiconductor layer 104. Then, a fourth electrode 110 is formed on the third semiconductor layer 104 by a process such as deposition, so that the potential of the third semiconductor layer 104 can be controlled to stabilize the threshold voltage of the device.

[0127] Tenth Implementation Plan

[0128] Now refer to Fig.25 A method for manufacturing the semiconductor device of the fifth embodiment will be exemplarily described.

[0129] The seventh embodiment may further include step 150. In step 150, the third semiconductor layer 104 is extended and grown in a direction perpendicular to the two-dimensional carrier charge flow direction, a through hole is formed by etching at a position of the first or second surface of the third semiconductor layer 104 not covered by the orthographic projection of the second electrode 108, and a fourth electrode 110 connected to the third semiconductor layer 104 is formed in the hole by a process such as sputtering, so that the potential can be controlled to stabilize the threshold voltage of the device.

[0130] Eleventh Embodiment

[0131] A power supply device includes any one of the semiconductor devices in the above embodiments. The power supply device includes a primary circuit, a secondary circuit, and a transformer, wherein both the primary circuit and the secondary circuit include a switching element, wherein the switching element adopts any one of the semiconductor devices in the above embodiments.

[0132] Twelfth Implementation Method

[0133] A mobile phone includes any one of the semiconductor devices in the above embodiments. The mobile phone includes a display screen, a charger, etc., wherein the charger includes any one of the semiconductor devices in the above embodiments.

[0134] Thirteenth Implementation Plan

[0135] An amplifier can be used as a power amplifier in the field of mobile phone base stations, etc. The power amplifier can include any one of the semiconductor devices in the above embodiments.

[0136] The present disclosure is described above in conjunction with specific implementation schemes, but it should be clear to those skilled in the art that these descriptions are exemplary and are not intended to limit the scope of protection of the present disclosure. Those skilled in the art can make various modifications and variations to the present disclosure based on the spirit and principles of the present disclosure, and these modifications and variations are also within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: substrate; a first semiconductor layer formed on the first surface of the substrate; a second semiconductor layer formed on a first surface of the first semiconductor layer; The first semiconductor layer has a smaller bandgap than the second semiconductor layer; A first electrode and a third electrode formed on the first or second semiconductor layer, and a second electrode formed on the second semiconductor layer; The length range of the third semiconductor layer projected onto the substrate is within the length range of the second electrode projected onto the substrate, and the third semiconductor layer is a P-type semiconductor layer; the third semiconductor layer is formed in the first semiconductor layer; The third semiconductor layer is a structure of a plurality of discrete layers greater than or equal to 2.

2. The semiconductor device according to claim 1, wherein the substrate is sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3 or single crystal silicon.

3. A semiconductor device as described in claim 1 or 2, wherein the first semiconductor layer is an intrinsic nitride semiconductor layer or an unintentionally doped nitride semiconductor layer, and the epitaxial direction of the intrinsic nitride semiconductor layer or the unintentionally doped nitride semiconductor layer parallel to the substrate is a [0001] direction.

4. The semiconductor device as claimed in claim 1, wherein a two-dimensional charge carrier gas is formed between the first semiconductor layer and the second semiconductor layer, and the third semiconductor layer depletes 95%-100% of the two-dimensional charge carrier gas in at least a partial area below the second electrode region, while substantially not depleting the two-dimensional charge carrier gas in other areas except the partial area. 5 . The semiconductor device according to claim 4 , wherein the third semiconductor layer has a length of 0.01-10 microns and a thickness of 0.01-10 microns.

6. The semiconductor device according to claim 1, wherein a two-dimensional charge carrier gas is formed between the first semiconductor layer and the second semiconductor layer, and when the bias voltage of the second electrode is 0, the two-dimensional charge carrier gas corresponding to at least a portion of the second electrode is less than 5E+11 / cm 2 . 7 . The semiconductor device according to claim 6 , wherein the third semiconductor layer has a length of 0.01-10 microns and a thickness of 0.01-10 microns.

8. The semiconductor device according to claim 1 or 4, wherein the epitaxial direction of the third semiconductor layer parallel to the substrate is the [0001] direction, and the lateral epitaxial direction is .

9. The semiconductor device as claimed in claim 8, wherein the first semiconductor layer has a second surface opposite to the first surface of the substrate and a first surface facing away from the first surface of the substrate, the third semiconductor layer has a second surface opposite to the first surface of the first semiconductor layer and a first surface facing away from the first surface of the second semiconductor layer, the third semiconductor layer also has a third surface connected to the first surface and the second surface of the third semiconductor layer, and the third surface of the third semiconductor layer forms an angle greater than 30 degrees and less than or equal to 90 degrees with the second surface of the third semiconductor layer. 10 . The semiconductor device according to claim 1 , wherein the plurality of discrete layer structures are discrete layer structures perpendicular to the substrate direction or discrete layer structures parallel to the substrate direction. 11 . The semiconductor device according to claim 1 , wherein the separate layer structures are in close contact with each other, or there is a certain interval between the separate layer structures. 12 . The semiconductor device according to claim 4 , wherein the third semiconductor layer is a layer structure with a gradient doping concentration.

13. The semiconductor device as described in claim 12, wherein the doping concentration of the third semiconductor layer gradually changes from the center of the third semiconductor layer to both sides parallel to the substrate, or the doping concentration of the third semiconductor layer gradually changes from the center of the third semiconductor layer to both sides perpendicular to the substrate, or the doping concentration of the third semiconductor layer is unilaterally gradual.

14. The semiconductor device according to claim 4 or 6, wherein the doping concentration of the third semiconductor layer is in the range of 1E+17 / cm 3 -5E+19 / cm 3 . 15 . The semiconductor device according to claim 4 , wherein the third semiconductor layer directly contacts the second semiconductor layer or is spaced apart from the second semiconductor layer by a certain thickness. 16 . The semiconductor device according to claim 1 , further comprising a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer. 17 . The semiconductor device according to claim 1 , further comprising a fifth semiconductor layer and / or a sixth semiconductor layer between the first semiconductor layer and the substrate. 18 . The semiconductor device according to claim 1 , further comprising a second insulating layer having an opening formed between the first semiconductor layer and the substrate, and a seed layer formed in the opening, the seed layer being located below the first electrode. 19 . The semiconductor device according to claim 1 , further comprising a first insulating layer and / or a third insulating layer between the second semiconductor layer and the second electrode. 20 . The semiconductor device according to claim 19 , wherein the first insulating layer and the third insulating layer are silicon dioxide, silicon nitride and / or Al 2 O 3 .

21. The semiconductor device according to claim 1, wherein the third semiconductor layer is connected to a fourth electrode. 22 . The semiconductor device according to claim 21 , wherein the fourth electrode is an independent electrode, or the fourth electrode is a non-independent electrode. 23 . The semiconductor device according to claim 22 , wherein the substrate has a second surface opposite to the first surface, and the fourth electrode connected to the third semiconductor layer is formed at the second surface of the substrate.

24. The semiconductor device according to claim 22, wherein the third semiconductor layer extends along a direction perpendicular to the two-dimensional charge carrier gas flow, and a fourth electrode connected to the third semiconductor layer is formed at a position not covered by a projection of the second electrode. 25 . The semiconductor device according to claim 22 , wherein a fourth electrode connected to the third semiconductor layer is formed at the first electrode of the semiconductor device.

26. A method for manufacturing a semiconductor device, comprising: Step S100: providing a substrate; Step S200: forming a first semiconductor layer on the first surface of the substrate; Step S300: forming a third semiconductor layer in the first semiconductor layer; Step S400: forming a second semiconductor layer on the first surface of the first semiconductor layer; The first semiconductor layer has a smaller bandgap than the second semiconductor layer, so that a two-dimensional charge carrier gas is formed at an interface between the first semiconductor layer and the second semiconductor layer; Step S500: forming a first electrode and a third electrode having ohmic contact with the two-dimensional charge carrier gas, and forming a second electrode located on the first surface side of the third semiconductor layer, Wherein, the length range of the third semiconductor layer projected onto the substrate is within the length range of the second electrode projected onto the substrate; The third semiconductor layer is formed by lateral epitaxy or ion implantation, and the third semiconductor layer is prepared as a discrete or doping concentration gradient structure.

27. The method as claimed in claim 26, before step S200, is to deposit a second insulating layer on the first surface of the substrate, wherein the second insulating layer covers the entire surface of the substrate, remove at least a portion of the second insulating layer to form an opening, and coplanarly deposit a seed material to form a seed layer, wherein the seed layer serves as a growth core for the first semiconductor layer.

28. The method as claimed in claim 26, before step S200, is to deposit a seed crystal material all over the first surface of the substrate, remove a portion of the seed crystal material, and then coplanarly deposit a second insulating layer, remove at least a portion of the second insulating layer until a portion of the seed crystal material is exposed, the exposed portion of the seed crystal material is a seed crystal layer, and the seed crystal layer serves as a growth core of the first semiconductor layer.

29. The method of claim 27 or 28, wherein removing at least a portion of the second insulating layer is removing at least a portion of the second insulating layer corresponding to a subsequent first electrode region; or the location of the exposed portion of the seed layer corresponds to the first electrode region. 30 . The method of claim 29 , wherein the first semiconductor layer and the third semiconductor layer are formed by core selection / lateral epitaxial growth process using a seed layer.

31. The method according to claim 29, wherein the third semiconductor layer is a P-type doped nitride layer, and its lateral growth direction is Crystal direction.

32. The method as claimed in claim 31, wherein a first region of the first semiconductor layer comprising a low-doped or unintentionally doped nitride semiconductor is laterally epitaxially grown with the seed crystal layer as the core, and the first region of the first semiconductor layer starts to grow from the position where the seed crystal layer is located, and by controlling its growth rate, the growth of the first region is stopped when the first semiconductor layer does not completely cover the second insulating layer.

33. A method as claimed in claim 32, wherein the P-type doped nitride layer is grown on the surface and side of the first region of the first semiconductor layer with the first region of the first semiconductor layer being grown as the core, and after growing the P-type doped nitride layer of a certain thickness, continuing to grow a low-doped or unintentionally doped nitride semiconductor layer, and then removing part of the low-doped or unintentionally doped nitride semiconductor layer and the P-type doped nitride layer to expose the P-type doped nitride layer and the first region of the first semiconductor layer, and the steps of growing the P-type doped nitride layer and continuing to grow the low-doped or unintentionally doped nitride semiconductor layer can be repeated multiple times.

34. The method of claim 26, wherein there is further provided a step 410 between step 400 and step 500; in step 410, an insulating material is deposited all over the first surface of the second semiconductor layer to form a first insulating layer, and / or a third insulating layer is formed by etching the insulating material at a position corresponding to the second electrode.

35. The method as claimed in claim 26 further comprises step 600: in step 600, a through hole is formed by etching at a position corresponding to the third semiconductor layer on the second surface of the substrate, the through hole directly reaches the third semiconductor layer, and a fourth electrode is formed in the through hole, thereby controlling the electric potential of the third semiconductor layer.

36. The method as claimed in claim 26, further comprising step 600: forming a through hole by etching on one side of the width of the third semiconductor layer not covered by the orthographic projection of the second electrode, and forming a fourth electrode connected to the third semiconductor layer in the through hole.

37. An electronic device, comprising the semiconductor device according to any one of claims 1 to 25, or comprising a semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 26 to 36.

38. The electronic device as claimed in claim 37 is a power supply device, a server, a charger, a mobile phone or an amplifier.

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