Silicon Carbide Field Effect Transistor

Abstract

The present disclosure relates to silicon carbide field effect transistors. In general, a silicon carbide field effect transistor may include: a substrate of a first conductivity type; a drift region of the first conductivity type disposed on the substrate; a diffusion layer of the first conductivity type disposed in the drift region; a body region of the second conductivity type disposed in the diffusion layer; and a source region of the first conductivity type disposed in the body region. The silicon carbide field effect transistor may also include: a spacer of the first conductivity type disposed on the source region, the body region, and the diffusion layer; and a lateral channel region of the first conductivity type disposed in the spacer. The silicon carbide field effect transistor may also include a gate structure, the gate structure including: an aluminum nitride layer disposed on the lateral channel region; and an aluminum gallium nitride layer of the second conductivity type disposed on the aluminum nitride layer.

Description

Technical Field

[0001] The present specification relates to a silicon carbide (SiC) semiconductor device including a field effect transistor (FET) having a built-in channel. Background Art

[0002] In power field effect transistors (FETs), the use of silicon carbide (SiC) as the semiconductor material can reduce static and dynamic power losses. Such FETs can be used in various power applications such as electric motor drive control, in which it is desired that these FETs are normally off at zero bias (e.g., at the gate or control terminal). In current implementations, metal oxide semiconductor FET (MOSFET) designs are typically used to implement normally off power SiC FETs. However, SiC MOSFETs have reliability issues (e.g., due to overstress of the gate oxide) and problems related to implementation in motor drive control applications (e.g., low short circuit survival time). In addition, the high specific on-resistance (R) due to low inversion layer carrier mobility (e.g., bulk mobility) leads to a high on-resistance. spon ), so current SiC MOSFET implementations can also be expensive. This high R is addressed by increasing the device size (e.g., increasing the channel width) to achieve a lower channel resistance and desired current rating for such SiC MOSFETs. spon SiC junction FETs (JFETs) are less susceptible to the reliability issues of SiC MOSFETs and can have much higher bulk carrier mobility (e.g., lower R spon ). However, the normally-off operation of current SiC JFETs may be problematic. In addition, current SiC JFET implementations may have low threshold voltages and low on-state currents, making them unsuitable for power device applications such as motor drive control. Summary of the invention

[0003] In general, a silicon carbide (SiC) field effect transistor (FET) may include: a substrate of a first conductivity type; a drift region of the first conductivity type disposed on the substrate; a diffusion layer of the first conductivity type disposed in the drift region; a body region of the second conductivity type disposed in the diffusion layer; and a source region of the first conductivity type disposed in the body region. The SiC FET may also include: a spacer of the first conductivity type disposed on the source region, the body region, and the diffusion layer; and a lateral channel region of the first conductivity type disposed in the spacer. The SiC FET may also include a gate structure, the gate structure including: an aluminum nitride (AlN) layer disposed on the lateral channel region; and an aluminum gallium nitride (AlGaN) layer of the second conductivity type disposed on the AlN layer.

[0004] In another general aspect, a silicon carbide (SiC) field effect transistor (FET) may include: an n-type substrate of a first conductivity type; an n-type drift region disposed on the substrate; an n-type diffusion layer disposed in the drift region; a p-type body region disposed in the diffusion layer; and an n-type source region disposed in the body region. The SiC FET may also include: an n-type spacer disposed on the source region, the body region, and the diffusion layer; and an n-type lateral channel region disposed in the spacer. The SiC FET may also include a gate structure, the gate structure including: an aluminum nitride (AlN) layer disposed on the lateral channel region; a p-type aluminum gallium nitride (AlGaN) layer disposed on the AlN layer; a p-type gallium nitride (GaN) layer disposed on the AlGaN layer; and a metal gate electrode disposed on the GaN layer, the metal gate electrode defining an ohmic contact with the GaN layer.

[0005] In another general aspect, a silicon carbide (SiC) field effect transistor (FET) may include: an n-type substrate of a first conductivity type; an n-type drift region disposed on the substrate; an n-type diffusion layer disposed in the drift region; a p-type body region disposed in the diffusion layer; and an n-type source region disposed in the body region. The SiC FET may also include: an n-type spacer disposed on the source region, the body region, and the diffusion layer; and an n-type lateral channel region, the lateral channel region being disposed in the spacer. The SiC FET may also include a gate structure, the gate structure including: an aluminum nitride (AlN) layer disposed on the lateral channel region; a p-type aluminum gallium nitride (AlGaN) layer disposed on the AlN layer; and an n-type gallium nitride (GaN) layer disposed on the AlGaN layer. The GaN layer may define a tunnel contact with the AlGaN layer. The gate structure may also include a metal gate electrode disposed on the GaN layer. The metal gate electrode may define an ohmic contact with the GaN layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram schematically illustrating a side cross-sectional view of a silicon carbide (SiC) field effect transistor (FET) according to an embodiment.

[0007] Figure 2 is a schematic diagram showing electron concentration contours of an on-state SiC FET according to an embodiment.

[0008] Figure 3 is a schematic diagram illustrating an on-state conduction band of a SiC FET according to an embodiment.

[0009] Figure 4A is a diagram showing simulated output on-state characteristics of a SiC FET according to an embodiment.

[0010] Figure 4Bis a schematic diagram showing simulated voltage blocking characteristics of a SiC FET according to an embodiment.

[0011] Figure 5 is a schematic diagram showing simulated gate current characteristics of a SiC FET device according to an embodiment.

[0012] Figure 6 is a schematic diagram showing the dependence of conduction band edges of intrinsic SiC and aluminum gallium nitride (AlGaN) on the fraction of aluminum nitride (AlN) in AlGaN according to an embodiment.

[0013] Figure 7 is a schematic diagram showing a simulated band diagram of a forward biased p-type gallium nitride (GaN) gate, according to an embodiment.

[0014] Figure 8 is a schematic diagram showing a conduction band of an n-type SiC—AlN-p-type GaN heterostructure under a positive gate bias according to an embodiment.

[0015] FIG. 9A to FIG. 9K is a schematic diagram of a side cross-sectional view showing a manufacturing process of a SiC field effect transistor (FET) according to an embodiment.

[0016] Fig.10 The structure of a gate stack with a tunnel GaN diode according to an embodiment is shown.

[0017] Fig.11 The manufacturing stages of a SiC FET according to an embodiment are shown.

[0018] Fig.12 is a diagram schematically showing a plan view of a SiC FET.

[0019] Fig.13 It is a graph showing the interface state density between various materials and SiC.

[0020] Fig.14 is a diagram schematically illustrating a side cross-sectional view of a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment.

[0021] In the drawings that are not necessarily drawn to scale, similar reference symbols may indicate similar and / or similar parts (elements, structures, etc.) in different views. The drawings generally illustrate various embodiments discussed in the present disclosure by way of example and not limitation. Reference symbols shown in one drawing may not be repeated for the same and / or similar elements in the related views. Reference symbols repeated in multiple figures may not be specifically discussed with respect to each of the figures in these figures, but are provided for context between the related views. In addition, not all similar elements in the drawings are specifically referenced with reference symbols when multiple instances of the element are shown. DETAILED DESCRIPTION

[0022] The present disclosure relates to silicon carbide (SiC) field effect transistor FETs (e.g., JFETs, junction gate FETs, gate-controlled JFETs, etc.) that overcome at least some of the disadvantages of the above-described current devices. In some embodiments, the SiC FETs described herein can be used in high power applications, such as applications with a desired blocking voltage of 600 volts (V) or higher (e.g., under reverse bias conditions of the rectifier diode of the FET). Such SiC power FETs can also have a low on-state specific resistance (R spon ) to allow high operating currents of power devices with sufficiently small areas to be cost-effective compared to current devices.

[0023] In some embodiments, the FETs described herein can have electrical performance parameters that are close to theoretical performance, such as with respect to blocking voltage and on-state resistance. For example, the R of a vertical non-injected power device (e.g., such as a SiC FET described herein) can be determined based on the resistance of the drift region of the power device. spon For example, for a non-punch-through power device, R can be given by the following equation 1: spon :

[0024] R spon =4BV 2 / (ε*mu*E c 3 ) – Equation 1,

[0025] where BV is the breakdown voltage, ε is the absolute dielectric constant of the semiconductor material in which the device is formed (e.g., SiC), mu is the bulk carrier mobility (e.g., electrons for an n-type device), and E c is the critical electric field for avalanche breakdown of the semiconductor material. In some embodiments, the high power switch may be defined as having a specific resistance R spon devices (e.g., gate-controlled JFETs) whose specific resistance does not exceed R given by equation 1 above spon For the purpose of this disclosure, R sponIt can be defined as the differential resistance of the on-state FET multiplied by the active area of ​​the FET device (e.g., in square centimeters), where the active area can be determined by multiplying the active area of ​​the unit cell of the FET device by the number of unit cells included in the switching device.

[0026] In some embodiments (such as those described herein), a vertical SiC FET (e.g., a vertical gated JFET) can include an n-type (e.g., top side) source region, an n-type (e.g., back side) drain region, and an n-type vertical drift region. Figure 1 The unit cell shown in FIG. 1 may further include a shielded p-body, an inactive vertical n-type JFET channel (e.g., a diffusion region or diffusion layer), and a gated lateral built-in channel on top of the shielded p-body and the vertical JFET channel. The lateral channel may be configured to provide a gated electrical connection between the (top side) source region and the inactive vertical JFET channel (diffusion layer). In some embodiments, the lateral built-in channel may have a channel depth of nanometer (nm) size, for example, a channel depth of 100 nm or less (e.g., 20 nm or less).

[0027] Such lateral channels can be controlled by a gate structure including a p-type (magnesium-doped) aluminum gallium nitride (AlGaN) alloy layer, wherein the AlGaN layer of the gate structure is separated (isolated) from the built-in channel by a thin aluminum nitride (AlN) buffer layer or interface layer. Under zero bias gate conditions, the lateral channel can be configured so that the built-in potential through the p-type AlGaN gate is pinched off (e.g., non-conductive). When a positive bias is applied to the gate, the lateral channel can be configured to become open (e.g., conductive), thereby providing a continuous electron flow path from the source region to the drain region (e.g., through the lateral channel, diffusion layer, and drift region). In the embodiments described herein, the use of a p-type AlGaN gate can provide a high threshold voltage (e.g., greater than 1V, greater than 2V, etc.), while the AlN buffer layer can provide a low interface trap density at the interface of the AlN layer with the SiC of the lateral channel and at the interface of the AlN layer with the AlGaN gate layer.

[0028] Figure 1 is a schematic diagram schematically showing a side cross-sectional view of a silicon carbide (SiC) FET 100. For example, Figure 1 A cross-sectional view of an exemplary embodiment of a unit cell of a SiC FET is shown. A unit cell of a FET 100 (such as Figure 1 ) can be combined with other examples of unit cells (e.g., Fig.12 ) are combined to form a gate-controlled SiC JFET, which can be used in power applications (such as motor control drives, industrial controls, etc.).

[0029] like Figure 1 As shown, FET 100 includes an n-type (heavily doped) substrate 101 and an n-type epitaxial drift region 102. FET 100 also includes an n-type diffusion layer 103 in an upper portion of the drift region 102. In some embodiments, the diffusion layer 103 may have a doping concentration higher than the doping concentration of the drift region 102. The diffusion layer may be formed using ion implantation and / or ion diffusion.

[0030] Figure 1 The FET 100 further includes a p-body region 120 and a source region 110 disposed in the diffusion layer 130. The portion of the n-type diffusion layer 103 disposed between the two p-body regions 120 may also be referred to as a vertical JFET region (vertical JFET channel, etc.). The p-body region 120 and the source region 110 may be formed by corresponding ion implantation operations.

[0031] like Figure 1 As shown, FET 100 also includes an n-type spacer 104 that can be formed using SiC regrowth. An n-type (heavily doped) lateral (built-in) channel region 105 can be formed in an upper portion of the spacer 104 using ion implantation. In this exemplary embodiment, a composite gate structure is disposed on top of the lateral channel region 105. In some embodiments (such as in FET 100), the composite gate structure can include a thin AlN buffer (interface) layer 131, wherein the thickness of the AlN layer 131 can range from a few monolayers to tens of nanometers (e.g., 1 nm to 30 nm).

[0032] In FET 100, the composite gate structure further includes a p-type (heavily doped) aluminum gallium nitride AlGaN layer 132 disposed on the AlN layer 131, wherein the AlGaN layer 132 defines a heterojunction (PN junction) with the n-type lateral channel region 105. In some embodiments, such as in FET 100, the composite gate structure may further include a p-type (heavily doped) gallium nitride GaN layer 133 disposed on the AlGaN layer 132 and a gate metal layer 135 disposed on the GaN layer 133 and defining an ohmic contact to the GaN layer. Since GaN has a lower bandgap than AlGaN alloys, the use of Figure 1 The illustrated GaN layer 133 can reduce the contact resistance between the gate metal layer 135 and the underlying elements of the composite gate structure (e.g., compared to an ohmic contact formed to the p-type AlGaN layer 132). As discussed further below, the mole fraction X of AlN in the AlGaN layer 132 can be greater than or equal to eighteen percent (e.g., to achieve conduction band alignment for efficient operation of the FET 100).

[0033] like Figure 1As shown, FET 100 further includes an ohmic contact 145 to the drain region of FET 100, wherein substrate 101 serves as the drain region of FET 100. FET 100 further includes an ohmic contact 141 to the source region 110, wherein ohmic contact 141 may also short p-body region 120 to the corresponding source region 110.

[0034] Forming ohmic contact 141 to p-body 120 may include forming p+ sub-contact region 121 , wherein sub-contact region 121 has a p-type doping concentration higher than the p-type doping of p-body 120 in order to reduce contact resistance of ohmic contact 141 .

[0035] FET 100 also includes a source pad metal 148 that can provide electrical connections to p-body 120 (through ohmic contact 141 and sub-contact region 121) and source region 110 for operating FET 100. Pad metal 148 (in conjunction with ohmic contact 141) can be referred to as a source metal structure. Figure 1 As shown, the source pad metal 148 is separated (electrically isolated) from the composite gate structure (e.g., gate stack) by the interlayer dielectric 139. In this embodiment, the backside metal layer 146 is disposed on the ohmic (drain) contact 145. In some embodiments, the backside metal layer 146 can facilitate the installation of the semiconductor die including the FET 100 into a semiconductor device package and / or into a semiconductor power module (e.g., a multi-chip module). In some embodiments, such a power module may include a power subcircuit (e.g., a half-bridge or full-bridge circuit topology) that is populated with a high-power SiC FET (such as those described herein). Of course, such a power module may also have a topology different from a bridge configuration and may also include, for example, a semiconductor-based drive circuit.

[0036] Various details and variations of SiC FETs (such as SiC FET 100) are shown in the accompanying drawings and described below. However, in short, such SiC FETs (refer to FET 100) can be configured so that under zero gate bias conditions (e.g., zero bias applied to the composite gate structure via gate metal layer 135), the lateral channel region 105 can be (completely) depleted (pinched off) by the built-in potential of the heterojunction defined by the p-type AlGaN layer 132 and the n-type lateral channel region 105. Therefore, under such zero bias conditions, for a given embodiment, the FET 100 can remain in the off state (e.g., not conducting from the source region 110 to the drain) until the full blocking voltage rating is reached.

[0037] In addition, when a positive bias (e.g., greater than 1 V) is applied to the gate metal layer 135 (and the p-type GaN layer 133), accumulation of free electrons may occur in the lateral channel region 105, thereby providing a path for electrons to flow from the source region 110 to the drain (e.g., the substrate 101), wherein the path for electron flow passes through the ohmic contact 141, the lateral channel region 105, the vertical channel (diffusion layer) 103, and the drift region 102.

[0038] In an exemplary embodiment of the SiC 100, the drift region 102 may have a Figure 1 The depth of the line T in FIG. 1 is about 9.5 micrometers (μm) (the thickness from the diffusion layer 103 to the substrate 101). The drift region 102 may have a thickness of 1×10 16 cm -3 For example, a 30-KeV arsenic (As) implant may be used to achieve a doping concentration of 6x10 12 cm -2 A lateral channel region 105 is formed at a depth of 18 nm (along line T) with a dose of . Figure 1 , the width of the unit cell of the FET 100 (eg, device pitch) may be 5 μm. In some embodiments of the SiC FET 100, R spon Can be less than or equal to 2 milliohms (mOhm) square centimeters (mOhm·cm 2 ), which is comparable to the R spon About twice as low.

[0039] As described above, the spacer 104 may be a regenerated SiC layer. In some embodiments, the spacer 104 (including the lateral channel region 105) may be formed along Figure 1 The line T in FIG. 1 has a thickness between 60 nm and 300 nm. The preferred thickness of the spacer is between about 100 nm and 200 nm. The AlGaN layer 132 of the composite gate structure may have a thickness greater than or equal to 1×10 18 cm -3 The magnesium doping concentration of the AlGaN layer 132 may be between 15% and 70% by mole fraction X of AlN. AlN , and X AlN The lateral channel region 105 may be a constant value over the thickness of the AlGaN layer 132. In some embodiments, the lateral channel region 105 may be formed along Figure 1 The line T1 in FIG. 1 has a depth less than or equal to 20 nm. The GaN layer 133 may have a depth greater than or equal to 10 19 cm -3 , or in some embodiments, greater than 10 20 cm -3Mg doping concentration.

[0040] Figure 2 2 is a diagram showing electron concentration contours of an on-state SiC FET according to an embodiment. For example, diagram 200 is a grayscale image showing simulated electron concentration in an embodiment of SiC FET 100. Figure 2 The darker shades in the image represent higher electron concentrations, such as Figure 2 As indicated in the included figure legend. Figure 2 The simulation of represents a SiC FET device (eg, a portion of SiC FET 100 ) with a 2.7V gate bias and a 0V drain bias (eg, operating in saturation mode). Figure 2 The 100 series reference numbers in Figure 1 That is, in Figure 2 , the diffusion layer 103, the spacer 104, the lateral channel region 105, the source region 110, the p-body region 120 and the AlGaN layer 132 are specifically pointed out.

[0041] Figure 2 The schematic diagram 200 shown shows the formation of an undepleted lateral channel in the lateral channel region 105 due to the effect of a 2.7V gate bias on the p-type AlGaN layer 132 of the composite gate structure of the FET 100. This is for a 30 percent AlN mole fraction X AlN The present invention is performed in accordance with an embodiment of the SiC FET 100. Figure 2 Line AA in the Figure 3 The locations of the cross sections of the conduction bands are shown in FIG. 1 and discussed below.

[0042] Figure 3 According to the embodiment shown Figure 2 300 is a diagram showing the characteristics of the on-state conduction band of a SiC FET. That is, the diagram 300 shows that for an on (open state, etc.) SiC FET (eg, operating in saturation mode), for Figure 2 The cross section of line AA is shown, the electron potential at the edge of the conduction band and the corresponding Fermi level.

[0043] Figure 3 The belt diagram 300 shown shows the distance along Figure 2 The electronic conduction band E is a function of the distance from the SiC-AlGaN 210 interface (eg, the interface with the AlGaN layer 132 and the lateral channel region 105) of the line AA in FIG. C As described above, in this example, the AlN mole fraction (X) in the AlGaN layer 132 is AlN) is 0.3. As pointed out above, Figure 3 The conduction band diagram 300 shown is for Figure 2 A cross section of a SiC FET (along line AA) is taken at a lateral distance of 100 nm from the right-hand edge of the source region 110 (eg, along line AA). Figure 2 The line D) in the Figure 3 In the schematic diagram 300 of FIG. 1 , the band diagram is drawn such that x=0 (eg, on the x-axis of the schematic diagram 300 ) corresponds to the p-AlGaN to n-type SiC interface 210 . Figure 3 In the p-AlGaN, negative distance numbers correspond to Figure 2 The line AA in FIG. 1 enters the composite gate structure from the interface 210. In addition, Figure 3 The positive distance numbers in correspond to the distances along line AA from the interface 210 into the lateral channel region 105, the spacer 104, and the p-body region 120. That is, further reference is made to Figure 3 , Figure 3 The conduction band profile drawn in corresponds to, for example, Figure 2 A cross section (along line AA) over the p-AlGaN layer 132 , lateral channel region 105 , spacer layer 104 , and p-body 120 of an embodiment of a SiC FET device 100 is shown.

[0044] like Figure 3 As shown, within the channel region 105 (eg, at a distance of about 20 nm from the interface 210), the energy of the conduction band Ec is close to the Fermi level E F , which indicates a high electron concentration in the lateral channel region 105. Figure 3 As shown, a discontinuity ΔEc of the conduction band Ec occurs at the interface 210 of the AlGaN layer 132 and the SiC of the lateral channel region 105. In some embodiments, as discussed further below, the location of this discontinuity ΔEc can play an important role in controlling the leakage current of the composite gate structure of a SiC FET, such as those described herein.

[0045] Figure 4A is a schematic diagram 400 showing simulated output on-state characteristics of a SiC FET according to an embodiment, and Figure 4B is a schematic diagram 450 showing simulated voltage blocking characteristics of a SiC FET, according to an embodiment. Figure 4A and Figure 4B The simulation results shown in the figure are for Figure 1 In an embodiment of the SiC FET 100 , the AlN mole fraction of the p-type AlGaN layer 132 is thirty percent, and the threshold voltage Vt of the SiC FET is greater than 1V.

[0046] Figure 4A Schematic diagram 400 shows the output characteristics of an exemplary SiC FET, where the drain current is plotted as a function of the gate bias (VG) at a constant drain bias (VD) of 1V (dashed line), and the drain current is plotted as a function of VD at a constant VG=2.3V (solid line). Figure 4A As shown in the results, it can be determined that the simulated SiC FET device (e.g., SiC FET 100) has a 1.8 mOhm cm 2 R spon .like Figure 4B As shown, the simulated SiC FET also has a blocking voltage (holding voltage, off-state voltage, etc.) sufficient to achieve the 1200V rating with ample margin, and also exhibits a low (tens of nanoamperes) reverse (leakage) current at a temperature of 175 degrees Celsius.

[0047] Figures 5 to 8 Various simulation results for SiC FET implementations are shown, including the characteristics and comparison of different composite gate structures. As discussed below, Figures 5 to 8 The simulation results of 130 show at least some beneficial effects of using a p-type AlGaN layer (e.g., AlGaN layer) 132 in combination with an AlN interface layer (e.g., AlN layer 131) to form a heterojunction between a composite gate structure and a lateral channel region (e.g., of SiC FET 100). For example, Figure 5 is a schematic diagram 500 showing simulated gate current characteristics of two SiC FET devices, one SiC FET device having a p-type AlGaN gate layer for forming a heterojunction with an n-type lateral channel layer, and the other SiC FET device having a p-type GaN gate layer for forming a heterojunction with an n-type lateral channel layer. Figure 5 A comparison of shows that the gate leakage current of SiC FET devices (such as those described herein) can depend on the exact structure of the composite gate structure (eg, p-type gate stack).

[0048] refer to Figure 5 Since the band gap of AlGaN increases with the percentage of AlN in the AlGaN alloy, the gate leakage current in SiC FETs can be improved by using p-type AlGaN to form a heterojunction compared to using p-type GaN to form a heterojunction. For example, a gate current of a SiC FET with a higher AlN mole fraction (X AlN ) will have a higher contact potential with SiC and therefore have lower leakage than p-type GaN, such as Figure 5 In this example, Figure 5The simulation results of FIG. 1 compare a p-type AlGaN layer 132 having a 30 mol% AlN content with p-GaN replacing the AlGaN layer 132 in the FET 100. Figure 5 As shown, for the gate current to turn on, X AlN =0.3 has a higher gate voltage than the p-GaN layer. In this example, the simulated SiC FET device has a gate voltage of 0.057 cm -2 active area and a unit cell width of 5μm.

[0049] Figure 6 600 is a diagram showing the dependence of the conduction band edges of intrinsic SiC and AlGaN on the mole fraction of AlN in AlGaN according to an embodiment. Figure 6 As shown, the conduction band of AlGaN can be aligned (eg, to SiC) by adjusting the AlN mole fraction in, for example, the AlGaN layer 132 of the FET 100. Specifically, Figure 6 Schematic diagram 600 shows the molar fraction X of AlN as AlN As shown in schematic 600, the conduction band edge of AlGaN remains below the conduction band edge of SiC until X AlN The molar fraction is about 18%. That is, for X AlN <0.18, the heterojunction of p-type AlGaN and SiC has type II properties, for example, the conduction band position decreases with increasing band gap energy. This heterojunction is not as effective an injector as a type I heterojunction, because the increase in the band gap of a type I heterojunction is also accompanied by an increase in E C The increase of Figure 6 As shown, X AlN At mole fractions greater than 18%, such Type I behavior can be achieved.

[0050] and Figure 3 Compared with the conduction band diagram of the p-type AlGaN heterojunction gate structure shown in Figure 7 A band diagram 700 is shown near a simulated forward biased p-type GaN heterojunction gate structure for a gate voltage VG=2.7V. Figure 7 As shown, the potential pit 710 generated by the type II heterojunction between p-type GaN and SiC may cause excessive forward gate current, especially when the interface between SiC (e.g., lateral channel region 105) and the p-type GaN layer has a high interface state density. This undesirable excess current may then flow to the SiC-GaN interface due to electron tunneling, such as Figure 7 As shown in the schematic diagram 700 shown.

[0051] In addition, if Figure 7 (and Figure 8 ) It can be seen that the type II heterojunction between p-type GaN and SiC (e.g., lateral channel region 105) has a conduction band discontinuity that is opposite in sign to the bandgap discontinuity at the interface of GaN and SiC. This conduction band discontinuity is undesirable in SiC FETs, where low forward current is expected in forward bias. As described herein, p-type AlGaN can be used to overcome this disadvantage.

[0052] In addition, the defect density (D it ) may also contribute to the gate leakage current of SiC FET implementations. Even for AlN mole fractions in AlGaN greater than 0.18, the discontinuity of the AlGaN conduction band (e.g. Figure 6 ) becomes positive, but it is advantageous to have at least a few pure AlN monolayers at the interface with SiC (e.g., the interface between the AlGaN layer 132 and the lateral channel region 105) due to a better interface match of AlN to SiC, resulting in a lower interface state density.

[0053] For example, see again Figure 1 Compared with directly placing the AlGaN layer 132 on SiC, placing the AlN layer 131 between the SiC (lateral channel region 105) and the AlGaN layer 132 (or GaN layer) can reduce D it For example, several monolayers of 30 nm AlN (such as those above relative to Figure 1 discussed) can achieve less than 1x10 11 cm -2 eV -1 D it Although a few monolayers of AlN layer 131 may not block the gate current, its presence at the interface between AlGaN layer 132 and lateral channel region 105 (e.g., in the embodiment of FET 100) will reduce the interface state density D at the heterojunction between the n-type SiC of lateral channel region 105 and the AlGaN layer 132 of the composite gate structure. it , and thus reduce gate leakage current.

[0054] Figure 8 800 is a schematic diagram showing the conduction band of a SiC JFET having an n-type SiC-AlN-p-type GaN heterostructure at a positive gate bias of 2.7 V according to an embodiment. Figure 7Compared to the schematic diagram 700 in FIG. 8 , the schematic diagram 800 is shown for a heterojunction formed using p-type GaN, but shows the beneficial effect of the AlN layer as an interface layer between SiC and the composite gate structure (for example, for a heterojunction formed using GaN or AlGaN). That is, Figure 8 The conduction band diagram 800 shows the simulation results of a forward biased p-type GaN layer with n-type SiC (eg, lateral channel region 104) and an AlN interfacial layer with a thickness of 2 nm. Figure 8 Schematic diagram 800 and Figure 7 As shown in the comparison of schematic diagram 700 (e.g., corresponding to a p-type GaN-n-type SiC heterojunction with no AlN interface layer), it can be seen that the 2nm AlN layer significantly suppresses both interface traps and tunneling. Similar beneficial effects are achieved for AlN interface layers between AlGaN and SiC, such as in the FETs described herein.

[0055] Although the interface state density at the interface of AlN and GaN or AlGaN can be low as discussed above, when a thin (eg, 1 nm to 30 nm) AlN layer is used to implement the interface layer 131, such as Figure 1 As shown, an excessively thick AlN layer for the interface layer 131 may result in the formation of a dense dislocation network and, therefore, a corresponding increase in the density of interface traps (eg, D it Depending on the particular implementation (eg, semiconductor process), the thickness of the AlN interface layer 131 may vary between approximately 10 nm and 40 nm. In other implementations, the AlN interface layer may have a thickness less than 10 nm, or a thickness greater than 40 nm.

[0056] FIG. 9A to FIG. 9K is a schematic diagram showing a side cross-sectional view of a semiconductor device manufacturing process for producing a SiC FET according to an embodiment. In some embodiments, a FIG. 9A to FIG. 9K The SiC FETs described herein may be produced by the process shown in or a similar process, such as for example Figure 1 FET 100 and / or Fig.14 MOSFET 1400. In other embodiments, other process flows may be used to produce the FETs described herein.

[0057] FIG. 9A to FIG. 9K The process ("process") such as Fig.9AThe process shown includes depositing an epitaxial layer (e.g., an epitaxial layer of a low-doped n-type SiC carbide material) to form a drift region layer 902 on a substrate 901. In some embodiments, the substrate 901 can be a heavily doped hexagonal n-type SiC, such as 4H polytype modified SiC. For example, the doping concentration and thickness of the drift region layer 902 can be selected based on the desired operating voltage (e.g., blocking voltage, rated voltage, etc.) of the corresponding FET produced by the process. For example, in some embodiments, for a FET with an operating (blocking) voltage of 1200V, the doping (donor doping) concentration of the drift region layer can be about 8x10 15 cm -3 Up to 1.3x10 16 cm -3 range, and the thickness may be in the range of approximately 8 microns to 12 microns.

[0058] Also like Fig.9A As shown, the upper portion of the epitaxial layer including the drift region layer 902 may have a higher donor (doping) concentration in order to form (define, etc.) an n-type diffusion layer 903 (e.g., a vertical JFET channel region). The doping of the diffusion layer 903 may be in the range of approximately 1.5 times to 5 times the doping concentration of the drift region layer 902, wherein the selected doping concentration of the diffusion layer 903 may depend on the desired width of the vertical JFET channel. In some embodiments, the additional (increased) n-type doping in the diffusion region 903 (compared to the drift region layer 902) may be achieved by increasing the flow rate of the n-type dopant during the corresponding epitaxial deposition process. In some embodiments, the additional (increased) n-type doping in the diffusion region 903 (compared to the drift region layer 902) may be achieved by blanket implanting donor atoms such as nitrogen, phosphorus, arsenic, or antimony into the upper portion of the epitaxial layer including the drift region layer 902.

[0059] Note that the exemplary numbers given above for the thickness and doping concentration of the drift region layer 902 are exemplary values ​​for a FET device (e.g., FET 100) having a blocking voltage of 1200 V. In some embodiments, if a FET device with a lower or higher blocking voltage is to be produced, the values ​​of the drift region doping concentration and thickness may be adjusted to support (block) the associated peak electric field in the off state of the FET device (e.g., within the limits of the electric strength of 4H silicon carbide).

[0060] like Fig. 9B As shown, the process may include forming an implant mask 920m and patterning it. Fig. 9CAs shown, implant mask 920m may be used as an implant blocking mask for forming (defining, etc.) p-type body region 920. In some embodiments, implant mask 920m may be formed of silicon dioxide, and acceptor ions may be implanted to form p-type body region 920 after implant mask 920m is formed.

[0061] See also Fig.9D After forming the p-type body region 920, the mask 920m may be removed. Then, a new implantation mask (not shown) may be formed and used to define the n-type source region 910. That is, Fig.9D As shown, donor ions may be implanted to form source regions 910, wherein an implantation mask may be used to define the locations where source regions 910 are formed (e.g., by blocking donor implantation where source regions 910 are not needed). In some embodiments, the acceptor doping concentration in the p-type body region 920 may be 10 18 cm -3 or higher, and the donor doping concentration in the source region 910 may be 5×10 18 cm -3 When forming (defining, implanting, etc.) source region 910 and body region 920, hot ion implantation at a substrate temperature between 200C and 600C may be used, which may help prevent undesired amorphization of SiC crystals.

[0062] See also Fig.9E , the implant mask used to define the source region 910 may be removed, for example, by etching, and epitaxial SiC regrowth may be used to form n-type spacer 904. In some embodiments (such as an exemplary 1200V rated FET), spacer 904 may have a thickness between about 80nm and 300nm. Then, a doping concentration of 2x10 19 cm -3 or higher thermal Al ion implantation to form the sub-contact p-type region 921. Fig.9F As shown, a blanket donor implant may be performed to define a lateral channel region 905 in an upper portion of the spacer 904, such as having the characteristics of the lateral channel region described herein.

[0063] like Figure 9G As shown, the n-type source subcontact region 911 and the p-type body subcontact region 921 may then be implanted (defined, formed, etc.) (eg, using one or more implantation masks). FIG. 9A to FIG. 9K Not shown, but when forming the sub-contact regions 911 and / or 921, the junction termination region around the periphery of the corresponding FET device may also be implanted.

[0064] exist FIG. 9A to FIG. 9KIn the process of forming the sub-contact regions 911 and 921, a post-implantation annealing may be performed at a temperature between about 1500° C. and 1900° C. to activate the implanted dopants (e.g., lateral channels 105, source regions 910, body regions 920, sub-contact regions 911 and 921, and / or termination regions). In some embodiments, such an annealing process may be performed using a carbon coating on the top side of the SiC wafer, which may avoid roughening of the upper surface of the SiC during the annealing.

[0065] After removing the carbon layer associated with the implant activation anneal process, a sacrificial oxidation of the SiC may be performed, which may include forming at least a few nanometers of sacrificial silicon dioxide. The sacrificial silicon dioxide may then be removed (which may reduce a number of surface defects caused by previous processing operations), and a gate stack including an AlN layer, an AlGaN layer, and a GaN layer may be deposited. Figure 9H In FIG. 1 , AlN, AlGaN, and GaN gate stacks are shown as a single composite gate stack 931 / 933. In some embodiments, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and / or plasma enhanced CVD may be used to deposit the gate stack. Figure 9H 1 / 933. In some embodiments, magnesium dopant may be provided during formation of the composite gate stack, for example, to ensure p-type conductivity of the AlGaN and GaN layers. In some embodiments, the doping concentration of the AlGaN and GaN layers of the composite gate stack 931 / 933 may be 1x10 19 cm -3 Then, an annealing may be performed, for example, in nitrogen or in a nitrogen-oxygen mixture, in order to activate the Mg dopant in the composite gate 931 / 933.

[0066] like Figure 9H and Fig.9I As further shown, a gate metal layer 935 can be deposited onto the composite gate stack 931 / 933 and patterned. In some embodiments, the gate metal layer 935 can include titanium nitride (TiN) or tantalum nitride (TaN).

[0067] Also like Fig.9I As shown, the composite gate stack 931 / 933 and gate metal layer 935 may then be etched (eg, dry etched) to define Fig.9I The gate stack structure is shown, and the SiC surface is also exposed (eg, for forming contacts with the source region 910 and the body region 920).

[0068] like Figure 9JAs shown, an interlayer dielectric 939 may then be deposited over the gate stack and patterned. In some embodiments, the interlayer dielectric 939 may include silicon nitride, silicon dioxide, or a stack of silicon nitride and silicon dioxide. Figure 9J As further shown, metal 941m (e.g., nickel) that can be used to form an ohmic contact with the SiC can then be deposited and patterned. Figure 9J As shown, a metal layer 945m (e.g., nickel) may also be deposited onto the back side of the associated SiC wafer, where the metal layer 945m may be used to define (form, produce, etc.) a backside ohmic contact. Annealing may then be performed to form silicide (e.g., nickel silicide from metal layers 941m and 945m and SiC) and produce (define, etc.) ohmic contacts 941 and 945, as shown. Figure 9K As shown. In this example, the resulting nickel silicide can penetrate into the silicon carbide during annealing (e.g., silicide reaction). In some embodiments, the formation of nickel silicide can allow the formation of sub-contact regions 911 and 921 to be omitted. For example, in some embodiments, since during the formation of silicide, the reacted nickel (with SiC) can penetrate through the entire depth of the subsequent channel region 905 and spacer 904, the formation of sub-contact regions 911 and 921 for defining ohmic contacts can be eliminated.

[0069] Although in Figure 9K , but in an exemplary process, a topside pad metal may then be deposited and patterned, and a backside metal may also be deposited, such as deposited on Figure 1 In some embodiments, this topside metal may include aluminum and the backside metal may include a stack of titanium, nickel, and silver, although other metals may also be used. After forming the topside pad metal, a passivation dielectric such as silicon nitride, silicon dioxide, and / or polyimide may be formed in the peripheral region of the FET 900. The gate pad region (which is located at the bottom of the gate) may be formed. Figure 1 and FIG. 9A to FIG. 9K ) may be connected to a source pad (such as Figure 1 The source pad metal 148 shown is formed simultaneously.

[0070] In some embodiments, a gate contact (e.g., between gate metal layer 935 and gate stack 931 / 933) may be formed without an annealing process, which may reduce gate leakage under forward gate bias conditions. In this example, a topside contact to silicon carbide may also be formed without annealing and formed as an as-deposited ohmic contact using sub-contact regions 911 and 921. In this exemplary embodiment, the respective doping concentrations of sub-contact regions 911 and 921 may be increased to above 1x10 20 cm -3value in order to facilitate (produce, result in, etc.) a contact having as-deposited ohmic contact characteristics.

[0071] Fig.10 1 shows a gate structure stack 1000 of a SiC JFET according to an embodiment, wherein the gate structure stack 1000 includes a GaN tunnel diode. In some embodiments, Figure 1 SiC FET 100 is implemented in Fig.10 The gate structure stack, for example, replaces the above relative to Figure 1 The gate structure stack discussed. Fig.10 , only a portion of the lateral channel region 1005 of the underlying SiC FET structure is shown for illustration purposes. The gate structure stack 1000 includes an AlN interface layer 1031, a p-type AlGaN layer 1032, a p-type GaN layer 1033, and an n-type GaN layer 1034 disposed on the lateral channel region 1005. The GaN layers 1033 and 1034 are heavily doped with acceptor ions and donor ions, respectively, so that a tunnel diode is defined between the layers 1033 and 1034.

[0072] In this exemplary embodiment, gate leakage may be controlled by controlling the respective doping concentrations of the p-type GaN layer 1033 and the n-type GaN layer 1034. The gate structure stack 1000 further includes a gate metal layer 1035 disposed on the n-type GaN layer 1034. In some embodiments, the p-type GaN layer 1033 may be omitted, and the n-type GaN layer 1034 may be disposed directly on the p-type AlGaN layer 1032. However, in some embodiments, the use of the n-type GaN layer 1034 may improve the quality (e.g., reduce resistance) of an ohmic contact (such as an ohmic contact between the gate metal layer and the p-type GaN layer) between the gate metal layer 1035 and the composite gate structure.

[0073] Fig.11 Shown with Figure 1 The SiC FET 100 of the present invention is structurally similar to the SiC FET 1100, in which the composite gate structure stack is disposed (e.g., using selective deposition) in a well 1139 defined in a SiO2 mask 1138. For example, the SiC FET 1100 includes a substrate 1101 of a first conductivity type, a drift region 1102 of a first conductivity type, a diffusion layer 1103 of a first conductivity type, a body region 1120 of a second conductivity type, a source region 1110 of a first conductivity type, a spacer 1104 of a first conductivity type, and a lateral channel region 1105 of a first conductivity type.

[0074] Also like Fig.11 As shown, the composite gate structure stack of SiC FET 1100 (with Figure 1The composite gate structure stack of the FET 110 in FIG. 1100 may be disposed in a well 1139 defined in a SiO2 mask 1138. For example, the gate structure stack of the SiC FET 1100 includes an AlN interface layer 1131, a p-type AlGaN layer 1132, and a p-type GaN layer 1133 disposed on the lateral channel region 1105. Fig.11 1139, but the gate structure stack of the SiC FET 1100 may also include a gate metal layer disposed on the p-type GaN layer 1033, such as shown in other exemplary embodiments described herein. As described above, the gate stack of the AlN layer 1131, the p-type AlGaN layer 1132, and the p-type GaN layer 1133 may be selectively deposited into the well 1139 or selectively grown in the well 1139. For embodiments using non-selective deposition techniques, the gate stack material deposited on the SiO2 mask 1138 (e.g., outside the well 1139) may be removed by selective etching.

[0075] Fig.12 1 is a schematic diagram schematically showing a plan view of SiC FET 1200. Fig.12 As shown, FET 1200 may include an active region including a one-dimensional array of linear unit cells 1260. In some embodiments, unit cells 1260 of SiC FET 1200 may have Figure 1 The structure of the SiC FET 100 may include, for example, Fig.10 and Fig.11 That is, in some embodiments, the unit cell 1260 may include and / or combine certain features of the various SiC FETs described herein.

[0076] Fig.12 The SiC FET 1200 may further include a termination region 1271 disposed around the active region of the SiC FET 1200. Different methods (structures) for junction termination may be included in the termination region 1271, wherein the specific termination structure used will depend on the implementation of the unit cell 1260 of the SiC FET 1200. In the SiC FET 1200, the termination region 1271 should have, for example, the same or higher breakdown voltage as the active region of the unit cell 1260 array.

[0077] Fig.13 is a graph 1300 showing the interface state density of various interface layer materials with SiC. Fig.13 As can be seen in the graph 1300, among the materials shown, AlN has the lowest D it , which in some cases is at least an order of magnitude smaller than other potential interfacial layer materials.

[0078] Fig.14 is a schematic diagram schematically illustrating a side cross-sectional view of a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) 1400 according to an embodiment. For example, Fig.14 14 shows a cross-sectional view of an exemplary embodiment of a unit cell of a SiC MOSFET 1400. Figure 1 Similar to FET 100, the unit cell of MOSFET 1400 (such as Fig.14 ) can be combined with other examples of unit cells (e.g., Fig.12 A similar arrangement as shown) is used to form a SiC MOSFET, which can be used in power applications such as motor control drives, industrial controls, etc.

[0079] In MOSFET 1400, the work function of p-GaN to SiC can be exploited to produce a silicon carbide MOSFET with improved performance. For example, current high performance power SiC MOSFETs may have significant performance issues due to low threshold voltages of only a few volts. Additionally, at elevated temperatures, such as after prolonged negative bias at the gate, undesirably high leakage currents may be observed during the off state of current SiC MOSFETs. Such biasing tends to cause positive charge to be trapped next to the SiC to oxide interface, causing off state leakage. These issues present performance and reliability issues for current SiC MOSFETs.

[0080] In contrast, power SiC MOSFETs with higher threshold voltages tend to have increased channel resistance due to a reduction in inversion layer mobility. While the exact physical mechanism by which mobility decreases with increasing threshold voltage is not fully understood, it is well established that inversion layer mobility in, for example, SiC MOSFETs is independent of the work function of the gate. Thus, implementing a gate having a gate electrode (gate stack) formed using (including) p-type GaN rather than conventional polysilicon may result in a MOSFET gate having a higher work function than n-type SiC and overcoming at least some of the disadvantages of current SiC MOSFET implementations.

[0081] like Fig.14As shown, MOSFET 1400 may include substrate 1401, drift region 1402, diffusion layer 1403, p body 1420 and n source 1410. MOSFET 1400 may also include p+ subcontact layer 1421. MOSFET 1400 also includes gate oxide 1406. Gate oxide 1406 may have a thickness between about 25nm and 100nm, and in some embodiments, may have a nitrided interface with SiC. Such a nitrided interface may be formed by annealing an oxidized SiC surface in an environment containing nitric oxide (NO) or nitrous oxide (N2O) at a temperature between about 1100C and 1400C. Nitriding may reduce the interface state density in gate oxide 1406 next to the SiC surface (at the interface with the SiC surface).

[0082] MOSFET 1400 also includes an ALD deposited intermediate layer of AlN and a gate of p-GaN, which can be crystalline or microcrystalline. MOSFET 1400 may also include an ohmic drain contact 1445, a drain metal 1446, an ohmic contact 1441 to a source (e.g., n-type) region 1410 and a body (e.g., p-type) region 1420, a gate metal 1435, an interlayer dielectric 1439, and a source pad metal 1448. At zero gate bias, MOSFET 1400 is in an off state, and this can block about the same voltage as FET 100, as described herein, provided that the doping concentration and thickness of drift region 1402 are similar to those described for drift region 102 of FET 100. A positive gate bias will cause an inversion electron channel at the interface of SiC and oxide 1406, and thus turn on (turn on) MOSFET 1400. Therefore, the high work function of p-GaN versus SiC may increase the threshold voltage of MOSFET 1400 without significantly affecting the on-state resistance of MOSFET 1400 .

[0083] It should also be understood that for the purpose of this disclosure, when an element such as a layer, a zone or a substrate is mentioned on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected to another element, or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term may not be used in the entire specific embodiment directly on ..., directly connected to ..., or directly coupled to ..., the element shown as directly on the element, directly connected or directly coupled can be mentioned in this manner. The claims of the present application may be revised to narrate the exemplary relationship described in the specification or shown in the drawings.

[0084] As used in this specification, singular forms may include plural forms unless the context clearly indicates a particular case. Spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent may include lateral adjacent or horizontal adjacent.

[0085] Some embodiments may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and the like.

[0086] Although certain features of the described embodiments have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of a specific implementation. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A silicon carbide field effect transistor, comprising: a substrate of a first conductivity type; a drift region of a first conductivity type, wherein the drift region of the first conductivity type is disposed on the substrate; a diffusion layer of a first conductivity type, wherein the diffusion layer of the first conductivity type is disposed in the drift region; a body region of a second conductivity type, the body region of the second conductivity type being disposed in the diffusion layer; A source region of a first conductivity type, wherein the source region of the first conductivity type is disposed in the body region; a spacer of a first conductivity type, the spacer of the first conductivity type being disposed on the source region, the body region and the diffusion layer; A lateral channel region of a first conductivity type, wherein the lateral channel region of the first conductivity type is disposed in the spacer; and A gate structure, the gate structure comprising: an aluminum nitride layer, wherein the aluminum nitride layer is disposed on the lateral channel region; and An aluminum gallium nitride layer of a second conductivity type is disposed on the aluminum nitride layer. 2 . The silicon carbide field effect transistor according to claim 1 , wherein the lateral channel region is configured to be pinched off under a zero bias condition of the gate structure.

3. The silicon carbide field effect transistor according to claim 1, wherein: The drift region is an epitaxial silicon carbide drift region; and The interlayer is a regenerated silicon carbide layer.

4. The silicon carbide field effect transistor according to claim 1, wherein the gate structure further comprises: A gallium nitride layer of a second conductivity type, wherein the gallium nitride layer of the second conductivity type is disposed on the aluminum gallium nitride layer; a gallium nitride layer of a first conductivity type, the gallium nitride layer of the first conductivity type being disposed on the gallium nitride layer of the second conductivity type, the gallium nitride layer of the first conductivity type defining a tunnel contact with the gallium nitride layer of the second conductivity type; and A metal gate electrode is disposed on the gallium nitride layer of the first conductivity type, and the metal gate electrode defines an ohmic contact with the gallium nitride layer of the first conductivity type. 5 . The silicon carbide field effect transistor of claim 1 , wherein the aluminum gallium nitride layer has an aluminum nitride mole fraction greater than or equal to 18 percent.

6. The silicon carbide field effect transistor according to claim 1, further comprising: an ohmic drain contact, the ohmic drain contact being disposed on the substrate; an interlayer dielectric, the interlayer dielectric being disposed on the gate structure; A source metal structure, the source metal structure comprising: An ohmic contact layer, wherein the ohmic contact layer is defined as: an ohmic contact to the body region; and an ohmic contact to the source region; and a metal layer, the metal layer being disposed on the ohmic contact, a portion of the lateral channel region and the interlayer dielectric, the gate structure being electrically isolated from the metal layer by the interlayer dielectric, in: an ohmic contact to the body region comprising a sub-contact region of the second conductivity type disposed in the body region, the sub-contact region having a doping concentration higher than a doping concentration of the body region; and The ohmic contact layer contacts the spacer and the lateral channel region. 7 . The silicon carbide field effect transistor according to claim 1 , wherein the diffusion layer comprises a vertical channel region of the silicon carbide field effect transistor, the vertical channel region having a doping concentration greater than a doping concentration of the drift region.

8. The silicon carbide field effect transistor according to claim 1, wherein the gate structure further comprises: A gallium nitride layer of a first conductivity type, the gallium nitride layer of the first conductivity type being disposed on the aluminum gallium nitride layer, the gallium nitride layer defining a tunnel contact with the aluminum gallium nitride layer; and A metal gate electrode is disposed on the gallium nitride layer, and the metal gate electrode defines an ohmic contact with the gallium nitride layer.

9. A silicon carbide field effect transistor, comprising: n-type substrate; An n-type drift region, wherein the n-type drift region is disposed on the substrate; an n-type diffusion layer, the n-type diffusion layer being disposed in the drift region; a p-type body region, the p-type body region being disposed in the diffusion layer; An n-type source region, wherein the n-type source region is located in the body region; An n-type spacer layer, the n-type spacer layer is arranged on the source region, the body region and the diffusion layer; An n-type lateral channel region, wherein the n-type lateral channel region is disposed in the spacer; and A gate structure, the gate structure comprising: an aluminum nitride layer, wherein the aluminum nitride layer is disposed on the lateral channel region; A p-type aluminum gallium nitride layer, wherein the p-type aluminum gallium nitride layer is disposed on the aluminum nitride layer; A p-type gallium nitride layer, the p-type gallium nitride layer being disposed on the aluminum gallium nitride layer; and A metal gate electrode is disposed on the gallium nitride layer, and the metal gate electrode defines an ohmic contact with the gallium nitride layer. 10 . The silicon carbide field effect transistor of claim 9 , wherein the aluminum gallium nitride layer has an aluminum nitride mole fraction greater than or equal to 18 percent.

11. A silicon carbide field effect transistor, comprising: n-type substrate; An n-type drift region, wherein the n-type drift region is disposed on the substrate; an n-type diffusion layer, the n-type diffusion layer being disposed in the drift region; a p-type body region, the p-type body region being disposed in the diffusion layer; An n-type source region, wherein the n-type source region is disposed in the body region; An n-type spacer layer, the n-type spacer layer is arranged on the source region, the body region and the diffusion layer; An n-type lateral channel region, wherein the lateral channel region is disposed in the spacer; and A gate structure, the gate structure comprising: an aluminum nitride layer, wherein the aluminum nitride layer is disposed on the lateral channel region; A p-type aluminum gallium nitride layer, wherein the p-type aluminum gallium nitride layer is disposed on the aluminum nitride layer; an n-type gallium nitride layer disposed on the aluminum gallium nitride layer, the gallium nitride layer defining a tunnel contact with the aluminum gallium nitride layer; and A metal gate electrode is disposed on the gallium nitride layer, and the metal gate electrode defines an ohmic contact with the gallium nitride layer. 12 . The silicon carbide field effect transistor of claim 11 , wherein the aluminum gallium nitride layer has an aluminum nitride mole fraction greater than or equal to 18 percent.

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