Circuit device for low input charge analog-to-digital conversion

Abstract

Various embodiments of this disclosure relate to circuit arrangements for analog-to-digital conversion with low input charge. The analog-to-digital converter includes: a sampling capacitor connected to a multiplexer output; a discharge circuit arrangement that discharges the sampling capacitor during a first time period at the beginning of a sampling cycle; and a level shifting circuit arrangement that charges the sampling capacitor to a voltage at a first analog input node during a second time period beginning after the first time period ends. The voltage at the first analog input node is modified by a mismatch voltage caused by a mismatch between a threshold voltage between a first transistor connected to the first analog input node and a second transistor connected to an output node. A first switch connects the first analog input node to the output node at the end of the second time period to charge the sampling capacitor to the voltage at the first analog input node, and disconnects the first analog input node from the output node at the end of the analog-to-digital converter's sampling cycle.

Description

Technical Field

[0001] This disclosure relates to the field of analog-to-digital conversion, and more particularly to a circuit for reducing the input charge of a sampling capacitor supplied from an analog input to an analog-to-digital converter. Background Technology

[0002] Analog-to-digital conversion (ADC) is widely used in applications involving numerous sensors (e.g., automotive applications). In some constant-scale ADC forms, an analog source (such as a sensor) provides input charge to a sampling capacitor, and the charge accumulates, so the voltage sampled on the sampling capacitor during the sampling period is converted into a digital value.

[0003] The goal is to reduce input charge, thereby decreasing the voltage drop across the input filter of the analog-to-digital converter (ADC) and enabling a higher sampling rate. Existing techniques use rail-to-rail buffers to sample the input voltage to achieve this. While this eliminates concerns about input charge, such buffers consume significant on-chip area and consume high power, especially at high sampling rates. They become prohibitively expensive in terms of both area and power consumption, particularly in situations with numerous analog input sources.

[0004] Therefore, further development is needed in this field. Summary of the Invention

[0005] One aspect disclosed herein relates to input circuitry for a multiplexer. The input circuitry includes a first analog input node, an output node, and a capacitive node connected to the output node. A first control circuit is configured to set the charge at the capacitive node to a desired voltage during a first time period, which begins in response to the start of a sampling period of the analog-to-digital converter (ADC), wherein the input of the ADC is driven by the output of the multiplexer. A second control circuit is configured to set the charge at the capacitive node to a voltage at the first analog input node during a second time period, which begins in response to the end of the first time period. The voltage at the first analog input node is modified by a mismatch voltage resulting from a threshold voltage mismatch between a first transistor connected to the first analog input node and a second transistor connected to the output node. A first channel selection switch closes to connect the first analog input node to the output node, thereby charging the capacitive node to the voltage at the first analog input node. The first channel selection switch closes in response to the end of the second time period. At the end of the ADC's sampling period, the first channel selection switch opens to disconnect the first analog input node from the output node.

[0006] Another aspect disclosed herein relates to an input circuit for an analog-to-digital converter (ADC). The input circuit includes a first channel selection switch that closes to connect a first analog input node to an intermediate node, thereby charging the intermediate node to the voltage at the first analog input node. The first channel selection switch closes during a first time period that begins in response to the start of the ADC's sampling period. A capacitive node is connected to an output node. A discharge circuit is connected between the first channel selection switch and the output node and configured to discharge the capacitive node during the first time period. A level shifting circuit is configured to charge the capacitive node to the voltage at the intermediate node minus the threshold voltage of a first transistor of the level shifting circuit during a second time period that begins in response to the end of the first time period. A selection switch closes to connect the intermediate node to the output node, thereby charging the output node to the voltage at the intermediate node. The selection switch closes in response to the end of the second time period. At the end of the ADC's sampling period, the selection switch opens to disconnect the intermediate node from the output node.

[0007] Another aspect disclosed herein relates to an input circuit for an analog-to-digital converter (ADC). The input circuit includes a first channel selection switch that closes to connect a first analog input node to an intermediate node, thereby charging the intermediate node to the voltage at the first analog input node. The first channel selection switch closes during a first time period that begins in response to the start of the ADC's sampling period. A capacitive node is connected to an output node. A charging circuit is connected between the first channel selection switch and the output node and is configured to charge the capacitive node to the supply voltage during the first time period. A level shifting circuit is configured to discharge the capacitive node to the voltage at the intermediate node plus a threshold voltage of a first transistor of the level shifting circuit during a second time period that begins in response to the end of the first time period. A selection switch closes to connect the intermediate node to the output node, thereby discharging the output node to the voltage at the intermediate node. The selection switch closes in response to the end of the second time period. At the end of the ADC's sampling period, the selection switch opens to disconnect the intermediate node from the output node.

[0008] The additional aspect relates to input circuitry for an analog-to-digital converter (ADC). The input circuitry includes a first channel selection switch that closes to connect a first analog input node to an intermediate node, thereby charging the intermediate node to the voltage at the first analog input node. The first channel selection switch closes during a first time period that begins in response to the start of the ADC's sampling period. A capacitive node is connected to an output node. A first control circuit is connected between the first channel selection switch and the output node and is configured to set the charge at the capacitive node to a desired voltage during the first time period. A second control circuit is configured to set the charge at the capacitive node to the voltage at the intermediate node during a second time period that begins in response to the end of the first time period. The voltage at the intermediate node is modified by a mismatch voltage resulting from a threshold voltage mismatch between a first transistor connected to the intermediate node and a second transistor connected to the output node. A selection switch closes to connect the intermediate node to the output node, thereby charging the output node to the voltage at the intermediate node. The selection switch closes in response to the end of the second time period. At the end of the ADC's sampling period, the selection switch opens to disconnect the intermediate node from the output node. Attached Figure Description

[0009] Figure 1 This is a block diagram of a multiplexed input circuit for an analog-to-digital converter according to the present disclosure.

[0010] Figure 2 It is such as being able to Figure 1 A schematic diagram of the sampling level shifting circuit used in the multiplexed input circuit.

[0011] Figure 3 yes Figure 2 The timing diagram shows the operation of the level shifting circuit device.

[0012] Figure 4 It is such as being able to Figure 1 A schematic diagram of the alternative sampling level shifting circuit device used in the multiplexed input circuit.

[0013] Figure 5 yes Figure 4 The timing diagram shows the operation of the level shifting circuit device.

[0014] Figure 6 This is a schematic diagram of another multiplexed input circuit for an analog-to-digital converter according to the present disclosure.

[0015] Figure 7 yes Figure 6 The timing diagram shows the operation of the multiplexed input circuit.

[0016] Figure 8 This is a schematic diagram of another multiplexed input circuit for an analog-to-digital converter according to the present disclosure.

[0017] Figure 9 yes Figure 8 The timing diagram shows the operation of the multiplexed input circuit.

[0018] Figure 10 This is a schematic diagram of another multiplexed input circuit for an analog-to-digital converter according to the present disclosure.

[0019] Figure 11 yes Figure 10 The timing diagram shows the operation of the multiplexed input circuit.

[0020] Figure 12 This is a schematic diagram of an additional multiplexed input circuit for an analog-to-digital converter according to the present disclosure.

[0021] Figure 13 yes Figure 12 The timing diagram shows the operation of the multiplexed input circuit.

[0022] Figure 14 Such as can with Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 10 and Figure 12 A schematic diagram of an input switch used together with a multiplexed input circuit.

[0023] Figure 15 This is a first diagram showing the input charge across different input voltages according to the design of this disclosure.

[0024] Figure 16 This is a second diagram showing the input charge across different input voltages according to the design of this disclosure. Detailed Implementation

[0025] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but should be given the widest scope consistent with the principles and features disclosed or suggested herein.

[0026] As used in the claims, the term "assertion" means that a signal has the logic level required to turn on a component that transmits the signal. For example, regardless of whether the transistor is n-channel or p-channel, an "assertion" signal will turn on the transistor; similarly, an "assertion" signal will close a switch.

[0027] Figure 1The diagram shown is of an eight-channel multiplexer 10, which has eight analog input nodes (AnalogInput). <0> -AnalogInput <7> The device receives eight analog inputs. Eight channel selection switches S0-S7 are connected to the analog input node AnalogInput. <0> -AnalogInput <7> Between node NX and each of the eight channels is selected by the signal ChSel. <0> -ChSel <7> To control. In the channel selection signal ChSel <0> -ChSel <7> Under the control of the channel selection switches S0-S7, according to the timing described below, the analog input node AnalogInput is selected one at a time. <0> -AnalogInput <7> The selected analog input node is connected to node NX, which is then connected to the input of analog-to-digital converter (ADC) 11 at node OUT, so that ADC 11 selects the analog input node AnalogInput. <0> -AnalogInput <7> The signal is digitized at this location. Level shifting circuit device 12 <0> -12 <7> Connected in parallel with channel selection switches S0-S7 at the AnalogInput node <0> -AnalogInput <7> Between node NX. As described below, before closing the channel selection switches S0-S7 of the selected channel, the level shifting circuit device 12 <0> -12 <7> This is used to charge or discharge the sampling capacitor C0 at the input of ADC 11 at node OUT to a level slightly below / above the selected channel's analog input node AnalogInput. <0> -AnalogInput <7> The voltage is such that when the channel selection switches S0-S7 of the selected channel are closed, the voltage from the AnalogInput node of the selected channel is... <0> -AnalogInput <7> The charge amplitude received by the sampling capacitor C0 is relatively small.

[0028] Now for reference Figure 2 To describe a possible variation of the graph level shifting circuit device <12x> (e.g., it can be used as...) Figure 1 Level shifting circuit device 12 in multiplexer 10 <0> -12 <7> Here, when connected to the AnalogInput analog input node... <x>An input voltage VIN exists at the input node Nin. Level shifting circuit device 12 <x>The system includes an n-channel transistor N3, whose drain is connected to node NX, source is grounded, and gate is connected to control signal CTRL2. A sampling capacitor C0 is connected between output node OUT and ground, and output node OUT is connected to node NX. A p-channel transistor P0 has its source connected to node A, drain connected to ground, and gate connected to input node Nin. A p-channel transistor P3 has its source connected to the supply voltage VCC, its drain connected to the source of p-channel transistor P0 via resistor R0, and its gate connected to the output of NOR gate 13. NOR gate 13 receives control signal CTRL2 and the complement of control signal CTRL1 (abbreviated as CTRL1B) as inputs and provides its output to the gate of p-channel transistor P3.

[0029] The drain of n-channel transistor N1 is connected to node B, the source is connected to ground, and the gate is connected to the control signal CTRL1. The drain of n-channel transistor N2 is connected to the drain of p-channel transistor P2, the source is connected to node NX, and the gate is connected to node B. The source of p-channel transistor P2 is connected to the supply voltage VCC, the drain is connected to the drain of n-channel transistor N2, and the gate is connected to the control signal CTRL1.

[0030] A transmission gate formed by a p-channel transistor P1 and an n-channel transistor N0 is connected between nodes A and B. Specifically, the source of the p-channel transistor P1 is connected to node A, the drain is connected to node B, and the gate is connected to the control signal CTRL1, while the drain of the n-channel transistor N0 is connected to node A, the source is connected to node B, and the gate is connected to the complement of the first control signal CTRL1B.

[0031] Now, additional references Figure 3 To describe the level shifting circuit device 12 <x>The following description pertains to the operation of the level shifting circuit device 12. <x>The associated channel is selected; each other channel is deselected (meaning the CTRL1 signal of the deselected channel remains high, while the CTRL2 signal of the deselected channel remains low). Therefore, for the level shifting circuit device 12... <x>For the associated selected channel, at time T0, in response to the rising edge of the first clock pulse CLK, the sampling phase of ADC 11 begins with the control signal CTRL2 rising to logic high, while the control signal CTRL1 remains at logic high. Note that ChSel <x>Keep it at a logical low level.

[0032] With CTRL2 high, n-channel transistor N3 is turned on, causing sampling capacitor C0 to discharge. With CTRL1 high, the transmission gate formed by p-channel transistor P1 and n-channel transistor N0 is turned off, p-channel transistor P2 is turned off, and n-channel transistor N1 is turned on to collect current from node B, thus keeping n-channel transistor N2 off.

[0033] Since CTRL2 is high and CTRL1B is low (because CTRL1 is high), the output of NOR gate 13 is logic low, thus turning on p-channel transistor P3. Because p-channel transistor P0 and resistor R0 form a source follower amplifier, the voltage at node A will rise to AnalogInput. <x>The voltage at node A is the sum of the threshold voltage Vth of the p-channel transistor P0. Therefore, the voltage at node A can be mathematically expressed as:

[0034] Va=VIN+|Th P0 |

[0035] At time T1, control signals CTRL2 and CTRL1 go low, and attention is again drawn to ChSel. <x>Keep it low. This turns on p-channel transistor P1 and n-channel transistor N0, and since it also turns off n-channel transistor N1, this allows the voltage at node B to be equal to the voltage at node A. Therefore, the voltage at node B can be mathematically expressed as:

[0036] Vb = Va = VIN + |Th P0 |

[0037] Since CTRL1 is low, p-channel transistor P2 is turned on. And because n-channel transistor N2 is a source follower, it provides current to output node N2 to charge the sampling capacitor C0 until the voltage at output node OUT becomes equal to the voltage at node B minus the threshold voltage of n-channel transistor N2. Mathematically, the voltage at output node OUT is equal to:

[0038] VOUT = Vb - Th N2 =VIN+|Th P0 |-Th N2

[0039] Due to process variations and the fact that transistors P0 and N2 are not ideal, this means that the threshold voltages of P0 and N2 are not equal. If the threshold voltage of N2 is greater than the threshold voltage of P0 by a significant margin, VOUT will be less than VIN. Conversely, VOUT can be slightly higher than VIN. The above equation remains accurate unless VIN is a threshold voltage lower than the supply voltage VCC.

[0040] At time T2, CTRL2 remains low, while CTRL1 rises to high. Note that for this, ChSel <x>The switch Sx is closed by rising to a high position to select the level shifting circuit device 12. <x>The associated channel, while the corresponding ChSel signal of each level shifting circuit device 12 for each other channel remains low to keep its corresponding switch Sx open. Closing switch Sx will cause current to flow from the AnalogInput node. <x>The current flows to the sampling capacitor C0 to charge it to VIN. However, since the sampling capacitor C0 will charge to near VIN (the difference between the magnitude of VIN being less than / greater than the threshold voltage of P0 and the threshold voltage of N2) between times T1 and T2, the current flows from the AnalogInput node... <x>The current flowing to the output node OUT will be very low, much smaller than the current that typically flows from the analog input node to the output node in existing technology designs.

[0041] The sampling phase ends at time T3.

[0042] Figure 4 Variant 12 is shown in the figure. <x>The main difference here is that the sampling capacitor C0 is charged to the supply voltage VCC and then discharged before the switch Sx is closed to keep it near VIN.

[0043] The details are as follows. Here, the source of p-channel transistor P3 is connected to the supply voltage VCC, the drain is connected to node NX, and the gate is connected to the control signal CTRL2. Additionally, a sampling capacitor C0 is connected between the output node OUT and ground. Node NX is connected to the output node OUT. The drain of n-channel transistor N0 is connected to VCC, the source is connected to node A, and the gate is connected to the input node Nin. The drain of n-channel transistor N3 is connected to node A via resistor R0, the source is connected to ground, and the gate is connected to the output of NAND gate 13'. NAND gate 13' receives control signals CTRL1 and CTRL2 as inputs and provides its output to the gate of n-channel transistor N3.

[0044] The source of P-channel transistor P1 is connected to VCC, the drain is connected to node B, and the gate is connected to the complement of the first control signal CTRL1B. The source of P-channel transistor P2 is connected to node NX, the drain is connected to the drain of n-channel transistor N2, and the gate is connected to node B. The drain of N-channel transistor N2 is connected to the drain of p-channel transistor P1, the source is connected to ground, and the gate is connected to the complement of the first control signal CTRL1B.

[0045] The transmission gate is formed by a p-channel transistor P0 and an n-channel transistor N1. Specifically, the source of the p-channel transistor P0 is connected to node B, the drain is connected to node A, and the gate is connected to the control signal CTRL1, while the drain of the n-channel transistor N1 is connected to node B, the source is connected to node A, and the gate is connected to the complement of the first control signal CTRL1B.

[0046] Now, additional references Figure 5 The following description describes the operation of the level shifting circuit device 12x'. The following description pertains to the selection and operation of the level shifting circuit device 12x'. <x>The associated channel status; each other channel is deselected (meaning the CTRL1 signal of the deselected channel remains high, while the CTRL2 signal of the deselected channel remains low). Therefore, for the level shifting circuit device 12... <x>'Associated selected channel. At time T0, in response to the rising edge of the first clock pulse CLK, the sampling phase of ADC 11 begins when control signal CTRL2 falls to logic low, while control signal CTRL1 remains at logic high. Note that ChSel <x>Keep it at a logical low level.

[0047] With CTRL2 low, p-channel transistor P3 is turned on, charging sampling capacitor C0 to the supply voltage VCC. With CTRL1 high, the transmission gate formed by p-channel transistor P0 and n-channel transistor N1 is turned off, n-channel transistor N2 is turned off, and p-channel transistor P1 is turned on to supply current to node B, thereby keeping p-channel transistor P2 off.

[0048] Since CTRL2 is low and CTRL1 is high, the output of NAND gate 13' is logic high, thus turning on the n-channel transistor N3. Because the n-channel transistor N0 and resistor R0 combine to form a source follower amplifier, the voltage at node A will rise to AnalogInput. <x>The voltage at node A is the difference between the voltage at node A and the threshold voltage Vth of the n-channel transistor N0. Therefore, the voltage at node A can be mathematically expressed as:

[0049] Va = VIN - Th N0

[0050] At time T1, control signal CTRL1 drops to low, while control signal CTRL2 rises to high. Note again ChSel <x>Keep it low. This turns on p-channel transistor P0 and n-channel transistor N1, and since it also turns off p-channel transistor P1, this allows the voltage at node B to become equal to the voltage at node A. The voltage at node B can therefore be mathematically expressed as:

[0051] Vb = Va = VIN - ThN0

[0052] Since CTRL1 is low, the n-channel transistor N2 is turned on. And because the p-channel transistor P2 is a source follower, it draws current from node NX, causing the sampling capacitor C0 to discharge until the voltage OUT at the output node equals the voltage at node B plus the threshold voltage of the p-channel transistor P2. Mathematically, the voltage at the output node OUT is equal to:

[0053] VOUT = Vb + ThP2 = VIN + |Th P2 |-Th N0

[0054] Due to process variations and the fact that transistors P2 and N0 are not ideal, this means that the threshold voltages of P2 and N0 are not equal. If the threshold voltage of N0 is greater than the threshold voltage of P2 by a significant margin, VOUT will be less than VIN. Conversely, VOUT can be slightly higher than VIN.

[0055] At time T2, CTRL2 remains high, while CTRL1 rises to high. Note that at this point, ChSel <x>The switch is raised to high, thereby closing the switch Sx to select the level shifting circuit device 12. <x>The associated channel, while the corresponding ChSel signal of each level shifting circuit device 12 for each other channel is kept low to keep its corresponding switch Sx open. Closing switch Sx will cause current to flow from the AnalogInput node. <x>The current flows to the sampling capacitor C0 to charge it to VIN. However, since the sampling capacitor C0 will charge to near VIN between times T1 and T2, the current flows from the AnalogInput node... <x>The current flowing to the output node OUT will be very low, much lower than the current flowing from the analog input node to the output node in existing technology designs.

[0056] The sampling phase ends at time T3. In both embodiments above, process tuning options can be used to eliminate the mismatch between the PMOS and NMOS threshold voltages to keep the charge from the analog input node to a minimum. For example, this can be achieved by fine-tuning the resistor R0.

[0057] Figure 6 The diagram illustrates another design for a multiplexer 10' that results in less current being supplied to the sampling capacitor C0 compared to existing designs. Here, the multiplexer 10' is an eight-channel multiplexer 10', with its eight analog input nodes (AnalogInput)... <0> -AnalogInput <7> The device receives eight analog inputs. Eight channel selection switches S0-S7 are connected to the analog input node AnalogInput. <0> -AnalogInput <7> Between node Nin1 and node Nin1, and selected by eight channels respectively via the selection signal ChSel <0> -ChSel <7> To control. In the channel selection signal ChSel <0> -ChSel <7> Under the control of the channel selection switches S0-S7, according to the timing described below, the analog input node AnalogInput is selected one at a time. <0> -AnalogInput <7> The selected analog input node is selectively connected to node Nin1.

[0058] Here, the final selection switch SF is connected between node Nin1 and node NX (node ​​NX is then connected to the output node OUT), and operates under the control of the final channel selection signal ChSelF. The drain of n-channel transistor N3 is connected to node NX, the source is connected to ground, and the gate is connected to the control signal CTRL2. The source of p-channel transistor P2 is connected to the supply voltage VCC, the drain is connected to the drain of n-channel transistor N2, and the gate is connected to the control signal CTRL1. The drain of n-channel transistor N2 is connected to the drain of p-channel transistor P2, the source is connected to node NX, and the gate is connected to node Nin1.

[0059] Now, additional references Figure 7 To describe the operation of multiplexer 10'.

[0060] At time T0, in response to the rising edge of the first clock pulse CLK, the sampling phase of ADC 11 begins when control signal CTRL2 rises to logic high, while control signal CTRL1 remains at logic high. Note that ChSel <x>(x corresponds to the ChSel of the selected channel) rises to logic high, while ChSelF remains logic low. The ChSel of channels that are never selected remains low.

[0061] In response to ChSel <x>When the signal rises to logic high, the corresponding switch S closes, charging node Nin1 to Vin. Since control signal CTRL1 remains logic high, p-channel transistor P2 remains off, allowing sampling capacitor C0 to discharge. Because control signal CTRL2 is logic high, n-channel transistor N3 will turn on, causing sampling capacitor C0 to discharge between time periods T0 and T1.

[0062] At time T1, in response to the rising of the second clock pulse CLK, both control signals CTRL1 and CTRL2 fall to logic low. Note that ChSel <x>The CTRL2 signal remains at a logic high, while the p-channel transistor P2 remains at a logic low. Since CTRL2 is logic low, the n-channel transistor N3 is off, and since CTRL1 is low, the p-channel transistor P2 is on. As a result, between times T1 and T2, the n-channel transistor N2 provides sufficient current to the sampling capacitor C0 to charge it to near VIN (VIN minus the threshold voltage of the n-channel transistor N2). Mathematically, this can be expressed as:

[0063] VOUT = VIN - Th N2

[0064] At time T2, in response to the rising of the third clock pulse CLK, control signal CTRL1 rises to logic high, while control signal CTRL2 remains at logic low. Note that here, ChSelF rises to logic high, while ChSel... <x>It remains at a logic high position. Since the switch SF closes in response to ChSelF going high, the selected analog input AnalogInput will provide sufficient current to the output node OUT to charge VOUT to equal VIN. The current flowing from the analog input AnalogInput to the output node OUT will be very low, much smaller than the current typically flowing from the analog input node to the output node in existing technology designs.

[0065] At time T3, the sampling phase of ADC 11 ends. Because only this small amount of logic is needed for the complete multiplexer 10' with the addition of switch SF, this is area-efficient logic. Here, the analog input AnalogInput always provides a charge corresponding to the threshold voltage of N2.

[0066] Now for reference Figure 8 To describe a variant of multiplexer 10". Multiplexer 10" is an eight-channel multiplexer 10, which has eight analog input nodes (AnalogInput). <0> -AnalogInput <7> The device receives eight analog inputs. Eight channel selection switches S0-S7 are connected to the analog input node AnalogInput. <0> -AnalogInput <7> Between node Nin1 and node Nin1, and selected by eight channels respectively via the selection signal ChSel <0> -ChSel <7> To control. In the channel selection signal ChSel <0> -ChSel <7> Under the control of the channel selection switches S0-S7, according to the timing described below, the analog input node AnalogInput is selected one at a time. <0> -AnalogInput <7> The selected analog input node is selectively connected to node Nin1.

[0067] Here, the final selection switch SF is connected between node Nin1 and node NX (node ​​NX is then connected to the output node OUT), and operates under the control of the final channel selection signal ChSelF. The drain of p-channel transistor P3 is connected to node NX, the source is connected to the supply voltage VCC, and the gate is connected to the control signal CTRL2. The source of p-channel transistor P2 is connected to node NX, the drain is connected to the drain of n-channel transistor N2, and the gate is connected to node Nin1. The drain of n-channel transistor N2 is connected to the drain of p-channel transistor P2, the source is connected to ground, and the gate is connected to the control signal CTRL1.

[0068] Additional reference Figure 9 Now, the operation of multiplexer 10” is described. At time T0, in response to the rising of the first clock pulse CLK, the sampling phase of ADC 11 begins when control signal CTRL2 falls to logic low, while control signal CTRL1 remains at logic low. Note that ChSel <x>It rises to a higher logical level, while ChSelF remains at a lower logical level.

[0069] In response to ChSel <x>When ChSel (corresponding to one of the channels of multiplexer 10) rises to logic high, the corresponding switch Sx closes, thereby charging node Nin1 to VIN. Since control signal CTRL1 remains logic low, n-channel transistor N2 remains off, allowing sampling capacitor C0 to charge. Because control signal CTRL2 is logic low, p-channel transistor P3 will turn on, thereby charging sampling capacitor C0 to VCC between time periods T0 and T1.

[0070] At time T1, in response to the rising of the second clock pulse CLK, control signals CTRL1 and CTRL2 rise to logic high. Note that ChSel <x>The p-channel transistor P3 remains at logic high, while the n-channel transistor N2 remains at logic low. Since CTRL2 is logic high, the p-channel transistor P3 is off, and since CTRL1 is also logic high, the n-channel transistor N2 is on. As a result, between times T1 and T2, the p-channel transistor P2 draws enough current from the sampling capacitor C0 to almost discharge the sampling capacitor to VIN (VIN plus the magnitude of the threshold voltage of the p-channel transistor P2). Mathematically, this can be expressed as:

[0071] VOUT = VIN + |Th P2 |

[0072] At time T2, in response to the rising third clock pulse CLK, control signal CTRL1 falls to logic low, while control signal CTRL2 remains at logic high. Note that here, ChSelF rises to logic high, while ChSel... <x>It remains at a logic high position. Since switch SF closes in response to ChSelF going high, the selected analog input AnalogInput will collect enough current from the output node OUT to discharge VOUT to equal VIN. The current flowing from the output node OUT to the analog input AnalogInput will be very low, much smaller than the current typically flowing from the output node to the analog input node in existing technology designs.

[0073] At time T3, the sampling phase of ADC 11 ends. Since the complete multiplexer 10” requires only such a small amount of logic with the addition of switch SF, this is very area-efficient logic. Here, the analog input node AnalogInput collects the charge corresponding to the threshold voltage of P2.

[0074] exist Figure 10 The diagram shows another variation of multiplexer 10”'. Multiplexer 10”' is an eight-channel multiplexer 10, which has eight analog input nodes (AnalogInput). <0> -AnalogInput <7> The device receives eight analog inputs. Eight channel selection switches S0-S7 are connected to the analog input node AnalogInput. <0> -AnalogInput <7> Between node Nin1 and node Nin1, and selected by eight channels respectively via the selection signal ChSel <0> -ChSel <7> To control. In the channel selection signal ChSel <0> -ChSel <7> Under the control of the channel selection switches S0-S7, according to the timing described below, the analog input node AnalogInput is selected one at a time. <0> -AnalogInput <7> The selected analog input node is selectively connected to node Nin1.

[0075] Here, the final selection switch SF is connected between node Nin1 and node NX (node ​​NX is then connected to output node OUT) and operates under the control of the final channel selection signal ChSelF.

[0076] Multiplexer 10" includes an n-channel transistor N3, whose drain is connected to node NX, source is connected to ground, and gate is connected to control signal CTRL2. A p-channel transistor P0 has its source connected to node A, its drain connected to ground, and its gate connected to node Nin1. A p-channel transistor P3 has its source connected to the supply voltage VCC, its drain connected to the source of p-channel transistor P0 via resistor R0, and its gate connected to the output of NOR gate 13. NOR gate 13 receives the complement of control signal CTRL2 and control signal CTRL1 (abbreviated as CTRL1B) as inputs and provides its output to the gate of p-channel transistor P3.

[0077] The drain of n-channel transistor N1 is connected to node B, the source is connected to ground, and the gate is connected to the control signal CTRL1. The drain of n-channel transistor N2 is connected to the drain of p-channel transistor P2, the source is connected to node NX, and the gate is connected to node B. The source of p-channel transistor P2 is connected to the supply voltage VCC, the drain is connected to the drain of n-channel transistor N2, and the gate is connected to the control signal CTRL1.

[0078] A transmission gate formed by a p-channel transistor P1 and an n-channel transistor N0 is connected between nodes A and B. Specifically, the source of the p-channel transistor P1 is connected to node A, the drain is connected to node B, and the gate is connected to the control signal CTRL1, while the drain of the n-channel transistor N0 is connected to node A, the source is connected to node B, and the gate is connected to the complement of the first control signal CTRL1B.

[0079] Now, additional references Figure 11 Let's describe the operation of multiplexer 10". At time T0, in response to the rising of the first clock pulse CLK, the sampling phase of ADC 11 begins when control signal CTRL2 rises to logic high, while control signal CTRL1 remains at logic high. Note that ChSel <x>It rises to a higher logical level, while ChSelF remains at a lower logical level.

[0080] With CTRL2 high, n-channel transistor N3 is turned on, causing sampling capacitor C0 to discharge. With CTRL1 high, the transmission gate formed by p-channel transistor P1 and n-channel transistor N0 is turned off, p-channel transistor P2 is turned off, and n-channel transistor N1 is turned on to collect current from node B, thus keeping n-channel transistor N2 in the off state.

[0081] Since CTRL2 is high and CTRL1B is low (because CTRL1 is high), the output of NOR gate 13 is logic low, thus turning on p-channel transistor P3. Because p-channel transistor P0 and resistor R0 form a source follower amplifier, the voltage at node A will rise to the magnitude of VIN plus the threshold voltage Vth of p-channel transistor P0. Therefore, the voltage at node A can be mathematically expressed as:

[0082] Va=VIN+|Th P0 |

[0083] At time T1, control signals CTRL2 and CTRL1 drop low, and attention is again drawn to ChSel. <x>Keep it high. This turns on p-channel transistor P1 and n-channel transistor N0, and since it also turns off n-channel transistor N1, this allows the voltage at node B to be equal to the voltage at node A. Therefore, the voltage at node B can be mathematically expressed as:

[0084] Vb = Va = VIN + |Th P0 |

[0085] Since CTRL1 is low, p-channel transistor P2 is turned on. And because n-channel transistor N2 is a source follower, it provides current to output node N2 to charge the sampling capacitor C0 until the voltage at output node OUT becomes equal to the voltage at node B minus the threshold voltage of n-channel transistor N2. Mathematically, the voltage at output node OUT is equal to:

[0086] VOUT = Vb - Th N2 =VIN+|Th P0 |-Th N2

[0087] Due to process variations and the fact that transistors P0 and N2 are not ideal, this means that the threshold voltages of P0 and N2 are not equal. If the threshold voltage of N2 is greater than the threshold voltage of P0 by a significant margin, VOUT will be less than VIN. Conversely, VOUT can be slightly higher than VIN.

[0088] At time T2, CTRL2 remains low, while CTRL1 rises to a level. Note that at this time, ChSelF rises high, thus closing switch SF. The closing of switch SF will cause current to flow from node Nin1 to the sampling capacitor C0 to charge it to VIN. However, since the sampling capacitor C0 will charge to near VIN (VIN minus the difference between the threshold voltage of P0 and the threshold voltage of N2) between times T1 and T2, the current flowing from node Nin1 to the output node OUT will be lower, with a magnitude much smaller than the current typically flowing to the output node in prior art designs.

[0089] The sampling phase ends at time T3. This is because it eliminates the requirement for the input charge from the analog input node corresponding to the threshold voltage of N2, thus... Figure 6 An improvement to the embodiment. Additionally, the complete multiplexer requires only this single circuit, making it a very area-efficient design.

[0090] exist Figure 12 A variation of multiplexer 10”” is shown. Here, the source of p-channel transistor P3 is connected to the supply voltage VCC, the drain is connected to node NX (and thus to the output node OUT), and the gate is connected to the control signal CTRL2. Additionally, the drain of n-channel transistor N0 is connected to VCC, the source is connected to node A, and the gate is connected to node Nin1. The drain of n-channel transistor N3 is connected to node A via resistor R0, the source is connected to ground, and the gate is connected to the output of NAND gate 13'. NAND gate 13' receives control signals CTRL1 and CTRL2 as inputs and provides its output to the gate of n-channel transistor N3.

[0091] The source of P-channel transistor P1 is connected to VCC, the drain is connected to node B, and the gate is connected to the complement of the first control signal CTRL1B. The source of p-channel transistor P2 is connected to node NX, the drain is connected to the drain of n-channel transistor N2, and the gate is connected to node B. The drain of N-channel transistor N2 is connected to the drain of p-channel transistor P1, the source is connected to ground, and the gate is connected to the complement of the first control signal CTRL1B.

[0092] The transmission gate is formed by a p-channel transistor P0 and an n-channel transistor N1. Specifically, the source of the p-channel transistor P0 is connected to node B, the drain is connected to node A, and the gate is connected to the control signal CTRL1, while the drain of the n-channel transistor N1 is connected to node B, the source is connected to node A, and the gate is connected to the complement of the first control signal CTRL1B.

[0093] Now, additional references Figure 13 Let's describe the operation of multiplexer 10". At time T0, in response to the rising of the first clock pulse CLK, the sampling phase of ADC 11 begins when control signal CTRL2 falls to logic low, while control signal CTRL1 remains at logic high. Note that ChSel <x>It rises to a higher logical level, while ChSelF remains at a lower logical level.

[0094] With CTRL2 low, p-channel transistor P3 is turned on, charging sampling capacitor C0 to the supply voltage VCC. With CTRL1 high, the transmission gate formed by p-channel transistor P0 and n-channel transistor N1 is turned off, n-channel transistor N2 is turned off, and p-channel transistor P1 is turned on to supply current to node B, keeping p-channel transistor P2 off.

[0095] Since CTRL2 is low and CTRL1 is high, the output of NAND gate 13' is logic high, thus turning on the n-channel transistor N3. Because the n-channel transistor N0 and resistor R0 form a source follower, the voltage at node A will rise to AnalogInput. <x>The voltage at node A is the difference between the voltage at node A and the threshold voltage Vth of the n-channel transistor N0. Therefore, the voltage at node A can be mathematically expressed as:

[0096] Va = VIN - Th N0

[0097] At time T1, control signal CTRL1 drops to low, while control signal CTRL2 rises to high, and again note that ChSel <x>Keeping it high, while ChSelF remains low. This turns on p-channel transistor P0 and n-channel transistor N1, and because it also turns off p-channel transistor P1, this allows the voltage at node B to be equal to the voltage at node A. Therefore, the voltage at node B can be mathematically expressed as:

[0098] Vb = Va = VIN - ThN0

[0099] Since CTRL1 is low, the n-channel transistor N2 is turned on. And because the p-channel transistor P2 is a source follower, it draws current from the output node OUT, causing the sampling capacitor C0 to discharge until the voltage at output node OUT becomes equal to the voltage at node B plus the threshold voltage of p-channel transistor P2. Mathematically, the voltage at output node OUT is equal to:

[0100] VOUT = Vb + ThP2 = VIN + |Th P2 |-Th N0

[0101] Due to process variations and the fact that transistors P2 and N0 are not ideal, this means that the threshold voltages of P2 and N0 are not equal. If the threshold voltage of N0 is greater than the threshold voltage of P2 by a significant margin, VOUT will be less than VIN. Conversely, VOUT can be slightly higher than VIN.

[0102] At time T2, CTRL2 remains high, while CTRL1 rises to high. Note that at this point, ChSel <x>The current remains high, while ChSelF rises high, thus closing switch Sx. Closing switch Sx causes current to flow from node Nin1 to the sampling capacitor C0, charging C0 to VIN. However, since the sampling capacitor C0 will charge to near VIN between times T1 and T2, the current flowing from node NX to the output node OUT will be very low, much smaller than the current typically flowing to the output node OUT in prior art designs.

[0103] The sampling phase ends at time T3.

[0104] like Figure 14 As shown, switches S0-S7 in any of the embodiments discussed can be implemented as transmission gates including p-channel transistor T1 and n-channel transistor T2.

[0105] The use of the above designs greatly reduces the current amplitude flowing from the analog input node of the selected channel to the sampling capacitor. Figures 15-16 The graph shown illustrates the charge magnitude from the analog input node of a selected channel to the sampling capacitor for different input voltages and for various designs. For example, as... Figure 15 As shown, without the above design, the charge amplitude from the analog input node would be 12.4 pC at an input voltage of 2.5 volts, but... Figure 2 , Figure 6 and Figure 10 In the case of the design, the charge amplitudes from the analog input nodes are 553.6 fC, 3.43 pC, and 975.6 fC, respectively. As another example, such as... Figure 1 As shown, without the above design, at an input voltage of 2.5V, the charge amplitude from the analog input node will be 12.4pC, but... Figure 4 , Figure 8 and Figure 12 In the case of the design, the charge amplitudes from the analog input nodes are 370.7fC, 1.109pC and 1.5pC, respectively.

[0106] Although this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure as disclosed herein. Therefore, the scope of this disclosure should be limited only by the appended claims.< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. An input circuit for a multiplexer, the input circuit comprising: First analog input node; Output node; A capacitive node is connected to the output node; A first control circuit, including a discharge circuit device, is configured to discharge the capacitive node to ground during a first time period that begins in response to the start of the sampling period of the analog-to-digital converter, wherein the input to the analog-to-digital converter is driven by the output from the multiplexer. A second control circuit, including a level shifting circuit, is configured to charge the capacitive node to the voltage at the first analog input node during a second time period that begins in response to the expiration of the first time period, wherein the level shifting circuit includes: A first p-channel transistor has a drain connected to ground, a source connected to a first node, and a gate connected to the first analog input node; and A second n-channel transistor has a source connected to the output node and a gate connected to the second node; and A first channel selection switch is closed to connect the first analog input node to the output node, thereby charging the capacitive node to the voltage at the first analog input node. The first channel selection switch is closed in response to the expiration of the second time period. At the end of the sampling period of the analog-to-digital converter, the first channel selection switch is turned off to disconnect the first analog input node from the output node. The input circuit further includes a control signal generator configured to: In response to the start of the sampling period of the analog-to-digital converter, assertion is made that the second control signal has reached the first time period; In response to the expiration of the first time period, the second control signal is de-asserted; In response to the expiration of the first time period, assert that the first control signal has reached the second time period; and In response to the expiration of the second time period, the first control signal is de-asserted, wherein the level shifting circuit device further includes: A first n-channel transistor has a drain connected to the second node, a source connected to ground, and a gate connected to the first control signal. A transmission gate is configured to connect the first node to the second node in response to an assertion of the first control signal; The second p-channel transistor has a drain connected to the drain of the second n-channel transistor, a source connected to the supply voltage, and a gate connected to the first control signal. The logic gate is configured to generate a logic signal based on the logic operation performed on the complement of the first control signal and the second control signal; A resistor having a first terminal connected to the first node; and The third p-channel transistor has a drain connected to a second terminal of the resistor, a source connected to the supply voltage, and a gate connected to the logic signal.

2. The input circuit according to claim 1, wherein the logic gate includes a NOR gate, the NOR gate receiving the complement of the first control signal and the second control signal as input, and generating the logic signal as output.

3. The input circuit of claim 1, wherein the discharge circuit device includes a third n-channel transistor having a drain connected to the output node, a source connected to ground, and a gate connected to the second control signal.

4. The input circuit according to claim 1, further comprising: Second analog input node; The second discharge circuit device is configured to discharge the capacitive node during the first time period; The second level shifting circuit is configured to charge the capacitive node to the voltage at the second analog input node during the second time period, the voltage at the second analog input node being modified by a mismatch voltage caused by a mismatch between a threshold voltage between a third transistor connected to the second analog input node and a fourth transistor connected to the output node; as well as A second channel selection switch is closed to connect the second analog input node to the output node, thereby charging the capacitive node to the voltage at the second analog input node. The second channel selection switch is closed in response to the expiration of the second time period. The second channel selection switch is turned off at the end of the sampling period of the analog-to-digital converter to disconnect the second analog input node from the output node; The first channel selection switch operates based on a first channel selection signal. If the first channel, including the analog input node, the discharge circuit device, the level shifting circuit device, and the first channel selection switch, is selected, the first channel selection signal is asserted upon the expiration of the second time period and deasserted at the end of the sampling period of the analog-to-digital converter. The second channel selection switch operates based on the second channel selection signal. If the second channel, which includes the second analog input node, the second discharge circuit device, the second level shift circuit device, and the second channel selection switch, is selected, the second channel selection signal is asserted in response to the expiration of the second time period and is deasserted at the end of the sampling period of the analog-to-digital converter.

5. An input circuit for a multiplexer, the input circuit comprising: First analog input node; Output node; A capacitive node is connected to the output node; A first control circuit, including a charging circuit device, is configured to charge the capacitive node to a supply voltage during a first time period that begins in response to the start of the sampling period of the analog-to-digital converter, wherein the input to the analog-to-digital converter is driven by the output from the multiplexer. A second control circuit, including a level shifting circuit, is configured to discharge the capacitive node to the voltage at the first analog input node during a second time period that begins in response to the expiration of the first time period, wherein the level shifting circuit includes: A first n-channel transistor has a drain connected to the supply voltage, a source connected to a first node, and a gate connected to the first analog input node; and A second p-channel transistor has a source connected to the output node and a gate connected to the second node; and A first channel selection switch is closed to connect the first analog input node to the output node, thereby charging the capacitive node to the voltage at the first analog input node. The first channel selection switch is closed in response to the expiration of the second time period. At the end of the sampling period of the analog-to-digital converter, the first channel selection switch is turned off to disconnect the first analog input node from the output node. The input circuit further includes a control signal generator configured to: In response to the start of the sampling period of the analog-to-digital converter, assertion is made that the second control signal has reached the first time period; In response to the expiration of the first time period, the second control signal is de-asserted; In response to the expiration of the first time period, assert that the first control signal has reached the second time period; and In response to the expiration of the second time period, the first control signal is de-asserted, wherein the level shifting circuit device further includes: A first p-channel transistor has a source connected to the supply voltage, a drain connected to the second node, and a gate connected to the complement of the first control signal. A transmission gate is configured to connect the first node to the second node in response to an assertion of the first control signal; The second n-channel transistor has a drain connected to the drain of the second p-channel transistor, a source connected to ground, and a gate connected to the complement of the first control signal. The logic gate is configured to generate a logic signal based on the logic operation performed on the second control signal and the first control signal; A resistor having a first terminal connected to the first node; and The third n-channel transistor has a drain connected to the second terminal of the resistor, a source connected to ground, and a gate connected to the logic signal.

6. The input circuit according to claim 5, wherein the logic gate includes a NAND gate, the NAND gate receiving the first control signal and the second control signal as inputs, and generating the logic signal as an output.

7. The input circuit of claim 5, wherein the charging circuit device includes a third p-channel transistor having a source connected to the supply voltage, a drain connected to the output node, and a gate connected to the second control signal.

8. The input circuit according to claim 5, further comprising: Second analog input node; The second charging circuit device is configured to charge the capacitive node to the supply voltage during the first time period; The second level shifting circuit is configured to discharge the capacitive node to the voltage at the second analog input node during the second time period, the voltage at the second analog input node being modified by a mismatch voltage caused by a mismatch between a threshold voltage between a third transistor connected to the second analog input node and a fourth transistor connected to the output node; as well as A second channel selection switch is closed to connect the second analog input node to the output node, thereby charging the capacitive node to the voltage at the second analog input node. The second channel selection switch is closed in response to the expiration of the second time period. The second channel selection switch is turned off at the end of the sampling period of the analog-to-digital converter to disconnect the second analog input node from the output node; The first channel selection switch operates based on a first channel selection signal. If the first channel, including the first analog input node, the charging circuit device, the level shifting circuit device, and the first channel selection switch, is selected, the first channel selection signal is asserted upon the expiration of the second time period and deasserted at the end of the sampling period of the analog-to-digital converter. The second channel selection switch operates based on the second channel selection signal. If the second channel, which includes the second analog input node, the second charging circuit device, the second level shifting circuit device, and the second channel selection switch, is selected, the second channel selection signal is asserted in response to the expiration of the second time period and is deasserted at the end of the sampling period of the analog-to-digital converter.

9. An input circuit for an analog-to-digital converter, the input circuit comprising: A first channel selection switch is closed to connect a first analog input node to an intermediate node, thereby charging the intermediate node to the voltage at the first analog input node. The first channel selection switch is closed during a first time period that begins in response to the start of the sampling period of the analog-to-digital converter. Capacitive nodes are connected to output nodes; A charging circuit device is connected between the first channel selection switch and the output node, and is configured to charge the capacitive node to the supply voltage according to a second control signal during the first time period. A level shifting circuit device is configured to, during a second time period that begins in response to the expiration of the first time period, discharge the capacitive node to the voltage at the intermediate node plus the threshold voltage of the first transistor of the level shifting circuit device according to a first control signal. as well as A selection switch is closed to connect the intermediate node to the output node, thereby discharging the output node to the voltage at the intermediate node. The selection switch is closed in response to the expiration of the second time period. When the sampling period of the analog-to-digital converter ends, the selection switch is turned off to disconnect the intermediate node from the output node.

10. The input circuit according to claim 9, further comprising: The control signal generator is configured as follows: In response to the start of the sampling period of the analog-to-digital converter, it is asserted that the second control signal has reached the first time period; In response to the end of the first time period, the second control signal is de-asserted; In response to the end of the first time period, assert that the first control signal has reached the second time period; and In response to the end of the second time period, the assertion of the first control signal is de-asserted.

11. The input circuit according to claim 10, The first transistor is located within the level shifting circuit device and includes a first p-channel transistor having a source connected to the output node and a gate connected to the intermediate node; and The level shifting circuit device further includes a first n-channel transistor having a drain connected to the drain of the first p-channel transistor, a source connected to ground, and a gate connected to the first control signal.

12. The input circuit of claim 11, wherein the charging circuit device includes a second p-channel transistor having a drain connected to the output node, a source connected to the supply voltage, and a gate connected to the second control signal.

13. The input circuit according to claim 9, further comprising: A second channel selection switch is closed to connect a second analog input node to the intermediate node, thereby discharging the intermediate node to the voltage at the second analog input node. The second channel selection switch is closed during the first time period. The first channel selection switch operates based on a first channel selection signal. If the first channel, including the first analog input node, the charging circuit device, the level shifting circuit device, and the first channel selection switch, is selected, the first channel selection signal is asserted upon the expiration of the second time period and deasserted at the end of the sampling period of the analog-to-digital converter. The second channel selection switch operates based on the second channel selection signal. If the second channel, which includes the second analog input node, the charging circuit device, the level shifting circuit device, and the second channel selection switch, is selected, the second channel selection signal is asserted in response to the expiration of the second time period and is deasserted at the end of the sampling period of the analog-to-digital converter.

14. An input circuit for an analog-to-digital converter, the input circuit comprising: A first channel selection switch is closed to connect a first analog input node to an intermediate node, thereby charging the intermediate node to the voltage at the first analog input node. The first channel selection switch is closed during a first time period that begins in response to the start of the sampling period of the analog-to-digital converter. Capacitive nodes are connected to output nodes; A first control circuit, including a discharge circuit device, is connected between the first channel selection switch and the output node, and is configured to discharge the capacitive node during the first time period. A second control circuit, including a level shifting circuit device, is configured to charge the capacitive node to the voltage at the intermediate node during a second time period that begins in response to the expiration of the first time period, wherein the level shifting circuit device includes: A first p-channel transistor has a source connected to a first node, a drain connected to ground, and a gate connected to the intermediate node; and A second n-channel transistor has a source connected to the output node and a gate connected to the second node; and A selection switch is closed to connect the intermediate node to the output node, thereby charging the output node to the voltage at the intermediate node. The selection switch is closed in response to the expiration of the second time period. At the end of the sampling period of the analog-to-digital converter, the selection switch is turned off to disconnect the intermediate node from the output node. The input circuit further includes a control signal generator, configured to: In response to the start of the sampling period of the analog-to-digital converter, it is asserted that the second control signal has reached the first time period; In response to the end of the first time period, the second control signal is de-asserted; In response to the end of the first time period, assert that the first control signal has reached the second time period; and In response to the end of the second time period, the first control signal is de-asserted, wherein the level shifting circuit device further includes: A first n-channel transistor has a drain connected to the second node, a source connected to ground, and a gate connected to the first control signal. The second p-channel transistor has a source connected to the supply voltage, a drain connected to the drain of the first n-channel transistor, and a gate connected to the first control signal. The logic gate is configured to generate a logic signal based on the logic operation performed on the complement of the first control signal and the second control signal; A resistor having a first terminal connected to the first node; A third p-channel transistor, the third p-channel transistor having a source connected to the supply voltage, a drain connected to the second terminal of the resistor, and a gate connected to the logic signal; and The transmission gate is configured to connect the first node to the second node in response to an assertion of the first control signal.

15. The input circuit of claim 14, wherein the discharge circuit device includes a third n-channel transistor having a drain connected to the output node, a source connected to ground, and a gate connected to the second control signal.

16. The input circuit of claim 14, wherein the logic gate includes a NOR gate, the NOR gate receiving the complement of the first control signal and the second control signal as inputs, and generating the logic signal as an output.

17. The input circuit according to claim 14, further comprising: A second channel selection switch is closed to connect a second analog input node to the intermediate node, thereby charging the intermediate node to the voltage at the second analog input node. The second channel selection switch is closed during the first time period. The first channel selection switch operates based on a first channel selection signal. If the first channel, including the first analog input node, the discharge circuit device, the level shifting circuit device, and the first channel selection switch, is selected, the first channel selection signal is asserted upon the expiration of the second time period and deasserted at the end of the sampling period of the analog-to-digital converter. The second channel selection switch operates based on the second channel selection signal. If the second channel, which includes the second analog input node, the discharge circuit device, the level shifting circuit device, and the second channel selection switch, is selected, the second channel selection signal is asserted in response to the expiration of the second time period and is deasserted at the end of the sampling period of the analog-to-digital converter.

18. An input circuit for an analog-to-digital converter, the input circuit comprising: A first channel selection switch is closed to connect a first analog input node to an intermediate node, thereby charging the intermediate node to the voltage at the first analog input node. The first channel selection switch is closed during a first time period that begins in response to the start of the sampling period of the analog-to-digital converter. Capacitive nodes are connected to output nodes; A first control circuit, including a charging circuit device, is connected between the first channel selection switch and the output node, and is configured to charge the capacitive node to the supply voltage during the first time period. A second control circuit, including a level shifting circuit device, is configured to discharge the capacitive node to the voltage at the intermediate node during a second time period that begins in response to the expiration of the first time period, wherein the level shifting circuit device includes: A first n-channel transistor has a drain connected to the supply voltage, a source connected to a first node, and a gate connected to the intermediate node; and A second p-channel transistor has a source connected to the output node and a gate connected to the second node; and A selection switch is closed to connect the intermediate node to the output node, thereby charging the output node to the voltage at the intermediate node. The selection switch is closed in response to the expiration of the second time period. At the end of the sampling period of the analog-to-digital converter, the selection switch is turned off to disconnect the intermediate node from the output node. The input circuit further includes a control signal generator, configured to: In response to the start of the sampling period of the analog-to-digital converter, it is asserted that the second control signal has reached the first time period; In response to the end of the first time period, the second control signal is de-asserted; In response to the end of the first time period, assert that the first control signal has reached the second time period; and In response to the end of the second time period, the first control signal is de-asserted, wherein the level shifting circuit device further includes: A transmission gate connects the first node to the second node in response to an assertion of the first control signal; A first p-channel transistor has a source connected to the supply voltage, a drain connected to the second node, and a gate connected to the complement of the first control signal. The second n-channel transistor has a drain connected to the drain of the second p-channel transistor, a source connected to ground, and a gate connected to the complement of the first control signal. A logic gate generates logic signals based on the logic operations performed on the first control signal and the second control signal; A resistor having a first terminal connected to the source of the first n-channel transistor; and The third n-channel transistor has a drain connected to the second terminal of the resistor, a source connected to ground, and a gate connected to the logic signal.

19. The input circuit of claim 18, wherein the logic gate includes a NAND gate, the NAND gate receiving inputs from the first control signal and the second control signal, and generating the logic signal as an output.

20. The input circuit of claim 18, wherein the charging circuit device includes a third p-channel transistor having a source connected to the supply voltage, a drain connected to the output node, and a gate connected to the second control signal.

21. The input circuit according to claim 18, further comprising: A second channel selection switch is closed during the first time period to connect the second analog input node to the intermediate node, thereby charging the intermediate node to the voltage at the second analog input node; The first channel selection switch operates based on a first channel selection signal. If the first channel, including the first analog input node, the charging circuit device, the level shifting circuit device, and the first channel selection switch, is selected, the first channel selection signal is asserted upon the expiration of the second time period and deasserted at the end of the sampling period of the analog-to-digital converter. The second channel selection switch operates based on the second channel selection signal. If the second channel, which includes the second analog input node, the charging circuit device, the level shifting circuit device, and the second channel selection switch, is selected, the second channel selection signal is asserted in response to the expiration of the second time period and is deasserted at the end of the sampling period of the analog-to-digital converter.

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