Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The method of forming the semiconductor device includes forming a sacrificial gate on an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed on the gate dielectric layer in the opening. A first protective layer is formed on the first work function layer in the opening. A first etching process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor device, and particularly to a method for forming a semiconductor device including a gate structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic products, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using lithography to pattern the various material layers to form circuit components and elements.

[0003] By continuously shrinking the smallest component size, the semiconductor industry has consistently improved the packing density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), enabling more components to be integrated into a given area. However, with the reduction in the smallest component size, other problems have also emerged that need to be addressed. Summary of the Invention

[0004] This invention provides a method for forming a semiconductor device, comprising: forming a sacrificial gate on an active region of a substrate; removing the sacrificial gate to form an opening; forming a gate dielectric layer on the sidewalls and bottom of the opening; forming a first work function layer on the gate dielectric layer in the opening; forming a first protective layer on the first work function layer in the opening; performing a first etching process to widen the upper portion of the opening; and filling the opening with a conductive material.

[0005] This invention provides a method for forming a semiconductor device, comprising: forming a sacrificial gate on an active region of a substrate; removing the sacrificial gate to form an opening; forming a gate dielectric layer on the sidewalls and bottom of the opening; forming a first work function layer on the gate dielectric layer in the opening; filling the opening with the sacrificial layer; etching back the sacrificial layer to expose the upper portion of the first work function layer in the opening; removing the upper portion of the first work function layer to expose the upper portion of the gate dielectric layer in the opening; removing the remaining portion of the sacrificial layer; and filling the opening with a conductive material.

[0006] This invention provides a semiconductor device, comprising: a gate stack located on an active region of a substrate, the gate stack comprising: a conductive material; a first protective layer lining the sidewalls and bottom surface of the conductive material; a second protective layer lining the sidewalls and bottom surface of the first protective layer, the first and second protective layers comprising different materials; an N-type work function layer lining the sidewalls and bottom surface of the second protective layer, the upper portion of the N-type work function layer being in solid contact with the upper portion of the first protective layer; and a gate dielectric layer lining the sidewalls and bottom surface of the N-type work function layer. Attached Figure Description

[0007] The embodiments of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0008] Figure 1 The following is a three-dimensional view of an example fin field-effect transistor (FinFET) according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 19A and Figure 19B This is a top view and cross-sectional schematic diagram showing an intermediate stage in the manufacture of a fin field-effect transistor device, according to some embodiments.

[0010] Figure 20P , Figure 20N , Figure 21P , Figure 21N , Figure 22P , Figure 22N , Figure 23P , Figure 23N , Figure 24P , Figure 24N , Figure 25P , Figure 25N , Figure 26P , Figure 26N , Figure 27P and Figure 27N This is a cross-sectional schematic diagram illustrating an intermediate stage in the fabrication of a gate structure, according to some embodiments.

[0011] Figure 28P , Figure 28N , Figure 29P , Figure 29N , Figure 30P , Figure 30N , Figure 31P , Figure 31N , Figure 32P , Figure 32N , Figure 33P , Figure 33N , Figure 34P , Figure 34N , Figure 35P and Figure 35N This is a cross-sectional schematic diagram illustrating an intermediate stage in the fabrication of a gate structure, according to some embodiments.

[0012] Figure 36P , Figure 36N , Figure 37P , Figure 37N , Figure 38P , Figure 38N , Figure 39P , Figure 39N , Figure 40P , Figure 40N , Figure 41P and Figure 41N This is a cross-sectional schematic diagram illustrating an intermediate stage in the fabrication of a gate structure, according to some embodiments.

[0013] Figure 42 This is a flowchart illustrating a method for forming a gate structure according to some embodiments.

[0014] Figure 43 This is a flowchart illustrating a method for forming a gate structure according to some embodiments.

[0015] Figure 44 This is a flowchart illustrating a method for forming a gate structure according to some embodiments.

[0016] Explanation of reference numerals in the attached figures:

[0017] 50: Base

[0018] 50N, 50P: Area

[0019] 51: Separator

[0020] 52: Fins

[0021] 54: Insulation materials

[0022] 56: Quarantine Zone

[0023] 58: Passage Area

[0024] 60: Dummy dielectric layer

[0025] 62: Dummy gate layer

[0026] 64: Masking layer

[0027] 72: Dummy gate

[0028] 74: Mask

[0029] 80: Gate sealing spacer

[0030] 82: Epitaxial source / drain region

[0031] 86: Gate spacer

[0032] 87: Contact Etching Stop Layer

[0033] 88: First interlayer dielectric

[0034] 89: Region

[0035] 90: Opening

[0036] 90N, 90P: Opening

[0037] 92: Gate dielectric layer

[0038] 92N, 92P: Gate dielectric layer

[0039] 94: Gate electrode

[0040] 94N, 94P: Gate electrode

[0041] 92N / 94N: Gate stacking

[0042] 92P / 94P: Gate stacking

[0043] 941: P-type work function layer

[0044] 942: N-type work function layer

[0045] 943: Protective layer

[0046] 944: Protective layer

[0047] 945: Adhesive layer

[0048] 946: Filler material

[0049] 947: Protective layer

[0050] 96: Gate mask

[0051] 108: Interlayer dielectric

[0052] 110: Gate contact

[0053] 112: Source / Drain Contact

[0054] 114: Silicide layer

[0055] 116, 118, 120: Etching process

[0056] 122: Sacrificial Layer

[0057] 124, 126: Etching process

[0058] 128: Hard Mask

[0059] 128A: First masking layer

[0060] 128B: Second masking layer

[0061] 130, 132: Opening

[0062] 134: Dielectric Materials

[0063] 136: Quarantine Zone

[0064] D1: Depth

[0065] D N D P :distance

[0066] H N H P :high

[0067] W1: First width

[0068] W2: Second width Detailed Implementation

[0069] Numerous embodiments or examples are disclosed below for implementing different elements of embodiments of the present invention. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the present invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0070] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0071] This invention describes gate structures for semiconductor devices and methods for forming them. The fin field-effect transistor devices discussed in the various embodiments herein are formed using a gate-last process. Some embodiments can be used for planar transistor devices, multiple-gate transistor devices, two-dimensional transistor devices, gate-all-around transistor devices, nanowire transistor devices, or other similar devices. The various embodiments discussed herein avoid damage to the gate structure during subsequent processes (e.g., gate dicing processes), for example, including the formation of seam void defects in the gate structure and oxidation of the work function layer of the gate structure. Therefore, the threshold voltage (V) due to oxidation of the work function layer of the gate structure can be reduced or avoided. t offset and gate resistance (R) G Increase. Furthermore, the critical voltage (V) can be reduced or avoided. t The various embodiments discussed herein can further reduce gate dielectric defects and avoid gate dielectric leakage and time-dependent gate dielectric breakdown (TDDB).

[0072] Figure 1 This is a three-dimensional view of an example fin field-effect transistor according to some embodiments. The fin field-effect transistor includes fins 52 located on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed on the substrate 50, and the fins 52 project upwards between adjacent isolation regions 56. Although the isolation regions 56 are described / shown as being separated by the substrate 50, the term "substrate" as used herein may refer only to a semiconductor substrate or a semiconductor substrate containing the isolation regions. Furthermore, although the fins 52 are shown as a single, continuous material as the substrate 50, the fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this document, fins 52 refer to the extension between adjacent isolation regions 56.

[0073] A gate dielectric layer 92 runs along the sidewall of fin 52 and is located above a top surface of fin 52, and a gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 82 are disposed on both sides of fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Section AA is along the longitudinal axis of the gate electrode 94, for example, in a direction perpendicular to the current direction between the source / drain regions 82 of the fin field-effect transistor. Section BB is perpendicular to section AA and runs along the longitudinal axis of fin 52, for example, in the current direction between the source / drain regions 82 of the fin field-effect transistor. Section CC is parallel to section AA and extends through the source / drain regions 82 of the fin field-effect transistor. For clarity of description, the following figures will refer to these reference sections.

[0074] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 19A and Figure 19B This is a top view and cross-sectional schematic diagram showing an intermediate stage in the manufacture of a fin field-effect transistor device, according to some embodiments. Figures 2 to 7 It is along Figure 1 The reference cross-section AA in the figure is drawn, except for the multiple fins / fin field-effect transistors in the figure. Figures 8A-14A , Figure 18A and Figure 19A It is along Figure 1 The reference section AA is drawn and Figures 8B-14B , Figure 18B and Figure 19B It is along Figure 1 The reference cross-section BB in the figure is drawn, except for the multiple fins / fin field-effect transistors in the figure. Figure 10C and Figure 10D It is along Figure 1 The reference cross-section CC is drawn in the figure, except for the multiple fin / fin field-effect transistors. Figures 15D-17D The top view is shown. Figures 15A-17A They are respectively along Figures 15D-17D The reference section AA is drawn in the middle. Figures 15B-17B They are respectively along Figures 15D-17D The reference section BB is drawn. Figures 15C-17C They are respectively along Figures 15D-17D The reference profile CC is drawn.

[0075] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or other similar substrate, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, this insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or other similar insulating layer. This insulating layer is placed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multi-layered or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0076] The substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, such as an n-type metal-oxide-semiconductor (NMOS) transistor, for example, an n-type fin field-effect transistor. Region 50P can be used to form a p-type device, such as a p-type metal-oxide-semiconductor (PMOS) transistor, for example, a p-type fin field-effect transistor. Region 50N may be physically separated from region 50P (as shown by separator 51), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between region 50N and region 50P.

[0077] exist Figure 3 In this process, fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be formed in the substrate 50 by etching trenches (not shown separately) into the substrate 50. The etching can be any suitable etching process, such as reactive ion etching (RIE), neutral particle beam etching (NBE), other similar processes, or combinations thereof. The etching process can be anisotropic.

[0078] Any suitable method can be used to form the fins. For example, one or more photolithography processes can be used to form the fins, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography with self-alignment processes, for example, to produce a smaller pattern spacing than that obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the sidewalls of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to form the fins.

[0079] exist Figure 4 An insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide (e.g., silicon oxide), a nitride, other similar materials, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flow-through chemical vapor deposition (FCVD) (e.g., chemical vapor deposition of a material in a remote plasma system followed by curing to convert it to another material, such as an oxide), other similar methods, or combinations thereof. Other insulating materials formed by any suitable process may also be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by a flow-through chemical vapor deposition process. An annealing process can be performed after the insulating material is formed. In one embodiment, the insulating material 54 is formed such that an excess of the insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, multiple layers may be used in some embodiments. For example, in some embodiments, a liner (not shown) may be formed first along the surfaces of the substrate 50 and the fins 52. Subsequently, a filler material, such as the materials discussed above, can be formed on the liner.

[0080] exist Figure 5In this process, an insulation material 54 removal process is performed to remove excess portion of the insulation material 54 on the fin 52. In some embodiments, planarization processes (e.g., chemical mechanical polishing), etch-back processes, combinations thereof, or other similar processes may be used. The fin 52 is exposed after the aforementioned planarization process, making the fin 52 flush with the top surface of the insulation material 54.

[0081] exist Figure 6 In the middle, insulating material 54 (see Figure 5 The insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The recess of the insulating material 54 causes the upper portion of the fin 52 in regions 50N and 50P to protrude between adjacent shallow trench isolation regions 56. The top surface of the shallow trench isolation region 56 may have a flat surface (as shown), a raised surface, a recessed surface (e.g., disc-shaped), or a combination thereof. The top surface of the shallow trench isolation region 56 can be formed as flat, raised, and / or recessed by appropriate etching. The isolation region 56 can be recessed using appropriate etching processes, such as etching processes selective for the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than etching the material of the fin 52). For example, appropriate etching processes (e.g., using diluted hydrofluoric acid (dHF)) can be used to remove chemical oxides.

[0082] exist Figures 2 to 6 The described process is merely one example of how fin 52 can be formed. In some embodiments, the fin can be formed using an epitaxial growth process. For example, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Furthermore, in some embodiments, heteroepitaxial structures can be used as fin 52. For example, a heteroepitaxial structure can be used... Figure 5 The fin 52 is recessed, and then a material different from the fin 52 is epitaxially grown on the recessed fin 52. In this embodiment, the fin 52 includes the recessed material and the epitaxial growth material disposed above the recessed material. In a further embodiment, a dielectric layer may be formed on the top surface of the substrate 50, and trenches through the dielectric layer may be etched to expose the underlying substrate 50. A heteroepitaxial structure may be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxial growth material may be in-situ doped during growth to omit previous or subsequent implantation, although in-situ doping and implantation doping may be used together.

[0083] Furthermore, it is advantageous that the material epitaxially grown in region 50N differs from the material in region 50P. In various embodiments, the upper portion of fin 52 may be formed of silicon germanium (Si... x Ge 1-x (where x can be between 0 and 1), silicon carbide, pure germanium or substantially pure germanium, group III-V semiconductor compounds, group II-VI semiconductor compounds, or similar materials. For example, materials that can form group III-V semiconductor compounds include (but are not limited to): InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, or similar materials.

[0084] exist Figure 6 In a further embodiment, suitable well regions may be formed in the substrate fin 52 and / or substrate 50. In some embodiments, a P-type well region may be formed in region 50N and an N-type well region may be formed in region 50P. In some embodiments, either a P-type or N-type well region may be formed in both region 50N and region 50P. In embodiments with different well region types, photoresist or other masks (not shown) may be used to implement different placement steps in region 50N and region 50P. For example, photoresist may be formed over the fin 52 and shallow trench isolation region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50. A spin-on technique may be used to form the photoresist, and it may be patterned using appropriate photolithography techniques. After the photoresist is patterned, n-type impurity placement is performed in region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being placed into region 50N. Type n impurities may be phosphorus, arsenic, antimony, or similar impurities, and their dose in the implanted area is less than or equal to 10. 15 cm -2 For example, about 10 12 cm -2 To about 10 15 cm -2 In some embodiments, the implantation energy of the n-type impurity can be from about 1 keV to about 10 keV. After implantation, the photoresist can be removed by, for example, a suitable ashing process followed by a wet cleaning process.

[0085] After the implantation in region 50P, photoresist is formed over the fins 52 and shallow trench isolation region 56 in region 50P. The photoresist is patterned to expose region 50N of the substrate 50. Spin coating can be used to form the photoresist, and appropriate photolithography techniques can be used to pattern it. After the photoresist is patterned, p-type impurity implantation is performed in region 50N, and the photoresist acts as a mask to substantially prevent the implantation of p-type impurities into region 50P. The p-type impurity can be boron, boron fluoride (BF2), indium, or similar impurities, with a implantation dose of less than or equal to 10-1 in the region. 15 cm -2 For example, about 10 12 cm -2 To about 10 15 cm -2 In some embodiments, the implantation energy of p-type impurities can be from about 1 keV to about 10 keV. After implantation, the photoresist can be removed by, for example, a suitable ashing process followed by a wet cleaning process.

[0086] After implantation in regions 50N and 50P, annealing can be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth to omit implantation, although in-situ doping and implantation doping can be used together.

[0087] exist Figure 7In this process, a dummy dielectric layer 60 is formed on the fin 52. For example, the dummy dielectric layer 60 may be silicon oxide, silicon nitride, or a combination thereof, and may be deposited or thermally grown using appropriate techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layer 60 and then planarized using a process, such as chemical mechanical polishing. The mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive material and may be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The deposition of the dummy gate layer 62 may be performed by physical vapor deposition, chemical vapor deposition, sputtering deposition, or other known techniques used in the art for depositing conductive materials. The dummy gate layer 62 may be formed of a material that has higher etch selectivity than the material of the shallow trench isolation region 56. For example, the mask layer 64 may include SiN, SiON, a combination thereof, or other similar materials. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across regions 50N and 50P. It should be noted that the dummy dielectric layer 60 shown only covering the fin 52 is for illustrative purposes. In some embodiments, the dummy dielectric layer 60 may be deposited to cover the shallow trench isolation region 56 and extend between the dummy gate layer 62 and the shallow trench isolation region 56.

[0088] Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 19A and Figure 19BThe various additional steps involved in manufacturing a fin field-effect transistor device are shown. Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 19A and Figure 19B The component shown in the diagram is in either region 50N or region 50P. For example, Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 19A and Figure 19BThe structure shown is applicable to both region 50N and region 50P. The structural differences between region 50N and region 50P (if any) will be described in the corresponding descriptions of the respective figures.

[0089] exist Figure 8A and Figure 8B In this process, appropriate photolithography and etching techniques can be used to pattern the mask layer 64 (see [link]). Figure 7 A mask 74 is formed. The pattern of the mask 74 can then be transferred to the dummy gate layer 62 to form the dummy gate 72. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by a suitable etching technique. The dummy gate 72 covers individual channel regions 58 of the fin 52. The pattern of the mask 74 can be used to separate each dummy gate 72 from adjacent dummy gate entities. The dummy gate 72 may also have a lengthwise direction substantially perpendicular to the lengthwise direction of the corresponding fin 52. As will be described in detail below, the dummy gate 72 is a sacrificial gate and will be subsequently replaced by a replacement gate. Therefore, the dummy gate 72 may also be referred to as a sacrificial gate. In other embodiments, some dummy gates 72 are not replaced and remain in the final structure of the fin field-effect transistor device.

[0090] exist Figure 8A and Figure 8B In a further embodiment, a gate sealing spacer 80 is formed on the exposed surfaces of the dummy gate 72, mask 74, and / or fin 52. The gate sealing spacer 80 can be formed by thermal oxidation or deposition followed by anisotropic etching. The gate sealing spacer 80 may comprise silicon oxide, silicon nitride, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbide (SiOCN), combinations thereof, or other similar materials. Lightly doped source / drain (LDD) regions (not specifically shown) may be implanted after the formation of the gate sealing spacer 80. In embodiments with different device types, similar to the above... Figure 6 The implantation discussed herein involves forming a mask (e.g., photoresist) over region 50N to expose region 50P, and implanting an appropriate type of impurity (e.g., p-type) onto the exposed fin 52 in region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity previously discussed, and the p-type impurity can be any p-type impurity previously discussed. The impurity dose of the lightly doped source / drain regions is approximately 10. 12 cm -2 To about 10 15 cm -2 In some embodiments, suitable impurities can be implanted using implantation energies of approximately 1 keV to approximately 10 keV. Annealing can be used to activate the implanted impurities.

[0091] exist Figure 9A and Figure 9B In this embodiment, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the shield 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching this insulating material. The insulating material of the gate spacer 86 may include silicon oxide, silicon nitride, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbide (SiOCN), combinations thereof, or other similar materials. In some embodiments, the gate spacer 86 may include multiple layers (not shown) comprising different materials.

[0092] exist Figure 10A and Figure 10B In this process, epitaxial source / drain regions 82 are formed in the fin 52 to apply stress in individual channel regions 58, thereby improving device performance. The epitaxial source / drain regions 82 are formed in the fin 52 such that each dummy gate 72 is disposed between each adjacent pair of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend to or penetrate the fin 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not cause a gate short circuit in the subsequently formed fin field-effect transistor device.

[0093] The epitaxial source / drain region 82 in region 50N can be formed by: masking region 50P and then etching the source / drain region of fin 52 in region 50N to form a groove in fin 52. The epitaxial source / drain region 82 of region 50N is then epitaxially grown in the groove. The epitaxial source / drain region 82 can comprise any suitable material, such as materials suitable for n-type fin field-effect transistors. For example, if fin 52 is silicon, the epitaxial source / drain region 82 in region 50N can comprise a material to which tensile strain is applied in channel region 58, such as silicon, silicon carbide (SiC), silicon carbide phosphide (SiCP), silicon phosphide (SiP), combinations thereof, or other similar materials. The epitaxial source / drain region 82 in region 50N may have a surface raised from the corresponding surface of fin 52 and may have facets.

[0094] The epitaxial source / drain region 82 in region 50P can be formed by: masking region 50N and then etching the source / drain region of fin 52 in region 50P to form a groove in fin 52. The epitaxial source / drain region 82 of region 50P is then epitaxially grown in the groove. The epitaxial source / drain region 82 can comprise any suitable material, such as materials suitable for p-type fin field-effect transistors. For example, if fin 52 is silicon, the epitaxial source / drain region 82 in region 50P can comprise a material to which compressive strain is applied in channel region 58, such as silicon germanium (SiGe), borosilicate germanium (SiGeB), germanium (Ge), germanium tin (GeSn), or other similar materials. The epitaxial source / drain region 82 in region 50P can also have a surface raised from the corresponding surface of fin 52 and can have facets.

[0095] Similar to the previously discussed process for forming lightly doped source / drain regions, epitaxial source / drain regions 82 and / or fins 52 can be implanted with dopants to form the source / drain regions, followed by annealing. The impurity concentration of the source / drain regions is approximately 10. 19 cm -3 To about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0096] Because epitaxial processes are used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 82 of the same fin field-effect transistor to merge, such as... Figure 10C As shown. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 82 remain separated, as shown. Figure 10D As shown.

[0097] exist Figure 11A and Figure 11B In the middle, the first interlayer dielectric (ILD) 88 was deposited. Figure 10A and Figure 10BThe structure shown is such that the first interlayer dielectric 88 can be formed of a dielectric material and can be deposited by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, flow-through chemical vapor deposition, a combination of the foregoing, or similar methods. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or similar materials. Other insulating materials formed by any suitable method may also be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first interlayer dielectric 88 and the epitaxial source / drain region 82, the mask 74, and the gate spacer 86. The contact etch stop layer 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, a combination thereof, or other similar materials, the etch rate of which is different from the etch rate of the material of the first interlayer dielectric 88 above it.

[0098] exist Figure 12A and Figure 12B In this process, a planarization process such as chemical mechanical polishing can be performed to make the top surface of the first interlayer dielectric 88 flush with the top surface of the dummy gate 72 or the mask 74 (see [link]). Figure 11A and Figure 11B The planarization process can also remove the mask 74 on the dummy gate 72, as well as a portion of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacers 80, the gate spacers 86, and the first interlayer dielectric 88 are flush with each other. Therefore, the top surface of the dummy gate 72 is exposed through the first interlayer dielectric 88. In some embodiments, the mask 74 may be left, in which case the planarization process makes the top surface of the first interlayer dielectric 88 flush with the top surface of the mask 74 (see [link to documentation]). Figure 11A and Figure 11B ).

[0099] exist Figure 13A and Figure 13BIn the etching step, the dummy gate 72 and the mask 74 (if present) are removed to form an opening 90. A portion of the dummy dielectric layer 60 in the opening 90 is also removed. In some embodiments, only the dummy gate 72 is removed, leaving the dummy dielectric layer 60 exposed by the opening 90. In some embodiments, the dummy dielectric layer 60 is removed from the opening 90 in a first region of the die (e.g., a core logic region) and retained in the opening 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the aforementioned etching process may include a dry etching process that uses reactive gases to selectively etch the dummy gate 72 without etching the first interlayer dielectric 88 or the gate spacer 86. Each opening 90 exposes a channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. When etching the dummy gate 72 during removal, the dummy dielectric layer 60 can be used as an etch stop layer. After removing the dummy gate 72, the dummy dielectric layer 60 can then be optionally removed.

[0100] exist Figure 14A and Figure 14B In this process, a gate dielectric layer 92 and a gate electrode 94 are formed as a replacement gate. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as a "gate stack". The gate stack can extend along the sidewalls and top surface of the channel region 58 of the fin 52. In some embodiments, the gate stack can be formed using the methods described below, and references are made to... Figure 20P , Figure 20N , Figure 21P , Figure 21N , Figure 22P , Figure 22N , Figure 23P , Figure 23N , Figure 24P , Figure 24N , Figure 25P , Figure 25N , Figure 26P , Figure 26N , Figure 27P and Figure 27N A detailed description of the method will be provided. In other embodiments, the gate stack can be formed using the method described below, and reference will be made to... Figure 28P , Figure 28N , Figure 29P , Figure 29N , Figure 30P , Figure 30N , Figure 31P , Figure 31N , Figure 32P , Figure 32N , Figure 33P , Figure 33N , Figure 34P , Figure 34N , Figure 35P and Figure 35N A detailed description of the method will be provided. In another embodiment, the gate stack can be formed using the method described below, and reference will be made to... Figure 36P , Figure 36N , Figure 37P , Figure 37N , Figure 38P , Figure 38N , Figure 39P , Figure 39N , Figure 40P , Figure 40N , Figure 41P and Figure 41N And will provide a detailed description of the method.

[0101] Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C and Figure 17D This illustrates the gate dicing process based on some implementations. Figures 15D-17D The top view is shown. Figures 15A-17A They are respectively along Figures 15D-17D The cross-section AA is shown. Figures 15B-17B They are respectively along Figures 15D-17D The cross-section BB is shown. Figures 15C-17C They are respectively along Figures 15D-17D The cross-section CC is shown. In Figure 15A , Figure 15B , Figure 15C and Figure 15DIn this process, a hard mask 128 is formed over the gate stack 92 / 94. In some embodiments, the hard mask 128 may comprise one or more layers of dielectric material, such as silicon oxide, titanium nitride, silicon nitride, silicon oxynitride, combinations thereof, or other similar materials, and may be deposited using chemical vapor deposition, atomic layer deposition, combinations thereof, or other similar processes. In some embodiments, the hard mask 128 may comprise one or more layers of dielectric material, such as silicon oxide, titanium nitride, silicon nitride, silicon oxynitride, combinations thereof, etc., and may be deposited using CVD, ALD, combinations thereof, etc. In one embodiment, the hard mask 128 includes: a first mask layer 128A comprising titanium nitride, and a second mask layer 128B comprising silicon nitride, the second mask layer 128B being formed on the first mask layer 128A. The hard mask 128 is patterned to form an opening 130 through the hard mask 128. In some embodiments, the hard mask 128 may be patterned using suitable photolithography and etching processes. The etching process may be a wet or dry etching process. The etching process can be an anisotropic etching process. In some embodiments, the opening 130 may have an elongated trench shape such that the length direction of each trench is substantially parallel to the length direction of the fin 52 and substantially perpendicular to the length direction of the gate stack 92 / 94.

[0102] exist Figure 16A , Figure 16B , Figure 16C and Figure 16DIn this process, a hard mask 128 is used to pattern the gate stack 92 / 94. In some embodiments, the hard mask 128 is used as an etching mask to pattern the gate stack 92 / 94 using one or more suitable etching processes. The etching process may include a wet etching process, a dry etching process, a combination of the foregoing, or a similar process. The etching process may be an isotropic etching process. In some embodiments, the etching process includes only a dry etching process. In other embodiments, the etching process includes a combination of both dry and wet etching processes. In some embodiments, when the etching process includes only a dry etching process, a wet cleaning process is performed after the etching process to remove etching residues. In some embodiments, a dry etching process may be performed using a mixture of etchants including Cl2, SiCl4, CH4, O2, CF4, BCl3, Ar, a combination of the foregoing, or other similar etchants. In some embodiments, a wet etching process may be performed using a mixture of HCl, H2O2, deionized water, a combination of the foregoing, or other similar etchants. In some embodiments, a wet cleaning process may be performed using deionized water, a mixture of deionized water and diluted HCl, or other similar etchants. In some embodiments, the gate electrode 94 of the gate stack 92 / 94 is removed by a dry etching process using a mixture of etchants including Cl2, SiCl4, O2, BCl3, combinations thereof, or other similar etchants. In some embodiments, the gate dielectric layer 92 of the gate stack 92 / 94 is removed by a dry etching process using a mixture of etchants including BCl3 or other similar etchants. A patterning process forms an opening 132 that extends through the gate stack 92 / 94 and into the isolation region 56. In some embodiments, the opening 132 has sloping sidewalls. In some embodiments, the top of the opening 132 has a first width W1 and the bottom of the opening 132 has a second width W2. In some embodiments, the first width W1 is greater than the second width W2. In some embodiments, the first width W1 is between about 14 nm and about 50 nm. In some embodiments, the second width W2 is between about 8 nm and about 30 nm. In some embodiments, the ratio W1 / W2 is between about 1.1 and about 1.4. In some embodiments, the opening 132 extends downward to a depth D1 from the topmost surface of the isolation region 56. In some embodiments, the depth D1 is about 20 nm to about 55 nm.

[0103] In some Figure 16A , Figure 16B , Figure 16C and Figure 16D In a further embodiment, the patterned gate stack 92 / 94 may be used to damage the etchant forming the opening 132. In some embodiments, etchant may penetrate from the sidewalls of the opening 132 into the patterned gate stack 92 / 94, and may damage the patterned gate stack 92 / 94. (Refer to...) Figures 20-41 and Figure 20N-Figure 41N By forming the gate stack 92 / 94 as described below, hole defects will not form in the gate stack 92 / 94, and the etchant of the gate cutting process will not penetrate into the hole defects and damage the gate stack 92 / 94.

[0104] exist Figure 17A , Figure 17B , Figure 17C and Figure 17D In the middle, dielectric material 134 is formed in opening 130 (see Figure 15A , Figure 15B , Figure 15C and Figure 15D ) and opening 132 (see Figure 16A , Figure 16B , Figure 16C and Figure 16D In some embodiments, the dielectric material 134 comprises silicon oxide, titanium nitride, silicon nitride, silicon oxynitride, combinations thereof, or other similar materials, and can be formed using chemical vapor deposition, atomic layer deposition, combinations thereof, or other similar processes. In some embodiments, the dielectric material 134 overfills the openings 130 and 132 such that a portion of the dielectric material 134 is disposed on the topmost surface of the hard mask 128.

[0105] exist Figure 18A and Figure 18B In the middle, a planarization process is performed to remove the hard mask 128 (see...). Figure 17A , Figure 17B , Figure 17C and Figure 17D ) and a portion of dielectric material 134 disposed on the top surface of the gate stack (see Figure 17A , Figure 17B , Figure 17C and Figure 17D In some embodiments, the planarization process may include a chemical mechanical polishing process, an etching process, a combination of the foregoing, or other similar processes. The remaining portion of the dielectric material 134 forms an isolation region 136, which separates and electrically isolates adjacent portions of the patterned gate stack 92 / 94. Figure 18A and Figure 18B In the illustrated embodiment, the partially patterned gate stack 92 / 94 overlaps with two fins of fin 52. In other embodiments, the partially patterned gate stack 92 / 94 may overlap with one or more fins of fin 52.

[0106] Figure 18A and Figure 18BIn a further embodiment, after performing a planarization process, a second interlayer dielectric 108 is deposited on the first interlayer dielectric 88 and the gate stack 92 / 94 (including the gate dielectric layer 92 and the corresponding gate electrode 94 above it). In some embodiments, the second interlayer dielectric 108 is a flowable film formed by flow chemical vapor deposition. In some embodiments, the second interlayer dielectric 108 is formed of a dielectric material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), combinations thereof, or similar materials, and can be deposited by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, combinations thereof, or similar methods. In some embodiments, before forming the second interlayer dielectric 108, the gate stack 92 / 94 is recessed such that a groove is formed directly above the gate stack 92 / 94 and between the two portions of the gate spacer 86. The gate mask 96 comprises one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, a combination thereof, or similar materials, which are filled into a recess and then planarized to remove excess dielectric material extending over the first interlayer dielectric 88. The gate contact 110 is subsequently formed (see...). Figure 19A and Figure 19B It passes through the gate shield 96 to contact the top surface of the corresponding recessed gate electrode 94.

[0107] exist Figure 19A and Figure 19BIn some embodiments, the gate contact 110 and the source / drain contact 112 are formed through the second interlayer dielectric 108 and the first interlayer dielectric 88. The opening for the source / drain contact 112 is formed through the first interlayer dielectric 88 and the second interlayer dielectric 108, and the opening for the gate contact 110 is formed through the second interlayer dielectric 108 and the gate mask 96. Suitable photolithography and etching techniques can be used to form the aforementioned openings. After forming the opening for the source / drain contact 112, a silicide layer 114 is formed through the opening for the source / drain contact 112. In some embodiments, a metal material is deposited in the opening for the source / drain contact 112. The metallic material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, combinations thereof, or other similar materials, and may be formed using physical vapor deposition, sputtering, combinations thereof, or other similar processes. An annealing process is then performed to form a silicide layer 114. In some embodiments where the epitaxial source / drain region 82 comprises silicon, the aforementioned annealing process causes the metallic material to react with the silicon to form a silicide of the metallic material at the interface between the metallic material and the epitaxial source / drain region 82. After forming the silicide layer 114, unreacted portions of the metallic material are removed using a suitable removal process. Subsequently, a liner (e.g., a diffusion barrier layer, an adhesive layer, or other layer) and a conductive material are formed in the openings for the source / drain contacts 112 and the openings for the gate contacts 110. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, or other similar materials. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, combinations thereof, or other similar materials. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the surface of the second interlayer dielectric 108. The remaining substrate and conductive material form source / drain contacts 112 and gate contacts 110 in the openings. The source / drain contacts 112 are physically and electrically coupled to the corresponding epitaxial source / drain regions 82, and the gate contacts 110 are physically and electrically coupled to the corresponding gate electrode 94. The source / drain contacts 112 and gate contacts 110 can be formed in different processes or in the same process. Although the shown source / drain contacts 112 and gate contacts 110 are formed in the same cross-section, it should be understood that the individual source / drain contacts 112 and gate contacts 110 can be formed in different cross-sections to avoid short circuits.

[0108] Figure 20P , Figure 20N , Figure 21P , Figure 21N , Figure 22P , Figure 22N , Figure 23P , Figure 23N , Figure 24P , Figure 24N , Figure 25P , Figure 25N , Figure 26P , Figure 26N , Figure 27P and Figure 27N This is a schematic cross-sectional view illustrating an intermediate stage in the fabrication of a gate stack, according to some embodiments. Figures 20-27 Area 50P is shown (see Figures 2-7 )middle Figure 14B Detailed view of area 89. Figures 20N-27N Area 50N is shown (see Figures 2-7 )middle Figure 14B Detailed view of area 89. Figure 20P and Figure 20N The opening 90 in region 50P is shown separately (see Figure 13B The opening 90P and the opening 90N in region 50N. The formation of the gate stack 92P / 94P (including the gate dielectric layer 92P and the corresponding gate electrode 94P above it) will be described in detail below. Figure 27P As shown, a gate stack 92N / 94N (including a gate dielectric layer 92N and a corresponding gate electrode 94N above it) is formed in the opening 90N.

[0109] exist Figure 20P and Figure 20NIn a further embodiment, a gate dielectric layer 92P is formed in an opening 90P in region 50P, and a gate dielectric layer 92N is formed in an opening 90N in region 50N. Gate dielectric layers 92P and 92N are compliantly deposited in openings 90P and 90N, for example, on the top surface and sidewalls of fin 52 and on the sidewalls of gate sealing spacer 80 / gate spacer 86. Gate dielectric layers 92P and 92N may also be formed on the top surface of the first interlayer dielectric layer 88. In some embodiments, each gate dielectric layer 92P and 92N may comprise a multilayer of silicon oxide, silicon nitride, or the aforementioned materials. In some embodiments, each gate dielectric layer 92N and 92P may comprise a high dielectric constant dielectric material, and in these embodiments, the dielectric constant of the gate dielectric layers 92P and 92N may be greater than about 7.0, and may comprise: metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, combinations thereof, or other similar materials. Methods for forming the gate dielectric layers 92P and 92N may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, combinations thereof, or similar methods. In embodiments where a portion of the dummy dielectric layer 60 is retained in the openings 90P and 90N, the gate dielectric layers 92P and 92N comprise the material of the dummy dielectric layer 60 (e.g., SiO2).

[0110] In some embodiments, the same dielectric material may be compliantly deposited simultaneously in openings 90P and 90N, forming gate dielectric layer 92P in region 50P and gate dielectric layer 92N in region 50N, respectively. In such embodiments, gate dielectric layers 92P and 92N comprise the same dielectric material. In other embodiments, the process for forming gate dielectric layer 92P in region 50P may be different from and not performed simultaneously with the process for forming gate dielectric layer 92N in region 50N. In such embodiments, gate dielectric layers 92P and 92N may comprise different dielectric materials. When using non-simultaneous processes, various masking steps can be used to mask and expose appropriate areas in regions 50P and 50N. In some embodiments, the thickness of gate dielectric layer 92P is approximately to approximately In some embodiments, the thickness of the gate dielectric layer 92N is approximately to approximately In some embodiments, when the thicknesses of the gate dielectric layer 92P and the gate dielectric layer 92N are less than approximately At this thickness, the smaller thickness results in high leakage current through the gate dielectric layers 92P and 92N. In some embodiments, when the thickness of the gate dielectric layers 92P and 92N is greater than... At that time, the greater thickness resulted in poorer device speed.

[0111] exist Figure 21P and Figure 21N In this embodiment, a P-type work function layer 941 is formed in the opening 90P of region 50P. In some embodiments, P-type work function material is formed in the openings 90P and 90N of both regions 50P and 50N. In such embodiments, the P-type work function material is then removed from region 50N, leaving only the P-type work function material in region 50P to form the P-type work function layer 941. In other embodiments, a masking layer is formed over region 50N, and the P-type work function material is formed in the opening 90P of region 50P. In such embodiments, after forming the P-type work function material in the opening 90P, the masking layer is removed. In some embodiments, the P-type work function layer 941 may include TiN, WN, TaN, Ru, Co, combinations thereof, multilayers of the aforementioned materials, or other similar materials, and may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, combinations thereof, or other similar processes. In some embodiments, the thickness of the P-type work function layer 941 is approximately to approximately In some embodiments, when the thickness of the P-type work function layer 941 is less than approximately At this time, this smaller thickness results in insufficient work function value of the device and uneven work function value and work function layer thickness across the entire wafer. In some embodiments, when the thickness of the P-type work function layer 941 is greater than approximately At this time, this larger thickness results in a high gate resistance (R). G ).

[0112] exist Figure 22P and Figure 22N In this process, an N-type work function layer 942 is formed in the opening 90P of region 50P and the opening 90N of region 50N. In some embodiments, the N-type work function layer 942 may include: Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, multilayers of the aforementioned materials, or other similar materials, and may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, combinations thereof, or other similar processes. In some embodiments, the thickness of the N-type work function layer 942 is approximately to approximately In some embodiments, when the thickness of the N-type work function layer 942 is less than approximately At this time, this smaller thickness results in insufficient work function value of the device and non-uniformity of work function value and work function layer thickness across the entire wafer. In some embodiments, when the thickness of the N-type work function layer 942 is greater than approximately At this time, this larger thickness results in a high gate resistance (R). G).

[0113] exist Figure 23P and Figure 23N In this process, a protective layer 943 is formed in the opening 90P of region 50P and the opening 90N of region 50N. In some embodiments, the protective layer 943 may include Ti, Si, TiN, TiSi, TiAl, SiC, TaN, combinations thereof, multilayers of the aforementioned materials, or other similar materials, and may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, combinations thereof, or other similar processes. In some embodiments, the protective layer 943 protects the N-type work function layer 942 from oxidation during subsequent process steps. In some embodiments, the thickness of the protective layer 943 is approximately to approximately In some embodiments, when the thickness of the protective layer 943 is less than approximately At this thickness, the smaller thickness cannot provide sufficient protection for the P-type work function layer 941 and the N-type work function layer 942, and results in poor overall wafer thickness uniformity. In some embodiments, when the thickness of the protective layer 943 is greater than approximately At this time, the greater thickness results in a higher gate resistance (R). G This leads to the decay of the effective work function.

[0114] In some embodiments where the widths of apertures 90P and 90N are from approximately 23 nm to approximately 300 nm, the aforementioned layers, such as gate dielectric layers 92P and 92N, P-type work function layer 941, N-type work function layer 942, and protective layer 943, may be non-compliantly deposited in apertures 90P and 90N. In some embodiments, the thickness of the layers disposed on the upper portions of the sidewalls of apertures 90P and 90N may be greater than the thickness of the layers disposed on the lower portions of the sidewalls of apertures 90P and 90N. This non-compliant deposition of the layers causes the upper portions of apertures 90P and 90N to narrow or pinch off. Narrowing of the upper portions of apertures 90P and 90N can prevent subsequent deposition of other layers in apertures 90P and 90N from completely filling apertures 90P and 90N. In some embodiments, due to the partial filling of apertures 90P and 90N, the resulting gate stack may contain via defects, thus adversely affecting the functionality of the gate stack. The etching process is described in more detail below to widen the upper portions of openings 90P and 90N, improve the filling properties of openings 90P and 90N, and reduce / avoid any gap defects.

[0115] exist Figure 24P and Figure 24NIn this process, an etching process (indicated by arrow 116) is performed to widen the upper portions of openings 90P and 90N. In some embodiments, the etching process 116 is a plasma process performed using plasma generated from a gas mixture, including Ar, He, H2, N2, CF4, Cl2, BCl3, combinations thereof, or other similar gases. In some embodiments, the etching process 116 is performed with a plasma power of approximately 200W to approximately 1400W. In some embodiments, the etching process 116 can be performed at a substrate bias of approximately 30V to approximately 250V. In some embodiments, the etching process 116 can be performed at a pressure of approximately 4mTorr to approximately 200mTorr. In some embodiments, the etching process 116 can be performed at a temperature of approximately 20°C to approximately 250°C. In some embodiments, the etching time for the etching process 116 is approximately 5s to 350s.

[0116] In some embodiments, etching process 116 removes a portion of the protective layer 943, the N-type work function layer 942, and / or the P-type work function layer 941 from the sidewalls of the upper portions of openings 90P and 90N to widen the upper portions of openings 90P and 90N. In some embodiments, the amount of material removed depends on the parameters of etching process 116 and can be adjusted by adjusting plasma power, substrate bias, pressure, temperature, etching time, and / or the plasma composition of etching process 116. In some embodiments, etching process 116 completely removes the protective layer 943 from the sidewalls of the upper portions of openings 90P and 90N. In other embodiments, in addition to completely removing the protective layer 943 from the sidewalls of the upper portions of openings 90P and 90N, etching process 116 also removes a portion of the P-type work function layer 941 from the sidewalls of the upper portion of opening 90N and removes a portion of the P-type work function layer 941 or a portion of the N-type work function layer 942 from the sidewalls of the upper portion of opening 90P.

[0117] In some embodiments, after etching process 116, the N-type work function layer 942 and the protective layer 943 have uneven thicknesses along the sidewalls of openings 90P and 90N. In some embodiments, the thickness of the protective layer 943 decreases as it extends away from the corresponding channel region 58 along the sidewalls of openings 90P and 90N. In some embodiments, the thickness of the N-type work function layer 942 decreases as it extends away from the corresponding channel region 58 along the sidewalls of openings 90P and 90N. In some embodiments, the N-type work function layer 942 may extend along the sidewalls of openings 90P and 90N to the top of openings 90P and 90N. In other embodiments, the N-type work function layer 942 may not reach the top of openings 90P and 90N and may partially liner the sidewalls of openings 90P and 90N.

[0118] exist Figure 25P and Figure 25N In the middle, after performing etching process 116 (see...) Figure 24P and Figure 24N The protective layer 944 is formed in the opening 90P of region 50P and the opening 90N of region 50N. In some embodiments, the protective layer 944 may be formed using materials and methods similar to those used for the protective layer 943 described above, and reference may be made to... Figure 23P and Figure 23N The description will not be repeated here. In some embodiments, protective layer 944 and protective layer 943 comprise the same material. In other embodiments, protective layer 944 and protective layer 943 comprise different materials. In some embodiments, protective layer 944 protects the exposed portions of the N-type work function layer 942 and / or the exposed portions of the P-type work function layer 941 from being picked up by O, C, and F during subsequent process steps. In some embodiments, the thickness of protective layer 944 is approximately to approximately In some embodiments, when the thickness of the protective layer 944 is less than approximately At this thickness, the smaller thickness cannot provide sufficient protection for the P-type work function layer 941 and the N-type work function layer 942, resulting in uneven thickness across the entire wafer. In some embodiments, when the thickness of the protective layer 944 is greater than approximately At this time, the greater thickness results in a higher gate resistance (R). G This leads to the decay of the effective work function.

[0119] exist Figure 26P and Figure 26N In this process, an adhesive layer 945 is formed in the opening 90P of region 50P and the opening 90N of region 50N. In some embodiments, the adhesive layer 945 may include Ti, TiN, Co, W, combinations thereof, multilayers of the aforementioned materials, or other similar materials, and may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, combinations thereof, or other similar processes. In some embodiments, the thickness of the adhesive layer 945 is approximately to approximately In some embodiments, when the thickness of adhesive layer 945 is less than approximately At this time, the relatively thin adhesive layer 945 may not completely cover the wafer and adversely affect the nucleation of the subsequently formed filler material 946. In some embodiments, when the thickness of the adhesive layer 945 is greater than approximately At this point, the greater thickness can lead to a higher gate resistance (R). GThen, a filler material 946 is formed in the opening 90P of region 50P and the opening 90N of region 50N. In some embodiments, the filler material 946 overfills the openings 90P and 90N, such that a portion of the filler material 946 extends along the top surface of the first interlayer dielectric 88. The filler material 946 may include: Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, the aforementioned alloys, combinations thereof, multilayers of the aforementioned materials, or other similar materials, and may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, combinations thereof, or other similar processes. (Referring to the above...) Figure 21P and Figure 21N As described above, by widening the openings 90P and 90N, the filling material 946 completely fills the openings 90P and 90N without forming any pore defects within the filling material 946.

[0120] By forming a filler material 946 free of pinhole defects, various problems caused by pinhole defects can be avoided. For example, problems caused by pinhole defects include high gate resistance (R0) due to air gaps within the filler material 946. G The device speed reduction caused by poor contact between the filler material 946 and other layers of the gate stack, and the gate resistance (R) caused by oxidation of the gate stack due to chemical / gas penetration into via defects during the subsequent gate dicing process. G The increase, as well as the work function and critical voltage (V) t )reduce.

[0121] Figure 27P and Figure 27NIn this process, after the filling material 946 is formed, a planarization process, such as chemical mechanical polishing, can be performed to remove excess portions of layers 92P, 92N, and 941-946, which are located above the top surface of the first interlayer dielectric 88. The remaining portion of the gate dielectric layer 92P within the opening 90P forms the gate dielectric 92P of the replacement gate stack of the fin field-effect transistor device obtained in region 50P. The remaining portion of layers 941-946 within the opening 90P forms the gate electrode 94P of the replacement gate stack of the fin field-effect transistor device obtained in region 50P. The gate electrode 94P and the corresponding gate dielectric 92P form the gate stack 92P / 94P in region 50P. The remaining portion of the gate dielectric layer 92N within the opening 90N forms the gate dielectric 92N of the replacement gate stack of the fin field-effect transistor device obtained in region 50N. The remaining portions of layers 942-946 within the opening 90N form the gate electrode 94N of the replacement gate stack of the fin field-effect transistor device obtained in region 50N. The gate electrode 94N and the corresponding gate dielectric 92N form the gate stack 92N / 94N in region 50N. In some embodiments, the remaining portion of the fill material 946 has a non-uniform width, such that the width of the remaining portion of the fill material 946 varies with the remaining portion of the fill material 946 from the top surface of the first interlayer dielectric 88 (see...). Figure 14B It extends toward the corresponding channel area 58 and decreases.

[0122] In some embodiments, after forming the gate stacks 92P / 94P and 92N / 94N, the gate stacks 92P / 94P and 92N / 94N can be patterned during the gate dicing process. In some embodiments, reference can be made to the above description and... Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C and Figure 17D The gate dicing process is then performed, which will not be described again here. (Refer to...) Figure 20P , Figure 20N , Figure 21P , Figure 21N , Figure 22P , Figure 22N , Figure 23P , Figure 23N , Figure 24P , Figure 24N , Figure 25P , Figure 25N , Figure 26P , Figure 26N , Figure 27P and Figure 27N By forming the gate stacks 92P / 94P and 92N / 94N as described above, via defects will not form in the gate stacks 92P / 94P and 92N / 94N, and the etchant from the gate dicing process will not penetrate into the via defects and damage the gate stacks 92P / 94P and 92N / 94N.

[0123] Figure 28P , Figure 28N , Figure 29P , Figure 29N , Figure 30P , Figure 30N , Figure 31P , Figure 31N , Figure 32P , Figure 32N , Figure 33P , Figure 33N , Figure 34P , Figure 34N , Figure 35P and Figure 35N This is a schematic cross-sectional view illustrating an intermediate stage in the fabrication of a gate stack, according to some embodiments. Figures 28-35 Area 50P is shown (see Figures 2-7 )middle Figure 14B Detailed view of area 89. Figure 28N-Figure 35N Area 50N is shown (see Figures 2-7 )middle Figure 14B A detailed view of region 89. The following will describe in detail the formation of gate stacks 92P / 94P (including gate dielectric 92P and corresponding gate electrodes 94P above) in the opening 90P of region 50P, and the formation of gate stacks 92N / 94N (including gate dielectric 92N and corresponding gate electrodes 94N above, such as...) Figure 35N (As shown) in the opening 90N in region 50N. In some embodiments, the following refers to Figure 28P , Figure 28N , Figure 29P , Figure 29N , Figure 30P , Figure 30N , Figure 31P , Figure 31N , Figure 32P , Figure 32N , Figure 33P , Figure 33N , Figure 34P , Figure 34N , Figure 35P and Figure 35N The described process steps are the same as those mentioned above. Figure 20P , Figure 20N , Figure 21P , Figure 21N , Figure 22P , Figure 22N , Figure 23P , Figure 23N , Figure 24P , Figure 24N , Figure 25P , Figure 25N , Figure 26P , Figure 26N , Figure 27P and Figure 27N The described process steps are similar, with the same parts marked with the same numerical symbols, and the same parts are not described again here.

[0124] exist Figure 28P and Figure 28N In the formation of the P-type work function layer 941 in the opening 90P of region 50P (as referred above) Figure 21P and Figure 21N After that, a protective layer 943 is formed in the opening 90P of region 50P and the opening 90N of region 50N (as described above). Figure 23P and Figure 23N (As mentioned above), it will not be repeated here.

[0125] exist Figure 29P and Figure 29N In this process, an etching process (indicated by arrow 118) is performed to widen the upper portions of openings 90P and 90N. In some embodiments, etching process 118 is the same as described above. Figure 24P and Figure 24N The etching process 116 is similar and will not be repeated here. In some embodiments, the etching process 118 removes a portion of the gate dielectric layer 92N, the P-type work function layer 941, or the protective layer 943 from the sidewalls of the upper portions of openings 90P and 90N to widen the upper portions of openings 90P and 90N. In some embodiments, the amount of material removed depends on the parameters of the etching process 118 and can be adjusted by adjusting the plasma power, substrate bias, pressure, temperature, etching time, and / or the plasma composition of the etching process 118. In some embodiments, the etching process 118 completely removes the protective layer 943 from the sidewalls of the upper portions of openings 90P and 90N. In other embodiments, in addition to completely removing the protective layer 943 from the sidewalls of the upper portions of openings 90P and 90N, the etching process 118 further removes a portion of the P-type work function layer 941 from the sidewalls of the upper portion of opening 90P and a portion of the gate dielectric layer 92N from the sidewalls of the upper portion of opening 90N.

[0126] In some embodiments, after etching process 118, the P-type work function layer 941 and the protective layer 943 have uneven thicknesses along the sidewalls of openings 90P and 90N. In some embodiments, the thickness of the protective layer 943 decreases as it extends away from the corresponding channel region 58 along the sidewalls of openings 90P and 90N. In some embodiments, the thickness of the P-type work function layer 941 decreases as it extends away from the corresponding channel region 58 along the sidewall of opening 90P. In some embodiments, the P-type work function layer 941 may extend along the sidewall of opening 90P all the way to the top of opening 90P. In other embodiments, the P-type work function layer 941 may not reach the top of opening 90P and may partially liner the sidewall of opening 90P.

[0127] exist Figure 30P and Figure 30N In the above reference Figure 22P and Figure 22N The N-type work function layer 942 is formed in the opening 90P of region 50P and the opening 90N of region 50N, which will not be described again here.

[0128] exist Figure 31P and Figure 31N In the above reference Figure 25P and Figure 25N The protective layer 944 is formed in the opening 90P of region 50P and the opening 90N of region 50N, which will not be described again here.

[0129] exist Figure 32P and Figure 32N In this process, another etching process (indicated by arrow 120) is performed to widen the upper portions of openings 90P and 90N. In some embodiments, etching process 120 is the same as described above. Figure 24P and Figure 24N The etching process 116 is similar and will not be repeated here. In some embodiments, etching process 120 removes a portion of the N-type work function layer 942 or a portion of the protective layer 944 from the sidewalls of the upper portions of openings 90P and 90N to widen the upper portions of openings 90P and 90N. In some embodiments, the amount of material removed depends on the parameters of etching process 120 and can be adjusted by adjusting plasma power, substrate bias, pressure, temperature, etching time, and / or the plasma composition of etching process 120. In some embodiments, etching process 120 completely removes the protective layer 944 from the sidewalls of the upper portions of openings 90P and 90N. In other embodiments, in addition to completely removing the protective layer 944 from the sidewalls of the upper portions of openings 90P and 90N, etching process 120 further removes a portion of the N-type work function layer 942 from the sidewalls of the upper portions of openings 90P and 90N.

[0130] In some embodiments, after etching process 120, the N-type work function layer 942 and the protective layer 944 have uneven thicknesses along the sidewalls of openings 90P and 90N. In some embodiments, the thickness of the protective layer 944 decreases as it extends away from the corresponding channel region 58 along the sidewalls of openings 90P and 90N. In some embodiments, the thickness of the N-type work function layer 942 decreases as it extends away from the corresponding channel region 58 along the sidewalls of openings 90P and 90N. In some embodiments, the N-type work function layer 942 may extend along the sidewalls of openings 90P and 90N to the top of openings 90P and 90N. In other embodiments, the N-type work function layer 942 may not reach the top of openings 90P and 90N and may partially liner the sidewalls of openings 90P and 90N.

[0131] exist Figure 33P and Figure 33N In this process, a protective layer 947 is formed in the opening 90P of region 50P and the opening 90N of region 50N. In some embodiments, the above-mentioned references can be used. Figure 23P and Figure 23N The protective layer 947 is formed using similar materials and methods to the protective layer 943, which will not be repeated here.

[0132] exist Figure 34P and Figure 34N In the process, an adhesive layer 945 is formed in the opening 90P of region 50P and the opening 90N of region 50N, as described above. Figure 26P and Figure 26N The above description will not be repeated here. Then, filling material 946 is formed in the opening 90P of region 50P and the opening 90N of region 50N, as described above. Figure 26P and Figure 26N As mentioned above, this will not be repeated here. (Refer to the above...) Figure 29P , Figure 29N , Figure 32P and Figure 32N As described above, by widening the openings 90P and 90N, the filling material 946 completely fills the openings 90P and 90N without forming any pore defects within the filling material 946 of the openings 90P and 90N.

[0133] Figure 35P and Figure 35NIn this process, after the filling material 946 is formed, a planarization process, such as chemical mechanical polishing, can be performed to remove excess portions of layers 92P, 92N, and 941-947, which are located above the top surface of the first interlayer dielectric 88. The remaining portion of the gate dielectric layer 92P within the opening 90P forms the gate dielectric 92P of the replacement gate stack of the fin field-effect transistor device obtained in region 50P. The remaining portion of layers 941-947 within the opening 90P forms the gate electrode 94P of the replacement gate stack of the fin field-effect transistor device obtained in region 50P. The gate electrode 94P and the corresponding gate dielectric 92P form the gate stack 92P / 94P in region 50P. The remaining portion of the gate dielectric layer 92N within the opening 90N forms the gate dielectric 92N of the replacement gate stack of the fin field-effect transistor device obtained in region 50N. The remaining portions of layers 942-947 within the opening 90N form the gate electrode 94N of the replacement gate stack for the fin field-effect transistor device obtained in region 50N. The gate electrode 94N and the corresponding gate dielectric 92N form the gate stack 92N / 94N in region 50N. In some embodiments, the remaining portion of the fill material 946 has a non-uniform width, such that the width of the remaining portion of the fill material 946 varies with the remaining portion of the fill material 946 from the topmost surface of the first interlayer dielectric 88 (see...). Figure 14B It extends toward the corresponding channel area 58 and decreases.

[0134] In some embodiments, after forming the gate stacks 92P / 94P and 92N / 94N, the gate stacks 92P / 94P and 92N / 94N can be patterned during the gate dicing process. In some embodiments, reference can be made to the above description and... Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C and Figure 17D The gate dicing process is then performed, which will not be described again here. (Refer to...) Figure 28P , Figure 28N , Figure 29P , Figure 29N , Figure 30P , Figure 30N , Figure 31P , Figure 31N , Figure 32P , Figure 32N , Figure 33P , Figure 33N , Figure 34P , Figure 34N , Figure 35P and Figure 35N By forming the gate stacks 92P / 94P and 92N / 94N as described above, via defects will not form in the gate stacks 92P / 94P and 92N / 94N, and the etchant from the gate dicing process will not penetrate into the via defects and damage the gate stacks 92P / 94P and 92N / 94N.

[0135] Figure 36P , Figure 36N , Figure 37P , Figure 37N , Figure 38P , Figure 38N , Figure 39P , Figure 39N , Figure 40P , Figure 40N , Figure 41P and Figure 41N This is a schematic cross-sectional view illustrating an intermediate stage in the fabrication of a gate stack, according to some embodiments. Figures 36P-41P Area 50P is shown (see Figures 2-7 )middle Figure 14B Detailed view of area 89. Figures 36N-41N Area 50N is shown (see Figures 2-7 )middle Figure 14B A detailed view of region 89. The formation of the gate stack 92P / 94P (including the gate dielectric layer 92P and the corresponding gate electrode 94P above it) will be described in detail below. Figure 41P As shown, in the opening 90P of region 50P, and forming gate stacks 92N / 94N (including gate dielectric layer 92N and corresponding gate electrode 94N above, as shown) Figure 41N (As shown) in the opening 90N in region 50N. In some embodiments, the following refers to Figure 36P , Figure 36N , Figure 37P , Figure 37N , Figure 38P , Figure 38N , Figure 39P , Figure 39N , Figure 40P , Figure 40N , Figure 41P and Figure 41N The described process steps are the same as those mentioned above. Figure 20P , Figure 20N , Figure 21P , Figure 21N , Figure 22P , Figure 22N , Figure 23P , Figure 23N , Figure 24P , Figure 24N , Figure 25P , Figure 25N , Figure 26P , Figure 26N , Figure 27P and Figure 27N The described process steps are similar, with the same parts marked with the same numerical symbols, and the same parts are not described again here.

[0136] Figure 36P and Figure 36N In the formation of the N-type work function layer 942, in the opening 90P of region 50P and the opening 90N of region 50N (as referred above) Figure 22P and Figure 22N Following the above, a sacrificial layer 122 is formed in the opening 90P of region 50P and the opening 90N of region 50N. In some embodiments, the sacrificial layer 122 overfills the openings 90P and 90N, such that a portion of the sacrificial layer 122 extends along the top surface of the first interlayer dielectric 88. In some embodiments, the sacrificial layer 122 may comprise an organic photosensitive cross-linking polymer material (e.g., an organic backside anti-reflective coating (BARC)), a photoresist, or other similar materials, and may be formed using a spin coating process or other similar processes. In some embodiments, an adhesion promoter (e.g., hexamethyl disilazane (HMDS)) and a hard mask layer (e.g., containing TiN) are formed prior to the formation of the sacrificial layer 122. In some embodiments, when the sacrificial layer 122 comprises an organic backside anti-reflective coating, the sacrificial layer 122 is formed using spin coating, followed by a baking process to remove the solvent. In some embodiments, the thickness of the sacrificial layer 122 is from about 300 nm to about 2000 nm.

[0137] exist Figure 37P and Figure 37N In this process, an etching process (indicated by arrow 124) is performed to etch back the sacrificial layer 122 beneath the top surface of the first interlayer dielectric 88. In some embodiments, the etching process 124 is a plasma process performed using plasma generated from a gas mixture, including H2, N2, combinations thereof, or other similar gases. In some embodiments, the etching process 124 is performed with a plasma power of approximately 20 W to approximately 300 W. In some embodiments, the etching process 124 can be performed at a substrate bias of approximately 25 V to approximately 150 V. In some embodiments, the etching process 124 can be performed at a pressure of approximately 8 mTorr to approximately 100 mTorr. In some embodiments, the etching process 124 can be performed at a temperature of approximately 20 °C to approximately 200 °C. In some embodiments, the etching process 124 is performed for an etching time of approximately 10 seconds to 400 seconds.

[0138] In some embodiments, the parameters of the etching process 124 can be adjusted to selectively etch the sacrificial layer 122 without significantly etching the N-type work function layer 942. In some embodiments, in region 50P, the top surface of the sacrificial layer 122 is recessed to a distance D from the top surface of the first interlayer dielectric 88. P In some embodiments, the distance D P The wavelength is approximately 32nm to approximately 80nm. In some embodiments, the distance D... P The height H of the opening is 90P. P Approximately 20% to approximately 75%. In some embodiments, in region 50N, the top surface of the sacrificial layer 122 is recessed to a distance D from the top surface of the first interlayer dielectric 88. N In some embodiments, the distance D N The wavelength is approximately 32nm to approximately 80nm. In some embodiments, the distance D... N The height H of the opening is 90N. N Approximately 20% to approximately 75%.

[0139] exist Figure 38P and Figure 38N In this process, an etching process (indicated by arrow 126) is performed to selectively remove portions of the P-type work function layer 941 and the N-type work function layer 942 to widen the upper portions of openings 90P and 90N and improve the filling properties of openings 90P and 90N. In some embodiments, the etching process 126 stops at the gate dielectric layer 92P when portions of the P-type work function layer 941 and the N-type work function layer 942 above the top surface of the recessed sacrificial layer 122 are completely removed. In some embodiments, after the etching process 126 is completed, the top surfaces of the P-type work function layer 941 and the N-type work function layer 942 are substantially flush with the top surface of the recessed sacrificial layer 122. In some embodiments, the etching process 126 is a wet etching process, which may be performed using a mixture containing HCl, H2O2, HF, NH4OH, H3PO4, deionized water, or other similar substances. Figure 38P and Figure 38N In the illustrated embodiment, etching process 126 can also remove a portion of the gate dielectric layer 92P, compared to Figure 37P and Figure 37N The corresponding surfaces shown alter the slope of the exposed surface of the gate dielectric layer 92P in openings 90P and 90N. In other embodiments, etching process 126 exhibits high selectivity for removing the P-type work function layer 941 and the N-type work function layer 942, while substantially not etching the gate dielectric layer 92P. In these embodiments, the slope of the exposed surface of the gate dielectric layer 92P in openings 90P and 90N remains substantially unchanged and is consistent with... Figure 37P and Figure 37N The corresponding surfaces shown are essentially the same.

[0140] In some embodiments, when the distance D N (D P The height H is less than the opening height of 90N (90P). N (H P At approximately 20% of the distance, this smaller distance is insufficient to widen the top of the opening 90N (90P) sufficiently to avoid problems associated with pore defects. In some embodiments, when the distance D... N (D P The height H is greater than the opening 90N (90P). N (H P At approximately 75% of its maximum, this large distance leads to a decline in the effective work function and a decrease in the critical voltage (V). t Increase, saturation current (I) sat This results in reduced performance and poorer device turn-on performance due to the reduction of the gate stack layers (e.g., the removal of portions of the P-type work function layer 941 and N-type work function layer 942).

[0141] exist Figure 39P and Figure 39N In the middle, remove the recessed sacrificial layer 122 (see Figure 38P and Figure 38N In some embodiments, the removal of the recessed sacrificial layer 122 may be performed using an ashing process followed by a wet cleaning process. In some embodiments, the ashing process is a plasma process performed using plasma generated from a gas mixture, including N2, H2, combinations thereof, or other similar gases. In some embodiments, when the ashing process is a plasma process, it is performed without any substrate bias. In some embodiments, when the ashing process is a plasma process, it is performed at a temperature between about 50°C and about 300°C. In some embodiments, a wet cleaning process may be performed using a mixture comprising deionized water, diluted hydrofluoric acid (dHF), combinations thereof, or other similar etchants.

[0142] exist Figure 40P and Figure 40N In the process, an adhesive layer 945 is formed in the opening 90P of region 50P and the opening 90N of region 50N, as described above. Figure 26P and Figure 26N The above description will not be repeated here. Then, filling material 946 is formed in the opening 90P of region 50P and the opening 90N of region 50N, as described above. Figure 26P and Figure 26N As mentioned above, this will not be repeated here. (Refer to the above...) Figure 38P and Figure 38NAs described above, by widening the openings 90P and 90N, the filling material 946 completely fills the openings 90P and 90N without forming any pore defects within the filling material 946 of the openings 90P and 90N.

[0143] Figure 41P and Figure 41N In this process, after the filling material 946 is formed, a planarization process, such as chemical mechanical polishing, can be performed to remove excess portions of layers 92P, 92N, 945, and 946, which are located above the top surface of the first interlayer dielectric 88. The remaining portion of the gate dielectric layer 92P within the opening 90P forms the gate dielectric 92P of the replacement gate stack of the fin field-effect transistor device obtained in region 50P. The remaining portions of layers 941, 942, 945, and 946 within the opening 90P form the gate electrode 94P of the replacement gate stack of the fin field-effect transistor device obtained in region 50P. The gate electrode 94P and the corresponding gate dielectric 92P form the gate stack 92P / 94P in region 50P. The remaining portion of the gate dielectric layer 92N within the opening 90N forms the gate dielectric 92N of the replacement gate stack of the fin field-effect transistor device obtained in region 50N. The remaining portions of layers 942, 945, and 946 within the opening 90N form the gate electrode 94N of the replacement gate stack of the fin field-effect transistor device obtained in region 50N. The gate electrode 94N and the corresponding gate dielectric 92N form the gate stack 92N / 94N in region 50N.

[0144] In some embodiments, after forming the gate stacks 92P / 94P and 92N / 94N, the gate stacks 92P / 94P and 92N / 94N can be patterned during the gate dicing process. In some embodiments, reference can be made to the above description and... Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C and Figure 17D The gate dicing process is then performed, which will not be described again here. (Refer to...) Figure 36P , Figure 36N , Figure 37P , Figure 37N , Figure 38P , Figure 38N , Figure 39P , Figure 39N , Figure 40P , Figure 40N , Figure 41P and Figure 41NBy forming the gate stacks 92P / 94P and 92N / 94N as described above, via defects will not form in the gate stacks 92P / 94P and 92N / 94N, and the etchant from the gate dicing process will not penetrate into the via defects and damage the gate stacks 92P / 94P and 92N / 94N.

[0145] Figure 42 This is a flowchart illustrating a method 4200 for forming a semiconductor device according to some embodiments. Method 4200 can be used to form a gate stack in both a p-type device region and an n-type device region of the semiconductor device. In some embodiments, when method 4200 forms a gate stack in the n-type device region of the semiconductor device, all process steps of method 4200 are performed. In some embodiments, when method 4200 forms a gate stack in the p-type device region of the semiconductor device, all process steps of method 4200 are performed except for step 4209. Method 4200 begins at step 4201, where a sacrificial gate (e.g., in...) is formed. Figure 8A and Figure 8B The gate 72 shown is on the substrate (e.g., in...) Figure 8A and Figure 8B On the active region of the substrate 50 shown above, as referenced above. Figure 8A and Figure 8B As described above. In step 4203, the sacrificial gate is removed to form an opening (e.g., in...). Figure 13A and Figure 13B The opening shown is 90 degrees, as referenced above. Figure 13A and Figure 13B As described above. In step 4205, a gate dielectric layer is formed (e.g., in...). Figure 20P The gate dielectric layer 92P shown is in the opening, as referenced above. Figure 20P As described above. In step 4207, a P-type work function layer is formed (e.g., in...). Figure 21P The P-type work function layer 941 shown is in the opening, as referenced above. Figure 21P In some embodiments, when method 4200 forms a gate stack in the p-type device region of the semiconductor device, step 4209 is omitted. In some embodiments, when method 4200 forms a gate stack in the n-type device region of the semiconductor device, step 4209 is performed, wherein the p-type work function layer is removed from the opening, as described above. Figure 21N As described above. In step 4211, an N-type work function layer is formed (e.g., in...). Figure 22P The N-type work function layer 942 shown is in the opening, as referenced above. Figure 22P As described above. In step 4213, a first protective layer is formed (e.g., in...). Figure 23P The protective layer 943 shown is in the opening, as referenced above. Figure 23PAs described above. In step 4215, an etching process is performed (e.g., in...). Figure 24P The etching process 116 shown above widens the upper portion of the opening, as referenced above. Figure 24P As described above. In step 4217, a second protective layer is formed (e.g., in...). Figure 25P The protective layer 944 shown is in the opening, as referenced above. Figure 25P As described above. In step 4219, a conductive material (e.g., in...) is used. Figure 26P The adhesive layer 945 and filler material 946 shown fill the opening, as described above. Figure 26P As described above. In step 4221, a gate dicing process is performed, as referred to above. Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C and Figure 17D As stated above.

[0146] Figure 43 This is a flowchart illustrating a method 4300 for forming a semiconductor device according to some embodiments. Method 4300 can be used to form a gate stack in both a p-type device region and an n-type device region of the semiconductor device. In some embodiments, when method 4300 forms a gate stack in the n-type device region of the semiconductor device, all process steps of method 4300 are performed. In some embodiments, when method 4300 forms a gate stack in the p-type device region of the semiconductor device, all process steps of method 4300 are performed except for step 4309. Method 4300 begins at step 4301, where a sacrificial gate (e.g., in...) is formed. Figure 8A and Figure 8B The gate 72 shown is on the substrate (e.g., in...) Figure 8A and Figure 8B On the active region of the substrate 50 shown above, as referenced above. Figure 8A and Figure 8B As described above. In step 4303, the sacrificial gate is removed to form an opening (e.g., in...). Figure 13A and Figure 13B The opening shown is 90 degrees, as referenced above. Figure 13A and Figure 13B As described above. In step 4305, a gate dielectric layer is formed (e.g., in...). Figure 20P The gate dielectric layer 92P shown is in the opening, as referenced above. Figure 20P As described above. In step 4307, a P-type work function layer is formed (e.g., in...). Figure 21PThe P-type work function layer 941 shown is in the opening, as referenced above. Figure 21P In some embodiments, when method 4300 forms a gate stack in the p-type device region of the semiconductor device, step 4309 is omitted. In some embodiments, when method 4300 forms a gate stack in the n-type device region of the semiconductor device, step 4309 is performed, wherein the p-type work function layer is removed from the opening, as described above. Figure 21N As described above. In step 4311, a first protective layer is formed (e.g., in...). Figure 28P The protective layer 943 shown is in the opening, as referenced above. Figure 28P As described above. In step 4313, a first etching process is performed (e.g., in...). Figure 29P The etching process 118 shown above widens the upper portion of the opening, as referenced above. Figure 29P As described above. In step 4315, an N-type work function layer is formed (e.g., in...). Figure 30P The N-type work function layer 942 shown is in the opening, as referenced above. Figure 30P As described above. In step 4317, a second protective layer is formed (e.g., in...). Figure 31P The protective layer 944 shown is in the opening, as referenced above. Figure 31P As described above. In step 4319, a second etching process is performed (e.g., in...). Figure 32P The etching process 120 shown above widens the upper portion of the opening, as referenced above. Figure 32P As described above. In step 4321, a third protective layer is formed (e.g., in...). Figure 33P The protective layer 947 shown is in the opening, as referenced above. Figure 33P As described above. In step 4323, a conductive material (e.g., in...) is used. Figure 34P The adhesive layer 945 and filler material 946 shown fill the opening, as described above. Figure 34P As described above. In step 4325, a gate dicing process is performed, as referred to above. Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C and Figure 17D As stated above.

[0147] Figure 44This is a flowchart illustrating a method 4400 for forming a semiconductor device according to some embodiments. Method 4400 can be used to form a gate stack in both a p-type device region and an n-type device region of the semiconductor device. In some embodiments, when method 4400 forms a gate stack in the n-type device region of the semiconductor device, all process steps of method 4400 are performed. In some embodiments, when method 4400 forms a gate stack in the p-type device region of the semiconductor device, all process steps of method 4400 are performed except for step 4409. Method 4400 begins at step 4401, where a sacrificial gate (e.g., in...) is formed. Figure 8A and Figure 8B The gate 72 shown is on the substrate (e.g., in...) Figure 8A and Figure 8B On the active region of the substrate 50 shown above, as referenced above. Figure 8A and Figure 8B As described above. In step 4403, the sacrificial gate is removed to form an opening (e.g., in...). Figure 13A and Figure 13B The opening shown is 90 degrees, as referenced above. Figure 13A and Figure 13B As described above. In step 4405, a gate dielectric layer is formed (e.g., in...). Figure 20P The gate dielectric layer 92P shown is in the opening, as referenced above. Figure 20P As described above. In step 4407, a P-type work function layer is formed (e.g., in...). Figure 21P The P-type work function layer 941 shown is in the opening, as referenced above. Figure 21P In some embodiments, when method 4400 forms a gate stack in the p-type device region of the semiconductor device, step 4409 is omitted. In some embodiments, when method 4400 forms a gate stack in the n-type device region of the semiconductor device, step 4409 is performed, wherein the p-type work function layer is removed from the opening, as described above. Figure 21N As described above. In step 4411, an N-type work function layer is formed (e.g., in...). Figure 22P The N-type work function layer 942 shown is in the opening, as referenced above. Figure 22P As described above. In step 4413, a sacrificial layer is formed (e.g., in...). Figure 36P The sacrificial layer 122 shown is in the opening, as referenced above. Figure 36P As described above. In step 4415, the sacrificial layer is etched back, as referred to above. Figure 37P As described above. In step 4417, a portion of the P-type work function layer and a portion of the N-type work function layer disposed above the remaining portion of the sacrificial layer are removed, as referred to above. Figure 38P As described above. In step 4419, the remaining portion of the sacrificial layer is removed, as referred to above. Figure 39PAs described above. In step 4421, a conductive material (e.g., in...) is used. Figure 40P The adhesive layer 945 and filler material 946 shown fill the opening, as described above. Figure 40P As described above. In step 4423, as referred to above. Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C and Figure 17D As stated above.

[0148] According to one embodiment, a method for forming a semiconductor device includes forming a sacrificial gate on an active region of a substrate; removing the sacrificial gate to form an opening; forming a gate dielectric layer on the sidewalls and bottom of the opening; forming a first work function layer on the gate dielectric layer in the opening; forming a first protective layer on the first work function layer in the opening; performing a first etching process to widen the upper portion of the opening; and filling the opening with a conductive material.

[0149] In some embodiments, the method of forming a semiconductor device further includes: forming a second work function layer between the gate dielectric layer and the first work function layer. In some embodiments, the method of forming a semiconductor device further includes: forming a second protective layer on the exposed surface of the gate dielectric layer before forming the first work function layer; and performing a second etching process after forming the second protective layer and before forming the first work function layer to widen the upper portion of the opening. In some embodiments, the method of forming a semiconductor device further includes: forming a second protective layer in the opening after performing a first etching process and before filling the opening with a conductive material. In some embodiments, the first etching process removes a portion of the first protective layer. In some embodiments, the first etching process further removes a portion of the first work function layer. In some embodiments, after removing a portion of the first protective layer, the thickness of an upper portion of the first protective layer becomes narrower.

[0150] According to another embodiment, a method for forming a semiconductor device includes forming a sacrificial gate on an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on the sidewalls and bottom of the opening. A first work function layer is formed on the gate dielectric layer within the opening. The opening is filled with the sacrificial layer. The sacrificial layer is etched back to expose the upper portion of the first work function layer within the opening. The upper portion of the first work function layer is removed to expose the upper portion of the gate dielectric layer within the opening. The remaining portion of the sacrificial layer is removed. The opening is filled with a conductive material.

[0151] In some embodiments, the method of forming a semiconductor device further includes: forming a second work function layer on the surface exposed by the gate dielectric layer before forming a first work function layer, wherein the first work function layer and the second work function layer are work function layers of different types. In some embodiments, the method of forming a semiconductor device further includes: removing a portion of the second work function layer between the upper portion of the gate dielectric layer and the upper portion of the first work function layer. In some embodiments, the first work function layer is an N-type work function layer, and the second work function layer is a P-type work function layer. In some embodiments, removing the upper portion of the first work function layer includes performing a wet etching process. In some embodiments, removing the remaining portion of the sacrificial layer includes performing a plasma process. In some embodiments, the method of forming a semiconductor device further includes: depositing a second work function layer on the surface exposed by the gate dielectric layer in an opening before forming the first work function layer; and removing the second work function layer from the opening before forming the first work function layer.

[0152] According to another embodiment, the semiconductor device includes a gate stack located on an active region of a substrate. The gate stack includes: a conductive material, a first protective layer lining the sidewalls and bottom surface of the conductive material, and a second protective layer lining the sidewalls and bottom surface of the first protective layer. The first and second protective layers comprise different materials. The gate stack also includes an N-type work function layer lining the sidewalls and bottom surface of the second protective layer. The upper portion of the N-type work function layer is in solid contact with the upper portion of the first protective layer. The gate stack also includes a gate dielectric layer lining the sidewalls and bottom surface of the N-type work function layer.

[0153] In some embodiments, the semiconductor device further includes a P-type work function layer located between the N-type work function layer and the gate dielectric layer. In some embodiments, the semiconductor device further includes a third protective layer located between the N-type and P-type work function layers, with the upper portion of the N-type work function layer in solid contact with the upper portion of the P-type work function layer. In some embodiments, the semiconductor device further includes a third protective layer located between the gate dielectric layer and the N-type work function layer, with the upper portion of the N-type work function layer in solid contact with the upper portion of the gate dielectric layer. In some embodiments, the topmost surface of the first protective layer is flush with the topmost surface of the conductive material. In some embodiments, the width of the second protective layer narrows as the second protective layer extends along the sidewall of the first protective layer away from the active region of the substrate.

[0154] According to another embodiment, a semiconductor device includes a gate stack located on an active region of a substrate. The gate stack includes a conductive material. The conductive material includes an upper portion having a first width and a lower portion having a second width. The first width is greater than the second width. An N-type work function layer and a P-type work function layer are lining the sidewalls and bottom surface of the lower portion of the conductive material. The N-type work function layer is located between the P-type work function layer and the lower portion of the conductive material. The top surfaces of the P-type and N-type work function layers are in solid contact with the bottom surface of the upper portion of the conductive material. A gate dielectric layer is lining the sidewalls and bottom surface of the lower portion of the conductive material and the sidewalls of the upper portion of the conductive material. The gate dielectric layer is in solid contact with the P-type work function layer and the sidewalls of the upper portion of the conductive material.

[0155] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the various aspects of the invention. Those skilled in the art will understand that they can readily utilize this invention as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not depart from the concept and scope of the invention, and that various changes, substitutions, and replacements can be made therein without departing from the concept and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: A sacrificial gate is formed on an active region of a substrate; Remove the sacrificial gate to form an opening; A gate dielectric layer is formed on the sidewall and bottom of the opening, wherein the thickness of the upper portion of the gate dielectric layer is greater than the thickness of the lower portion of the gate dielectric layer; A first work function layer is formed on the gate dielectric layer in the opening; A first protective layer is formed on the first work function layer in the opening, wherein the first protective layer covers the surface of the first work function layer outside the opening, and wherein the first protective layer partially fills the opening; After the first protective layer is formed, a first etching process is performed to widen an upper portion of the opening; as well as The opening is filled with a conductive material, wherein at least a portion of the first protective layer remains in the opening after the opening is filled with the conductive material.

2. The method of forming a semiconductor device as claimed in claim 1, further comprising forming a second work function layer between the gate dielectric layer and the first work function layer.

3. The method for forming a semiconductor device as claimed in claim 1, further comprising: Before forming the first work function layer, a second protective layer is formed on the exposed surface of the gate dielectric layer; as well as After the second protective layer is formed and before the first work function layer is formed, a second etching process is performed to widen the upper portion of the opening.

4. The method of forming a semiconductor device as claimed in claim 1, further comprising forming a second protective layer in the opening after performing the first etching process and before filling the opening with the conductive material.

5. The method of forming a semiconductor device as claimed in claim 1, wherein the first etching process removes a portion of the first protective layer.

6. The method of forming a semiconductor device as claimed in claim 5, wherein the first etching process further removes a portion of the first work function layer.

7. The method of forming a semiconductor device as claimed in claim 5, wherein after removing the portion of the first protective layer, the thickness of an upper portion of the first protective layer is narrowed.

8. A method for forming a semiconductor device, comprising: A sacrificial gate is formed on an active region of a substrate; Remove the sacrificial gate to form a first opening; A gate dielectric layer is formed on the sidewall and bottom of the first opening, wherein the thickness of the upper portion of the gate dielectric layer is greater than the thickness of the lower portion of the gate dielectric layer. A first work function layer is formed on the gate dielectric layer in the first opening; The first opening is filled with a sacrificial layer, wherein the width of the sacrificial layer increases as the sacrificial layer extends from a top of the first opening to a bottom of the first opening; The sacrificial layer is etched back to expose an upper portion of the first work function layer within the first opening; Remove the upper portion of the first work function layer to expose the upper portion of the gate dielectric layer within the first opening; Remove the remaining portion of the sacrifice layer; The first opening is filled with a conductive material; The gate dielectric layer, the first work function layer, and the conductive material are patterned to form a second opening, wherein the second opening includes a top having a first width and a bottom having a second width, wherein the first width is greater than the second width, and wherein the second opening extends through the gate dielectric layer, the first work function layer, and the conductive material; and The second opening is filled with a dielectric material, wherein the bottom surface of the gate dielectric layer is higher than the bottom surface of the dielectric material.

9. The method of forming a semiconductor device as claimed in claim 8, further comprising forming a second work function layer on the exposed surface of the gate dielectric layer before forming the first work function layer, wherein the first work function layer and the second work function layer are work function layers of different types.

10. The method of forming a semiconductor device as claimed in claim 9, further comprising removing a portion of the second work function layer between the upper portion of the gate dielectric layer and the upper portion of the first work function layer.

11. The method of forming a semiconductor device as claimed in claim 9, wherein the first work function layer is an N-type work function layer, and wherein the second work function layer is a P-type work function layer.

12. The method of forming a semiconductor device as claimed in claim 8, wherein removing the upper portion of the first work function layer comprises performing a wet etching process.

13. The method of forming a semiconductor device as claimed in claim 8, wherein removing the remaining portion of the sacrificial layer comprises performing a plasma process.

14. The method of forming a semiconductor device as claimed in claim 8, further comprising: Before forming the first work function layer, a second work function layer is deposited on the surface of the gate dielectric layer exposed in the first opening; as well as Before forming the first work function layer, the second work function layer is removed from the first opening.

15. A method for forming a semiconductor device, comprising: A sacrificial gate is formed on an active region of a substrate; The sacrificial gate is removed to form an opening that exposes the active region; A gate dielectric layer is deposited on the sidewalls and bottom of the opening, wherein the thickness of the upper portion of the gate dielectric layer is greater than the thickness of the lower portion of the gate dielectric layer; A first work function layer is deposited on the gate dielectric layer in the opening; A first protective layer is deposited on the first work function layer in the opening, wherein the first protective layer partially fills the opening; After the first protective layer is deposited, a portion of the first protective layer is removed to expose a first portion of the first work function layer deposited along the upper portion of the sidewall of the opening, wherein a second portion of the first work function layer deposited along the lower portion of the sidewall of the opening is covered by the remaining portion of the first protective layer. as well as The opening is filled with a conductive material, wherein after the opening is filled with the conductive material, the remaining portion of the first protective layer remains in the opening.

16. The method of forming a semiconductor device as claimed in claim 15, wherein removing the portion of the first protective layer includes performing an etching process on the first protective layer.

17. The method of forming a semiconductor device as claimed in claim 15, further comprising: Before depositing the first work function layer, a second protective layer is deposited on the gate dielectric layer in the opening; as well as Before depositing the first work function layer, a portion of the second protective layer is removed to expose a first portion of the gate dielectric layer deposited along the upper portion of the sidewall of the opening, wherein a second portion of the gate dielectric layer deposited along the lower portion of the sidewall of the opening is covered by the remainder of the second protective layer.

18. The method of forming a semiconductor device as claimed in claim 17, wherein removing the portion of the second protective layer includes performing an etching process on the second protective layer.

19. The method of forming a semiconductor device as claimed in claim 15, further comprising depositing a second protective layer on the first protective layer in the opening before filling the opening with the conductive material, the second protective layer being in contact with the first protective layer and the first work function layer.

20. The method of forming a semiconductor device as claimed in claim 15, further comprising depositing a second work function layer on the gate dielectric layer in the opening prior to depositing the first work function layer.

21. A semiconductor device, comprising: A gate stack, located on an active region of a substrate, the gate stack comprising: A conductive material; A first protective layer is applied to the sidewalls and bottom surface of the conductive material; A second protective layer is lining the sidewalls and bottom surface of the first protective layer, the first protective layer and the second protective layer comprising different materials; An N-type work function layer is lining the sidewalls and bottom surface of the second protective layer, with the upper portion of the N-type work function layer in solid contact with the upper portion of the first protective layer; and A gate dielectric layer is lining the sidewalls and bottom surface of the N-type work function layer, wherein the thickness of the upper portion of the gate dielectric layer is greater than the thickness of the lower portion of the gate dielectric layer.

22. The semiconductor device of claim 21, further comprising a P-type work function layer located between the N-type work function layer and the gate dielectric layer.

23. The semiconductor device of claim 22, further comprising a third protective layer located between the N-type work function layer and the P-type work function layer, wherein the upper portion of the N-type work function layer is in solid contact with the upper portion of the P-type work function layer.

24. The semiconductor device of claim 21, further comprising a third protective layer located between the gate dielectric layer and the N-type work function layer, wherein the upper portion of the N-type work function layer is in solid contact with the upper portion of the gate dielectric layer.

25. The semiconductor device of claim 21, wherein the topmost surface of the first protective layer is flush with the topmost surface of the conductive material.

26. The semiconductor device of claim 21, wherein the width of the second protective layer narrows as the second protective layer extends away from the active region of the substrate along the sidewall of the first protective layer.

27. The semiconductor device of claim 21, wherein the upper portion of the N-type work function layer is in solid contact with the upper portion of the gate dielectric layer.

28. A semiconductor device, comprising: A gate stack, located on an active region of a substrate, the gate stack comprising: A conductive material; A first protective layer is applied to the sidewalls and bottom surface of the conductive material; A second protective layer is applied to the sidewalls and bottom surface of the first protective layer; An N-type work function layer is lining the sidewalls and bottom surface of the second protective layer, with the upper portion of the N-type work function layer in solid contact with the upper portion of the first protective layer. A third protective layer is located on the sidewalls and bottom surface of the N-type work function layer; and A gate dielectric layer is lining the sidewalls and bottom surface of the third protective layer, the upper portion of the gate dielectric layer being in solid contact with the upper portion of the N-type work function layer, wherein the thickness of the upper portion of the gate dielectric layer is greater than the thickness of the lower portion of the gate dielectric layer.

29. The semiconductor device of claim 28, wherein in a cross-sectional view, the third protective layer completely covers the bottom of the N-type work function layer.

30. The semiconductor device of claim 29, wherein in the cross-sectional view, the second protective layer completely covers the bottom of the first protective layer.

31. The semiconductor device of claim 28, wherein the upper surface of the first protective layer is flush with the upper surface of the conductive material.

32. The semiconductor device of claim 31, wherein the upper surface of the first protective layer is flush with the upper surface of the N-type work function layer.

33. The semiconductor device of claim 28, wherein the upper surface of the first protective layer is flush with the upper surface of the gate dielectric layer.

34. The semiconductor device of claim 28, wherein the conductive material comprises a conductive adhesive layer and a conductive filler on the conductive adhesive layer.

35. The semiconductor device of claim 28, wherein, in a cross-sectional view, the N-type work function layer completely separates the third protective layer from the second protective layer and the first protective layer.

36. A semiconductor device, comprising: A gate stack, located on an active region of a substrate, the gate stack comprising: A conductive material includes an upper region and a lower region, wherein the width of the upper region is greater than the width of the lower region; An N-type work function layer is lining the sidewalls and bottom surface of the underlying portion of the conductive material; and A gate dielectric layer is lining the sidewalls and bottom surface of the N-type work function layer, the upper portion of the gate dielectric layer being in solid contact with the sidewall of the upper region of the conductive material, wherein the thickness of the upper portion of the gate dielectric layer is greater than the thickness of the lower portion of the gate dielectric layer.

37. The semiconductor device of claim 36, further comprising a P-type work function layer located between the N-type work function layer and the gate dielectric layer.

38. The semiconductor device of claim 36, wherein the conductive material comprises a conductive substrate and a filler material on the conductive substrate.

39. The semiconductor device of claim 38, wherein in a cross-sectional view, the conductive substrate is in solid contact with the uppermost surface of the N-type work function layer.

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