Semiconductor device package and method of manufacturing the same

Abstract

The present invention relates to a semiconductor device package and a method for manufacturing the same, the semiconductor device package comprising: an interconnect structure having a first portion and a second portion extending from the first portion, the second portion having a width smaller than that of the first portion; and a dielectric layer surrounding the interconnect structure, wherein the dielectric layer and the second portion of the interconnect structure define a space.

Description

Technical Field

[0001] Among other things, the present invention relates to semiconductor device packaging and methods for manufacturing the same. Background Technology

[0002] Semiconductor device packages may include semiconductor devices stacked on top of each other. Hybrid bonding techniques can be used to form semiconductor device packages, which may refer to bonding involving two or more materials (e.g., Cu-to-Cu bonding and dielectric-to-dielectric bonding). However, a mismatch in the coefficients of thermal expansion (CTE) of the two or more materials during or after thermal cycling can cause delamination problems (e.g., delamination occurs at the interface between two dielectric layers), which adversely affects the reliability or performance of the semiconductor device package. Summary of the Invention

[0003] According to some exemplary embodiments of this disclosure, a semiconductor device package includes an interconnect structure and a dielectric layer. The interconnect structure has a first portion and a second portion extending from the first portion. The second portion has a width smaller than that of the first portion. The dielectric layer surrounds the interconnect structure. The dielectric layer and the second portion of the interconnect structure define a space.

[0004] According to some exemplary embodiments of this disclosure, a semiconductor device package includes an interconnect structure and a dielectric layer. The interconnect structure has a first portion and a second portion disposed on the first portion. The dielectric layer exposes a portion of the upper surface of the first portion of the interconnect structure. The dielectric layer and the exposed portion of the upper surface of the first portion of the interconnect structure define a space.

[0005] According to some examples of embodiments of the present disclosure, a method of manufacturing a semiconductor device package includes: forming a first portion of an interconnect structure on a substrate; forming a second portion of the interconnect structure on the first portion; and forming a dielectric layer to surround the interconnect structure and define a space through the interconnect structure. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of the invention will be readily understood from the following detailed description. It should be noted that the various features may not be drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0008] Figure 1B Is it like this? Figure 1A An enlarged view of the connection structure shown.

[0009] Figure 1C Is it like this? Figure 1A An enlarged view of the connection structure shown.

[0010] Figure 1D Explained as follows Figure 1C The lattice orientation of the connection structure shown.

[0011] Figure 1E This is a cross-sectional view of a semiconductor device package according to some embodiments of the present invention.

[0012] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J , Figure 2K , Figure 2L , Figure 2M , Figure 2N , Figure 2O and Figure 2P The various stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are described.

[0013] Figure 3A This is a cross-sectional view of another semiconductor device according to some embodiments of the present invention.

[0014] Figure 3B Is it like this? Figure 3A An enlarged view of the connection structure shown.

[0015] Figure 3C Is it like this? Figure 3A An enlarged view of the connection structure shown.

[0016] Figure 3D Explained as follows Figure 3C The lattice orientation of the connection structure shown.

[0017] Figure 3E This is a cross-sectional view of another semiconductor device package according to some embodiments of the present invention.

[0018] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M , Figure 4N , Figure 4O and Figure 4PThe various stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are described.

[0019] Figure 5A This is a cross-sectional view of another connection structure according to some embodiments of the present invention.

[0020] Figure 5B This is a cross-sectional view of another connection structure according to some embodiments of the present invention.

[0021] Figure 5C This is a cross-sectional view of another connection structure according to some embodiments of the present invention.

[0022] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. The invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In this invention, references to the formation of a first feature on or over a second feature in the following description may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0024] Embodiments of the invention are described in detail below. However, it should be understood that the invention provides many applicable concepts that can be implemented in a wide variety of specific situations. The specific embodiments described are merely illustrative and do not limit the scope of the invention.

[0025] Figure 1A This is a cross-sectional view of a semiconductor device 1A according to some embodiments of the present invention.

[0026] refer to Figure 1A The semiconductor device 1A may include, for example, but not limited to, a microcontroller (MCU), a microprocessor (e.g., single-core or multi-core), a memory device, a memory controller, a chipset, a graphics device, a high-bandwidth memory (HBM), or an application-specific integrated circuit (ASIC).

[0027] The semiconductor device 1A may include a carrier 10a, some connection structures 1a and a dielectric layer 12.

[0028] The carrier 10a may contain semiconductor material, glass or other suitable material.

[0029] The carrier 10a may include a circuit electrically connected to the connection structure 1a (not in Figure 1A (As shown in the diagram). The carrier 10a may include a redistribution layer (RDL) structure electrically connected to the connection structure 1a (not shown in the diagram). Figure 1A (As shown in the diagram). The semiconductor substrate 10a may include conductive pads, traces, or vias electrically connected to the connection structure 1a (not shown in the diagram). Figure 1A (Intercourse).

[0030] The connection structure 1a may contain a conductive material, such as, but not limited to, copper (Cu), gold (Au), aluminum (Al), or other suitable materials.

[0031] The connection structure 1a may be surrounded by the dielectric layer 12.

[0032] The connection structure 1a may be covered by the dielectric layer 12. The connection structure 1a may be partially covered by the dielectric layer 12.

[0033] Connection structure 1a can be embedded within dielectric layer 12. Connection structures 1a can be separated from each other or spaced apart. Connection structure 1a can be separated from another connection structure 1a at a certain distance. Connection structures 1a can be separated or spaced apart through dielectric layer 12.

[0034] The connecting structure 1a may include two parts 14a and 14b. Part 14a may be formed or disposed on the carrier 10a. Part 14b may be formed or disposed on part 14a. Parts 14a and 14b may have different widths. Part 14a may have a width greater than that of part 14b. Part 14a may also be referred to as "first part 14a". Part 14b may also be referred to as "second part 14a".

[0035] Part 14a may include the upper surface (not in Figure 1A (indicated in the middle), lower surface (not in) Figure 1A (represented in the middle) and the transverse surface extending between the upper and lower surfaces (not in the middle) Figure 1A (as indicated in the diagram). The lower surface of portion 14a may be in direct contact with the carrier 10a. The lateral surface of portion 14a may be in direct contact with the dielectric layer 12. The upper surface of portion 14a may be in direct contact with portion 14b. The upper surface of portion 14a may be exposed. The upper surface of portion 14a may be in direct contact with the dielectric layer 12.

[0036] Part 14b may include the upper surface (not in) Figure 1A (indicated in the middle), lower surface (not in) Figure 1A (represented in the middle) and the transverse surface extending between the upper and lower surfaces (not in the middle) Figure 1A(as indicated in the diagram). The lower surface of portion 14b may be in direct contact with portion 14a. The lateral surface of portion 14b may be separated from or spaced apart from the dielectric layer 12 by space 18. The lateral surface of portion 14b may be exposed. The lateral surface of portion 14b may be exposed to space 18.

[0037] Figure 1B Is it like this? Figure 1A An enlarged view of the connection structure 1a shown.

[0038] refer to Figure 1B The connecting structure 1a may comprise two parts 14a and 14b. Part 14a has a width W1, and part 14b has a width W2. Width W1 may be greater than width W2.

[0039] Part 14a may include interconnect layers 14a1, 14a2, and 14a3. Interconnect layer 14a2 may also be referred to as "first interconnect layer 14a2". Interconnect layer 14a3 may also be referred to as "second interconnect layer 14a3".

[0040] Part 14b may contain interconnect layers 14b1, 14b2, and 14b3. Interconnect layer 14b2 may also be referred to as "third interconnect layer 14b2". Interconnect layer 14b3 may also be referred to as "fourth interconnect layer 14b3". Interconnect layer 14b1 may also be referred to as "fifth interconnect layer 14b1".

[0041] Each of the interconnect layers 14a1, 14a2, 14a3, 14b1, 14b2 and 14b3 may contain, for example but not limited to, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W) or other suitable materials (e.g., metallic, alloy or non-metallic conductive materials).

[0042] Part of 14b can be embedded in part 14a. For example, part of interconnect layer 14b3 can be embedded in part 14a.

[0043] Interconnect layer 14a1 may have a rectangular or rectangular-like outline. Interconnect layer 14a1 may have a circular or circular-like outline.

[0044] Interconnect layer 14a1 may surround interconnect layer 14b3. Interconnect layer 14a1 may enclose interconnect layer 14b3.

[0045] Interconnect layer 14a1 may be exposed to space 18. Interconnect layer 14a1 may be exposed to air in space 18. Interconnect layer 14a1 may be covered by dielectric layer 12. Interconnect layer 14a1 may be in direct contact with dielectric layer 12.

[0046] Interconnect layer 14a2 may have a U-shaped or U-like structure. Interconnect layer 14a2 may contain a cup or cup-like structure. Interconnect layer 14a2 may surround interconnect layer 14a1. Interconnect layer 14a2 may enclose interconnect layer 14a1. Interconnect layer 14a2 may be in direct contact with interconnect layer 14a1. Interconnect layer 14a2 may be in direct contact with dielectric layer 12. Interconnect layer 14a2 may be covered by dielectric layer 12. Interconnect layer 14a2 may be disposed between interconnect layer 14a1 and interconnect layer 14a3.

[0047] Interconnect layer 14a3 may have a U-shaped or U-like structure. Interconnect layer 14a3 may contain a cup or cup-like structure. Interconnect layer 14a3 may surround interconnect layer 14a1. Interconnect layer 14a3 may surround interconnect layer 14a2. Interconnect layer 14a3 may enclose interconnect layer 14a1. Interconnect layer 14a3 may enclose interconnect layer 14a2. Interconnect layer 14a3 may be in direct contact with interconnect layer 14a2. Interconnect layer 14a3 may be in direct contact with dielectric layer 12. Interconnect layer 14a3 may be in direct contact with carrier 10a. Interconnect layer 14a3 may be covered by dielectric layer 12. Interconnect layer 14a3 may be disposed between interconnect layer 14a2 and dielectric layer 12.

[0048] Interconnect layer 14b2 may be formed or disposed on interconnect layer 14b3. Interconnect layer 14b1 may be formed or disposed on interconnect layer 14b2. Interconnect layer 14b1 may have substantially the same width as interconnect layer 14b2. Interconnect layer 14b1 may have substantially the same width as interconnect layer 14b3.

[0049] A portion S11 of the upper surface S1 of interconnect layer 14a1 can be exposed through dielectric layer 12. A portion S11 of the upper surface S1 of interconnect layer 14a1 can be exposed to space 18. A portion S12 of the upper surface S1 of interconnect layer 14a1 can be covered by dielectric layer 12. A portion S12 of the upper surface S1 of interconnect layer 14a1 can be in direct contact with dielectric layer 12.

[0050] The lateral surface of interconnect layer 14b2 can be exposed to space 18. The lateral surface of interconnect layer 14b2 can be in direct contact with the air in space 18. The lateral surface of interconnect layer 14b1 can be exposed to space 18. The lateral surface of interconnect layer 14b1 can be in direct contact with the air in space 18.

[0051] Space 18 can be a vacuum. Air may be present in space 18. Space 18 may be defined or surrounded by a portion S11 of the upper surface S1 of interconnect layer 14a1, the lateral surfaces of interconnect layer 14b1, interconnect layer 14b2, and dielectric layer 12. The boundary of space 18 may be formed or defined by a portion S11 of the upper surface S1 of interconnect layer 14a1, the lateral surfaces of interconnect layer 14b1, interconnect layer 14b2, and dielectric layer 12.

[0052] Figure 1C Is it like this? Figure 1A An enlarged view of the connection structure 1a shown.

[0053] refer to Figure 1C The connection structure 1a is similar to that in the reference. Figure 1B The connection structure 1a described and illustrated differs in that interconnect layer 14b3 may be surrounded by interconnect layer 14a1. The entire interconnect layer 14b3 may be surrounded by interconnect layer 14a1. Interconnect layer 14b3 may be enclosed by interconnect layer 14a1. The entire interconnect layer 14b3 may be enclosed by interconnect layer 14a1. Interconnect layer 14b3 may be embedded within interconnect layer 14a1. The entire interconnect layer 14b3 may be embedded within interconnect layer 14a1. The upper surface of interconnect layer 14a1 may be substantially coplanar with the upper surface of interconnect layer 14b3.

[0054] Figure 1D Explained as follows Figure 1C The lattice orientation of the connection structure shown.

[0055] refer to Figure 1D The interconnect layer 14b1 may have a crystal structure. The interconnect layer 14b1 may have a crystal orientation or lattice orientation as indicated by arrow D1. The crystal orientation or lattice orientation D1 may include the orientation of (111) (Miller index).

[0056] Figure 1E This is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present invention.

[0057] refer to Figure 1E The semiconductor device package 1 may include two semiconductor devices 1A and 1B. Semiconductor device 1A may include multiple connection structures 1a on carrier 10a. Semiconductor device 1B may include multiple connection structures 1b on carrier 10b.

[0058] Semiconductor device 1B may be the same as or similar to semiconductor device 1A. Semiconductor device 1B may be different from semiconductor device 1A.

[0059] Connection structure 1b may be the same as or similar to connection structure 1a. Connection structure 1b may also be different from connection structure 1a.

[0060] Hybrid bonding technology can be used to form a semiconductor device package 1. The semiconductor device package 1 can be formed by heating and compression operations. Hybrid bonding can refer to bonding involving two or more materials (e.g., metal-to-metal bonding and dielectric-to-dielectric bonding). An interconnect layer (e.g., interconnect layer 14b1) of connection structure 1a can be bonded to an interconnect layer (e.g., interconnect layer 14b1) of connection structure 1b. A dielectric layer 12 of connection structure 1a can be bonded to a dielectric layer 12 of connection structure 1b.

[0061] Semiconductor device 1A may include having, for example Figure 1D The interconnect structure 1a shows the lattice orientation. The semiconductor device 1B may include an interconnect structure with the lattice orientation shown. Figure 1D The interconnect structure 1b is shown with a lattice orientation. The bonding between the interconnect layer 14b1 of semiconductor device 1A and the interconnect layer 14b1 of semiconductor device 1B can be performed or achieved at a relatively low temperature because of their lattice orientation (e.g., (111) orientation). In other words, relatively little heat is required to bond the interconnect layer 14b1 of semiconductor device 1A to the interconnect layer 14b1 of semiconductor device 1B.

[0062] Interconnect layer 14b, which has a relatively large coefficient of thermal expansion (CTE) compared to dielectric layer 12, can be positioned away from dielectric layer 12 via space 18. Space 18 can act as a buffer, so that reliability problems (e.g., delamination problems) caused by CTE mismatch during or after thermal cycling can be mitigated or alleviated.

[0063] For example, the tensile stress TS that can be generated by heating and compression operations may remain in the dielectric layer 12 after the heating and compression operations. The residual tensile stress TS can peel off the upper dielectric layer 12 from the lower dielectric layer 12. However, the interconnect layer 14a, which has a relatively large width compared to the interconnect layer 14b, can act as a support structure that can resist the tensile stress TS. In other words, delamination that may occur or appear at the interface (or boundary) between the upper and lower dielectric layers 12 can be avoided.

[0064] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J , Figure 2K , Figure 2L , Figure 2M , Figure 2N , Figure 2O and Figure 2PThe various stages of a method for manufacturing a semiconductor device package 1 according to some embodiments of this application are described.

[0065] refer to Figure 2A The dielectric layer 12a may be formed or deposited on the carrier 10a. The dielectric layer 12a may be formed by, for example but not limited to, sputtering, deposition (e.g., chemical vapor deposition (CVD)) or other suitable techniques. The dielectric layer 12a may comprise, for example but not limited to, silicon oxide or other suitable materials.

[0066] refer to Figure 2B A patterned mask 13a can be formed on the dielectric layer 12a to expose the dielectric layer 12a. The patterned mask (or photomask) 13a may contain, for example, but not limited to, a photoresist (PR) material or other suitable materials. The patterned mask 13a can be formed by, for example, but not limited to, photolithography (which may involve coating, exposure, development) or other suitable techniques.

[0067] refer to Figure 2C The portion of dielectric layer 12a not covered by patterned mask 13a can be removed. The removal operation can be performed by, for example but not limited to, etching (e.g., dry etching) or other suitable techniques.

[0068] refer to Figure 2D The patterned mask 13a can be removed. The patterned mask 13a can be removed by, for example, but not limited to, segmentation, etching or other suitable techniques.

[0069] refer to Figure 2E Interconnect layer 14a2 can be formed on the disposed portion of dielectric layer 12a and carrier 10a. Interconnect layer 14a1 can be formed on interconnect layer 14a2. Interconnect layer 14a3 (not included) may be further included. Figure 2E (As indicated in the text) to surround the interconnect layer 14a3.

[0070] Interconnect layers 14a1 and 14a2 can be formed by, for example but not limited to, sputtering, deposition (e.g., physical vapor deposition (PVD)) or other suitable techniques. Interconnect layers 14a1 and 14a2 can be formed by, for example but not limited to, etching or other suitable techniques.

[0071] refer to Figure 2F A planarization operation can be performed to expose interconnect layer 14a2. The planarization operation can be formed by, for example, but not limited to, chemical mechanical polishing (CMP), grinding, dry polishing, etching, or other suitable techniques.

[0072] refer to Figure 2GDielectric layer 12b can be formed or deposited accordingly. Dielectric layer 12b can be formed by, for example but not limited to, sputtering, deposition (e.g., chemical vapor deposition (CVD)) or other suitable techniques. Dielectric layer 12b may comprise, for example but not limited to, silicon oxide or other suitable materials.

[0073] refer to Figure 2H A patterned mask 13b can be formed on the dielectric layer 12 to expose the dielectric layer 12. The patterned mask (or photomask) 13b may contain, for example, but not limited to, a photoresist (PR) material or other suitable materials. The patterned mask 13b can be formed by, for example, but not limited to, photolithography techniques (which may involve coating, exposure, development) or other suitable techniques.

[0074] refer to Figure 2I The portion of dielectric layer 12 not covered by the patterned mask 13b can be removed. The removal operation can be performed by, for example but not limited to, etching (e.g., dry etching) or other suitable techniques.

[0075] refer to Figure 2J The patterned mask 13b can be removed. The patterned mask 13b can be removed by, for example, but not limited to, segmentation, etching or other suitable techniques.

[0076] refer to Figure 2K Interconnect layer 14b2 can be formed on the disposed portions of dielectric layer 12 and interconnect layer 41a1. Interconnect layer 14b2 can be formed by, for example, but not limited to, sputtering, deposition (e.g., physical vapor deposition (PVD)) or other suitable techniques.

[0077] refer to Figure 2L A patterned mask 13c can be formed on the interconnect layer 14b2 to expose the interconnect layer 14b2. The patterned mask (or photomask) 13b may contain, for example, but not limited to, a photoresist (PR) material or other suitable materials. The patterned mask 13c can be formed by, for example, but not limited to, photolithography techniques (which may involve coating, exposure, development) or other suitable techniques.

[0078] refer to Figure 2M Interconnect layer 14b1 may be formed on dielectric layer 12 and surrounded by patterned mask 13c. Interconnect layer 14b1 may be formed by, for example, but not limited to, sputtering, deposition (e.g., physical vapor deposition (PVD)) or other suitable techniques.

[0079] refer to Figure 2N The patterned mask 13c can be removed. The patterned mask 13c can be removed by, for example, but not limited to, segmentation, etching or other suitable techniques.

[0080] refer to Figure 2O The portion of interconnect layer 14b2 not covered by interconnect layer 14b1 can be removed. The removal operation can be performed by, for example but not limited to, etching (e.g., dry etching) or other suitable techniques.

[0081] refer to Figure 2P A planarization operation can be performed so that the interconnect layer 14b1 is substantially coplanar with the dielectric layer 12. The planarization operation can be formed by, for example, but not limited to, chemical mechanical polishing (CMP), grinding, dry polishing, etching, or other suitable techniques.

[0082] Figure 3A This is a cross-sectional view of another semiconductor package 1A according to some embodiments of the present invention.

[0083] refer to Figure 3A According to several different embodiments, the semiconductor device 1A may include, for example, but not limited to, a microcontroller (MCU), a microprocessor (e.g., single-core or multi-core), a memory device, a memory controller, a chipset, a graphics device, a high-bandwidth memory (HBM), or an application-specific integrated circuit (ASIC).

[0084] The semiconductor device 1A may include a carrier 10a, some connection structures 1a and a dielectric layer 12.

[0085] The carrier 10a may contain semiconductor material, glass or other suitable material.

[0086] The carrier 10a may include a circuit electrically connected to the connection structure 1a (not in Figure 3A (As shown in the diagram). The carrier 10a may include a redistribution layer (RDL) structure electrically connected to the connection structure 1a (not shown in the diagram). Figure 3A (As shown in the diagram). The semiconductor substrate 10a may include conductive pads, traces, or vias electrically connected to the connection structure 1a (not shown in the diagram). Figure 3A (as shown in the image).

[0087] The connection structure 1a may contain a conductive material, such as, but not limited to, copper (Cu), gold (Au), aluminum (Al), or other suitable materials.

[0088] The connection structure 1a may be surrounded by the dielectric layer 12.

[0089] The connection structure 1a may be covered by the dielectric layer 12. The connection structure 1a may be partially covered by the dielectric layer 12.

[0090] Connection structure 1a can be embedded within dielectric layer 12. Connection structures 1a can be separated from each other or spaced apart. Connection structure 1a can be separated from another connection structure 1a at a certain distance. Connection structures 1a can be separated or spaced apart through dielectric layer 12.

[0091] The connecting structure 1a may include two parts 14a and 14b. Part 14a may be formed or disposed on the carrier 10a. Part 14b may be formed or disposed on part 14a. Parts 14a and 14b may have different widths. Part 14a may have a width greater than that of part 14b.

[0092] Part 14a may include the upper surface (not in Figure 3A (indicated in the middle), lower surface (not in) Figure 3A (represented in the middle) and the transverse surface extending between the upper and lower surfaces (not in the middle) Figure 3A (as indicated in the diagram). The lower surface of portion 14a may be in direct contact with the carrier 10a. The lateral surface of portion 14a may be in direct contact with the dielectric layer 12. The upper surface of portion 14a may be in direct contact with portion 14b. The upper surface of portion 14a may be exposed. The upper surface of portion 14a may be in direct contact with the dielectric layer 12.

[0093] Part 14b may include the upper surface (not in) Figure 3A (indicated in the middle), lower surface (not in) Figure 3A (represented in the middle) and the transverse surface extending between the upper and lower surfaces (not in the middle) Figure 3A (as indicated in the diagram). The lower surface of portion 14b may be in direct contact with portion 14a. The lateral surface of portion 14b may be separated from or spaced apart from the dielectric layer 12 by space 18. The lateral surface of portion 14b may be exposed. The lateral surface of portion 14b may be exposed to space 18.

[0094] Figure 3B Is it like this? Figure 3A An enlarged view of the connection structure 1a shown.

[0095] refer to Figure 3B The connecting structure 1a may comprise two parts 14a and 14b. Part 14a has a width W1, and part 14b has a width W2. Width W1 may be greater than width W2.

[0096] Part 14a may contain interconnect layers 14a1, 14a2 and 14a3.

[0097] Part 14b may contain interconnect layers 14b1, 14b2 and 14b3.

[0098] Each of the interconnect layers 14a1, 14a2, 14a3, 14b1, 14b2 and 14b3 may contain, for example but not limited to, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W) or other suitable materials (e.g., metallic, alloy or non-metallic conductive materials).

[0099] Interconnect layer 14a1 may have a rectangular or rectangular-like outline. Interconnect layer 14a1 may have a circular or circular-like outline.

[0100] Interconnect layer 14a1 may be exposed to space 18. Interconnect layer 14a1 may be exposed to air in space 18. Interconnect layer 14a1 may be covered by dielectric layer 12. Interconnect layer 14a1 may be in direct contact with dielectric layer 12.

[0101] Interconnect layer 14a2 may have a U-shaped or U-like structure. Interconnect layer 14a2 may contain a cup or cup-like structure. Interconnect layer 14a2 may surround interconnect layer 14a1. Interconnect layer 14a2 may enclose interconnect layer 14a1. Interconnect layer 14a2 may be in direct contact with interconnect layer 14a1. Interconnect layer 14a2 may be in direct contact with dielectric layer 12. Interconnect layer 14a2 may be covered by dielectric layer 12. Interconnect layer 14a2 may be disposed between interconnect layer 14a1 and interconnect layer 14a3.

[0102] Interconnect layer 14a3 may have a U-shaped or U-like structure. Interconnect layer 14a3 may contain a cup or cup-like structure. Interconnect layer 14a3 may surround interconnect layer 14a1. Interconnect layer 14a3 may surround interconnect layer 14a2. Interconnect layer 14a3 may enclose interconnect layer 14a1. Interconnect layer 14a3 may enclose interconnect layer 14a2. Interconnect layer 14a3 may be in direct contact with interconnect layer 14a2. Interconnect layer 14a3 may be in direct contact with dielectric layer 12. Interconnect layer 14a3 may be in direct contact with carrier 10a. Interconnect layer 14a3 may be covered by dielectric layer 12. Interconnect layer 14a3 may be disposed between interconnect layer 14a2 and dielectric layer 12.

[0103] A portion S11 of the upper surface S1 of interconnect layer 14a1 can be exposed through dielectric layer 12. A portion S11 of the upper surface S1 of interconnect layer 14a1 can be exposed to space 18. A portion S12 of the upper surface S1 of interconnect layer 14a1 can be covered by dielectric layer 12. A portion S12 of the upper surface S1 of interconnect layer 14a1 can be in direct contact with dielectric layer 12.

[0104] Interconnect layer 14b1 may have a rectangular or rectangular-like outline. Interconnect layer 14b1 may have a circular or circular-like outline.

[0105] Interconnect layer 14b2 may have a U-shaped or U-like structure. Interconnect layer 14b2 may contain a cup-like or cup-like structure. Interconnect layer 14b2 may surround interconnect layer 14b1. Interconnect layer 14b2 may enclose interconnect layer 14b1. Interconnect layer 14b2 may be in direct contact with interconnect layer 14b1. Interconnect layer 14b2 may be in direct contact with interconnect layer 14b1. Interconnect layer 14b2 may be disposed between interconnect layer 14b1 and interconnect layer 14b3.

[0106] Interconnect layer 14b3 may have a U-shaped or U-like structure. Interconnect layer 14b3 may contain a cup or cup-like structure. Interconnect layer 14b3 may surround interconnect layer 14b1. Interconnect layer 14b3 may surround interconnect layer 14b2. Interconnect layer 14b3 may enclose interconnect layer 14b1. Interconnect layer 14b3 may enclose interconnect layer 14b2. Interconnect layer 14b3 may be in direct contact with interconnect layer 14b2. Interconnect layer 14b3 may be positioned between interconnect layer 14b2 and space 18.

[0107] The lateral surface of interconnect layer 14b3 may be exposed to space 18. Space 18 may be a vacuum. Air may be present in space 18. The lateral surface of interconnect layer 14b3 may be in direct contact with the air in space 18. Space 18 may be defined or surrounded by a portion S11 of the upper surface S1 of interconnect layer 14a1, the lateral surface of interconnect layer 14b3, and the lateral surface of dielectric layer 12. The boundary of space 18 may be formed or defined by a portion S11 of the upper surface S1 of interconnect layer 14a1, the lateral surface of interconnect layer 14b3, and the lateral surface of dielectric layer 12.

[0108] Figure 3C Is it like this? Figure 3A An enlarged view of the connection structure 1a shown. (Reference) Figure 3C The connection structure 1a is similar to that in the reference. Figure 3B The connection structure 1a described and illustrated differs in that a portion S11 of the upper surface S1 of the interconnect layer 14a1 is non-uniform or rough due to over-etching by etching (e.g., dry etching) or other suitable techniques.

[0109] refer to Figure 3D The connection structure 1a is similar to that in the reference. Figure 3C The connection structure 1a described and illustrated differs in that the lattice of the interconnect layer 14b1 can be further explained. (See reference...) Figure 3D Interconnect layer 14b1 may have a crystal structure. Interconnect layer 14b1 may have a crystal orientation or lattice orientation as indicated by arrow D1. The crystal orientation or lattice orientation D1 may include the orientation (111) (Miller index). The lattice of interconnect layer 14b1 may extend in at least two different directions from interconnect layer 14b2. The lattice of interconnect layer 14b1 may extend along several directions D1, D2, and D3.

[0110] Figure 3E This is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present invention. The semiconductor device package 1 may include two semiconductor devices 1A and 1B. The joint pair 1A may include a plurality of connection structures 1a on a carrier 10a. The joint pair 1B may include a plurality of connection structures 1b on a carrier 10b.

[0111] Hybrid bonding technology can be used to form a semiconductor device package 1. Hybrid bonding can refer to bonding involving two or more materials (e.g., metal-to-metal bonding and dielectric-to-dielectric bonding). The interconnect layer of portion 1a can be bonded to the interconnect layer of portion 1b. The dielectric layer of portion 1a can be bonded to the dielectric layer of portion 1b.

[0112] However, a mismatch in the coefficients of thermal expansion (CTE) of two or more materials during or after thermal cycling can cause delamination problems (e.g., delamination occurs at the interface between two dielectric layers), which adversely affects the reliability or performance of the semiconductor device package 1.

[0113] When CTE mismatch occurs, space 18 can be used as a trench or buffer. Due to the CTE mismatch, the contact surfaces of the materials will not be damaged or degraded. Therefore, during thermal cycling, delamination of the semiconductor device package 1 can be prevented by arranging space 18 between the interconnect layer and the dielectric layer.

[0114] During thermal cycling, compressive stress CS can be generated from portions 14a and 14b due to thermal expansion. Another tensile stress TS can be generated from the dielectric layer corresponding to the aforementioned compressive stress CS. Portion 14a can have a width greater than that of portion 14b. The upper and lateral surfaces of portion 14a are in direct contact with the dielectric layer 12. Therefore, a portion of the tensile stress TS can be offset or compensated by the compressive stress CS of portion 14a. Thus, delamination or degradation can be further reduced.

[0115] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M , Figure 4N , Figure 4O and Figure 4P This paper describes the various stages of a method for manufacturing a semiconductor device package 1 according to some embodiments of this application. Figures 4A to 4K Similar to the reference Figures 2A to 2K Those things that have been explained and described will not be explained further.

[0116] refer to Figure 4K Interconnect layer 14b2 can be formed or deposited accordingly. Interconnect layer 14b2 can be formed by, for example but not limited to, sputtering, deposition (e.g., physical vapor deposition (PVD)) or other suitable techniques.

[0117] refer to Figure 4L Interconnect layer 14b1 can be formed on interconnect layer 14b2. Interconnect layer 14b1 can be formed by, for example, but not limited to, sputtering, deposition (e.g., physical vapor deposition (PVD)) or other suitable techniques.

[0118] refer to Figure 4M A planarization operation can be performed to expose the interconnect layer 14b2 and the dielectric layer 12. The planarization operation can be formed by, for example, but not limited to, chemical mechanical polishing (CMP), grinding, dry polishing, etching or other suitable techniques.

[0119] refer to Figure 4N A patterned mask 13c can be formed on the dielectric layer 12 to expose interconnect layers 14b1 and 14b2. The patterned mask (or photomask) 13c may contain, for example, but not limited to, a photoresist (PR) material or other suitable materials. The patterned mask 12c can be formed by, for example, but not limited to, photolithography (which may involve coating, exposure, development) or other suitable techniques.

[0120] refer to Figure 4O The portion of the dielectric layer 12 not covered by the patterned mask 13c can be removed. The removal operation can be performed by, for example, but not limited to, etching (e.g., dry etching) or other suitable techniques.

[0121] refer to Figure 4P A planarization operation can be performed so that interconnect layers 14b1 and 14b2 are substantially coplanar with dielectric layer 12. The planarization operation can be formed by, for example, but not limited to, chemical mechanical polishing (CMP), grinding, dry polishing, etching, or other suitable techniques.

[0122] Figure 5A This is a cross-sectional view of another connection structure according to some embodiments of the present invention.

[0123] refer to Figure 5A The connection structure 2a has interconnect structures 24a and 24b. Interconnect structure 24a can also be referred to as "first interconnect structure 24a". Interconnect structure 24b can also be referred to as "second interconnect structure 24b". Interconnect structure 24a has interconnect layers 24a1, 24a2, and 24a3. Interconnect layer 24a2 can also be referred to as "first interconnect layer 24a2". Interconnect layer 24a3 can also be referred to as "second interconnect layer 24a3". Interconnect structure 24b has interconnect layers 24b1, 24b2, and 24b3. Interconnect layer 24b2 can also be referred to as "third interconnect layer 24b2". Interconnect layer 24b3 can also be referred to as "fourth interconnect layer 24b3". Interconnect layer 24b1 can also be referred to as "fifth interconnect layer 24b1". Interconnect structure 24a has a relatively smaller width compared to interconnect structure 24b.

[0124] The interconnect structure 2a can be formed by removing the dielectric layer 22 around or adjacent to the interconnect structure 24b. However, a relatively non-uniform bottom surface (e.g., the bottom surface of the defining space 18a may be higher than the bottom surface of the defining space 18b) can be formed after the removal of the dielectric layer 22.

[0125] Furthermore, relatively rough surfaces 22s can be formed after the removal of dielectric layer 22. Delamination can occur at the interface between dielectric layer 22 and interconnect structure 24b (e.g., interconnect layer 24b3).

[0126] Figure 5B This is a cross-sectional view of another connection structure according to some embodiments of the present invention.

[0127] refer to Figure 5B The connecting structure 2a' can be manufactured as follows: Figure 5A The connection structure 2a shown is formed through a similar process, except that only the conductive material is removed, while the dielectric layer 22, which is in direct contact with the interconnect layer 24b3, is retained. For example, materials such as... Figure 5A The interconnect layers 24b1 and 24b2 shown are partially used to form interconnect layers 24b1' and 24b2', while interconnect layer 24b3 may be retained. Interconnect structure 24a has a relatively smaller width compared to interconnect structure 24b'.

[0128] Interconnect layer 24b3 has a relatively large CTE compared to dielectric layer 22. During or after thermal cycling, delamination may occur at the interface between dielectric layer 22 and interconnect structure 24b (e.g., interconnect layer 24b3) due to CTE mismatch.

[0129] Figure 5C This is a cross-sectional view of another connection structure according to some embodiments of the present invention.

[0130] refer to Figure 5C The connection structure 2a'' is similar to that in the reference. Figure 5B The connection structure 2a' described and illustrated differs in that the interconnect layer 24b1' is replaced by the interconnect layer 24b1''.

[0131] As used herein, spatial relative terms such as “below,” “lower,” “lower,” “higher,” “upper,” “lower,” “left,” “right,” and similar terms may be used herein for ease of description to describe the relationship between one element or feature and another element or feature as illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of a device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein may be interpreted similarly accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0132] As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurs precisely or where it occurs very approximately. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term “substantially coplanar” may refer to two surfaces located along the same plane within a few micrometers (μm), for example, within 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane. When referring to the same numerical value or characteristic, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said value.

[0133] The foregoing outlines several embodiments and detailed features of the present invention. The embodiments described herein can readily serve as the basis for designing or modifying other processes and structures for performing the same or similar purposes and / or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the invention, and various changes, substitutions, and variations can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device package comprising: A connection structure having a first portion and a second portion extending from the first portion, the second portion having a width smaller than that of the first portion, wherein the first portion of the connection structure includes a first interconnect layer and wherein the first interconnect layer has a cup structure, wherein the second portion includes a third interconnect layer and a fourth interconnect layer, and wherein the third interconnect layer is formed on the fourth interconnect layer; as well as A dielectric layer surrounds the connection structure. The dielectric layer and the second portion of the connection structure define a space, and at least a portion of the lateral surface of the third interconnect layer contacts the space.

2. The semiconductor device package of claim 1, wherein the first interconnect layer has a U-shaped or U-shaped structure.

3. The semiconductor device package of claim 1 or 2, wherein the first portion of the interconnect structure includes a second interconnect layer surrounding the first interconnect layer.

4. The semiconductor device package of claim 2, wherein a first portion of the first part of the connection structure is covered by the dielectric layer and a second portion of the first part of the connection structure is exposed through the dielectric layer.

5. The semiconductor device package of claim 4, wherein the second portion of the first portion of the connection structure, the dielectric layer, and the second portion of the connection structure define the space.

6. The semiconductor device package of claim 1, wherein a portion of the fourth interconnect layer is surrounded by the first interconnect layer.

7. The semiconductor device package of claim 1, wherein the second portion further includes a fifth interconnect layer on the third interconnect layer, and the lattice of the fifth interconnect layer extends in a direction from the third interconnect layer.

8. The semiconductor device package according to claim 7, wherein the orientation is the (111) orientation.

9. A semiconductor device package comprising: A connection structure having a first portion and a second portion disposed on the first portion, wherein the first portion of the connection structure includes a first interconnect layer and a second interconnect layer, and wherein the first interconnect layer has a U-shaped or U-shaped structure, wherein portions of the first interconnect layer and the second interconnect layer are covered by the dielectric layer, wherein the second portion of the connection structure includes a fifth interconnect layer and a third interconnect layer and a fourth interconnect layer surrounding the fifth interconnect layer in a U-shaped or U-shaped structure; as well as A dielectric layer that exposes a portion of the upper surface of the first part of the connection structure. The exposed portion of the upper surface of the first portion of the dielectric layer and the connection structure defines a space, wherein the lateral surface of the fourth interconnect layer is exposed in the space.

10. The semiconductor device package of claim 9, wherein the first interconnect layer has a cup structure.

11. The semiconductor device package of claim 9 or 10, wherein the second interconnect layer surrounds the first interconnect layer.

12. The semiconductor device package of claim 9, wherein a first portion of the first part of the connection structure is covered by the dielectric layer and a second portion of the first part of the connection structure is exposed through the dielectric layer.

13. The semiconductor device package of claim 9, wherein a portion of the upper surface of the first portion contacts the space.

14. The semiconductor device package of claim 9, wherein the lattice of the fifth interconnect layer extends in at least two different directions from the third interconnect layer.

Images