Display device and method of manufacturing the same

Abstract

The present invention relates to a display device and a method of manufacturing the display device. The display device includes a substrate including a first surface, a second surface opposite the first surface, a display region defined on the first surface, and a non-display region defined on the second surface; a plurality of display elements at the display region on the first surface of the substrate; a drive circuit on the second surface and overlapping the display region of the substrate; a first conductive pattern on the second surface of the substrate; and a second conductive pattern on the first surface of the substrate and connected to the first conductive pattern via a contact hole extending through the substrate. A surface roughness of the second surface of the substrate is greater than a surface roughness of the first surface of the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0111558, filed on September 9, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to a display device and a method of manufacturing the display device, and more specifically, to a display device and a method of manufacturing the display device that includes a reduced peripheral region outside the display area (e.g., surrounding the periphery of the display area). Background Technology

[0004] Typically, display devices operate using thin-film transistors and display elements (such as organic light-emitting diodes) formed on a substrate and emitting light. Such display devices can be used in small products such as cell phones, or in large products such as televisions (TVs).

[0005] The display device includes a display area in which an image is displayed externally and a peripheral area outside the display area. Multiple pixels are disposed in the display area. Circuitry and wiring (each configured to send signals to the multiple pixels) are disposed in the peripheral area.

[0006] In recent years, the applications of display devices have diversified. Furthermore, as display devices have become thinner and lighter, their use has become increasingly widespread. With the utilization of display devices in various fields, research is rapidly underway to reduce the size of the peripheral area outside the display area.

[0007] The information disclosed in this background section is intended to enhance the understanding of the background technology of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0008] One or more exemplary embodiments of this disclosure may be directed to a display device in which a peripheral area outside the display area (e.g., around the periphery of the display area) is reduced, and a method of manufacturing the display device.

[0009] However, this disclosure is not limited thereto, and additional aspects and features will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing one or more embodiments of this disclosure.

[0010] According to one or more exemplary embodiments of this disclosure, a display device includes: a substrate including a first surface, a second surface opposite to the first surface, a display area defined on the first surface, and a non-display area defined on the second surface; a plurality of display elements at the display area on the first surface of the substrate; a driving circuit on the second surface and overlapping the display area of ​​the substrate; a first conductive pattern on the second surface of the substrate; and a second conductive pattern on the first surface of the substrate and connected to the first conductive pattern via a contact hole extending through the substrate. The surface roughness of the second surface of the substrate is greater than the surface roughness of the first surface of the substrate.

[0011] In an example embodiment, the material composition of the first surface may be different from that of the second surface.

[0012] In an example embodiment, the first conductive pattern may be embedded within the substrate.

[0013] In an example embodiment, the first conductive pattern may include: a surface, another surface opposite to the surface, and a side surface extending between the surface and the other surface to connect the surface to the other surface; the surface of the first conductive pattern may be located on the same plane as the plane of the first surface of the substrate; and the other surface and the side surface of the first conductive pattern may be in direct contact with the substrate.

[0014] In an example embodiment, the substrate may include a first substrate layer and a second substrate layer on the first substrate layer, and the display device may further include a connection pattern disposed between the first substrate layer and the second substrate layer, and electrically connecting the first conductive pattern to the second conductive pattern.

[0015] In an example embodiment, the first conductive pattern may be connected to the connecting pattern via a first contact hole in a first substrate layer, and the connecting pattern may be connected to the second conductive pattern via a second contact hole in a second substrate layer.

[0016] In an example embodiment, the display device may further include an electronic structure on a second surface and electrically connected to a first conductive pattern to overlap with the display area.

[0017] In an example embodiment, the display device may further include: a plurality of first signal lines extending in a first direction in the display area and a plurality of second signal lines extending in a second direction intersecting the first direction, and the second conductive pattern may be connected to the plurality of first signal lines or the plurality of second signal lines.

[0018] In an example embodiment, the display device may further include a plurality of pixel circuits located in the display area and respectively connected to a plurality of display elements. Each pixel circuit includes: a thin-film transistor comprising a semiconductor layer, a gate electrode at least partially overlapping the semiconductor layer, and an electrode layer connected to the semiconductor layer; and a storage capacitor comprising a lower electrode corresponding to at least a portion of the gate electrode and an upper electrode on the lower electrode. The second conductive pattern may include the same material as at least one selected from the gate electrode, the electrode layer, the lower electrode, and the upper electrode.

[0019] In an example embodiment, multiple second signal lines can be electrically connected to the drive circuit via a second conductive pattern.

[0020] In an example embodiment, the display device may further include a power line that overlaps with the display area of ​​the substrate on a second surface.

[0021] According to one or more example embodiments of this disclosure, a display device includes: a substrate comprising: an organic buffer layer, a first base layer on the organic buffer layer, and a second base layer on the first base layer; a plurality of display elements on the second base layer; a first conductive pattern between the organic buffer layer and the first base layer; a connection pattern between the first and second base layers and connected to the first conductive pattern via a first contact hole in the first base layer; a second conductive pattern on the second base layer and connected to the connection pattern via a second contact hole in the second base layer; and an electronic structure electrically connected to the first conductive pattern. The organic buffer layer has an opening exposing at least a portion of the first conductive pattern.

[0022] In an example embodiment, the electronic structure can be in direct contact with a first conductive pattern exposed via an opening.

[0023] According to one or more example embodiments of the present disclosure, a method of manufacturing a display device includes: forming an organic buffer layer on a carrier substrate; forming a first conductive pattern on the organic buffer layer; forming a first base layer on the organic buffer layer to cover the first conductive pattern; forming a connection pattern on the first base layer, the connection pattern being connected to the first conductive pattern via a first contact hole extending through the first base layer; forming a display unit on the first base layer including a plurality of pixel circuits and a plurality of display elements respectively connected to the plurality of pixel circuits to overlap with the first conductive pattern; separating the organic buffer layer from the carrier substrate; exposing the first conductive pattern by removing at least a portion of the organic buffer layer; and attaching an electronic structure to the exposed first conductive pattern.

[0024] In an example embodiment, prior to forming the display unit, the method may further include: forming a second substrate layer on a first substrate layer to cover the connection pattern; and forming a second conductive pattern on the second substrate layer, the second conductive pattern being connected to the connection pattern via a second contact hole extending through the second substrate layer.

[0025] In an example embodiment, in order to expose the first conductive pattern, the method may further include removing the entire organic buffer layer to expose the surface of the first base layer.

[0026] In an example embodiment, the surface roughness of the surface of the first substrate layer may be greater than the surface roughness of another surface of the first substrate layer on the opposite side of the surface of the first substrate layer.

[0027] In an example embodiment, the first conductive pattern may be embedded within the first substrate layer.

[0028] In an example embodiment, the exposed surface of the first conductive pattern may be on the same plane as the surface of the first substrate layer.

[0029] In an example embodiment, in order to expose the first conductive pattern, the method may further include forming an opening in the organic buffer layer corresponding to at least a portion of the first conductive pattern.

[0030] One or more embodiments of the above and other embodiments of this disclosure can be implemented using a system, method, computer program or a combination thereof. Attached Figure Description

[0031] The above and other aspects and features of this disclosure will become more apparent to those skilled in the art from the following detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0032] Figure 1A This is a schematic plan view of the front of the display device according to an embodiment;

[0033] Figure 1B This is a schematic plan view of the back of the display device according to an embodiment;

[0034] Figure 2 This is an equivalent circuit diagram of the pixels of the display device according to an embodiment;

[0035] Figure 3 yes Figure 1A Enlarged view of part IIIa;

[0036] Figure 4 This is a schematic cross-sectional view of a portion of a display device according to an embodiment;

[0037] Figure 5 yes Figure 4A schematic enlarged view of part A;

[0038] Figures 6 to 7 This is a schematic cross-sectional view of a part of a display device according to one or more embodiments;

[0039] Figures 8A to 8G This is a schematic cross-sectional view illustrating various operations of a method for manufacturing a display device according to an embodiment;

[0040] Figures 9 to 12 This is a schematic cross-sectional view of a portion of a display device according to one or more embodiments; and

[0041] Figure 13 The illustration shows an example application of a display device according to an embodiment. Detailed Implementation

[0042] Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals denote the same elements throughout. However, this disclosure may be embodied in various different forms and should not be construed as being limited to the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be comprehensive and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques that are not essential for a full understanding of the aspects and features of this disclosure may not be described. Furthermore, a particular process sequence may differ from the described process sequence when particular embodiments can be implemented differently. For example, two processes described consecutively may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described process. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description may not be repeated.

[0043] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of interpretation, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below,” “under,” or “below” to other elements or features will subsequently be oriented “above” to other elements or features. Thus, the exemplary terms “below” and “below” can include both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or otherwise) and the spatial relative descriptors used herein should be interpreted accordingly. In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other or may represent different directions that are not perpendicular to each other.

[0044] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, the first element, component, region, layer, or section described below may be referred to as the second element, component, region, layer, or section without departing from the spirit and scope of this disclosure.

[0045] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intermediate elements or layers may exist. Similarly, when a layer, region, or component is referred to as being "electrically connected to" or "electrically coupled to" another layer, region, or component, it can be electrically "indirectly connected to" or electrically "indirectly coupled to" that other layer, region, or component, and / or electrically "directly connected to" or electrically "directly coupled to" that other layer, region, or component, with one or more intermediate elements between them. Furthermore, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may exist.

[0046] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, the singular form “a” is intended to include the plural form as well, unless the context explicitly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” and “having” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, “A and / or B” refers to A or B, or A and B. When following a list of elements, expressions such as “at least one of” modify the entire list of elements without modifying any individual element in the list. For example, the expression “at least one of a, b, and c” may indicate only a, only b, only c, both a and b, both a and c, both b and c, all or variations thereof of a, b, and c.

[0047] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the terms “use,” “being used,” and “being exploited” can be considered to have the same meaning as the terms “utilize,” “being exploited,” and “being exploited,” respectively. Additionally, the term “exemplary” is intended to refer to an example or illustration.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] Figure 1A This is a schematic plan view of the front of the display device 1 according to an embodiment. Figure 1B This is a schematic plan view of the back of the display device 1 according to an embodiment. Figure 2 This is an equivalent circuit diagram of the pixels of the display device 1 according to an embodiment. Figure 3 yes Figure 1A A magnified view of part IIIa.

[0050] Reference Figure 1A and Figure 1BThe substrate 100 may include a display area DA on the front side where an image is displayed, and a non-display area NDA on the back side where driving circuitry configured to display an image and wiring connected to the driving circuitry are disposed. The display area DA may be defined on a first surface 100a of the substrate 100. The non-display area NDA may be defined on a second surface 100b, which is the opposite surface of the first surface 100a. Therefore, the first surface 100a of the substrate 100 can be understood as the display surface, and the second surface 100b of the substrate 100 can be understood as the non-display surface.

[0051] The substrate 100 may include various materials such as glass, metal, and plastic. According to an embodiment, the substrate 100 may include a flexible material, such that the substrate 100 may be bendable, foldable, foldable, rollable, etc. (e.g., it can be easily bent, folded, rolled, etc.). The substrate 100 including the flexible material may include, for example, ultrathin glass, metal, and plastic.

[0052] The display unit (e.g., display panel or display layer) 200 may be located in the display area (e.g., in the center) of the substrate 100. The display unit 200 may include a plurality of pixels P comprising various display elements (e.g., such as organic light-emitting diodes OLEDs). The plurality of pixels P may be arranged in various forms (e.g., such as strip arrangement, honeycomb arrangement, mosaic arrangement, etc.) to realize an image.

[0053] In the following description, display device 1 may be described as an organic light-emitting display device as a representative example according to embodiments. However, this disclosure is not limited thereto. For example, in other embodiments, display device 1 may be any suitable type of display device, such as inorganic light-emitting display devices (e.g., inorganic electroluminescent (EL) display devices), quantum dot light-emitting display devices, etc. For example, in various embodiments, the emitting layer of the display element in display device 1 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, inorganic materials and quantum dots, etc.

[0054] Each of the pixels P may include a display element (e.g., such as) capable of emitting light having a suitable or desired color (e.g., a predetermined color). Figure 2 The organic light-emitting diode (OLED) shown is an example of an OLED. An OLED can emit light, for example, red, green, and / or blue light, or it can emit light, for example, red, green, blue, and / or white light. Each OLED can be electrically connected to a pixel circuit PC.

[0055] Reference Figure 2The pixel circuit PC may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. The second thin-film transistor T2 may be a switching thin-film transistor connected to the scan line SL and the data line DL. The second thin-film transistor T2 can send a data voltage input from the data line DL to the first thin-film transistor T1 according to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second thin-film transistor T2 and the drive voltage line PL. The storage capacitor Cst can store a voltage corresponding to the difference between the voltage sent from the second thin-film transistor T2 and the first power supply voltage ELVDD applied to the drive voltage line PL.

[0056] The first thin-film transistor T1 can be a driving thin-film transistor connected to the driving voltage line PL and the storage capacitor Cst. The first thin-film transistor T1 can control the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) based on the value of the voltage stored in the storage capacitor Cst. The OLED can emit light with a suitable or desired brightness (e.g., a predetermined brightness) based on the driving current. The counter electrode (e.g., the cathode) of the OLED can receive a second power supply voltage ELVSS.

[0057] Although Figure 2 The illustrated pixel circuit PC includes two thin-film transistors and one storage capacitor, but this disclosure is not limited thereto. For example, in other embodiments, as known to those skilled in the art, the number of thin-film transistors and the number of storage capacitors can be modified differently depending on the design (e.g., structure) of the pixel circuit PC.

[0058] Return to reference Figure 1A Because the display device 1 according to this embodiment includes a display area DA on the front side, the shape of the display area DA can correspond to the shape of the substrate 100 in a plan view. For example... Figure 1A As shown, the display area DA may have a rectangular shape in the plan view, but this disclosure is not limited thereto. For example, in other embodiments, the display area DA may have a shape in the plan view corresponding to a circle, a polygon (e.g., such as a triangle, pentagon, hexagon, etc.), an ellipse, an irregular shape, etc., depending on the shape of the substrate 100.

[0059] The display area DA may include multiple data lines DL extending in a first direction D1 and multiple scan lines SL extending in a second direction D2 intersecting the first direction D1. A pixel P located in the display area DA (e.g., in the middle) is connected to the corresponding data line DL and the corresponding scan line SL, and can receive data signals and scan signals from the corresponding data line DL and the corresponding scan line SL, respectively.

[0060] like Figure 1A As shown, the light emission control line EL and the drive voltage line PL can be further positioned at the display area DA (e.g., in the middle). For example, the light emission control line EL can extend in the same or substantially the same direction as the scan line SL, and the drive voltage line PL can extend in the same or substantially the same direction as the data line DL.

[0061] On the first surface 100a of the substrate 100, the inorganic region IRA (e.g., reference) Figure 11 The inorganic region IRA can be located outside the display area DA. As will be described in more detail below, the inorganic region IRA can be the area where the first inorganic encapsulation layer 241 and the second inorganic encapsulation layer 243 of the thin film encapsulation layer 240 intersect each other.

[0062] The non-display area NDA is located on the opposite surface of the display area DA and can be an area where the image is not displayed (e.g., in the middle). The wiring and drive circuitry for conveying (e.g., transmitting) the electrical signals to be applied to the display area DA can be located at the non-display area NDA (e.g., in the middle).

[0063] The display area DA can be as follows: Figure 1A The image shown is provided on the first surface 100a of the substrate 100. In other words, a plurality of pixels P at the display area DA (e.g., in the middle) can be disposed on the first surface 100a of the substrate 100. Therefore, an image realized via the display area DA can be realized at the first surface 100a of the substrate 100 (e.g., in the middle).

[0064] Reference Figure 1B The substrate 100 includes a second surface 100b on the opposite side of the first surface 100a. The second surface 100b may include (e.g., may be) a driving circuit configured therein (e.g., in) for displaying an image, and wiring connected to the driving circuit may be provided in a non-display area NDA. A protective film may be on (e.g., may be attached to or connected to) the second surface 100b of the substrate 100.

[0065] Driving circuitry (e.g., such as a first scan driving circuit 110, a second scan driving circuit 120, and a data driving circuit 150), terminals 140, a first power line 160, and a second power line 170 may be disposed on the second surface 100b of the substrate 100 at a non-display area NDA (e.g., in the middle). However, this disclosure is not limited thereto, and in another embodiment, at least some of the driving circuitry configured to display an image and the wiring connected to the driving circuitry may be located on the first surface 100a. Figure 1BIn the embodiment shown, both the driving circuit configured to display an image and the wiring connected to the driving circuit can be disposed on the second surface 100b of the substrate 100, and the entire first surface 100a can correspond to (e.g., it can be) the display area DA.

[0066] The first scan driving circuit 110 can provide scan signals to at least some of the pixels P via corresponding scan lines SL. In some embodiments, the driving circuit may further include a light-emitting driving circuit. The light-emitting driving circuit can provide light-emitting control signals to each of the pixels P via corresponding light-emitting control lines EL.

[0067] The second scan driving circuit 120 can be configured to be spaced apart from and parallel to the first scan driving circuit 110. Some pixels P in the display area DA (e.g., in the middle) can be electrically connected to the first scan driving circuit 110, and other pixels P in the display area DA (e.g., in the middle) can be connected to the second scan driving circuit 120. In this case, the pixels P connected to the first scan driving circuit 110 can receive scan signals from the first scan driving circuit 110, and the pixels P connected to the second scan driving circuit 120 can receive scan signals from the second scan driving circuit 120. However, this disclosure is not limited thereto; for example, in another embodiment, the second scan driving circuit 120 can be omitted. In this case, each of the pixels P can receive a scan signal from the first scan driving circuit 110 via a corresponding scan line SL.

[0068] In this embodiment, reference will be made to at least the following. Figure 3 In more detail, the scan line SL located on the first surface 100a of the substrate 100 can be transmitted via a contact hole CNT extending through (e.g., penetrating) the substrate 100 (e.g., refer to...). Figure 3 It is electrically connected to the first scan drive circuit 110 or the second scan drive circuit 120.

[0069] Terminal 140 may be disposed on the second surface 100b of substrate 100. Terminal 140 may not be covered by an insulating layer and may be exposed (e.g., for electrical connection to electronic structure 300). Electronic structure 300 may be implemented as an integrated circuit (IC) or a flexible printed circuit board (FPCB) (e.g., may be in the form of an IC or an FPCB). For convenience, Figure 1BThe illustrated electronic structure 300 is implemented as an FPCB, but this disclosure is not limited thereto. When the electronic structure 300 is implemented as an FPCB, the terminals of the FPCB can be electrically connected to the terminals 140 of the display device 1. In an embodiment, the FPCB can transmit signals or power from the controller to the display device 1. Control signals generated from the controller can be transmitted to the first scan drive circuit 110 and the second scan drive circuit 120 via connection wirings 111 and 112, respectively.

[0070] The data drive circuit 150 is electrically connected to the data line DL. The data signal of the data drive circuit 150 can be provided to each of the pixels P via the corresponding data line DL connected to the connection wiring 151, which is connected to the terminal 140. Figure 1B The illustrated data driving circuit 150 is disposed on a printed circuit board. However, this disclosure is not limited thereto, and in another embodiment, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between terminal 140 and the first power line 160.

[0071] The first power line 160 and the second power line 170 can connect the first power supply voltage ELVDD and the second power supply voltage ELVSS (e.g., refer to...) via connecting wiring 161 and 171. Figure 2 A first power supply voltage ELVDD can be provided to each of the pixels P via a drive voltage line PL connected to the first power supply line 160. A second power supply voltage ELVSS can be provided to the counter electrode 223 of the pixel P connected to the second power supply line 170 (e.g., see reference 160). Figure 9 As an example, the second power line 170 can be provided as a loop with an open side.

[0072] Terminals 140 on the second surface 100b of substrate 100 may include a plurality of pads 400 (hereinafter referred to as a first conductive pattern). The plurality of pads 400 may be arranged adjacent to each other and may be spaced apart from each other. Each of the pads 400 may be a component electrically connected to electronic structure 300, which may be an FPCB, integrated circuit (IC) chip, etc., configured to drive and / or control display device 1. Each of the pads 400 may include a conductive material.

[0073] In an example embodiment, pads 400 on the second surface 100b of substrate 100 may be electrically connected to multiple wirings (e.g., data lines DL) included at the display unit 200 on the first surface 100a of substrate 100 (e.g., in the middle or on top).

[0074] Reference Figure 3Multiple data lines DL on the first surface 100a can be electrically connected to multiple pads 400 on the second surface 100b via contact holes CNTs extending through (e.g., penetrating) the substrate 100. In this case, the multiple data lines DL (e.g., each of the multiple data lines DL) can be directly connected to the multiple pads 400. However, this disclosure is not limited thereto, and in another embodiment, the multiple data lines DL (e.g., each of the multiple data lines DL) can be connected to the multiple pads 400 via a conductive layer that can be formed using a separation process.

[0075] Furthermore, multiple scan lines SL on the first surface 100a can be electrically connected to the first scan drive circuit 110 or the second scan drive circuit 120 on the second surface 100b via contact holes CNTs extending through (e.g., penetrating) the substrate 100.

[0076] According to one or more example embodiments, in order to achieve full display on the entire surface or substantially the entire surface of the display device 1, the entire surface (e.g., the first surface 100a or the front surface) or substantially the entire surface of the display device 1 may correspond to (e.g., may be) the display area DA where the image is displayed (e.g., in the center). In this case, the display device 1 may not include a non-display area (e.g., a peripheral area or a border area) surrounding the display area DA (e.g., around the periphery of the display area DA) (or may include a substantially reduced or minimized non-display area surrounding the periphery of the display area DA). For example, when a driving circuit configured to display an image and wiring connected to the driving circuit are disposed on a second surface 100b (e.g., the back surface) of the substrate 100, and the driving circuit and wiring connected to the driving circuit are electrically connected to wiring of the display unit 200 located on the first surface 100a (e.g., the front surface) via contact holes CNTs extending through (e.g., penetrating) the substrate 100, all or substantially all of the first surface 100a (e.g., the front surface) may be implemented as the display area DA.

[0077] Figure 4 This is a schematic cross-sectional view of a portion of the display device 1 according to an embodiment. For example, Figure 4 It can be illustrated along Figure 3 An example cross-sectional view of display device 1 taken by line IV-IV'. Figure 5 yes Figure 4 A schematic enlarged view of part A.

[0078] Reference Figure 4 The substrate 100 includes a first surface 100a and a second surface 100b on the side opposite to the first surface 100a. The display unit 200 may be located on the first surface 100a corresponding to the display area DA. Figure 1AAs shown, the display unit 200 may include a plurality of pixels P. The following will refer to... Figure 9 The detailed configuration of the display unit 200 is described in more detail.

[0079] The first conductive pattern CP1 (e.g., the aforementioned plurality of pads 400) may be located at the second surface 100b of the substrate 100 (e.g., in the middle or on top). Figure 4 As shown, the first conductive pattern CP1 can be configured to overlap with the display unit 200 located at the display area DA (e.g., in the middle).

[0080] In some embodiments, the first conductive pattern CP1 may be located within the second surface 100b, such that at least a portion of the first conductive pattern CP1 can be exposed to the outside via the second surface 100b. This is structurally different from a first conductive pattern CP1 located on the second surface 100b. For example, in Figure 4 In the illustrated embodiment, the first conductive pattern CP1 can be embedded within the substrate 100, and therefore, the surface of the first conductive pattern CP1 can be exposed to the outside via the second surface 100b. Alternatively, the side surfaces of the first conductive pattern CP1 may not be exposed to the outside via the second surface 100b.

[0081] For example, refer to the enlarged view illustrating the first conductive pattern CP1. Figure 5 The first conductive pattern CP1 includes a surface (e.g., a bottom surface) CP1a, another surface (e.g., a top surface) CP1b located on the opposite side of surface CP1a, and a side surface CP1c extending between surfaces CP1a and CP1b (e.g., connecting the bottom surface CP1a to the top surface CP1b). As described above, the first conductive pattern CP1 can be provided as embedded within the substrate 100. In other words, the other surface CP1b and the side surface CP1c of the first conductive pattern CP1 can be in direct contact with the substrate 100, and the surface CP1a of the first conductive pattern CP1 can be exposed to the outside via the second surface 100b of the substrate 100.

[0082] In an embodiment, the surface CP1a of the first conductive pattern CP1 may be located on the same plane as the plane of the second surface 100b of the substrate 100. This structure can be obtained by a method for manufacturing the display device 1 according to an embodiment. For example, during the manufacturing process according to an embodiment, both the surface CP1a of the first conductive pattern CP1 and the second surface 100b of the substrate 100 can be disposed on the organic buffer layer 101 (e.g., as shown in the embodiment). Figures 8A to 8C As shown in the diagram, after the organic buffer layer 101 is removed, the remaining portion of the surface CP1a of the first conductive pattern CP1 and the second surface 100b of the substrate 100 can be on the same plane as each other.

[0083] Return to reference Figure 4 During etching processes in which the organic buffer layer 101 is removed (e.g., ashing processes and / or dry etching processes), the second surface 100b of the substrate 100 may be irregularly damaged. For example, as in Figure 4 As shown in the enlarged portion of the first surface 100a and the second surface 100b, the surface roughness of the second surface 100b of the substrate 100, which can be obtained by a process of removing the organic buffer layer 101, can be greater than the surface roughness of the first surface 100a of the substrate 100 on which the process was not performed. In other words, the second surface 100b can be formed to be more irregular and rougher than the first surface 100a.

[0084] Furthermore, the material composition 100S of the second surface 100b of the substrate 100, which can react with the etching gas in the process of removing the organic buffer layer 101, may differ from the material composition of the first surface 100a of the substrate 100. The characteristics of the material composition 100S can be examined via compositional analysis of the surface of the substrate 100. For example, the material composition 100S of the second surface 100b of the substrate 100 may be the etching gas composition partially remaining after the second surface 100b reacts with the etching gas. The material composition 100S of the second surface 100b may differ from the material composition of the substrate 100 at a depth (e.g., a specific depth or a certain depth) D of the substrate 100 from the second surface 100b. In embodiments, the material composition 100S of the second surface 100b may be modified differently depending on the type or kind of etching gas used, and therefore, this disclosure is not limited to a specific element or compound for the material composition 100S. In this case, the material composition 100S of the second surface 100b may be a component not initially included in the material of the substrate 100.

[0085] A second conductive pattern CP2 may be disposed on a first surface 100a of the substrate 100. In one embodiment, the second conductive pattern CP2 may be a line (e.g., a data line DL) included at (e.g., in or above) the display unit 200 and extending over (e.g., across) the display unit 200. In another embodiment, the second conductive pattern CP2 may be a separate conductive layer electrically connected to the line (e.g., the data line DL). The second conductive pattern CP2 may be connected to the first conductive pattern CP1 via a contact hole CNT extending through (e.g., penetrating) the substrate 100.

[0086] The electronic structure 300 (e.g., an FPCB or IC chip) connected to the second conductive pattern CP2 can be disposed on the second surface 100b of the substrate 100. In a comparative example, when the pads and electronic structure are disposed on the front side of the substrate (e.g., the first surface), the area where the pads and electronic structure are located (e.g., in the middle) can be provided as a non-display area. In this case, there may be limitations in achieving a full display. For example, in the comparative example, the non-display area may be adjacent to the display area on the front side (e.g., the first surface), and therefore, the entire front side may not be implemented as a display area. On the other hand, in the embodiment, because the first conductive pattern CP1 is disposed on the back side of the substrate 100 (e.g., the second surface 100b), the electronic structure 300 can be disposed directly on the back side of the substrate 100 (e.g., the second surface 100b). Therefore, the peripheral area PA (e.g., the non-display area NDA) outside the display area DA (e.g., adjacent to the display area DA) can be significantly reduced.

[0087] Figure 6 and Figure 7 This is a schematic cross-sectional view of a portion of a display device according to one or more embodiments. For example, Figure 6 and Figure 7 It can be illustrated along Figure 3 An example cross-sectional view of display device 1 taken by line IV-IV'.

[0088] Figure 6 and Figure 7 The substrate 100 of the display device 1' and display device 1" shown in the figure can be provided to have a multilayer structure. Figure 6 and Figure 7 The illustration shows that the substrate 100 includes a two-layer structure of a first base layer 102 and a second base layer 104. However, this disclosure is not limited thereto, and in other embodiments, the substrate 100 may include a structure comprising three or more layers.

[0089] Reference Figure 6The substrate 100 may include a first base layer 102 and a second base layer 104 sequentially stacked on a third third direction D3 (e.g., the z-axis direction) perpendicular to the first directions D1 and D2. A first conductive pattern CP1 may be located on a second surface 100b of the substrate 100 (e.g., the surface of the first base layer 102). A connection pattern CP3 may be located between the first base layer 102 and the second base layer 104. A second conductive pattern CP2 may be located on a first surface 100a of the substrate 100 (e.g., the surface of the second base layer 104). The connection pattern CP3 may be connected to the first conductive pattern CP1 via a first contact hole CNT1 extending through (e.g., penetrating) the first base layer 102. The second conductive pattern CP2 may be connected to the connection pattern CP3 via a second contact hole CNT2 extending through (e.g., penetrating) the second base layer 104.

[0090] The first conductive pattern CP1 can be exposed to the outside via the second surface 100b of the substrate 100. The electronic structure 300 can be electrically connected to the exposed first conductive pattern CP1 as described above.

[0091] Reference Figure 7 The first conductive pattern CP1 can be exposed to the outside via the second surface 100b of the substrate 100, and can also be exposed to the outside via an opening 101OP in the organic buffer layer 101, which can be provided to contact the second surface 100b of the substrate 100. In this case, due to the height difference at the opening 101OP (e.g., in the middle or above), the electronic structure 300 can be exposed via the conductive material layer 310 (e.g., see...). Figure 11 (For example, such as bumps) are electrically connected to the first conductive pattern CP1.

[0092] In the following text, refer to Figures 8A to 8G A method for manufacturing the display device 1 according to an embodiment will be described in more detail.

[0093] Figures 8A to 8G This is a schematic cross-sectional view illustrating various operations of a method for manufacturing a display device according to an embodiment. (Refer to...) Figures 8A to 8G The described manufacturing method can be compared with Figure 6 The display device 1' corresponds to it.

[0094] Reference Figure 8AAn organic buffer layer 101 may be formed on a carrier substrate 10. The carrier substrate 10 may be divided into a display area DA (e.g., a first surface 100a or front side) where a plurality of pixels are to be disposed, and a peripheral area PA (e.g., a second surface 100b or back side) at an outer portion of the display area DA. The organic buffer layer 101, along with the first base layer 102 and the second base layer 104, which will be described in more detail below, may form a structure constituting at least a portion of the substrate 100. The organic buffer layer 101, the first base layer 102, and the second base layer 104 may be formed on the entire surface of the carrier substrate 10.

[0095] The organic buffer layer 101 may include, for example, a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0096] In an embodiment, the thickness t of the organic buffer layer 101 may be less than (e.g., less than) the thickness of the first substrate layer 102 and the second substrate layer 104, because a portion or all of the organic buffer layer 101 can be removed during the manufacturing process. The thickness t of the organic buffer layer 101 can be in the range of several micrometers (μm). For example, in an embodiment, the thickness t of the organic buffer layer 101 may be formed in the range of approximately 0.5 μm to approximately 2 μm.

[0097] like Figure 8B As shown, a first conductive pattern CP1 may be formed on the organic buffer layer 101. The first conductive pattern CP1 may refer to a pad to which a module such as the electronic structure 300 is connected. Figure 8B The diagram illustrates a structure in which a first conductive pattern CP1 is disposed in the peripheral region PA (e.g., the second surface 100b or the back side) (e.g., the center). However, in another embodiment, the first conductive pattern CP1 may be disposed in the display region DA (e.g., the first surface 100a or the front side) (e.g., the center). Considering the conductivity of the first conductive pattern CP1, the first conductive pattern CP1 may include at least one metal selected from, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), and copper (Cu). The first conductive pattern CP1 may comprise a single layer or multiple layers.

[0098] The first substrate layer 102 can be formed on the first conductive pattern CP1, such as Figure 8C As shown in the figure. The first substrate layer 102 may be formed on the entire surface of the carrier substrate 10 to cover the first conductive pattern CP1.

[0099] A connection pattern CP3 may be formed on the first substrate layer 102. The connection pattern CP3 may be connected to the first conductive pattern CP1 via a first contact hole CNT1 in the first substrate layer 102. Before the connection pattern CP3 is formed, the first contact hole CNT1 may be patterned to extend through (e.g., penetrate) the first substrate layer 102 so that a portion of the first conductive pattern CP1 is exposed to the outside.

[0100] The connecting pattern CP3 can be a structure configured to electrically connect the first conductive pattern CP1 to the second conductive pattern CP2, as will be described in detail below. The connecting pattern CP3 can include various suitable shapes in a planar view. In embodiments, the connecting pattern CP3 can include multiple conductive lines. The multiple conductive lines can have a fan-out shape in a planar view or a cross-sectional view. Considering the conductivity of the connecting pattern CP3, the connecting pattern CP3 can include at least one metal selected from, for example, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, and Cu. The connecting pattern CP3 can include a single layer or multiple layers.

[0101] like Figure 8D As shown, a second base layer 104 can be formed on the connection pattern CP3. The second base layer 104 can be configured to cover the connection pattern CP3.

[0102] The first substrate layer 102 and the second substrate layer 104 may comprise, for example, polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The first substrate layer 102 and the second substrate layer 104 may comprise the same or substantially the same materials as each other, but this disclosure is not limited thereto. For example, in another embodiment, the first substrate layer 102 and the second substrate layer 104 may comprise different materials as each other.

[0103] The second contact hole CNT2 can be formed in the second base layer 104 to expose a portion of the connection pattern CP3.

[0104] The first base layer 102 and the second base layer 104 may form at least a portion of the substrate 100. In some embodiments, an inorganic buffer layer may be disposed between the first base layer 102 and the second base layer 104.

[0105] The second conductive pattern CP2 can be formed on the second substrate layer 104. The second conductive pattern CP2 can be formed using the same or substantially the same process as one of the conductive layers comprising conductive material included at (e.g., in or above) the display unit 200. For example, in an embodiment, the second conductive pattern CP2 may include... Figure 9 The material of the gate electrode GE of the thin-film transistor TFT shown in the figure or related to Figure 9 The material of the upper electrode CE2 of the storage capacitor Cst shown is the same as or substantially the same as that of the capacitor. Considering the conductivity of the second conductive pattern CP2, the second conductive pattern CP2 may include at least one metal selected from, for example, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, and Cu. The second conductive pattern CP2 may comprise a single layer or multiple layers.

[0106] The display unit 200 may be formed at the display area DA (e.g., the first surface 100a or the front surface) of the second substrate 104 (e.g., in the middle), such as Figure 8E As shown in the diagram. For example, the display unit 200 may be formed on the second substrate layer 104 to cover the second conductive pattern CP2. For convenience, Figure 8E The stacked structure of display unit 200 is not shown in the figure. However, display unit 200 may include a structure formed by stacking and patterning at least one inorganic layer including an inorganic insulating material, at least one organic layer including an organic insulating material, and at least one conductive layer including a conductive material. Display unit 200 may include: a pixel circuit PC including a thin-film transistor and a storage capacitor, and a display element (e.g., such as an organic light-emitting diode OLED) electrically connected to the pixel circuit PC. See below for further details. Figure 9 The structure of the display unit 200 will be described in more detail.

[0107] After the display unit 200 is formed (or after the second conductive pattern CP2 is formed), the carrier substrate 10 can be separated (e.g., removed). After the carrier substrate 10 is separated, the process of etching the organic buffer layer 101 can be performed as follows: Figure 8F The process is performed as shown. For example, ashing and / or dry etching methods can be used as the etching process. In various embodiments, a portion (e.g., partially) or all (e.g., entirely) of the organic buffer layer 101 can be removed. For example, as shown... Figure 8G As shown, in one embodiment, the entire organic buffer layer 101 can be removed. In another example, in one embodiment, when a portion of the organic buffer layer 101 is removed, an opening 101OP of the first conductive pattern CP1 is exposed (e.g., see...). Figure 7 It can be formed in the organic buffer layer 101.

[0108] Figure 8G The diagram illustrates the structure obtained after the entire organic buffer layer 101 has been removed. (Refer to...) Figure 8G An enlarged view of the second surface 100b of the substrate 100 shows that, as a result of removing the organic buffer layer 101 by an etching process, the second surface 100b of the substrate 100 may have a surface roughness. The surface roughness of the second surface 100b of the substrate 100 may be greater than the surface roughness of the first surface 100a of the substrate 100 on which the etching process was not performed. In other words, the second surface 100b may be formed to be more irregular and rougher than the first surface 100a. In an embodiment, the surface roughness of the second surface 100b of the substrate 100 may be greater than the surface roughness of the opposite surface of the first base layer 102. In an embodiment, the second surface 100b of the substrate 100 may mean a surface of the first base layer 102 located on the back side of the substrate 100, and the first surface 100a of the substrate 100 may mean a surface of the second base layer 104 located on the upper surface of the substrate 100. However, the first surface 100a of the substrate 100 may mean another surface of the first base layer 102 arranged to face the second base layer 104.

[0109] Furthermore, the material composition 100S of the second surface 100b of the substrate 100, which reacts with the etching gas in the etching process, may differ from the material composition of the first surface 100a of the substrate 100. The characteristics of the material composition 100S can be examined from the compositional analysis of the surface of the substrate 100. For example, the material composition 100S of the second surface 100b of the substrate 100 may be the etching gas composition that may partially remain after the second surface 100b reacts with the etching gas. The material composition 100S of the second surface 100b may differ from the material composition of the substrate 100 at a depth (e.g., a specific depth) D of the substrate 100 from the second surface 100b. The material composition 100S of the second surface 100b is not limited to a specific element or compound and may be modified differently depending on the etching gas used. In this case, the material composition 100S of the second surface 100b may be a component not initially included in the material of the substrate 100.

[0110] The first conductive pattern CP1, which is exposed in the direction toward the second surface 100b of the substrate 100 by the above manufacturing process, can be electrically connected to the electronic structure 300.

[0111] Figure 9 and Figure 10 This is a schematic cross-sectional view of a part of a display device according to one or more embodiments.

[0112] Reference Figure 9A buffer layer 201 may be disposed on the substrate 100. The buffer layer 201 may be formed to prevent or substantially prevent impurities from penetrating into the semiconductor layer Act of the thin-film transistor (TFT). The buffer layer 201 may include an inorganic insulating layer, such as silicon nitride, silicon oxynitride, or silicon oxide. The buffer layer 201 may include a single-layer structure or a multilayer structure comprising one or more of the above-mentioned inorganic insulating materials.

[0113] The pixel circuit PC can be disposed on the buffer layer 201. The pixel circuit PC includes a thin-film transistor (TFT) and a storage capacitor Cst. The thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and / or a drain electrode DE (e.g., an electrode layer).

[0114] In an embodiment, Figure 9 The thin-film transistor TFT shown can be compared with a reference. Figure 2 The described driving thin-film transistor corresponds to this. The data line DL of the pixel circuit PC can be electrically connected to the switching thin-film transistor of the pixel circuit PC (e.g., see [link]). Figure 2 ).exist Figure 9 In the illustrated embodiment, the gate electrode GE is depicted as a top gate electrode disposed on the semiconductor layer Act, and a gate insulating layer 203 is present between the gate electrode GE and the semiconductor layer Act. However, this disclosure is not limited thereto, and in another embodiment, the thin-film transistor (TFT) may be a bottom gate transistor.

[0115] In one embodiment, the semiconductor layer Act may include polycrystalline silicon. In other embodiments, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, organic semiconductor, etc. In another embodiment, the pixel circuit PC may include multiple semiconductor layer Acts. In this case, at least one of the multiple semiconductor layer Acts may include polycrystalline silicon, and at least one other semiconductor layer Act may include oxide semiconductor.

[0116] The gate electrode GE may include a low-resistance metallic material. The gate electrode GE may include conductive materials such as Mo, Al, Cu, and titanium (Ti). The gate electrode GE may include a single layer or multiple layers comprising one or more of the above materials.

[0117] The gate insulating layer 203 is disposed between the semiconductor layer Act and the gate electrode GE, and may comprise an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The gate insulating layer 203 may comprise a single layer or multiple layers comprising one or more of the above materials.

[0118] The source electrode SE and drain electrode DE can be connection electrodes electrically connected to the semiconductor layer Act. The source electrode SE and drain electrode DE can be located on the same layer as the data line DL and can comprise the same or substantially the same material as the data line DL. The source electrode SE, drain electrode DE, and data line DL can comprise materials having a desired or suitable (e.g., good) conductivity. The source electrode SE and drain electrode DE can comprise conductive materials including, for example, Mo, Al, Cu, Ti, etc. The source electrode SE and drain electrode DE can comprise a single layer or multiple layers comprising one or more of the above materials. In an embodiment, the source electrode SE, drain electrode DE, and data line DL can comprise a multilayer comprising Ti / Al / Ti.

[0119] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2, which overlap each other and have a first interlayer insulating layer 205 between them. The storage capacitor Cst may be overlapped with a thin-film transistor (TFT). For example, Figure 9 The gate electrode GE of the illustrated thin-film transistor TFT is the lower electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst may not overlap with the thin-film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may include a conductive material such as Mo, Al, Cu, Ti, etc. The upper electrode CE2 may include a single layer or multiple layers comprising one or more of the above materials.

[0120] The first interlayer insulation layer 205 and the second interlayer insulation layer 207 may include inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The first interlayer insulation layer 205 and the second interlayer insulation layer 207 may include a single layer or multiple layers comprising one or more of the above-mentioned materials.

[0121] In this embodiment, the thin-film transistor (TFT) and the storage capacitor Cst may be covered by an inorganic insulating layer. The inorganic insulating layer can prevent, or substantially prevent, the exposure of wiring, including metals (e.g., aluminum) that may be damaged by etchants during the manufacturing process of the display device, to the etching environment. In this case, the inorganic insulating layer may cover the source electrode SE and the drain electrode DE, and may be disposed between the second interlayer insulating layer 207 and the first organic insulating layer 209.

[0122] The inorganic insulating layer may include inorganic insulating materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) and may comprise a single layer or multiple layers. In an embodiment, the inorganic insulating layer may include silicon nitride (SiN). x Inorganic insulating layers can have approximately The thickness. In other embodiments, the inorganic insulating layer may have approximately [a certain thickness]. or larger, approximately or larger, approximately or larger, approximately or larger, approximately or larger, approximately or larger, approximately or larger, approximately or larger, approximately or larger, approximately or larger, approximately or larger, approximately Or a greater thickness. In another embodiment, the inorganic insulating layer may have a thickness of approximately up to approximately The thickness is within the range.

[0123] A first organic insulating layer 209 may be disposed on a thin-film transistor (TFT). The first organic insulating layer 209 may include an approximately flat (e.g., flat or substantially flat) upper surface.

[0124] The pixel circuit PC can be electrically connected to the pixel electrode 221. For example, as... Figure 9 As shown, a contact metal layer CM (e.g., a second electrode layer) can be disposed between the thin-film transistor TFT and the pixel electrode 221. The contact metal layer CM can be connected to the thin-film transistor TFT via contact holes in the first organic insulating layer 209. The pixel electrode 221 can be connected to the contact metal layer CM via contact holes in the second organic insulating layer 211. The contact metal layer CM may include conductive materials such as Mo, Al, Cu, Ti, etc. The contact metal layer CM may include a single layer or multiple layers comprising one or more of the above materials. In an embodiment, the contact metal layer CM may include multiple layers comprising Ti / Al / Ti.

[0125] The first organic insulating layer 209 and the second organic insulating layer 211 may comprise organic insulating materials, such as general-purpose polymers (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), phenolic polymer derivatives, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or combinations thereof (e.g., mixtures). In an embodiment, the first organic insulating layer 209 and the second organic insulating layer 211 may comprise polyimide.

[0126] Pixel electrode 221 may be disposed on the second organic insulating layer 211. Pixel electrode 221 may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, pixel electrode 221 may include a reflective layer comprising, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or combinations thereof (e.g., compounds). In another embodiment, pixel electrode 221 may further include a layer comprising ITO, IZO, ZnO, or In2O3 that may be disposed above or below the aforementioned reflective layer.

[0127] A pixel defining layer 215 may be disposed on the pixel electrode 221. The pixel defining layer 215 may include an opening exposing the upper surface of the pixel electrode 221 and may cover the edge of the pixel electrode 221. In one embodiment, the pixel defining layer 215 may include an organic insulating layer. In another embodiment, the pixel defining layer 215 may include an inorganic insulating material, such as SiN. x Silicon oxynitride (SiON) and / or silicon oxide (SiO) x In another embodiment, the pixel defining layer 215 may include an organic insulating layer and an inorganic insulating layer.

[0128] Intermediate layer 222 includes emitting layer 222b. Intermediate layer 222 may include a first functional layer 222a below emitting layer 222b and / or a second functional layer 222c on emitting layer 222b. Emitting layer 222b may include a polymeric organic material or a low molecular weight organic material for emitting light of a desired color.

[0129] The first functional layer 222a may comprise a single layer or multiple layers. For example, when the first functional layer 222a comprises a polymer material, it may have a single-layer structure comprising a hole transport layer (HTL) and poly(3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). When the first functional layer 222a comprises a low molecular weight material, it may comprise a hole injection layer (HIL) and an HTL.

[0130] In some embodiments, the second functional layer 222c may be omitted. For example, when the first functional layer 222a and the emitter layer 222b comprise polymer materials, the second functional layer 222c may be included. The second functional layer 222c may comprise a single layer or multiple layers. The second functional layer 222c may comprise an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0131] The emitting layer 222b in the intermediate layer 222 can be disposed at each of the pixels P in the display area DA (e.g., in the middle) (e.g., in the middle or on top). The emitting layer 222b can be patterned to correspond to the pixel electrode 221. Unlike the emitting layer 222b, the first functional layer 222a and / or the second functional layer 222c in the intermediate layer 222 can be integrally formed with the display area DA and exist in both the display area DA and the intermediate layer 222 (e.g., in the middle).

[0132] The counter electrode 223 may include a conductive material with a low work function. For example, the counter electrode 223 may include a (semi-)transparent layer comprising, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, and alloys thereof. In another embodiment, the counter electrode 223 may further include a layer comprising ITO, IZO, ZnO, or In2O3 that may be disposed on a (semi-)transparent layer comprising one or more of the above-described materials. The counter electrode 223 may be disposed at the intermediate layer 222 (e.g., in the middle or on top) and at the display area DA (e.g., in the middle). The first functional layer 222a, the second functional layer 222c, and the counter electrode 223 may be formed using a thermal deposition method.

[0133] A capping layer 230 may be disposed on the counter electrode 223. For example, the capping layer 230 may comprise lithium fluoride (LiF) and may be formed using a thermal deposition method. However, this disclosure is not limited thereto, and in another embodiment, the capping layer 230 may be omitted.

[0134] Spacer 217 may be disposed on pixel defining layer 215. Spacer 217 may include an organic insulating material, such as polyimide. In other embodiments, spacer 217 may include an inorganic insulating material, or a combination of organic and inorganic insulating materials.

[0135] The spacer 217 may comprise a material different from that of the pixel defining layer 215, or may comprise the same or substantially the same material as that of the pixel defining layer 215. For example, the pixel defining layer 215 and the spacer 217 may be formed together in a masking process using a halftone mask. In an embodiment, the pixel defining layer 215 and the spacer 217 may comprise polyimide.

[0136] Organic light-emitting diodes (OLEDs) can be covered by encapsulation components. Figure 9 The illustrated organic light-emitting diode (OLED) is covered by an encapsulation component such as a thin-film encapsulation layer 240. However, this disclosure is not limited thereto. For example, as Figure 10 As shown, organic light-emitting diodes (OLEDs) can be isolated from external air via encapsulation components such as an upper substrate 500 or glass frit.

[0137] The thin-film encapsulation layer 240 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 9 The thin-film encapsulation layer 240 is shown to include a first inorganic encapsulation layer 241 and a second inorganic encapsulation layer 243, and an organic encapsulation layer 242 disposed between the first inorganic encapsulation layer 241 and the second inorganic encapsulation layer 243. In another embodiment, as known to those skilled in the art, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order of the organic and inorganic encapsulation layers can be modified differently.

[0138] The first inorganic encapsulation layer 241 and the second inorganic encapsulation layer 243 may include at least one inorganic material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 241 and the second inorganic encapsulation layer 243 may include a single layer or multiple layers comprising one or more of the above-mentioned materials.

[0139] The organic encapsulation layer 242 may include monomeric or polymeric materials. Polymeric materials may include, for example, acrylic resins, epoxy resins, polyimides, polyethylene, etc. In this embodiment, the organic encapsulation layer 242 may include acrylates.

[0140] The first inorganic encapsulation layer 241 may have a thickness different from that of the second inorganic encapsulation layer 243. For example, the first inorganic encapsulation layer 241 may have a thickness greater than that of the second inorganic encapsulation layer 243. However, this disclosure is not limited thereto, and in other embodiments, the second inorganic encapsulation layer 243 may have a thickness greater than that of the first inorganic encapsulation layer 241, or the first inorganic encapsulation layer 241 and the second inorganic encapsulation layer 243 may have the same or substantially the same thickness as each other.

[0141] Figure 11 and Figure 12 This is a schematic cross-sectional view of a part of a display device according to one or more embodiments.

[0142] Figure 11 and Figure 12 The diagram illustrates a structure in which wiring (e.g., data line DL or scan line SL) at the display unit 200 (e.g., middle or top) is connected to pads (e.g., first conductive pattern CL1) on the second surface 100b (e.g., back side) of the substrate 100 or connected to circuitry (e.g., first scan drive circuit 110 or second scan drive circuit 120).

[0143] The buffer layer 201 and the gate insulating layer 203 may extend to the edge 100e of the substrate 100. A second conductive pattern CL2 may be located on the gate insulating layer 203. In this case, the second conductive pattern CL2 may include the same or substantially the same material as the gate electrode GE. In another embodiment, the second conductive pattern CL2 may be located on the first interlayer insulating layer 205 extending to the inorganic region IRA. In this case, the second conductive pattern CL2 may include the same or substantially the same material as the upper electrode CE2 of the storage capacitor Cst. In another embodiment, the second conductive pattern CL2 may include multiple conductive lines. In this case, the multiple conductive lines may include: conductive lines that can be configured to alternate with each other, including conductive lines that include the same or substantially the same material as the gate electrode GE and conductive lines that include the same or substantially the same material as the upper electrode CE2.

[0144] The second conductive pattern CL2 can be a pattern connected to signal lines or voltage lines included in the pixel circuit PC. In an embodiment, the second conductive pattern CL2 can be connected to a data line DL. The data line DL can be electrically connected to the second conductive pattern CL2 via contact holes defined in the first interlayer insulating layer 205 and the second interlayer insulating layer 207.

[0145] The second conductive pattern CL2 can be connected to the connection pattern CL3 below the second conductive pattern CL2 via a second contact hole CNT2 extending through (e.g., penetrating) the gate insulating layer 203, the buffer layer 201, and the second base layer 104. The connection pattern CL3 can be connected to the first conductive pattern CL1 via a first contact hole CNT1 extending through (e.g., penetrating) the first base layer 102.

[0146] The second conductive pattern CL2 can be electrically connected to the first conductive pattern CL1 via the connecting pattern CL3. Figure 11 In this configuration, one side of the connecting pattern CL3 can be connected to the second conductive pattern CL2, and the other side of the connecting pattern CL3 can be connected to the first conductive pattern CL1.

[0147] The connection pattern CL3 on the first base layer 102 can have various suitable shapes in the planar view. In one or more embodiments, because the connection pattern CL3 is electrically connected to the data line DL, the connection pattern CL3 can have a fan-out shape in the planar view (e.g., as shown in the image). Figure 1B (as shown in the image).

[0148] The electronic structure 300 can be electrically connected to the first conductive pattern CL1 using a conductive material layer 310 as a dielectric. The electronic structure 300 may include a data driver configured to provide data signals to each of the pixels. In an embodiment, the electronic structure 300 may include the aforementioned data driver, wiring for providing a first power supply voltage and / or a second power supply voltage, and circuitry configured to provide various control signals to the pixels. The electronic structure 300 may be in IC form or FPCB form.

[0149] The conductive material layer 310 may include (e.g., may be) bumps included at (e.g., in the middle or on) the electronic structure 300. For example, bumps at the lower part (e.g., in the middle or on) of the electronic structure 300 may directly contact the first conductive pattern CL1 to be electrically connected to the first conductive pattern CL1. In another embodiment, the conductive material layer 310 may include (e.g., may be) a conductive adhesion layer, such as an anisotropic conductive film. In this case, bumps at (e.g., in the middle or on) the electronic structure 300 may contact conductive balls at (e.g., in the middle or on) the conductive material layer 310 including the anisotropic conductive film. When the conductive balls contact the first conductive pattern CL1, the electronic structure 300 may be electrically connected to the first conductive pattern CL1.

[0150] Figure 11 The illustration includes an electronic structure 300 in which a data driver IC is in chip form and electrically connected to a first conductive pattern CL1 via a conductive material layer 310. In this case, the conductive material layer 310 may be a bump corresponding to a portion of the IC, or an anisotropic conductive film comprising conductive balls. The IC may include the aforementioned data driver as well as wiring and circuitry configured to apply a power supply voltage. In another embodiment, the FPCB may be electrically connected to the first conductive pattern CL1 via a conductive material layer 310 comprising an anisotropic conductive film.

[0151] Reference Figure 12 The scan line SL included at the display unit 200 (e.g., in the middle or on top) can be electrically connected to the first scan drive circuit 110 (or the second scan drive circuit 120) via the connection pattern CL3. Figure 12 The illustration shows an embodiment in which the scan line SL and the second conductive pattern CL2 are provided integrally. However, in another embodiment, the scan line SL may be connected via a contact hole to the second conductive pattern CL2 provided on a different layer than the scan line SL.

[0152] The second conductive pattern CL2 can be electrically connected to the connecting pattern CL3 via the second contact hole CNT2. The connecting pattern CL3 can be electrically connected to the first conductive pattern CL1 included in the first scan driving circuit 110 (or the second scan driving circuit 120) via the first contact hole CNT1. In an embodiment, in Figure 12 In this process, the first conductive pattern CL1 may be the semiconductor layer of a thin-film transistor (TFT) included in the first scan driving circuit 110 (or the second scan driving circuit 120).

[0153] like Figure 12 As shown, the first substrate layer 102 includes a first scan driving circuit 110 and / or a second scan driving circuit 120, and the driving circuit includes thin-film transistors (TFTs), etc. Therefore, the first substrate layer 102 may include an inorganic layer and / or an organic / inorganic composite layer, and may include a multilayer structure.

[0154] Figure 12 The diagram illustrates a structure where scan line SL is connected to the first scan drive circuit 110 (or the second scan drive circuit 120). However, Figure 12 The structure can also be applied to cases where the light-emitting control line EL is connected to the light-emitting drive circuit. Furthermore, the display unit 200 can be configured as follows: Figure 1B The conductive layers shown, connected to the various circuits and / or wirings on the second surface 100b of the substrate 100, can be referenced. Figure 4 , Figure 6 , Figure 7 , Figure 11 and / or Figure 12 Connect using one or more methods as described.

[0155] Figure 13 The illustration shows an example application of the display device 1 according to an embodiment.

[0156] Reference Figure 13 Multiple display devices 1 according to one or more embodiments can be connected to each other to realize a large display device 1A (e.g., a tilted display). Therefore, when multiple display devices 1 are connected to each other, a boundary region (e.g., a non-display area) can be generated at the connection portion. As a comparative example, when the display device includes a display area on the front side of the substrate and a non-display area outside the display area on the front side of the substrate (e.g., surrounding the periphery of the display area), the width of the non-display area can be shown at the boundary region (e.g., in the middle or at the top) of the connection portion of the display devices. For example, when dividing the screen in a large display device, the width of the non-display area can be identified. Therefore, the quality of the large display device may be degraded.

[0157] Therefore, in the display device 1 according to one or more embodiments of the present disclosure, a first conductive pattern CL1 including pads connected to the electronic structure 300 can be disposed on the back side (e.g., the second surface 100b) of the substrate 100 and can be electrically connected to a second conductive pattern CL2 including wiring extending through (e.g., penetrating) the substrate 100 and disposed on the front side (e.g., the first surface 100a) of the substrate 100. Thus, the entire first surface 100a (e.g., the front side) of the substrate 100 can be the display area DA. Furthermore, the aforementioned electronic structure 300 and pads, as well as various driving circuits and wiring that may not be disposed at the display area DA (e.g., in the middle), can also be disposed on the second surface 100b (e.g., the back side) of the substrate 100 to overlap with the display area DA. Therefore, the entire (or substantially all) first surface 100a (e.g., the front side) of the substrate 100 can be implemented as the display area DA to achieve full display.

[0158] As described above, according to one or more exemplary embodiments of the present disclosure, a display device and a method of implementing the display device are provided, wherein a peripheral region outside the display area (e.g., surrounding the periphery of the display area) is reduced. However, the aspects and features of the present disclosure are not limited thereto.

[0159] Although some exemplary embodiments have been described, those skilled in the art will readily recognize that various modifications are possible in the exemplary embodiments without departing from the spirit and scope of this disclosure. It will be understood that the description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments, unless otherwise described. Therefore, it is to be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed herein, and various modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate, the substrate including a first surface, a second surface opposite to the first surface, a display area defined on the first surface and a non-display area defined on the second surface; A plurality of display elements at the display area on the first surface of the substrate; A power line that overlaps with the display area of ​​the substrate on the second surface, the power line having a ring shape and one side of the power line being open; A driving circuit on the second surface and overlapping with the display area of ​​the substrate; A first conductive pattern on the second surface of the substrate. as well as A second conductive pattern is located on the first surface of the substrate and is connected to the first conductive pattern via a contact hole extending through the substrate. Wherein, the surface roughness of the second surface of the substrate is greater than the surface roughness of the first surface of the substrate.

2. The display device according to claim 1, wherein, The material composition of the first surface is different from that of the second surface.

3. The display device according to claim 1, wherein, The first conductive pattern is embedded in the substrate.

4. The display device according to claim 3, wherein: The first conductive pattern includes: a surface, another surface opposite to the surface, and a side surface extending between the surface and the other surface to connect the surface to the other surface; The surface of the first conductive pattern and the plane of the first surface of the substrate are located on the same plane; and The other surface and the side surface of the first conductive pattern are in direct contact with the substrate.

5. The display device according to claim 1, wherein, The substrate includes: a first base layer and a second base layer on the first base layer, and The display device further includes a connection pattern disposed between the first substrate layer and the second substrate layer, and electrically connecting the first conductive pattern to the second conductive pattern.

6. The display device according to claim 5, wherein, The first conductive pattern is connected to the connection pattern via a first contact hole in the first substrate layer, and The connection pattern is connected to the second conductive pattern via a second contact hole in the second substrate layer.

7. The display device of claim 1, further comprising an electronic structure on the second surface and electrically connected to the first conductive pattern to overlap with the display area.

8. The display device according to claim 1, further comprising: Multiple first signal lines extending in a first direction within the display area, and multiple second signal lines extending in a second direction intersecting the first direction. The second conductive pattern is connected to either the plurality of first signal lines or the plurality of second signal lines.

9. The display device according to claim 8, further comprising a plurality of pixel circuits, the plurality of pixel circuits being located in the display area and respectively connected to the plurality of display elements, each of the plurality of pixel circuits comprising: A thin-film transistor, comprising: a semiconductor layer, a gate electrode at least partially overlapping the semiconductor layer, and an electrode layer connected to the semiconductor layer; and A storage capacitor, the storage capacitor comprising: a lower electrode corresponding to at least a portion of the gate electrode and an upper electrode on the lower electrode. The second conductive pattern comprises the same material as at least one of the gate electrode, the electrode layer, the lower electrode, and the upper electrode.

10. The display device according to claim 8, wherein, The plurality of second signal lines are electrically connected to the drive circuit via the second conductive pattern.

11. A display device, comprising: A substrate, the substrate comprising an organic buffer layer, a first base layer on the organic buffer layer, and a second base layer on the first base layer; Multiple display elements on the second substrate layer; A first conductive pattern between the organic buffer layer and the first substrate layer; A connection pattern is located between the first substrate layer and the second substrate layer, and is connected to the first conductive pattern via a first contact hole in the first substrate layer; A second conductive pattern is on the second substrate layer and is connected to the connection pattern via a second contact hole in the second substrate layer; A scan driving circuit, the scan driving circuit being located between the organic buffer layer and the second substrate layer, and including the first conductive pattern; as well as An electronic structure electrically connected to the first conductive pattern. The organic buffer layer has an opening that exposes at least a portion of the first conductive pattern.

12. The display device according to claim 11, wherein, The electronic structure is in direct contact with the first conductive pattern exposed through the opening.

13. A method of manufacturing a display device, the method comprising: An organic buffer layer with a thickness of 0.5 μm to 2.0 μm is formed on the carrier substrate; A first conductive pattern is formed on the organic buffer layer; A first base layer is formed on the organic buffer layer to cover the first conductive pattern; A connection pattern is formed on the first substrate layer, the connection pattern being connected to the first conductive pattern via a first contact hole extending through the first substrate layer; A display unit comprising a plurality of pixel circuits and a plurality of display elements respectively connected to the plurality of pixel circuits is formed on the first substrate layer to overlap with the first conductive pattern; The organic buffer layer is separated from the carrier substrate by an etching process; The first conductive pattern is exposed by removing at least a portion of the organic buffer layer; as well as The electronic structure is attached to the exposed first conductive pattern.

14. The method according to claim 13, wherein, Before forming the display unit, the method further includes: A second base layer is formed on the first base layer to cover the connection pattern; and A second conductive pattern is formed on the second substrate layer, and the second conductive pattern is connected to the connection pattern via a second contact hole extending through the second substrate layer.

15. The method according to claim 14, wherein, To expose the first conductive pattern, the method further includes removing all of the organic buffer layer to expose the surface of the first substrate layer.

16. The method according to claim 15, wherein, The surface roughness of the surface of the first substrate layer is greater than the surface roughness of another surface of the first substrate layer on the opposite side of the surface of the first substrate layer.

17. The method according to claim 15, wherein, The first conductive pattern is embedded in the first substrate layer.

18. The method according to claim 17, wherein, The exposed surface of the first conductive pattern lies on the same plane as the surface of the first substrate layer.

19. The method of claim 14, wherein, To expose the first conductive pattern, the method further includes forming an opening in the organic buffer layer corresponding to at least a portion of the first conductive pattern.

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