Semiconductor devices

Abstract

It is difficult to achieve both suppression of oscillation during switching and improvement of large current short-circuit tolerance. A semiconductor device is provided, comprising: a semiconductor layer of a first conductivity type having a first surface and a second surface, the second surface being located on the opposite side of the first surface; and a semiconductor layer of a second conductivity type being arranged in contact with the first surface of the semiconductor layer of the first conductivity type, the semiconductor layer of the first conductivity type having a plurality of impurity concentration peaks at different positions in a first direction from the first surface to the second surface, and an integrated concentration in the first direction from a first surface which is a bonding interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type to a boundary between a first impurity concentration peak closest to the first surface and a second impurity concentration peak second closest to the first surface, among the plurality of impurity concentration peaks, being less than a critical integrated concentration.

Description

[0001] This application is a divisional application of an application with an international application date of June 13, 2016, an international application number of PCT / JP2016 / 067597, an application number entering China of 201680003832.6, and an invention name of “Semiconductor Device”. Technical Field

[0002] The present invention relates to a semiconductor device. Background Art

[0003] Conventionally, an IGBT (insulated gate bipolar transistor) device is provided with a region doped with hydrogen ions or the like that functions as a field stop layer (FS layer) (for example, see Patent Documents 1 and 2).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application No. 2010-541266

[0007] Patent Document 2: Japanese Patent Application Publication No. 2014-99643 Summary of the invention

[0008] Technical issues

[0009] Normally, the FS layer is disposed near the collector of the IGBT. However, if the FS layer is disposed at a position closer to the emitter than usual, it is possible to suppress oscillation during switching and collector-emitter leakage current when the gate voltage is zero, and it is possible to improve RBSOA (reverse bias safe operating area). In particular, in order to suppress oscillation during switching, etc., the greater the concentration of the FS layer, the more effective it is. In contrast, if the FS layer is disposed at a position close to the collector, the drift layer becomes thicker than when it is disposed at a position close to the emitter, thereby improving high-current short-circuit tolerance and withstand voltage. In particular, in order to improve high-current short-circuit tolerance, etc., the smaller the concentration of the FS layer, the more effective it is. In this way, suppressing oscillation during switching, etc. and improving high-current short-circuit tolerance, etc. are opposite requirements for the FS layer, and therefore it is difficult to take both into account.

[0010] Here, the high-current short-circuit tolerance is defined as the current amount when the IGBT is destroyed by gradually increasing the gate voltage. In order to measure the high-current short-circuit tolerance, the time width of the switch on time is fixed, and the IGBT is turned on and off multiple times. As the number of switch on times increases, the input gate voltage is gradually increased, thereby flowing a large current through the IGBT. When the FS layer is set closer to the emitter than usual and the concentration of the FS layer is greater than usual, the movement of holes from the collector side is suppressed. As a result, the ratio of electrons in the current component of the IGBT becomes greater than that of holes, and the electric field on the collector side increases. If the electric field on the collector side increases too much, the IGBT is damaged.

[0011] Technical Solution

[0012] In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device may include: a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type. The semiconductor layer of the first conductivity type may have a first surface and a second surface. The second surface may be located on the opposite side of the first surface. The semiconductor layer of the second conductivity type may be arranged in a manner of contacting the first surface of the semiconductor layer of the first conductivity type. The semiconductor layer of the first conductivity type may have a plurality of impurity concentration peaks at different positions in a first direction. The first direction may be a direction from the first surface toward the second surface. The integral concentration from the first surface to the boundary between the first impurity concentration peak closest to the first surface and the second impurity concentration peak second closest to the first surface among the plurality of impurity concentration peaks may be less than the critical integral concentration. The first surface may be a bonding interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type in the first direction. The impurity concentration of the first impurity concentration peak may be higher than the impurity concentration of the second impurity concentration peak.

[0013] The integrated concentration from the first surface in the first direction to the boundary between the second impurity concentration peak and a third impurity concentration peak that is third closest to the first surface among the plurality of impurity concentration peaks may be equal to or lower than the critical integrated concentration.

[0014] The first conductivity type semiconductor layer has an impurity concentration peak other than protons at a position closer to the second surface than a third impurity concentration peak among the plurality of impurity concentration peaks.

[0015] The integrated concentration from the first surface in the first direction to the boundary between the third impurity concentration peak and the impurity concentration peak other than protons may be equal to or less than the critical integrated concentration.

[0016] The integrated concentration from the first surface to the third impurity concentration peak in the first direction may be equal to or less than the critical integrated concentration.

[0017] The first conductivity type semiconductor layer may have a second conductivity type impurity concentration peak between the second surface and the non-proton impurity concentration peak, the impurity concentration of which is higher than the non-proton impurity concentration peak.

[0018] From the front surface of the second conductive type semiconductor layer located on the opposite side of the bonding interface to the position of the first impurity concentration peak, the percentage of the total length of the first conductive type semiconductor layer and the second conductive type semiconductor layer in the first direction may be in the range of greater than 85% and less than 89%. From the front surface to the position of the second impurity concentration peak, the percentage of the total length of the first conductive type semiconductor layer and the second conductive type semiconductor layer in the first direction may be in the range of greater than 89% and less than 91%. From the front surface to the position of the third impurity concentration peak, the percentage of the total length of the first conductive type semiconductor layer and the second conductive type semiconductor layer in the first direction may be in the range of greater than 96% and less than 98%. From the front surface to the position of the impurity concentration peak other than protons, the percentage of the total length of the first conductive type semiconductor layer and the second conductive type semiconductor layer in the first direction may be in the range of greater than 98% and less than 100%.

[0019] The position of the first impurity concentration peak may be in a range of greater than 94 μm and less than 97 μm from the front side of the second conductive semiconductor layer located on the opposite side to the bonding interface. The position of the second impurity concentration peak may be in a range of greater than 97 μm and less than 100 μm from the front side. The position of the third impurity concentration peak may be in a range of greater than 105 μm and less than 108 μm from the front side. The position of the impurity concentration peak other than protons may be in a range of greater than 108 μm and less than 110 μm from the front side.

[0020] From the front surface of the second conductive type semiconductor layer located on the opposite side of the bonding interface to the position of the first impurity concentration peak, the percentage of the total length of the first conductive type semiconductor layer and the second conductive type semiconductor layer in the first direction may be in the range of greater than 77% and less than 81%. From the front surface to the position of the second impurity concentration peak, the percentage of the total length of the first conductive type semiconductor layer and the second conductive type semiconductor layer in the first direction may be in the range of greater than 81% and less than 86%. From the front surface to the position of the third impurity concentration peak, the percentage of the total length of the first conductive type semiconductor layer and the second conductive type semiconductor layer in the first direction may be in the range of greater than 93% and less than 97%. From the front surface to the position of the impurity concentration peak other than protons, the percentage of the total length of the first conductive type semiconductor layer and the second conductive type semiconductor layer in the first direction may be in the range of greater than 97% and less than 100%.

[0021] The position of the first impurity concentration peak may be in a range of greater than 54 μm and less than 57 μm from the front side of the second conductive type semiconductor layer located on the opposite side to the bonding interface. The position of the second impurity concentration peak may be in a range of greater than 57 μm and less than 60 μm from the front side. The position of the third impurity concentration peak may be in a range of greater than 65 μm and less than 68 μm from the front side. The position of the impurity concentration peak other than the proton may be in a range of greater than 68 μm and less than 70 μm from the front side.

[0022] The semiconductor device may further include a gate insulating film and a gate. The gate insulating film may be provided in a groove shape at least in a portion of the second conductivity type semiconductor layer. The gate may be provided in contact with the gate insulating film.

[0023] Donors constituting the first impurity concentration peak, the second impurity concentration peak, and the third impurity concentration peak may include composite donors based on hydrogen, vacancies, and oxygen.

[0024] The integrated concentration may reach the critical integrated concentration at a position closer to the second surface than the boundary between the second impurity concentration peak and a third impurity concentration peak that is third closest to the first surface among the plurality of impurity concentration peaks.

[0025] In a second aspect of the present invention, a semiconductor device is provided. The semiconductor device may include: a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type. The semiconductor layer of the first conductivity type may have a first surface and a second surface. The second surface may be located on the opposite side of the first surface. The semiconductor layer of the second conductivity type may be arranged in contact with the first surface of the semiconductor layer of the first conductivity type. The semiconductor layer of the first conductivity type may have a plurality of impurity concentration peaks at different positions in a first direction. The first direction may be a direction from the first surface toward the second surface. There may also be a plurality of first impurity concentration peaks between a first impurity concentration peak closest to the first surface among the plurality of impurity concentration peaks and a second impurity concentration peak closest to the second surface among the plurality of impurity concentration peaks, and the impurity concentrations of the plurality of first impurity concentration peaks may be lower than the impurity concentrations of the first impurity concentration peaks and the impurity concentrations of the second impurity concentration peaks.

[0026] It should be noted that the above technical solutions do not list all the necessary features of the present invention. In addition, the re-combination of these feature groups can also constitute an invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 1 is a diagram showing a cross section of an IGBT 100 according to the embodiment of the present invention.

[0028] Figure 2 (a) to (d) are diagrams showing the manufacturing process of the IGBT 100 .

[0029] Figure 3 The impurity concentration peak (P x ) and the boundary between the impurity concentration peak (V y )’s picture.

[0030] Figure 4 It is shown Figure 3 An enlarged view from position 80 [μm] to position 110 [μm].

[0031] Figure 5 The impurity concentration peak (P x ) versus the critical integral concentration.

[0032] Figure 6 It is shown Figure 5 An enlarged view from position 80 [μm] to position 110 [μm].

[0033] Figure 7 The impurity concentration peak (P x ) and the boundary between the impurity concentration peak (V y )’s picture.

[0034] Figure 8 It is shown Figure 7 An enlarged view from position 40 [μm] to position 70 [μm].

[0035] Fig. 9 The impurity concentration peak (P x ) versus the critical integral concentration.

[0036] Fig.10 is the critical electric field strength E relative to the donor concentration. c and the critical integral concentration n c Graph of the relationship.

[0037] Explanation of symbols

[0038] 10: Semiconductor substrate

[0039] 12: Drift layer

[0040] 14: Side 1

[0041] 16: Side 2

[0042] 18: Grassroots

[0043] 19: Positive

[0044] 20: Semiconductor layer

[0045] 22: FS layer

[0046] 24: Buffer layer

[0047] 26: Collector layer

[0048] 32: Gate

[0049] 34: Gate insulation film

[0050] 36: Interlayer insulation film

[0051] 42: Contact area

[0052] 44: Emitter region

[0053] 50: Gate terminal

[0054] 51: Emitter terminal

[0055] 52: Emitter

[0056] 53: Collector terminal

[0057] 54: Collector

[0058] 100: IGBT DETAILED DESCRIPTION

[0059] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the solution of the invention.

[0060] In this specification, n or p indicates that electrons or holes are majority carriers, respectively. In addition, for + or - marked on the upper right of n or p, + indicates that the carrier concentration is higher than that of the unmarked +, and - indicates that the carrier concentration is lower than that of the unmarked -. In addition, in the examples described in this specification, the first conductivity type indicates the n-type and the second conductivity type indicates the p-type, but in other examples, the first conductivity type may indicate the p-type and the second conductivity type may indicate the n-type.

[0061] Figure 1 The IGBT 100 is a semiconductor device that includes a semiconductor substrate 10 , an emitter electrode 52 and an interlayer insulating film 36 provided in contact with the front surface 19 of the semiconductor substrate 10 , and a collector electrode 54 provided in contact with the back surface of the semiconductor substrate 10 .

[0062] The semiconductor substrate 10 has n as a semiconductor layer of the first conductivity type. -The drift layer 12 is a p-type drift layer 12, and a p-type base layer 18 as a second conductivity type semiconductor layer. The drift layer 12 has a first surface 14 and a second surface 16. The first surface 14 is also the bonding interface between the drift layer 12 and the base layer 18. It should be noted that the second surface 16 is located on the opposite side of the first surface 14, which is consistent with the back side of the above-mentioned semiconductor substrate 10. The base layer 18 is provided in contact with the first surface 14. The base layer 18 has a front surface 19 located on the opposite side of the first surface 14 (bonding interface). It should be noted that Figure 1 In the embodiment of the present invention, the contact region 42 and the emitter region 44 are located on the front side 19 of the base layer 18. The front side 19 is also the front side of the semiconductor substrate 10.

[0063] The drift layer 12 has a semiconductor layer 20 on the second surface 16 side. The semiconductor layer 20 is formed by doping impurities from the second surface 16 of the drift layer 12. The semiconductor layer 20 has a plurality of impurity concentration peaks at different positions in the first direction. In this specification, a peak represents a peak of an impurity concentration of a first conductivity type or a second conductivity type. The semiconductor layer 20 has a FS layer 22 of a first conductivity type, a buffer layer 24 of a first conductivity type, and a collector layer 26 of a second conductivity type. The FS layer 22, the buffer layer 24, and the collector layer 26 are arranged side by side in the first direction in the order of the FS layer 22, the buffer layer 24, and the collector layer 26. The first direction refers to a direction from the first surface 14 toward the second surface 16. The first direction may also be referred to as a thickness direction of the semiconductor substrate 10 from the emitter 52 toward the collector 54.

[0064] The first conductivity type FS layer 22 has three impurity concentration peaks at different positions in the first direction. The FS layer 22 of this example has the function of preventing the depletion layer from expanding. That is, the FS layer 22 has the function of preventing the depletion layer extending from the vicinity of the first surface 14 from extending to the second surface 16. The FS layer 22 of this example is doped with protons (H + ) and having protons (H + ) caused by doping. The donor constituting the impurity concentration peak caused by proton doping is a composite donor, which is a composite donor based on a composite defect of hydrogen (H) introduced by proton implantation, a vacancy (V) formed as a crystal defect at the time of implantation, and oxygen (O) present in the semiconductor substrate 10, that is, a composite donor based on a VOH defect. The composite donor obtained from the VOH defect is also called a hydrogen-related donor.

[0065] The first conductivity type buffer layer 24 is a layer having a higher first conductivity type impurity concentration than the FS layer 22. That is, in this example, the FS layer 22 is n-type and the buffer layer 24 is n-type. +The buffer layer 24 may also have the function of preventing the depletion layer from expanding, similarly to the FS layer 22. The buffer layer 24 of this example has a first conductivity type impurity concentration peak other than protons. The buffer layer 24 of this example is a region doped with phosphorus (P). However, the buffer layer 24 may also be doped with protons (H) in a manner having a higher impurity concentration than the FS layer 22. + ) instead of phosphorus (P).

[0066] The second conductivity type collector layer 26 has a function of supplying holes from the semiconductor substrate 10. The collector layer 26 is a layer having an impurity concentration peak higher than the impurity concentration peak of the buffer layer 24. The collector layer 26 in this example is a region doped with boron (B).

[0067] The semiconductor substrate 10 further includes a trench-shaped gate 32, a gate insulating film 34, a first conductivity type emitter region 44, and a second conductivity type contact region 42. The gate insulating film 34 is provided in a trench shape at least in a portion of the base layer 18. The gate 32 is provided in contact with the gate insulating film 34.

[0068] It should be noted that in other examples, the IGBT 100 may also have a planar gate and gate insulating film. In the trench type IGBT 100, the amount of electrons entering the collector 54 from the emitter 52 is greater than that of the planar type. Therefore, the configuration of the semiconductor layer 20 of this example, which supplies holes from the collector layer 26 to alleviate the electric field concentration on the collector 54 side, is more effective in the trench type than in the planar type.

[0069] The gate electrode 32 is electrically isolated from the emitter electrode 52 by an interlayer insulating film 36 provided in contact with the front surface 19. A voltage is applied to the plurality of gate electrodes 32 via a gate terminal 50. The emitter electrode 52 is electrically connected to an emitter terminal 51, and the collector electrode 54 is electrically connected to a collector terminal 53.

[0070] When the gate 32 is turned on, a channel region is formed in the base layer 18 near the gate 32. At this time, if an appropriate potential difference is formed between the emitter 52 and the collector 54, current flows from the collector 54 to the emitter 52. The emitter region 44 is a region that provides a current path connected to the channel formation region.

[0071] The contact region 42 is a region that provides low contact resistance between the emitter electrode 52 and the semiconductor substrate 10. When the IGBT 100 is powered on, current flows from the collector electrode 54 to the emitter electrode 52 via the emitter region 44 and the contact region 42.

[0072] Figure 2(a) to (d) are figures showing the manufacturing process of IGBT100. (a) shows the process of forming a base layer 18 on the front side 19 of a semiconductor substrate 10 having a drift layer 12. The semiconductor substrate 10 can be an n-type single crystal substrate obtained by a floating zone (FZ) method, a single crystal substrate obtained by a Czochralski (CZ) method, or a single crystal substrate obtained by a magnetic field Czochralski (MCZ) method. In addition, the semiconductor substrate 10 can be 100 [μm] thick or more and have a resistivity of 50 [Ωcm] or more. The semiconductor substrate 10 in this example has a thickness of 110 [μm] and a resistivity of 70 [Ωcm] or more.

[0073] (b) shows a process of forming a gate 32, a gate insulating film 34, a contact region 42 and an emitter region 44, and then forming an interlayer insulating film 36 and an emitter 52 on the front side 19 of the semiconductor substrate 10. The gate 32 may be polysilicon, and the gate insulating film 34 may be silicon oxide. In addition, the contact region 42 may be a region of the second conductivity type doped with boron (B) as an impurity. The emitter region 44 may be a region of the first conductivity type doped with arsenic (As) or phosphorus (P) as an impurity. The interlayer insulating film 36 may be silicon oxide, and the emitter 52 may be an alloy of aluminum and silicon (Al-Si).

[0074] (c) shows a process of forming the FS layer 22, the buffer layer 24, and the collector layer 26 by doping impurities from the second surface 16 of the drift layer 12. In the process shown in (c) of this example, first, protons (H + ) to form a FS layer 22 having three peaks at different positions in the first direction. By adjusting the acceleration voltage of protons, the peak position of the impurity concentration can be adjusted.

[0075] In this example, in order to form the first peak at a position 15 μm away from the second surface 16, the dose is 1.0E13 cm -2 and an accelerating voltage of 1.00 MeV to incorporate protons (H + ). In addition, in order to form a second peak at a position 10 μm away from the second surface 16, a dose of 7.0E12 cm -2 and an accelerating voltage of 0.80 MeV to incorporate protons (H + ). Further, in order to form a third peak at a position 4.2 μm away from the second surface 16, a dose of 1.0E13 cm -2 and an accelerating voltage of 0.40 MeV to incorporate protons (H + ). However, after activation annealing, the peak position slightly deviates from the above-mentioned set position. It should be noted that E represents a power of 10, for example, 1.0E13 represents 1.0×10 13 .

[0076] After forming the FS layer 22, phosphorus (P) is doped to form the buffer layer 24. In this example, in order to form a peak at a position 0.7 μm away from the second surface 16, the dose is 1.7E12 cm -2 After forming the buffer layer 24, the phosphorus (P) was doped at 2.0E13 cm -2 Boron (B) is doped to form the collector layer 26 .

[0077] (d) shows a process of forming the collector electrode 54 in contact with the second surface 16. The collector electrode 54 can be formed by stacking titanium (Ti), nickel (Ni) and gold (Au) in this order. Then, the gate terminal 50, the emitter terminal 51 and the collector terminal 53 are provided. Thus, the IGBT 100 is completed.

[0078] Figure 3 The impurity concentration peak (P x ) and the boundary between the impurity concentration peak (V y ) in the present specification. x (x=1 to 5) indicates the peak of impurity concentration. Peak P x It is the maximum value of impurity concentration. x The position and the height of the impurity concentration can be set according to the acceleration voltage and impurity concentration of the doped impurities. y (y=1-4) represents the boundary between two Ps. Boundary V y For the two peaks P x The minimum impurity concentration between.

[0079] exist Figure 3 The vertical axis represents the impurity concentration [ / cm 3 ] and represents the net impurity concentration (net doping) combining the first conductivity type and the second conductivity type. Figure 3 Corresponds to Figure 1 The impurity concentration on A1-A2 of FIG. 1 is shown in FIG. 1 . The horizontal axis represents the position of the semiconductor substrate 10 in the first direction. The front surface 19 is set to position 0 [μm], and the second surface 16 is set to position 110 [μm]. The first surface 14 of the drift layer 12 is located between position 0 [μm] and position 10 [μm].

[0080] This example is a doping pattern of impurity concentration in an IGBT 100 having a withstand voltage of 1200 V. In this example, A1 - A2 is a region along the first direction from the front surface 19 to the second surface 16 .

[0081] In this specification, the first impurity concentration peak closest to the first surface 14 among the plurality of impurity concentration peaks is referred to as the first peak P. 1Similarly, the impurity concentration peak that is the second closest to the first surface 14 is referred to as the second peak P 2 The impurity concentration peak that is the third closest to the first surface 14 is called the third peak P 3 The impurity concentration peak that is fourth closest to the first surface 14 is called the fourth peak P 4 Furthermore, the peak closest to the second surface 16 is set as the fifth peak P 5 In this case, peak P 1 ~P 3 For protons (H + ) peak. 3 The fourth peak P closer to the second surface 16 4 In addition, the fifth peak P 5 Located between the second surface 16 and the fourth peak P 4 Between the fourth peak P 4 Compared with the high impurity concentration peak P 5 .

[0082] In addition, peak P 1 With P 2 There is a boundary V between 1 Similarly, peak P 2 With P 3 There is a boundary V between 2 , peak P 3 With P 4 There is a boundary V between 3 , peak P 4 With P 5 There is a boundary V between 4 .

[0083] In this example, at peak P 3 The peak P is referred to as the first doping pattern to the fourth doping pattern in order of impurity concentration from low to high. It should be noted that the integrated concentration described below is from low to high in the order of the first doping pattern to the fourth doping pattern. 3 The impurity concentration of the first doping pattern to the fourth doping pattern is different, but the peak P 3 The positions of are the same at the first to fourth doping patterns.

[0084] Figure 3 This is a graph showing four different doping patterns in one graph. Different types of doping patterns correspond to different IGBTs 100. One IGBT 100 as a finished product has one doping pattern. When the total dose of the first doping pattern is set to 1, the total dose of the second doping pattern is 1.4, the total dose of the third doping pattern is 2.6, and the total dose of the fourth doping pattern is 4.5. The difference in total dose is particularly significant near the third peak and the third boundary.

[0085] Four different first to fourth doping patterns are located at the third peak P 3-1 , P 3-2 , P 3-3 and P 3-4 and the third boundary V 3-1 、V 3-2 、V 3-3 and V 3-4 The four different doping patterns are consistent in other regions. For example, in the region from position 0 [μm] to position 100 [μm], the four different doping patterns are consistent. 4 、V 4 and P 5 The first to fourth doping patterns are also consistent. It should be noted that the impurity concentration of the third peak is calculated according to P 3-1 , P 3-2 , P 3-3 and P 3-4 The impurity concentration of the third boundary increases according to V 3-1 、V 3-2 、V 3-3 and V 3-4 The order becomes higher.

[0086] Figure 4 Show Figure 3 This is an enlarged view from position 80 [μm] to position 110 [μm]. Figure 4 It can be seen that the four different doping patterns have different 2 To the fourth peak P 4 Exactly the same outside the range.

[0087] It should be noted that at the second boundary V 2 and the third peak P in the first doping pattern 3-1 A third peak P 3-1 However, at the second boundary V 2 With the third peak P 3-1 The minimum and maximum values ​​of the impurity concentration between are not intentionally formed according to the acceleration voltage and impurity concentration of the doped impurities. Therefore, in this specification, they are not referred to as the peak P and the boundary V.

[0088] In this example, peak P 1 The position of the peak P is in the range of greater than 94 [μm] and less than 97 [μm]. 2 The position of the peak P is in the range of greater than 97 [μm] and less than 100 [μm]. 3 The peak P is located in the range of greater than 105 [μm] and less than 108 [μm].4 The position is in the range of greater than 108 [μm] and less than 110 [μm].

[0089] In this example, if the length of the drift layer 12 and the base layer 18 in the first direction is referred to as the substrate length L, the above range can be described in another way as follows. 1 The percentage of the position relative to the substrate length L is in the range of greater than 85% and less than 89%. 2 The percentage of the position relative to the substrate length L is in the range of greater than 89% and less than 91%. 3 The percentage of the position relative to the substrate length L is in the range of greater than 96% and less than 98%. In addition, from the 0 [μm] position to the peak P 4 The percentage of the position with respect to the substrate length L is in the range of greater than 98% and less than 100%.

[0090] Figure 5 The impurity concentration peak (P x ) and the critical integrated concentration. The vertical axis represents the integrated concentration [ / cm 2 ], the horizontal axis and Figure 3 and Figure 4 Similarly, the position in the first direction of the semiconductor substrate 10 is shown. In this example, due to the scale, the curve near 110 [μm] is omitted.

[0091] In this specification, the value obtained by integrating the impurity concentration along the first direction from the first surface 14, which is the bonding interface between the drift layer 12 and the base layer 18, to a specific position of the drift layer 12 is referred to as the integrated concentration. Further, in this specification, when a forward bias is applied between the collector 54 and the emitter 52 and the maximum value of the electric field intensity reaches the critical electric field intensity and avalanche breakdown occurs, when the first surface 14 is depleted to a specific position in the first direction of the drift layer 12, the value obtained by integrating the impurity concentration at the specific position is said to reach the critical integrated concentration. It should be noted that in the IGBT 100, the forward bias applied between the collector 54 and the emitter 52 means that the potential of the collector 54 is higher than the potential of the emitter 52.

[0092] When a forward bias is applied, the drift layer 12 is depleted up to a specific position where the critical integrated concentration is reached, but the region ahead of the specific position in the first direction is not depleted. 1 ~Peak P 3), the position of the critical integrated concentration in the drift layer 12 can be adjusted. The critical integrated concentration can be 1.2E12[ / cm 2 ] and 2.0E12[ / cm 2 ] The critical integral concentration in this case is about 1.4E12[ / cm 2 ].

[0093] In this example, in the first to fourth doping patterns, the first direction from the first surface 14 to the boundary V 1 The integrated concentration from the first surface 14 to the boundary V in the first direction is less than the critical integrated concentration. 2 The integrated concentration up to this point is below the critical integrated concentration.

[0094] Further, in this example, in the first doping pattern, from the first surface 14 to the boundary V in the first direction 3-1 The integrated concentration from the first surface 14 to the boundary V in the first direction is less than the critical integrated concentration. 3-2 The integrated concentration from the first surface 14 to the boundary V in the first direction is also less than the critical integrated concentration. 3-3 or Boundary V 3-4 The integrated concentration from the first surface 14 to the peak P in the first direction exceeds the critical integrated concentration. 3-2 The integrated concentration up to this point is below the critical integrated concentration.

[0095] Figure 6 It is shown Figure 5 This is an enlarged view from position 80 [μm] to position 110 [μm]. In this example, the peak P 1 , P 2 and P 3 These three peaks form the FS layer 22. 1 Since the critical integrated concentration is not reached at the FS layer 22, the FS layer 22 can be provided relatively close to the emitter 52 and at a relatively high concentration. Thus, the oscillation during switching can be suppressed. In addition, in this example, since the critical integrated concentration is reached in the FS layer 22 or the buffer layer 24, the extension of the depletion layer can be suppressed in the FS layer 22 or the buffer layer 24.

[0096] In this example, there is also a buffer layer 24 (peak P 4 ), and the collector layer 26 (peak P) with a higher concentration than the buffer layer 24 5 ). With respect to the impurity concentration of the FS layer 22 being 1.0E14 to 1.0E16, the peak P 4The impurity concentration is 1.0E16~1.0E17, peak P 5 The impurity concentration is 1.0E17~1.0E18. Figure 6 Peak P is not shown in the figure 4 HefengP 5 . In this example, the injection characteristics of carriers can be controlled by the buffer layer 24 and the collector layer 26. For example, the characteristics of hole injection into the drift layer 12 can be improved by the collector layer 26. Thus, since carriers can be supplied to the depletion layer when turned off, the rise of the electric field on the collector side can be mitigated. Therefore, the large current short-circuit tolerance can be improved. In this way, by adopting the structure of this example, it is possible to take into account both the suppression of oscillation during switching and the improvement of large current short-circuit tolerance.

[0097] In this example, the collector voltage Vcc = 680 [V], the gate on-resistance Rgon = 4.1 [Ω], the gate off-resistance Rgoff = 20 [Ω], the gate input pulse time = 2 [μs], the chip junction temperature Tj = 25 [℃], and the gate-emitter potential Vge is gradually increased from 15 [V] to conduct a large current short-circuit withstand test. The IGBT100 of this example was tested at a collector-emitter current Ic = 4300 [A / cm 2 ] was not destroyed. It should be noted that due to the limitation of the device, the 2 ] Stop the energization. The collector voltage Vcc is the voltage applied to the collector terminal 53. The gate-emitter potential Vge is the potential difference between the gate terminal 50 and the emitter terminal 51. The collector-emitter current Ic is the current flowing between the collector terminal 53 and the emitter terminal 51.

[0098] In this example, the collector voltage Vcc is 870 [V], the collector-emitter current Ice is 300 [A / cm 2 ], gate on-resistance Rgon=1[Ω], gate off-resistance Rgoff=1[Ω], floating inductance Ls=70[nH], chip junction temperature Tj=25[℃], and the gate-emitter potential Vge was turned off from 15[V] to 0[V] to perform a turn-off surge test. The peak value of the collector-emitter voltage Vce of the IGBT100 in this example at turn-off is 1125[V]. This means that the surge voltage at turn-off is suppressed more than before. In addition, the turn-off vibration is also suppressed more than before.

[0099] Figure 7 The impurity concentration peak (P x ) and the boundary between the impurity concentration peak (V y). The vertical and horizontal axes are Figure 3 In this example, the second surface 16 corresponds to the position 70 [μm]. In the IGBT 100 of this example, the thickness of the drift layer 12 is thinner than that of the first embodiment, and has a withstand voltage of 600V. In this example, the peak P x The position of is different from that of the first embodiment. Other aspects may be the same as those of the first embodiment. It should be noted that this example shows a doping pattern.

[0100] Figure 8 It is shown Figure 7 This is an enlarged view from position 40 [μm] to position 70 [μm]. In this example, peak P 1 The position of the peak P is in the range of greater than 54 [μm] and less than 57 [μm]. 2 The position of the peak P is located in the range of greater than 57 [μm] and less than 60 [μm]. 3 The peak P is located in the range of greater than 65 [μm] and less than 68 [μm]. 4 The position is in the range of greater than 68 [μm] and less than 70 [μm].

[0101] In this example, if the length of the drift layer 12 and the base layer 18 in the first direction is referred to as the substrate length L, the above range can be described in another way as follows. 1 The percentage of the position relative to the substrate length L is in the range of greater than 77% and less than 81%. 2 The percentage of the position relative to the substrate length L is in the range of greater than 81% and less than 86%. 3 The percentage of the position relative to the substrate length L is in the range of greater than 93% and less than 97%. In addition, from the 0 [μm] position to the peak P 4 The percentage of the position with respect to the substrate length L is in the range of greater than 97% and less than 100%.

[0102] Fig. 9 The impurity concentration peak (P x ) and the critical integrated concentration. In this example, the first direction from the first surface 14 to the boundary V 1 The integrated concentration from the first surface 14 to the peak P in the first direction is less than the critical integrated concentration. 2 The integrated concentration from the first surface 14 to the boundary V in the first direction is less than the critical integrated concentration. 2 The integrated concentration from the first surface 14 to the peak P in the first direction is also below the critical integrated concentration.3 The integrated concentration up to this point exceeds the critical integrated concentration.

[0103] The manufacturing process of the IGBT 100 in the second embodiment is basically the same as that in the first embodiment. The differences are listed as follows: The semiconductor substrate 10 in the second embodiment can be less than 100 [μm] thick and less than 50 [Ωcm] in resistivity. The thickness of the semiconductor substrate 10 in this example is 70 [μm] and the resistivity is 30 [Ωcm]. In the manufacturing process of the FS layer 22, in order to form the third peak at a distance of 4.2 μm from the second surface 16, the FS layer 22 is made of a 1.0E14 cm -2 The protons are doped with an accelerating voltage of 0.40 MeV. Other aspects are the same as those of the first embodiment. In this example, the same effects as those of the first embodiment can also be obtained.

[0104] In this example, the collector voltage Vcc = 360 [V], the gate on-resistance Rgon = 1 [Ω], the gate off-resistance Rgoff = 90 [Ω], the gate input pulse time = 2 [μs], the chip junction temperature Tj = -40 [℃], and the gate-emitter potential Vge is gradually increased from 15 [V] to conduct a large current short-circuit withstand test. The IGBT100 of this example was tested at a collector-emitter current Ic = 4300 [A / cm 2 ] was not destroyed. It should be noted that due to the limitation of the device, the 2 ]Stop powering on.

[0105] In this example, the collector voltage Vcc is 410 [V], the collector-emitter current Ice is 310 [A / cm 2 ], gate on-resistance Rgon=3.9[Ω], gate off-resistance Rgoff=3.9[Ω], floating inductance Ls=70[nH], chip junction temperature Tj=175[℃], and the gate-emitter potential Vge was turned off from 15[V] to 0[V] to conduct a shutdown surge test. The peak of the collector-emitter voltage Vce of the IGBT100 in this example at shutdown is about 700[V]. The surge voltage at shutdown is suppressed more than before. In addition, the shutdown vibration is also suppressed more than before.

[0106] Furthermore, in this example, the collector voltage Vcc = 350 [V], the collector-emitter current Ice = 490 [A / cm 2], and the other conditions were the same as those of the above-mentioned shutdown surge test. The peak of the collector-emitter voltage Vce of the IGBT100 in this example at shutdown was about 750 [V]. The surge voltage at shutdown was suppressed more than before. In addition, the shutdown vibration was also suppressed more than before.

[0107] Fig.10 is the critical electric field strength E relative to the donor concentration. c and the critical integral concentration n c The horizontal axis is the donor concentration (n-type impurity concentration) [ / cm 3 ], the left side of the vertical axis is the critical electric field strength E c [V / cm], the right side of the vertical axis is the critical integral concentration n c [ / cm 2 ]. Next, the critical electric field strength E relative to the donor concentration is c and critical integral concentration n c The corresponding relationship is explained.

[0108] In a planar pn junction, consider a one-sided abrupt junction in which the concentration of the p-type layer is several orders of magnitude higher than that of the n-type layer. In the case of a one-sided abrupt junction, if a reverse bias voltage is applied to the pn junction, the depletion layer can be considered to expand only in the n-type layer. Due to the application of the reverse bias voltage, the depletion layer expands, and the electric field intensity reaches a maximum value near the pn junction. If the maximum value of the electric field intensity reaches a predetermined value, avalanche breakdown occurs due to impact ionization.

[0109] In the first and second embodiments, the n-type layer corresponds to the drift layer 12 and the p-type layer corresponds to the base layer 18. Applying a reverse bias voltage to the pn junction corresponds to applying a forward bias voltage to the IGBT 100 such that the collector 54 has a higher potential than the emitter 52.

[0110] The value of the electric field strength that causes avalanche breakdown is called the critical electric field strength. Avalanche breakdown depends on the constituent elements of the semiconductor, the impurities doped into the semiconductor, and the concentration of the impurities. If the donor concentration is N D , the critical electric field strength is set to E C , and using the impact ionization coefficient of silicon (Si) for ionization integration, the critical electric field strength is expressed by equation 1.

[0111] [Formula 1]

[0112] E C =4010·(N D ) 1 / 8

[0113] From formula 1, we can see that if the donor concentration N is determined D , then the critical electric field strength E C In addition, when only one-dimensional direction (set as x direction) is considered, Poisson's equation is expressed by Formula 2.

[0114] [Formula 2]

[0115] dE / dx=(q / ε r ε 0 )(p-n+N D -N A )

[0116] Here, q is the elementary charge (1.602×10 -19 [C]), ε 0 is the vacuum dielectric constant (8.854×10 -14 [F / cm]), ε r is the relative dielectric constant of the material. In the case of silicon, ε r =11.9. p is the hole concentration, n is the electron concentration, N A is the acceptor concentration. Since only the n-type layer is considered in the single-sided abrupt junction, there is no acceptor (N A =0). Furthermore, if it is assumed that there is no depletion layer in which holes and electrons are completely depleted (n=p=0), equation 3 can be obtained by integrating equation 2 with depth x.

[0117] [Formula 3]

[0118] E=(q / ε r ε 0 )∫N D dx

[0119] The position of the pn junction is defined as the origin 0, and the position of the end of the depletion layer located on the opposite side of the pn junction in the n-type layer is defined as x. 0 And, if the entire depletion layer from 0 to x 0 If the maximum value of the electric field intensity distribution is set as E m , then E m It is expressed by formula 4.

[0120] [Formula 4]

[0121]

[0122] If the maximum value of the electric field intensity distribution E m Reaching the critical electric field strength E c , then Equation 4 is expressed by Equation 5.

[0123] [Formula 5]

[0124]

[0125] Both sides of Formula 5 are constants. The right side of Formula 5 is the range in which the n-type layer is completely depleted, and therefore, according to the definition described in this specification, it represents the critical integrated concentration n c . This gives the following formula 6. Formula 6 represents the critical integral concentration n c and the critical electric field strength E c Thus, the critical integral concentration n c becomes the critical electric field strength E c The corresponding constant.

[0126] [Formula 6]

[0127] E c (ε r ε 0 / q)=n c

[0128] It should be noted that Fig.10 In the above example, it is assumed that the donor concentration N D The concentration distribution in the x direction of the n-type layer is uniform. c Depends on the donor concentration N in the n-type layer D (Refer to Formula 5), ​​so the critical integral concentration n c It also depends on the donor concentration N in the n-type layer. D . At the donor concentration N D 1×10 13 ~1×10 15 ( / cm 3 ) in the range of critical integral concentration n c becomes 1.1×10 12 ~2.0×10 12 ( / cm 2 ). If the donor concentration is a concentration range that covers multiple orders of magnitude, it can be regarded as the critical integral concentration n c Almost constant.

[0129] For example, in the 1200 V example of the first embodiment, if the donor concentration N of the drift layer 12 is D Set to 6.1×10 13 ( / cm 3 ) (refer to Figure 3 and Figure 4 ), then according to formula 6, it can be evaluated as the critical integral concentration n c About 1.4×10 12 ( / cm 2). In the 600 V example of the second embodiment, if the donor concentration N of the drift layer 12 is D Set to 1.4×10 14 ( / cm 3 ) (refer to Figure 7 and Figure 8 ), then according to formula 6, it can be evaluated as the critical integral concentration n c About 1.55×10 12 ( / cm 2 ).

[0130] In the first and second embodiments, by adjusting the peak P x The position of the critical integral concentration n is adjusted c Since the first peak P in FS layer 22 1 The critical integral concentration n is not reached c , so the FS layer 22 can be set relatively close to the emitter 52 and with a relatively high concentration. As a result, oscillation during switching can be suppressed. In addition, leakage current can be suppressed, and RBSOA can be improved. Furthermore, by controlling the hole injection characteristics with the collector layer 26 having a higher impurity concentration than the FS layer 22, the critical integrated concentration n can be suppressed. c The critical electric field strength E at the position c As a result, it is not necessary to make the FS layer 22 closer to the collector 54 than before, and it is not necessary to make the concentration of the FS layer 22 lower than before, so that the large current short-circuit tolerance can be improved. In addition, the withstand voltage can also be improved. In this way, it is possible to achieve both the improvement of the large current short-circuit tolerance and the suppression of oscillation during switching.

[0131] In the case of including the FS layer 22 having a plurality of impurity concentration peaks as in the present application, the donor concentration N of the drift layer 12 is D It is not possible to make it uniform in the FS layer 22. However, due to the critical integral concentration n c Since it is the integrated amount in the first direction of the depletion layer expansion, the increase or decrease of the impurity concentration in the FS layer 22 is absorbed by the integrated amount.

[0132] In addition, the above discussion on the critical total impurity level is not limited to silicon, but can also be applied to silicon carbide (SiC), gallium nitride (GaN), diamond, gallium oxide (Ga 2 O 3 That is, for the impact ionization coefficient used to derive the equation 1 and the relative dielectric constant in the equation 2, it is sufficient to use the values ​​of the respective substances.

[0133] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the manner in which such changes or improvements are made can obviously also be included in the technical scope of the present invention.

[0134] It should be noted that the execution order of each process such as actions, processes, steps and stages in the device, system, program and method shown in the claims, specifications and drawings can be implemented in any order as long as "earlier than" or "in advance" is not specifically stated, and the previous processing results are not used in the subsequent processing. Even if the action flow in the claims, specifications and drawings is explained using "first" or "next" for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: have: A first semiconductor layer of a first conductivity type having a first surface and a second surface, wherein the second surface is located on an opposite side of the first surface; and A second semiconductor layer of a second conductivity type is provided on the first surface side of the first semiconductor layer, The first semiconductor layer has: A drift layer of the first conductivity type is arranged in contact with the first surface; Three or more impurity concentration peaks of the first conductivity type are arranged at different positions in a first direction from the first surface to the second surface on the side closer to the second surface than the drift layer, and the impurity concentration is higher than the impurity concentration of the drift layer; as well as A third semiconductor layer of the second conductivity type is provided in contact with the second surface, The integrated concentration from the first surface to the second impurity concentration peak which is the second closest to the second surface among the impurity concentration peaks is smaller than the critical integrated concentration, The critical integral concentration is defined by the following formula: E c (ε r ε0 / q)=n c Among them, n c is the critical integral concentration, E c is the critical electric field strength, ε0 is the vacuum dielectric constant, ε r is the relative dielectric constant of the semiconductor, q is the elementary charge, The second semiconductor layer has a front surface located on the opposite side to the first semiconductor layer, The percentage of the length from the front surface to the position of the second impurity concentration peak relative to the first length of the first semiconductor layer and the second semiconductor layer in the first direction is greater than 96% and less than 98%, A percentage of a length from the front surface to a position closest to an impurity concentration peak of the first surface relative to the first length is greater than 85%.

2. A semiconductor device, characterized in that: have: A first semiconductor layer of a first conductivity type having a first surface and a second surface, wherein the second surface is located on an opposite side of the first surface; and A second semiconductor layer of a second conductivity type is provided on the first surface side of the first semiconductor layer, The first semiconductor layer has: A drift layer of the first conductivity type is arranged in contact with the first surface; Three or more impurity concentration peaks of the first conductivity type are arranged at different positions in a first direction from the first surface to the second surface on the side closer to the second surface than the drift layer, and the impurity concentration is higher than the impurity concentration of the drift layer; as well as A third semiconductor layer of the second conductivity type is provided in contact with the second surface, The integrated concentration from the first surface to the second impurity concentration peak which is the second closest to the second surface among the impurity concentration peaks is smaller than the critical integrated concentration, The critical integral concentration is defined by the following formula: E c (ε r ε0 / q)=n c Among them, n c is the critical integral concentration, E c is the critical electric field strength, ε0 is the vacuum dielectric constant, ε r is the relative dielectric constant of the semiconductor, q is the elementary charge, A first impurity concentration peak closest to the second surface among the three or more impurity concentration peaks has impurities other than protons, The second semiconductor layer has a front surface located on the opposite side to the first semiconductor layer, The percentage of the length from the front surface to the position of the second impurity concentration peak relative to the first length of the first semiconductor layer and the second semiconductor layer in the first direction is greater than 93% and less than 97%, A percentage of a length from the front surface to a position closest to an impurity concentration peak of the first surface relative to the first length is greater than 77%.

3. A semiconductor device, characterized in that: have: A first semiconductor layer of a first conductivity type having a first surface and a second surface, wherein the second surface is located on an opposite side of the first surface; and A second semiconductor layer of a second conductivity type is provided on the first surface side of the first semiconductor layer, The first semiconductor layer has: A drift layer of the first conductivity type is arranged in contact with the first surface; Three or more impurity concentration peaks of the first conductivity type are arranged at different positions in a first direction from the first surface to the second surface on the side closer to the second surface than the drift layer, and the impurity concentration is higher than the impurity concentration of the drift layer; as well as A third semiconductor layer of the second conductivity type is provided in contact with the second surface, The integrated concentration from the first surface to the second impurity concentration peak which is the second closest to the second surface among the impurity concentration peaks is smaller than the critical integrated concentration, The critical integral concentration is defined by the following formula: E c (ε r ε0 / q)=n c Among them, n c is the critical integral concentration, E c is the critical electric field strength, ε0 is the vacuum dielectric constant, ε r is the relative dielectric constant of the semiconductor, q is the elementary charge, A first impurity concentration peak closest to the second surface among the three or more impurity concentration peaks has impurities other than protons, The three or more impurity concentration peaks include a plurality of impurity concentration peaks between the first impurity concentration peak and the impurity concentration peak closest to the first surface, The impurity concentrations of the plurality of impurity concentration peaks are lower than the impurity concentration of any one of the first impurity concentration peak and the impurity concentration peak closest to the first surface.

4. The semiconductor device according to claim 3, wherein: The first conductivity type semiconductor layer has a second conductivity type impurity concentration peak between the second surface and the first impurity concentration peak, the impurity concentration of which is higher than the first impurity concentration peak.

5. The semiconductor device according to claim 3 or 4, characterized in that: Also features: a gate insulating film provided in a groove shape at least on a portion of the second semiconductor layer; and The gate is provided in contact with the gate insulating film.

6. The semiconductor device according to claim 3 or 4, characterized in that: Among the three or more impurity concentration peaks, the impurity concentration peaks other than the first impurity concentration peak include composite donors based on hydrogen, vacancies, and oxygen.

7. The semiconductor device according to claim 3 or 4, characterized in that: The drift layer has a donor concentration of 1×10 13 / cm 3 ~1×10 15 / cm 3 area.

8. A semiconductor device, characterized in that: have: A first semiconductor layer of a first conductivity type having a first surface and a second surface, wherein the second surface is located on an opposite side of the first surface; and A second semiconductor layer of a second conductivity type is provided on the first surface side of the first semiconductor layer, The first semiconductor layer has: A drift layer of the first conductivity type is arranged in contact with the first surface; Three or more impurity concentration peaks of the first conductivity type are arranged at different positions in a first direction from the first surface to the second surface on the side closer to the second surface than the drift layer, and the impurity concentration is higher than the impurity concentration of the drift layer; as well as A third semiconductor layer of the second conductivity type is provided in contact with the second surface, The integrated concentration from the first surface to the second impurity concentration peak which is the second closest to the second surface among the impurity concentration peaks is smaller than the critical integrated concentration, The critical integral concentration is defined by the following formula: E c (ε r ε0 / q)=n c Among them, n c is the critical integral concentration, E c is the critical electric field strength, ε0 is the vacuum dielectric constant, ε r is the relative dielectric constant of the semiconductor, q is the elementary charge, A first impurity concentration peak closest to the second surface among the three or more impurity concentration peaks has impurities other than protons, Among the three or more impurity concentration peaks, an impurity concentration of an impurity concentration peak that is closest to the first surface is higher than an impurity concentration of an impurity concentration peak that is second closest to the first surface.

9. A semiconductor device, characterized in that: have: A first semiconductor layer of a first conductivity type having a first surface and a second surface, wherein the second surface is located on an opposite side of the first surface; and A second semiconductor layer of a second conductivity type is provided on the first surface side of the first semiconductor layer, The first semiconductor layer has: A drift layer of the first conductivity type is arranged in contact with the first surface; Three or more impurity concentration peaks of the first conductivity type are arranged at different positions in a first direction from the first surface to the second surface on the side closer to the second surface than the drift layer, and the impurity concentration is higher than the impurity concentration of the drift layer; as well as A third semiconductor layer of the second conductivity type is provided in contact with the second surface, The integrated concentration from the first surface to the second impurity concentration peak which is the second closest to the second surface among the impurity concentration peaks is smaller than the critical integrated concentration, The critical integral concentration is defined by the following formula: E c (ε r ε0 / q)=n c Among them, n c is the critical integral concentration, E c is the critical electric field strength, ε0 is the vacuum dielectric constant, ε r is the relative dielectric constant of the semiconductor, q is the elementary charge, A first impurity concentration peak closest to the second surface among the three or more impurity concentration peaks has impurities other than protons, The integrated concentration from the first surface in the first direction to a boundary between the second impurity concentration peak and the non-proton impurity concentration peak is smaller than the critical integrated concentration.

10. A semiconductor device, characterized in that: have: A first semiconductor layer of a first conductivity type having a first surface and a second surface, wherein the second surface is located on an opposite side of the first surface; and A second semiconductor layer of a second conductivity type is provided on the first surface side of the first semiconductor layer, The first semiconductor layer has: A drift layer of the first conductivity type is arranged in contact with the first surface; Three or more impurity concentration peaks of the first conductivity type are arranged at different positions in a first direction from the first surface to the second surface on the side closer to the second surface than the drift layer, and the impurity concentration is higher than the impurity concentration of the drift layer; as well as A third semiconductor layer of the second conductivity type is provided in contact with the second surface, The integrated concentration from the first surface to the second impurity concentration peak which is the second closest to the second surface among the impurity concentration peaks is smaller than the critical integrated concentration, The critical integral concentration is defined by the following formula: E c (ε r ε0 / q)=n c Among them, n c is the critical integral concentration, E c is the critical electric field strength, ε0 is the vacuum dielectric constant, ε r is the relative dielectric constant of the semiconductor, q is the elementary charge, A first impurity concentration peak closest to the second surface among the three or more impurity concentration peaks has impurities other than protons, The second semiconductor layer has a front surface located on the opposite side to the first semiconductor layer, The three or more impurity concentration peaks include a third impurity concentration peak that is third closest to the second surface and a fourth impurity concentration peak that is fourth closest to the second surface, The percentage of the length from the front surface to the position of the fourth impurity concentration peak relative to the first length of the first semiconductor layer and the second semiconductor layer in the first direction is greater than 85% and less than 89%, The percentage of the length from the front surface to the position of the third impurity concentration peak relative to the first length is greater than 89% and less than 91%, The percentage of the length from the front surface to the position of the second impurity concentration peak relative to the first length is greater than 96% and less than 98%, A percentage of a length from the front surface to the position of the first impurity concentration peak relative to the first length is in a range of greater than 98% and less than 100%.

11. A semiconductor device, characterized in that: have: A first semiconductor layer of a first conductivity type having a first surface and a second surface, wherein the second surface is located on an opposite side of the first surface; and A second semiconductor layer of a second conductivity type is provided on the first surface side of the first semiconductor layer, The first semiconductor layer has: A drift layer of the first conductivity type is arranged in contact with the first surface; Three or more impurity concentration peaks of the first conductivity type are arranged at different positions in a first direction from the first surface to the second surface on the side closer to the second surface than the drift layer, and the impurity concentration is higher than the impurity concentration of the drift layer; as well as A third semiconductor layer of the second conductivity type is provided in contact with the second surface, The integrated concentration from the first surface to the second impurity concentration peak which is the second closest to the second surface among the impurity concentration peaks is smaller than the critical integrated concentration, The critical integral concentration is defined by the following formula: E c (ε r ε0 / q)=n c Among them, n c is the critical integral concentration, E c is the critical electric field strength, ε0 is the vacuum dielectric constant, ε r is the relative dielectric constant of the semiconductor, q is the elementary charge, A first impurity concentration peak closest to the second surface among the three or more impurity concentration peaks has impurities other than protons, The three or more impurity concentration peaks include a third impurity concentration peak that is third closest to the second surface and a fourth impurity concentration peak that is fourth closest to the second surface, The length from the second surface to the position of the fourth impurity concentration peak is within a range of less than 16 μm and greater than 13 μm, The length from the second surface to the position of the third impurity concentration peak is within a range of less than 13 μm and greater than 10 μm, The length from the second surface to the position of the second impurity concentration peak is within a range of less than 5 μm and greater than 2 μm, The length from the second surface to the position of the first impurity concentration peak is within a range of less than 2 μm and greater than 0 μm.

12. A semiconductor device, characterized in that: have: A first semiconductor layer of a first conductivity type having a first surface and a second surface, wherein the second surface is located on an opposite side of the first surface; and A second semiconductor layer of a second conductivity type is provided on the first surface side of the first semiconductor layer, The first semiconductor layer has: A drift layer of the first conductivity type is arranged in contact with the first surface; Three or more impurity concentration peaks of the first conductivity type are arranged at different positions in a first direction from the first surface to the second surface on the side closer to the second surface than the drift layer, and the impurity concentration is higher than the impurity concentration of the drift layer; as well as A third semiconductor layer of the second conductivity type is provided in contact with the second surface, The integrated concentration from the first surface to the second impurity concentration peak which is the second closest to the second surface among the impurity concentration peaks is smaller than the critical integrated concentration, The critical integral concentration is defined by the following formula: E c (ε r ε0 / q)=n c Among them, n c is the critical integral concentration, E c is the critical electric field strength, ε0 is the vacuum dielectric constant, ε r is the relative dielectric constant of the semiconductor, q is the elementary charge, A first impurity concentration peak closest to the second surface among the three or more impurity concentration peaks has impurities other than protons, The second semiconductor layer has a front surface located on the opposite side to the first semiconductor layer, The three or more impurity concentration peaks include a third impurity concentration peak that is third closest to the second surface and a fourth impurity concentration peak that is fourth closest to the second surface, The percentage of the length from the front surface to the position of the fourth impurity concentration peak relative to the first length of the first semiconductor layer and the second semiconductor layer in the first direction is greater than 77% and less than 81%, The percentage of the length from the front surface to the position of the third impurity concentration peak relative to the first length is greater than 81% and less than 86%, The percentage of the length from the front surface to the position of the second impurity concentration peak relative to the first length is greater than 93% and less than 97%, A percentage of a length from the front surface to the position of the first impurity concentration peak relative to the first length is in a range of greater than 97% and less than 100%.

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