Method for manufacturing wafer capacitor, wafer capacitor and electronic device

Abstract

The invention discloses a method for manufacturing a wafer capacitor, a wafer capacitor and an electronic device. The method comprises: thinning the back side of a wafer substrate so that the thickness of the wafer substrate reaches a set thickness, the wafer substrate is provided with a channel, the channel is filled with a copper column, the side provided with the channel is the front side, and the side opposite to the front side is the back side; patterning the back side of the wafer substrate, etching the back side of the wafer substrate to obtain a groove, and exposing the copper column in the channel of the wafer substrate through the groove; preparing a contact metal layer in the groove to obtain a wafer electrode; selecting two wafer electrodes, and preparing a dielectric material layer on the surface of the contact metal layer of one of the wafer electrodes; the dielectric constant of the dielectric material layer is greater than 200C 2 / (N·M 2 ); bonding two wafer electrodes to form a wafer capacitor, wherein the dielectric material layer is located between the contact metal layers of the two wafer electrodes. The wafer capacitor provided by the present invention can withstand high voltage and is not easily broken down.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a wafer capacitor, a wafer capacitor and an electronic device. Background Art

[0002] In the semiconductor manufacturing process, the existing technology uses MOS tubes (Metal-Oxide-Semiconductor, also known as field effect tubes) to replace capacitors for circuit design, or uses existing technology to make capacitors on a two-dimensional plane. This capacitor has a small capacity and a large impedance at the same frequency. In the existing technical solution, two layers of metal can be used, and silicon dioxide or other dielectric materials are deposited in the middle using the CVD method (i.e., vapor deposition method). Due to the problem of material stress, the deposited dielectric material is thin and the material is relatively simple, which is not suitable for making large capacitors. At the same time, due to the defects of the current manufacturing process, it is not resistant to high voltage and is easy to break down, which can easily damage the entire circuit. Summary of the invention

[0003] The embodiments of the present application provide a method for manufacturing a wafer capacitor, a wafer capacitor and an electronic device. The wafer capacitor provided by the present invention can withstand high voltage and is not easily broken down.

[0004] The present invention provides a method for manufacturing a wafer capacitor, comprising:

[0005] The back side of the wafer substrate is thinned so that the thickness of the wafer substrate reaches a set thickness, the wafer substrate is provided with a channel, the channel is filled with a copper column, the side of the wafer substrate provided with the channel is the front side, and the side opposite to the front side is the back side;

[0006] Performing image processing on the back side of the wafer substrate, and etching the back side of the wafer substrate to obtain a groove, through which the copper column in the channel of the wafer substrate is exposed;

[0007] preparing a contact metal layer in the groove to obtain a wafer electrode;

[0008] Select two wafer electrodes, prepare a dielectric material layer on the surface of the contact metal layer of one of the wafer electrodes, and the dielectric constant of the dielectric material layer is greater than 200C 2 / (N·M 2 );

[0009] The two wafer electrodes are bonded to form a wafer capacitor, and the dielectric material layer is located between the contact metal layers of the two wafer electrodes.

[0010] Preferably, the step of preparing a contact metal layer in the groove to obtain a wafer electrode comprises:

[0011] A first copper layer, a second copper layer, a nickel layer and a gold layer are sequentially prepared on the surface of the groove to form the contact metal layer.

[0012] Preferably, the step of sequentially forming a first copper layer, a second copper layer, a nickel layer and a gold layer on the surface of the groove comprises:

[0013] forming the first copper layer on the bottom surface and sidewalls of the groove,

[0014] forming the second copper layer on the surface of the first copper layer and the sidewall of the groove,

[0015] forming the nickel layer on the surface of the second copper layer, and

[0016] The gold layer is formed on the surface of the nickel layer.

[0017] Preferably, a ratio of a thickness of the second copper layer on the sidewall of the groove to a thickness of the second copper layer on the bottom surface of the groove is between 1:5 and 1:10.

[0018] Preferably, the method of sequentially preparing a first copper layer, a second copper layer, a nickel layer and a gold layer on the surface of the groove further comprises:

[0019] After the first copper layer is formed on the bottom surface and side wall of the groove by a sputtering method, and the second copper layer is formed on the surface of the first copper layer and the side wall of the groove by an electroplating method, the first copper layer and the second copper layer on the side wall of the groove are removed by a wet etching method.

[0020] Preferably, the dielectric material layer is made of titanium dioxide and / or barium titanate; and the etching solution used in the wet etching is one of ferric chloride, ferric sulfate and hydrogen peroxide.

[0021] Preferably, the etching of the wafer substrate to obtain the groove is specifically performed as follows:

[0022] The wafer substrate is etched by a deep silicon dry etching method to obtain the groove.

[0023] Preferably, the step of preparing a dielectric material layer on the surface of the contact metal layer of one of the wafer electrodes comprises:

[0024] The dielectric material layer is prepared on the surface of the contact metal layer by spin coating or printing.

[0025] The present invention also provides a wafer capacitor, which is manufactured by the above manufacturing method.

[0026] The present invention also provides an electronic device, which includes a wafer capacitor prepared by the above-mentioned manufacturing method. The implementation of the present invention has the following beneficial effects: the dielectric material layer of the wafer capacitor in the present invention is made of titanium dioxide and / or barium titanate, and the dielectric constants of titanium dioxide and barium titanate are greater than those of silicon dioxide, and can withstand high voltage and are not easily broken down, and can be used as a large-capacity capacitor. Moreover, the dielectric constants of titanium dioxide and barium titanate are relatively large, and the thickness of the dielectric material layer can be prepared to be thinner, which solves the problem of material stress and is not easily broken. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 It is a flow chart of the method for manufacturing a wafer capacitor provided by the present invention;

[0029] Figure 2 is a schematic diagram of a wafer substrate provided by the present invention;

[0030] Figure 3 The present invention provides Figure 2 Schematic diagram of the channels in the wafer substrate;

[0031] Figure 4 The present invention provides Figure 2 A schematic diagram of forming a groove on the back side of the wafer substrate;

[0032] Figure 5 The present invention provides Figure 4 A schematic diagram of preparing a contact metal layer and a dielectric material layer on the groove;

[0033] Figure 6 It is a schematic diagram of bonding two wafer electrodes to form a wafer capacitor provided by the present invention. Specific implementation methods

[0034] In order to enable technicians in the technical field to which the present application belongs to understand the present application more clearly, the technical solution of the present application is described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0035] The present invention provides a method for manufacturing a wafer capacitor, such as Figure 1 As shown, the manufacturing method includes:

[0036] S1. Yes Figure 2 The back side of the wafer substrate 1 is thinned so that the thickness of the wafer substrate 1 reaches a set thickness; Figure 3 As shown, the wafer substrate 1 is provided with a channel, and the channel 11 is filled with a copper pillar 2. The side of the wafer substrate 1 provided with the channel 11 is the front side, and the side opposite to the front side is the back side. The wafer substrate 1 is a silicon wafer substrate, that is, the channel 11 is formed on the silicon material layer, and the channel 11 is filled with a copper pillar 2.

[0037] A wafer is provided. The wafer comprises a first surface and a second surface which are arranged opposite to each other. A hole 11 is arranged on the first surface. The second surface is thinned so that the thickness of the wafer 1 reaches a set thickness.

[0038] In one embodiment, Figure 2 The back side of the wafer substrate 1 shown is thinned, and the thinning process can be performed by a wafer back side grinding process or a semiconductor grinding machine.

[0039] The via 11 can be drilled by TSV (Through Silicon Via) method.

[0040] S2, image processing is performed on the back side of the wafer substrate 1, and the back side of the wafer substrate 1 is etched to obtain Figure 4 The groove 12 is shown, through which the copper pillar 2 in the hole 11 of the wafer substrate 1 is exposed.

[0041] S3, such as Figure 5 As shown, a contact metal layer 3 is prepared in the groove 12 to obtain a wafer electrode, which includes a wafer substrate 1 , a copper column 2 and a contact metal layer 3 .

[0042] S4. Select two wafer electrodes and prepare a dielectric material layer 4 on the surface of the contact metal layer 3 of one of the wafer electrodes.

[0043] S5, such as Figure 6 As shown, two wafer electrodes are bonded to form a wafer capacitor, that is, a silicon wafer capacitor, and a dielectric material layer 4 is located between the contact metal layer 3 of the two wafer electrodes; the wafer capacitor includes two wafer electrodes and a dielectric material layer 4, and the dielectric constant of the dielectric material layer is greater than 200C 2 / (N·M 2 Bonding is a technology that directly combines two homogeneous or heterogeneous semiconductor materials with clean and atomically flat surfaces under certain conditions through surface cleaning and activation treatment, and bonds the wafers into one through van der Waals forces, molecular forces, and even atomic forces.

[0044] A contact metal layer 3 is prepared in the groove 12 to obtain a wafer electrode, including:

[0045] A first copper layer 31 , a second copper layer 32 , a nickel layer 33 and a gold layer 34 are sequentially prepared on the surface of the groove 12 to form a contact metal layer 3 .

[0046] A first copper layer 31, a second copper layer 32, a nickel layer 33 and a gold layer 34 are sequentially prepared on the surface of the groove 12, including:

[0047] A first copper layer 31 is formed on the bottom surface and side wall of the groove 12 by a sputtering method, a second copper layer 32 is formed on the surface of the first copper layer 31 and the side wall of the groove 12 by an electroplating method, a nickel layer 33 is formed on the surface of the second copper layer 32 by a chemical plating method, and a gold layer 34 is formed on the surface of the nickel layer 33 by a chemical plating method.

[0048] Forming the first copper layer 31 by sputtering can ensure uniform thickness of the first copper layer 31, thereby ensuring uniform thickness between the two electrodes of the capacitor. Forming the second copper layer 32 by electroplating can ensure thickening of the capacitor electrodes at a fast speed.

[0049] The nickel layer 33 is arranged between the second copper layer 32 and the gold layer 34, and can separate the second copper layer 32 from the gold layer 34 to prevent atomic diffusion between the second copper layer 32 and the gold layer 34; when copper atoms diffuse into the gold layer 34, oxygen in the dielectric material layer 4 will penetrate into the gold layer 34, oxidizing the copper, causing the capacitor electrode to rust, thereby reducing the service life of the capacitor. Therefore, the preparation method adopted by the present invention can also prevent the capacitor electrode from being oxidized, thereby extending the service life of the wafer capacitor.

[0050] Furthermore, the capacitor electrodes in the present invention use copper as electrodes, and any electrode can be used as the positive and negative electrodes, thereby increasing the application range of the wafer capacitor.

[0051] In one embodiment, the nickel layer 33 may be a nickel metal layer or a nickel-palladium alloy layer 34 .

[0052] A first copper layer 31, a second copper layer 32, a nickel layer 33 and a gold layer 34 are sequentially prepared on the surface of the groove 12, further comprising:

[0053] After a first copper layer 31 is formed on the bottom surface and side wall of the groove 12 by a sputtering method, and a second copper layer 32 is formed on the surface of the first copper layer 31 and the side wall of the groove 12 by an electroplating method, the first copper layer 31 and the second copper layer 32 on the side wall of the groove 12 are removed by a wet etching method.

[0054] A thicker copper layer can be formed on the surface of the first copper layer 31 by electroplating, so that the thickness of the second copper layer 32 can meet the requirements of the capacitor electrode. The thickness of the second copper layer is greater than that of the first copper layer.

[0055] When the first copper layer 31 and the second copper layer 32 on the side wall of the groove 12 are removed by wet etching, the etching solution used in the wet etching can be one of ferric chloride, ferric sulfate, and hydrogen peroxide. The etching solution is isotropic, and by adjusting the etching time of the etching solution, the first copper layer 31 and the second copper layer 32 on the side wall of the groove 12 can be etched away, and the first copper layer 31 and the second copper layer 32 on the bottom surface of the groove 12 are retained.

[0056] Among them, the first copper layer 31 is formed on the bottom surface and side wall of the groove 12 by sputtering method, the thickness ratio of the first copper layer 31 on the bottom surface of the groove 12 and the first copper layer 31 on the side wall of the groove 12 is 1:1, and the thickness of the second copper layer on the side wall of the groove 12 and the thickness of the second copper layer 32 on the bottom surface of the groove 12 are in the ratio of 1:5 to 1:10.

[0057] When the second copper layer 32 is prepared by the electroplating method, current is connected through the copper pillar 2 in the channel 11 and the first copper layer 31 electrically connected to the copper pillar 2. By controlling the size and time of the current connected to the first copper layer 31, the thickness of the second copper layer 32 reaches a preset thickness value. Combined with the thickness ratio of the second copper layer 32 on the bottom surface of the groove 12 and the second copper layer 32 on the side wall of the groove 12 obtained by electroplating experience, the thickness value of the second copper layer on the side wall of the groove 12 is calculated.

[0058] In another embodiment, the thickness of the second copper layer on the side wall of the groove 12 may also be measured by a scanning electron microscope or an X-ray analysis method.

[0059] When the first copper layer 31 and the second copper layer 32 on the side wall of the groove 12 are removed by wet etching, the etching time of the etching solution can be calculated based on the etching speed of the etching solution and the thickness of the second copper layer on the side wall of the groove 12, thereby accurately controlling the progress of the wet etching.

[0060] The wafer substrate 1 is etched to obtain the groove 12, specifically:

[0061] The wafer substrate 1 is etched by a deep silicon dry etching method to obtain a groove 12 .

[0062] A dielectric material layer 4 is prepared on the surface of the contact metal layer 3 of one of the wafer electrodes, comprising:

[0063] The dielectric material layer 4 is prepared on the surface of the contact metal layer 3 by spin coating or printing.

[0064] The material of the dielectric material layer 4 may include titanium dioxide and / or barium titanate. The dielectric constant of barium titanate is between 1800 and 2700°C. 2 / (N·M 2 ), the dielectric constant of titanium dioxide is between 500C 2 / (N·M 2) below, the dielectric constant of barium titanate is relatively high. When a large-capacity capacitor is required, barium titanate can be used to prepare the dielectric material layer 4. When the prepared capacitor capacity is relatively small, titanium dioxide material can be used to prepare the dielectric material layer 4. When the prepared capacitor capacity is moderate, a mixed material of titanium dioxide and barium titanate can be selected to prepare the dielectric material layer 4.

[0065] Traditional capacitors use silicon dioxide as a dielectric material, which has a small dielectric constant and a small capacitance. The dielectric constant of titanium dioxide and barium titanate is greater than that of silicon dioxide. Therefore, the capacity of the wafer capacitor provided by the present invention is larger than that of traditional capacitors, and the energy storage effect is better. When the circuit is powered off, it can discharge slowly.

[0066] The present invention also provides a wafer capacitor, which is manufactured by the above manufacturing method.

[0067] The present invention also provides an electronic device, which comprises a wafer capacitor manufactured by the above manufacturing method.

[0068] In summary, the wafer capacitor manufacturing method, wafer capacitor and electronic device provided by the present invention can directly prepare capacitors on wafers, and there is no need to prepare capacitors on PCB (Printed Circuit Board), which saves the use area of ​​PCB. Moreover, the material of the dielectric material layer 4 of the wafer capacitor in the present invention is titanium dioxide and / or barium titanate, and the dielectric constant of titanium dioxide and barium titanate is greater than that of silicon dioxide, which can withstand high voltage and is not easy to be broken down, and can be used as a large-capacity capacitor. In addition, in the prior art, capacitors are prepared on PCBs, and then the capacitors on PCBs are integrated onto wafers. The length of the wire between the capacitors on PCBs and wafer integrated circuits is greater than 1 mm. The wafer capacitor provided in the present invention has a wire length between the capacitor and the wafer integrated circuit that is equivalent to the depth of the channel 11, that is, 50 microns to 200 microns. Therefore, the length of the wire between the wafer capacitor provided by the present invention and the wafer integrated circuit is relatively short, which reduces the transmission distance of the current and reduces the power consumption of the circuit.

[0069] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0070] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for manufacturing a wafer capacitor, characterized in that: include: The back side of the wafer substrate is thinned so that the thickness of the wafer substrate reaches a set thickness, the wafer substrate is provided with a channel, the channel is filled with a copper column, the side of the wafer substrate provided with the channel is the front side, and the side opposite to the front side is the back side; Patterning the back side of the wafer substrate, and etching the back side of the wafer substrate to obtain a groove, through which the copper column in the channel of the wafer substrate is exposed; preparing a contact metal layer in the groove to obtain a wafer electrode; Select two wafer electrodes, prepare a dielectric material layer on the surface of the contact metal layer of one of the wafer electrodes, and the dielectric constant of the dielectric material layer is greater than 200C2 / (N·M 2 ); Bonding the two wafer electrodes to form a wafer capacitor, wherein the dielectric material layer is located between the contact metal layers of the two wafer electrodes; Characterized in that the step of preparing a contact metal layer in the groove to obtain a wafer electrode comprises: Sequentially preparing a first copper layer, a second copper layer, a nickel layer and a gold layer on the surface of the groove to form the contact metal layer; The step of sequentially forming a first copper layer, a second copper layer, a nickel layer and a gold layer on the surface of the groove comprises: forming the first copper layer on the bottom surface and sidewalls of the groove, forming the second copper layer on the surface of the first copper layer and the sidewall of the groove, forming the nickel layer on the surface of the second copper layer, and forming the gold layer on the surface of the nickel layer; The ratio of the thickness of the second copper layer on the side wall of the groove to the thickness of the second copper layer on the bottom surface of the groove is between 1:5 and 1:10; The step of sequentially preparing a first copper layer, a second copper layer, a nickel layer and a gold layer on the surface of the groove further comprises: After the first copper layer is formed on the bottom surface and side wall of the groove by a sputtering method, and the second copper layer is formed on the surface of the first copper layer and the side wall of the groove by an electroplating method, the first copper layer and the second copper layer on the side wall of the groove are removed by a wet etching method.

2. The method for manufacturing a wafer capacitor according to claim 1, characterized in that: The material of the dielectric material layer is titanium dioxide and / or barium titanate; the etching solution used in the wet etching is one of ferric chloride, ferric sulfate and hydrogen peroxide.

3. The method for manufacturing a wafer capacitor according to claim 1, characterized in that: The etching of the wafer substrate to obtain the groove is specifically performed as follows: The wafer substrate is etched by a deep silicon dry etching method to obtain the groove.

4. The method for manufacturing a wafer capacitor according to claim 1, characterized in that: The step of preparing a dielectric material layer on the surface of the contact metal layer of one of the wafer electrodes comprises: The dielectric material layer is prepared on the surface of the contact metal layer by spin coating or printing.

5. A wafer capacitor, characterized in that: The wafer capacitor is manufactured by the manufacturing method according to any one of claims 1 to 4.

6. An electronic device, characterized in that: A wafer capacitor prepared by the manufacturing method according to any one of claims 1 to 4.

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