Semiconductor device

Abstract

Semiconductor devices and methods of fabricating the same are disclosed. An exemplary semiconductor device includes a substrate; a gate structure disposed on the substrate and a channel region of the semiconductor device, wherein the gate structure includes a gate stack and a spacer disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed on the gate stack, wherein the first metal layer laterally contacts the spacer on the gate dielectric layer and the gate electrode; and a gate via disposed on the first metal layer.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular to a semiconductor structure including vias. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to multiple generations of ICs, each featuring smaller and more complex circuits than the previous generation. During the evolution of ICs, functional density (the number of interconnects per unit chip area) typically increases while geometry (the smallest element (or line) that can be created using manufacturing processes) decreases. This miniaturization process usually benefits by increasing production efficiency and reducing associated costs.

[0003] However, this miniaturization also increases the complexity of integrated circuit manufacturing and production, and similar advancements are needed in integrated circuit manufacturing and production to achieve the aforementioned progress. For example, it has been observed that due to the miniaturization of semiconductor devices, the space between the gate via and the source / drain (S / D) contacts is gradually decreasing. If the space between the gate via and the S / D contact is too small, for example, due to the displacement of the stacked mask during manufacturing, leakage current may occur between the gate and the S / D conductive material. Furthermore, due to the smaller contact area between the metal gate and the gate via, and between the S / D contact and the S / D via, and the different conductive materials, the resistance between the metal gate and the gate via, and between the S / D contact and the S / D via, will be higher. Therefore, improvements are needed. Summary of the Invention

[0004] A semiconductor device includes: a substrate; a gate structure disposed on the substrate and on a channel region of the semiconductor device, wherein the gate structure includes a gate stack and a plurality of spacers disposed along a plurality of sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed on the gate stack, wherein the first metal layer laterally contacts the spacers on the gate dielectric layer and the gate electrode; and a gate via disposed on the first metal layer.

[0005] A semiconductor device includes: a substrate including a channel region formed between a plurality of source / drain regions; a gate structure disposed on the channel region of the substrate, wherein the gate structure includes a gate stack and a plurality of spacers disposed along a plurality of sidewalls of the gate stack, and the top surfaces of the spacers are located above the top surface of the gate stack; a plurality of source / drain contacts disposed on an S / D region of the substrate; a first metal layer disposed on the S / D contacts; an S / D via having the same material as the first metal layer and disposed on the first metal layer, wherein the area of ​​the bottom surface of the S / D via is smaller than the area of ​​the bottom surface of the first metal layer; and an interlayer dielectric (ILD) layer formed on the gate structure, wherein the top surface of the ILD layer extends on the top surface of the spacers.

[0006] A method for forming a semiconductor device includes: forming a fin on a substrate; forming a gate structure on a channel region of the fin, wherein the gate structure includes a gate stack and a plurality of spacers disposed along a plurality of sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; epitaxially growing a source / drain component on the source / drain region of the fin; forming a first interlayer dielectric layer on the S / D component and the substrate; etching the gate structure including the spacers and the gate stack such that the top surface of the spacers is lower than the top surface of the first ILD layer, and the top surface of the gate stack is lower than the top surface of the spacers; and forming a first metal layer on the gate stack by a bottom-up growth process, wherein the first metal layer covers the top surface of the gate stack including the gate dielectric layer and the gate electrode. Attached Figure Description

[0007] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0008] Figure 1 Flowcharts of exemplary methods for manufacturing semiconductor devices are shown according to some embodiments of this disclosure;

[0009] Figure 2 A three-dimensional perspective view of an exemplary semiconductor device is shown according to some embodiments of the present disclosure;

[0010] Figure 3 , Figure 4 , Figures 6 to 15 , Figure 17 ,and Figure 18 Some embodiments of the present disclosure illustrate that... Figure 1 An example of the intermediate stage of the method in semiconductor devices along Figure 2 The cross-sectional view of plane AA shown;

[0011] Figure 5A A three-dimensional perspective view of the contact profile between the gate electrode and the first metal layer of an exemplary semiconductor device is shown according to some embodiments of the present disclosure.

[0012] Figures 5B to 5F According to some embodiments of this disclosure, the contact profile between the gate electrode and the first metal layer of an exemplary semiconductor device is shown along... Figure 5A A cross-sectional view of face BB shown in the figure;

[0013] Figure 16 A three-dimensional perspective view of the contact profile between the S / D contact and the second metal layer of an exemplary semiconductor device is shown according to some embodiments of the present disclosure;

[0014] Figure 19 A three-dimensional perspective view of the contact contours of the gate electrode, the first metal layer, and the gate via of an exemplary semiconductor device is shown according to some embodiments of the present disclosure.

[0015] Figure 20 A three-dimensional perspective view of the contact contours of an S / D contact, a second metal layer, and an S / D via of an exemplary semiconductor device is shown according to some embodiments of this disclosure; and

[0016] Figures 21-23 According to some embodiments of this disclosure, an exemplary semiconductor device is shown along... Figure 2 The cross-sectional view of plane AA shown.

[0017] Explanation of reference numerals in the attached figures:

[0018] 100: Method

[0019] 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130: Operations

[0020] 200: Semiconductor devices

[0021] 202: Substrate

[0022] 204: Fins

[0023] 210: Gate structure

[0024] 211: Gate Stack

[0025] 212: Gate dielectric layer

[0026] 213: Gate electrode

[0027] 214: Gate spacer (spacer)

[0028] 214-1: Dielectric layer

[0029] 214-2: Pattern Layer

[0030] 218: Trench

[0031] 218-1: Top

[0032] 218-2: Bottom

[0033] 220: Epitaxial S / D component (S / D component)

[0034] 230: First ILD layer

[0035] 240: First metal layer

[0036] 242: Sacrifice Layer

[0037] 244: Contact opening

[0038] 246: First isolation component

[0039] 248: Second ILD layer

[0040] 250: S / D contact

[0041] 252: Second isolation component

[0042] 252': Isolation layer

[0043] 254: Second metal layer

[0044] 260: Contact Etching Stop Layer (CESL layer)

[0045] 270: Third ILD layer

[0046] 280: S / D contact hole

[0047] 290: Gate via

[0048] AA,BB:face

[0049] H1, H2, H3, H4, H5, H6: Height

[0050] x, y, z: Direction Detailed Implementation

[0051] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For instance, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact.

[0052] Furthermore, reference values ​​and / or letters may be repeated in various embodiments of the present invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed. Additionally, the formation of a component located on, connected to, and / or coupled to another component in this disclosure may include embodiments where the components are in direct contact, or embodiments where additional components are inserted into these components such that the components are not in direct contact. Furthermore, spatially relative terms, such as “lower,” “higher,” “horizontal,” “vertical,” “above,” “on,” “below,” “under,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.), are used to facilitate the description of the relationship between one component and another in this disclosure. Spatially relative terms are used to include different orientations of components contained in the device. Moreover, when a number or a range of numbers is described using terms such as “about,” “approximately,” and similar terms, these terms are used to cover numbers falling within a reasonable range including the described number, such as falling within + / - 10% of the described number or other values ​​understood by those skilled in the art. For example, the term "about 5nm" covers a scale range from 4.5nm to 5.5nm.

[0053] This disclosure generally relates to semiconductor devices and their fabrication. Due to the miniaturization of semiconductor devices, the geometric dimensions between different components are becoming increasingly smaller, which can cause problems and impair the performance of the semiconductor device. For example, in existing manufacturing processes, the space between the gate via and the S / D contact can be very small due to hard mask stack-up shifts and / or manufacturing variations. The short path between the gate via and the S / D contact can lead to leakage current. This can result in low yield and impaired semiconductor device performance. Furthermore, there is always a need to reduce the resistance between the metal gate and the gate via, and / or between the S / D contact and the S / D via.

[0054] This disclosure provides a semiconductor device with hard mask isolation between a gate via and an S / D contact. The hard mask isolation may include one or more film layers that provide a safe space between the gate via and the S / D contact, thereby mitigating leakage current. Furthermore, to reduce the resistance between the gate and the gate via and / or between the S / D contact and the S / D via, this disclosure provides a semiconductor device in which an additional metal layer is disposed between the gate and the gate via and / or between the S / D contact and the S / D via. The additional metal layer comprises the same material as the via and increases the contact area between the contact (e.g., a metal gate or S / D contact) and the via (e.g., a gate via or S / D via), thereby reducing the contact resistance between them. Therefore, the performance of the semiconductor device can be improved. Of course, these advantages are merely illustrative, and no particular advantage is essential for any particular embodiment.

[0055] Figure 1 A flowchart of a method 100 for forming a semiconductor device 200 (hereinafter referred to as "device 200") is shown according to some embodiments of this disclosure. Method 100 is merely an example and is not intended to limit this disclosure to anything beyond the scope expressly described in the relevant applications. Additional operations may be performed before, during, and after method 100, and some described operations may be replaced, deleted, or moved for other embodiments of the above method. Method 100 is described below in conjunction with other accompanying drawings, which show various three-dimensional and cross-sectional views of device 200 in intermediate steps of method 100. In particular, Figure 2 A three-dimensional diagram of the originally provided device 200 is shown. Figure 3 , Figure 4 , Figures 6 to 15 , Figure 17 and Figure 18 The device 200 is shown along Figure 2 The cross-sectional view of plane AA (i.e., along the x-direction) is shown.

[0056] Device 200 may be an intermediate device manufactured during integrated circuit (IC) fabrication, and may include: static random-access memory (SRAM) and / or other logic circuitry; passive components, such as resistors, capacitors, and inductors; and active components, such as p-type FETs (PFETs), n-type FETs (NFETs), Fin-like FETs (FinFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. Device 200 may be a core region (typically referred to as a logic region), memory region (e.g., a static random access memory (SRAM) region), analog region, edge region (typically referred to as an input / output (I / O) region), dummy region, other suitable region, or a combination thereof, which is a portion of an integrated circuit (IC). In some embodiments, device 200 may be a portion of an IC chip, a system-on-a-chip (SoC), or a portion thereof. This disclosure is not limited to any particular number of devices or device regions, or to any particular device configuration. For example, although the illustrated device 200 is a three-dimensional FET device, this disclosure may also provide embodiments for fabricating planar FET devices.

[0057] Reference Figure 1 and Figure 2In operation 102, method 100 provides a semiconductor device 200. The semiconductor device 200 includes one or more fins 204 protruding from a substrate 202 and separated by an isolation structure 208. One or more gate structures 210 are disposed on the substrate 202 and the fins 204. The gate structures 210 define a channel region (covered by the gate structure 210), a source region, and a drain region (both referred to as source / drain (S / D) regions) of the fins 204. The gate structure 210 may include a gate stack 211 and gate spacers 214 disposed along the sidewalls of the gate stack 211. The gate structure 210 may include other components, such as one or more gate dielectric layers (disposed on the substrate 202 and below the gate stack 211), a barrier layer, a glue layer, a capping layer, other suitable films, or combinations thereof. Various gate hard mask layers may be disposed on the gate stack 211 and may be considered part of the gate structure 210. Device 200 may also include an S / D component 220 epitaxially grown on substrate 202 and fin 204. Device 200 may also include an interlayer dielectric (ILD) layer 230 disposed on substrate 202 and fin 204 and between gate structure 210. It should be understood that the components included in device 200 are not limited to those shown above. Figure 2 The number and configuration shown. Device 200 may contain more or fewer components, such as more or fewer gate structures and / or S / D components.

[0058] exist Figure 2 In the depicted embodiments, device 200 includes a substrate (wafer) 202. In the depicted embodiments, substrate 202 is a bulk substrate comprising silicon. Alternatively or additionally, the bulk substrate comprises another element semiconductor, compound semiconductor, alloy semiconductor, or a combination thereof. Alternatively, substrate 202 is a semiconductor-on-insulator (SII) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SII substrate can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Substrate 202 may include various doped regions. In some embodiments, the substrate 202 includes an n-type doped region (e.g., an n-type wall) doped with an n-type dopant, wherein the n-type dopant is, for example, phosphorus (e.g.,31 P), arsenic, other n-type dopants, or combinations thereof. In some embodiments, substrate 202 includes p-type doped regions (e.g., p-type walls) doped with p-type dopants, wherein the p-type dopant is, for example, boron (e.g., arsenic), other n-type dopants, or combinations thereof. 11 B, BF2), indium, other p-type dopants, or combinations thereof. Ion implantation, diffusion, and / or other suitable doping processes can be performed to form various doped regions.

[0059] Semiconductor fins 204 are formed on substrate 202. Each fin 204 may be adapted to provide an n-type FET or a p-type FET. The fins 204 are oriented substantially parallel to each other. Each fin 204 has at least one channel region defined along its length in the x-direction, and at least one source region and one drain region, wherein the at least one channel region is covered by a gate structure and disposed between the S / D regions. In some embodiments, the fin 204 is a portion of substrate 202 (e.g., part of a material layer of substrate 202). For example, in the depicted embodiment, substrate 202 comprises silicon, and fin 204 comprises silicon. Alternatively, in some embodiments, fin 204 is defined in a material layer, such as one or more semiconductor material layers overlying substrate 202. For example, fin 204 may comprise a stack of semiconductor layers having various semiconductor layers (e.g., heterostructures) disposed on substrate 202. The semiconductor layers may comprise any suitable semiconductor material, such as silicon, germanium, silicon germanium, other suitable materials, or combinations thereof. The semiconductor layer may contain the same or different materials, etch rates, atomic percentages, weight percentages, thicknesses, and / or configurations, depending on the design requirements of device 200. The fin 204 is formed by any suitable process including various deposition, photolithography, and / or etching processes.

[0060] An isolation structure 208 is formed on the substrate 202 and separates the lower portion of the fins 204. The isolation structure 208 electrically isolates the active and / or passive regions of the device 200. The isolation structure can be configured in different ways, such as shallow trench isolation (STI), deep trench isolation (DTI), local oxidation of silicon (LOCOS), or combinations thereof. The isolation structure 208 contains an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials, or combinations thereof. The isolation structure 208 is deposited using the following processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic vapor deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable deposition processes, or combinations thereof. In some embodiments, the isolation structure 208 is formed prior to the formation of the fin 204 (isolation-first scheme). In some other embodiments, the fin 204 is formed prior to the formation of the isolation structure 208 (fin-first scheme). Planarization processes, such as chemical mechanical polishing (CMP), can be performed on the isolation structure 208.

[0061] exist Figure 2In the depicted embodiments, various gate structures 210 are formed on fins 204. The gate structures 210 extend along the y-direction and are configured to be substantially parallel to each other. The gate structures 210 engage the respective channel regions of the fins 204, allowing current to flow between the respective S / D regions of the fins 204 during operation. Each gate structure 210 may include a gate stack 211 and spacers 214. The gate stack 211 may include a gate dielectric layer 212, a gate electrode 213, a hard mask layer (not shown), and / or other suitable films. The gate dielectric layer 212 may comprise a high-k dielectric material having a dielectric constant greater than that of silicon dioxide (SiO2) (approximately 3.9). The gate electrode 213 may comprise a metal-containing material. In some embodiments, the gate electrode 213 may include a work function metal component and a fill metal component. The work function metal component is configured to adjust the work function of its corresponding FET to achieve a desired threshold voltage (Vt). In various embodiments, the work function metal component may comprise TiAl, TiAlN, TaCN, TiCN, TiN, WN, W, other suitable materials, or combinations thereof. The fill metal component is configured to serve as the primary conductive portion of the functional gate structure. In various embodiments, the fill metal component may comprise aluminum (Al), tungsten (W), copper (Cu), or combinations thereof. Each gate structure 210 has a gate length along the x-direction between the S / D regions.

[0062] Spacers 214 are disposed along the sidewalls of the gate stack 211. Spacers 214 may comprise one or more dielectric layers and patterned layers. For example, such as... Figure 2As depicted, spacer 214 includes a dielectric layer 214-1 disposed along the sidewalls of gate stack 211 and a patterned layer 214-2 disposed along the sidewalls of dielectric layer 214-1. In some embodiments, dielectric layer 214-1 may comprise any suitable dielectric material, such as silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide (SiC), low-k (k<3.9) dielectrics). In some embodiments, patterned layer 214-2 may comprise any suitable material having an etch rate different from that of the dielectric layer, such as silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), other suitable materials, or combinations thereof. For example, the patterned layer 214-2 of spacer 214 comprises nitrogen-rich SiN, wherein the molar ratio of the nitride is about 20% to about 60% (e.g., more than 50%). The formation of spacer 214 can include various steps. For example, firstly, dielectric layer 214-1 is conformally formed on substrate 202, and patterned layer 214-2 is conformally formed on dielectric layer 214-1. Dielectric layer 214-1 can be formed by any suitable method, such as ALD, CVD, PVD, other suitable methods, or combinations thereof. Patterned layer 214-2 can be deposited to any suitable thickness by any suitable method, such as ALD. Subsequently, the top of dielectric layer 214-1 and patterned layer 214-2 is removed by an anisotropic etching process or any other suitable process. The etching process can be a dry etching process, a wet etching process, a reactive ion etching (RIE) process, or a combination thereof. The remaining portions of dielectric layer 214-1 and pattern layer 214-2 form gate spacer 214.

[0063] In some other embodiments, the gate structure 210 is formed after other components of the fabrication apparatus 200 (e.g., the epitaxial S / D component 220 and the first ILD layer 230) using a gate replacement process. In the gate replacement process, dummy gate structures are formed on the channel region of the fin 204. Each dummy gate structure may include a dummy gate electrode containing polysilicon (or polycrystalline silicon) and various other film layers, such as a hard mask layer disposed on the dummy gate electrode, and an interface layer disposed on the fin 204 and the substrate 202 and below the dummy gate electrode. Spacers 214 are then formed along the sidewalls of the dummy gate structures using any of the aforementioned suitable methods. After the formation of the epitaxial S / D component 220 and the first ILD layer 230, the dummy gate structures are removed along the spacers 214 using one or more etching processes (e.g., wet etching, dry etching, RIE, or other etching techniques), thus leaving openings in the channel region of the fin 204 to replace the removed dummy gate structures. Next, the openings are filled with dielectric material to form the gate dielectric layer 212 using various processes, such as ALD, CVD, PVD, and / or other suitable processes. Then, a metal gate material (e.g., gate electrode 213 comprising work function components and metal fill components) is deposited on the gate dielectric layer to form a metal gate stack 211. The gate stack 211 is formed by various deposition processes, such as ALD, CVD, PVD, and / or other suitable processes. A CMP process can be performed to remove excess material from the gate stack 211 and / or spacers 214 to planarize the gate structure 210.

[0064] In some embodiments, the height H1 of the gate structure 210 and the first ILD layer 230 along the z-direction is about 30 nm to about 60 nm.

[0065] Still refer to Figure 2The device 200 also includes epitaxial S / D components 220 formed on the source / drain regions of the fin 204. For example, a semiconductor material (e.g., silicon germanium (SiGe), silicon phosphide (SiP), or silicon carbide (SiC)) is epitaxially grown on the fin 204 to form the epitaxial S / D components 220 on the fin 204. In some further embodiments, the epitaxial source / drain components 220 extend laterally (grow) along the y-direction, such that the epitaxial source / drain components 220 are merged into epitaxial source / drain components spanning more than one fin. In some embodiments, the epitaxial source / drain components 220 include partially merged portions and / or fully merged portions. In some other embodiments, the epitaxial source / drain components 220 are separate on their respective fins 204 and are not laterally merged. The epitaxial process can implement CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process can use gaseous and / or liquid precursors that interact with the composition of fin 204. In some embodiments intended to form an N-type FET device, the S / D component 220 may comprise epitaxially grown silicon (epiSi). Alternatively, when forming a P-type FET device, the S / D component 220 may comprise epitaxially grown silicon germanium (SiGe). In some embodiments, the S / D component 220 may be in-situ doped or undoped during the epitaxial process. In some embodiments, the S / D component 220 is doped with an n-type dopant (e.g., phosphorus or arsenic) and / or a p-type dopant (e.g., boron or BF2), depending on the type of FET fabricated in the respective FET device region. In some embodiments, the S / D component 220 includes a material and / or dopant that achieves desired tensile and / or compressive stresses in the channel region. In some embodiments, the epitaxial S / D component 220 is doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the epitaxial S / D component 220 is doped by an ion implantation process following the deposition process. In some embodiments, annealing is performed to activate the dopant in the epitaxial S / D component 220 of the device 200.

[0066] Still refer to Figure 2The device 200 includes a first interlayer dielectric (ILD) layer 230 formed on the source / drain regions of the substrate 202 and between the gate structure 210. In some embodiments, the first interlayer dielectric layer 230 may comprise silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), an oxide formed of tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, and black... (Applied Materials of Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. The first ILD layer 230 contains a dielectric material different from that of the spacers 214 (especially the spacer pattern layer 214-2), thereby achieving etch selectivity in subsequent etching processes. For example, when the spacer pattern layer 214-2 contains nitrogen-rich SiN, wherein the mole ratio of nitrides is about 20% to about 60% (e.g., more than 50%), the first ILD layer 230 contains oxide-rich SiO2, wherein the mole ratio of oxides is about 20% to about 60% (e.g., more than 50%). In some embodiments, the first ILD layer 230 has a multilayer structure having multiple dielectric materials. In some embodiments, the first ILD layer 230 may be formed by a deposition process (e.g., CVD, FCVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof) to cover the substrate 202, the S / D component 220, and the gate structure 210. After depositing the first ILD layer 230, a CMP process and / or other planarization processes may be performed to expose the gate structure 210.

[0067] Now refer to Figure 1and Figure 3 In operation 104, the gate structure 210, including the gate stack 211 and spacers 214, is etched such that each gate stack 211 and spacer 214 has a top surface below the top surface of the first ILD layer 230. In some embodiments, such as Figure 3 As depicted, the gate stack 211 and spacer 214 are etched to different heights, such that the top surface of the gate stack 211 is below the top surface of the spacer 214, and both are below the top surface of the first ILD layer 230. The etching process may include more than one step. For example, in a first step, the gate structure 210 including the gate stack 211 and spacer 214 is etched to a height H2, which is less than the height H1 of the first ILD layer 230; then, in a second step, the gate stack 211 is further etched to a height H3, which is less than the height H2 of the spacer 214. The etching process may include different etching processes, such as dry etching, wet etching, or a combination thereof. In some embodiments, the gate structure 210 including the gate stack 211 and spacer 214 is etched from height H1 to height H2 by selective dry etching, and then the gate stack 211 is further etched to height H3 by a combination of wet etching and dry etching. In the described embodiment, a T-shaped trench 218 is formed on the gate structure 210, which includes the gate stack 211 and spacers 214, and between the first ILD layer 230. For example... Figure 3 As depicted, trench 218 includes a top 218-1 and a bottom 218-2, forming a T-shaped profile in the xz plane, wherein the top 218-1 has a larger opening than the bottom 218-2. In the depicted embodiment, the top 218-1 of trench 218 is located on the top surface of spacer 214 and is surrounded by a portion of the sidewalls of the first ILD layer 230, while the bottom 218-2 of trench 218 is located on the top surface of gate stack 211, below the top surface of spacer 214, and is surrounded by a portion of the sidewalls of spacer 214.

[0068] In some embodiments, the height H1 of the first ILD layer 230 along the z-direction is about 30 nanometers (nm) to about 60 nm; the height H2 of the spacer 214 along the z-direction is about 20 nm to about 40 nm, and H2 is about 5 nm to about 20 nm lower than the height H1 of the first ILD layer 230. In some further embodiments, the height H2 of the spacer 214 is about 50% to about 80% of the height H1 of the first ILD layer 230. In some embodiments, the height H3 of the gate stack 211 along the z-direction is about 5 nm to about 20 nm, and H3 is about 10 nm to about 30 nm lower than the height H2 of the spacer 214. In some further embodiments, the height H3 of the gate stack 211 is about 30% to about 50% of the height H2 of the spacer 214, which is about 20% to about 40% of the height H1 of the first ILD layer 230. Figure 3 In the depicted embodiment, the height H1 of the first ILD layer is approximately 40 nm, the height H2 of the spacer 214 is approximately 30 nm, and the height H3 of the gate stack 211 is approximately 10 nm. In the conventional structure of a semiconductor device, the height of the spacer is approximately the same as the height of the ILD layer; and the height of the gate electrode is approximately 50% of the height of the spacer and the ILD layer. Therefore, in this disclosure, the height difference between the gate stack 211 and the spacer 214 is larger than that of the conventional structure of a semiconductor device, and further, the height difference between the gate stack 211 and the first ILD layer 230 is larger than that of the conventional structure of a semiconductor device. This can increase the distance between the gate stack 211 and the subsequently formed S / D via 280 (shown in…). Figure 18 The distance between them. Furthermore, the T-groove 218 will use low-k material (shown in...) Figure 18 The low-k material can provide better isolation than the material of spacer 214. This improves the isolation between the gate electrode and the S / D via, as well as between the S / D contact and the gate via, mitigating leakage current problems caused by stacking shifts during manufacturing.

[0069] Reference Figure 1 , Figure 4 ,and Figure 5A In operation 106, a first metal layer 240 is deposited on the gate stack 211. For example... Figure 5A As depicted, a first metal layer 240 is deposited to substantially cover the entire top surface of the gate stack 211 along both the x-direction (gate length direction) and the y-direction (direction perpendicular to the gate length direction). Figure 4As depicted, the top surface of the first metal layer 240 is located below the top surface of the spacer 214. Furthermore, the first metal layer 240 laterally contacts the sidewalls of the spacer 214. In some embodiments, the first metal layer 240 comprises a metallic material such as tungsten (W), cobalt (Co), aluminum (Al), zirconium (Zr), gold (Au), platinum (Pt), copper (Cu), ruthenium (Ru), a metal compound, or a combination thereof. In some embodiments, the material of the first metal layer 240 is different from the material of the gate stack 211. In some further embodiments, the material of the first metal layer 240 is different from the material of the subsequently formed gate via 290 (shown in…). Figure 18 The same applies. In some embodiments, the first metal layer 240 is formed from the gate stack 211 through a bottom-up growth process. A tungsten-containing catalyst can be used to promote the bottom-up growth of the first metal layer 240. In some embodiments, the thickness H4 of the first metal layer 240 is about 10% to about 30% of the height H3 of the gate stack 211. For example, the thickness H4 of the first metal layer 240 along the z-direction is about 1 nm to about 10 nm. Figure 4 In the depicted embodiment, the thickness H4 of the first metal layer 240 is approximately 3 nm.

[0070] In the depicted embodiment, the first metal layer 240 is grown to cover the entire top surface of the gate stack 211, although the top surface of the gate stack 211 may be flat or uneven after the etching process of operation 104. Figures 5B to 5F According to various embodiments of the present disclosure, an edge is shown between the first metal layer 240 and the gate stack 211. Figure 5A A cross-sectional view of the contact profile of surface BB. (See attached image.) Figures 5B to 5F As depicted, the gate stack 211 may include a gate dielectric layer 212 containing a high-k dielectric material. This dielectric layer may be deposited in a U-shape along the sidewalls of the spacer 214 and on the top surface of the substrate 202. The gate stack 211 also includes a gate electrode 213 comprising a work function layer and a fill metal layer. The work function layer comprises a work function metal material and may be conformally formed along the gate dielectric layer 212. The fill metal layer comprises a metal material and may be deposited to fill trenches formed in the work function layer. The gate stack 211 may include other elements not shown. Figures 5B to 5F The top surface of the gate stack 211 can therefore contain a high-k dielectric material (gate dielectric layer 212) and a conductive / metallic material (gate electrode 213). Due to the different etching rates of different materials, the top surface of the gate stack 211 can be of various shapes after the etching process of operation 104, such as... Figures 5B to 5FAs depicted. For example, the top surface of the gate stack 211 can be a flat surface ( Figure 5B ), stepped U-shaped Figure 5C ), continuous U-shaped Figure 5D ), stepped ∩ shape ( Figure 5E ), or continuous ∩ shape ( Figure 5F Regardless of the shape of the top surface of the gate stack 211, the first metal layer 240 is grown from the metal / conductive material from bottom to top and extends to the dielectric material to conformally or non-conformally cover the entire surface of the gate stack 211.

[0071] like Figure 5A As shown, the contact surface between the gate stack 211 and the first metal layer 240 is the entire top surface of the gate stack 211, which is much larger than the contact surface between the gate via and the gate electrode in existing structures. Furthermore, the first metal layer 240 can contain the same conductive material as the subsequently formed gate via 290, and the resistance between the gate via and the first metal layer is very small and negligible. Thus, because the contact resistance is inversely proportional to the contact area, the metal gate (e.g., gate stack 211) and the gate via (e.g., ... Figure 18 The contact resistance between the described gate vias (290) can be reduced, and device performance can be improved.

[0072] Still refer to Figure 1 and Figure 4 In operation 108, a sacrificial layer 242 is deposited on substrate 202. The material of the sacrificial layer 242 may comprise silicon, silicon compounds, nitride compounds, oxide compounds, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), other dielectric materials, or combinations thereof. In some embodiments, the material of the sacrificial layer 242 differs from the materials of the spacer 214 and the first ILD layer 230 (having different etch selectivity). For example, the sacrificial layer 242 comprises silicon-rich SiN, wherein the moiré ratio of silicon is about 20% to about 60% (e.g., more than 50%); the spacer pattern layer 214-2 comprises nitrogen-rich SiN, wherein the moiré ratio of nitride is about 20% to about 60% (e.g., more than 50%), and the first ILD layer 230 comprises oxygen-rich SiO2, wherein the moiré ratio of oxide is about 20% to about 60% (e.g., more than 50%). The sacrificial layer 242 can be deposited by CVD, PVD, ALD, other deposition processes, or combinations thereof. A planarization process (e.g., CMP) can then be used to remove the top of the sacrificial layer 242 until the first ILD layer 230 is exposed.

[0073] Reference Figure 1 and Figure 6In operation 110, the first ILD layer 230 is etched along the sidewalls of the sacrificial layer 242 and the spacers 214 (particularly the spacer pattern layer 214-2), thus leaving contact openings 244 in the source / drain regions of the device 200 to replace the removed first ILD layer. Because the material of the first ILD layer 230 has different etch selectivity than the materials of the spacer pattern layer 214-2 and the sacrificial layer 242, the selective etching process removes only the first ILD layer 230 without damaging the spacers 214 and the sacrificial layer 242. In some embodiments, such as Figure 6 As depicted, the first ILD layer 230 is substantially completely removed, thus the contact opening 244 has a bottom surface on the source / drain region of the device 200 and sidewalls formed by the sidewalls of the spacer 214 and the sacrificial layer 242. In some embodiments, the first ILD layer may not be completely removed. In subsequent processes, conductive material (i.e., Figure 7 The S / D contact 250 is filled into the contact opening 244 to form the S / D contact 250, so that the critical dimension (CD) of the source / drain contact can be maximized by this self-aligned S / D contact formation process, which helps to reduce S / D resistance and increase the alignment window of the S / D via. In some embodiments, the selective etching process of the first ILD layer 230 may include wet etching, dry etching, RIE, or a combination thereof.

[0074] Reference Figure 1 and Figure 7 In operation 112, conductive material is deposited in contact opening 244 to form S / D contact 250. In some embodiments, S / D contact 250 may comprise tungsten (W), cobalt (Co), thallium (Ta), titanium (Ti), aluminum (Al), zirconium (Zr), gold (Au), platinum (Pt), copper (Cu), ruthenium (Ru), metal compounds such as titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof. S / D contact 250 may be formed by suitable deposition processes, such as CVD, PVD, ALD, and / or other suitable processes. A CMP process may be performed to remove any excess material from S / D contact 250 such that the top surface of S / D contact 250 is substantially coplanar with sacrificial layer 242. Figure 7 In the depicted embodiment, the height of the S / D contact 250 along the z-direction is the same as H1, ranging from approximately 30 nm to approximately 60 nm. As described above, the CD of the S / D contact 250 can be maximized due to the self-aligned forming process.

[0075] Reference Figure 1 and Figure 8 In operation 114, sacrificial layer 242 is removed. Because of the high selective etching ratio between the material of sacrificial layer 242 (e.g., containing silicon-rich SiN) and the material of spacer 214 (e.g., containing nitrogen-rich SiN), sacrificial layer 242 can be removed using a selective dielectric etching process. Selective dielectric etching can substantially completely remove sacrificial layer 242 and stops at spacer 214 and the metal layer containing the first metal layer 240 and the S / D contact 250.

[0076] Reference Figure 1 and Figure 9 In operation 116, a first isolation component 246 is deposited on substrate 202 in a T-shaped trench 218. In some embodiments, the first isolation component 246 may comprise a dielectric material, including, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), other silicon compounds, nitride compounds, oxide compounds, or combinations thereof. The material of the first isolation component 246 should provide good rigidity and good isolation between the conductive materials of different contacts and / or vias, according to the design requirements of device 200. In some embodiments, the first isolation component 246 may comprise a multilayer structure having multiple dielectric materials. The first isolation component 246 is conformally formed in the T-shaped trench 218 by a deposition process. Figure 9 In the depicted embodiment, the first isolation member 246 is conformally formed on the first metal layer 240 by an ALD process, extending along the top of the sidewall of the spacer 214 (above the top surface of the first metal layer 240) to the top surface of the spacer 214, and further along the top sidewall of the S / D contact 250 (above the top surface of the spacer 214) to the top surface of the S / D contact 250. In the depicted embodiment, the first isolation member 246 is conformally deposited such that the thickness of the first isolation member 246 is substantially the same along different directions. In some embodiments, the thickness of the first isolation member 246 is about 10% to about 30% of the height of the gate electrode. For example, the thickness of the second hard mask layer is about 1 nm to about 10 nm. Figure 9 In the depicted embodiment, the thickness of the first isolation member 246 is approximately 3 nm. Because the first isolation member 246 is conformally deposited in the T-shaped trench 218, a small T-shaped opening 218' is formed above the first isolation member 246, such as... Figure 9The T-shaped opening 218' is depicted in a cross-sectional view in the xz plane, wherein the top of the T-shaped opening 218' has a larger opening than the bottom. Compared to existing structures that do not provide an additional dielectric layer between the various contacts and vias, the first isolation component 246 in this disclosure can be positioned between the source / drain contacts (e.g., S / D contacts 250) and the gate vias (e.g., Figure 18 Between the gate via 290 and the metal gate (e.g., gate stack 211) and the S / D via (e.g., Figure 18 Enhanced isolation is provided between the S / D vias 280 in the process, thereby mitigating leakage current problems caused by stacking displacement during manufacturing.

[0077] Still refer to Figure 1 and Figure 10 In operation 118, a second ILD layer 248 is deposited on the first isolation member 246. The second ILD layer 248 fills the smaller T-shaped trench 218' surrounded by the first isolation member 246. In some embodiments, the second ILD layer 248 may comprise a low-k dielectric material, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), an oxide formed of TEOS, PSG, BPSG, other suitable dielectric materials, or combinations thereof. In some embodiments, the second ILD layer 248 has a multilayer structure containing multiple dielectric materials. The second ILD layer 248 is formed on the first isolation member 246 by a deposition process, such as CVD, FCVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof.

[0078] Reference Figure 1 and Figure 11 While still operating at 118, a planarization process, such as CMP, can be used to remove any excess material from the first isolation component 246 and the second ILD layer 248 to expose the top surface of the S / D contact 250.

[0079] Reference Figure 1 and Figure 12 In operation 120, the top of the S / D contact 250 is removed, causing the S / D contact 250 to be etched from height H1 to height H5. In some embodiments, such as Figure 12As depicted, the height H5 of the etched S / D contact 250 is greater than the height H2 of the spacer 214. In other words, the top surface of the etched S / D contact 250 is located above the top surface of the spacer 214. Therefore, the etched S / D contact 250 contacts both the sidewalls of the spacer 214 and the sidewalls of the first isolation member 246. In some other embodiments, the height H5 of the etched S / D contact 250 may be less than the height H2 of the spacer 214. In other words, the top surface of the etched S / D contact 250 is located below the top surface of the spacer 214. Therefore, the sidewalls of the etched S / D contact 250 only contact the sidewalls of the spacer 214 but not the sidewalls of the first isolation member 246. In some embodiments, the S / D contact 250 is etched by a reactive ion etching (RIE) process. For example, a chemically reactive plasma is generated by an electromagnetic field. High-energy ions from the plasma are released and attack the top surface of the S / D contact 250, reacting with it. The reaction time is controlled according to the design requirements of the device 200, allowing the S / D contact 250 to be etched to an appropriate height H5. In some embodiments, the S / D contact 250 is etched to a certain degree H6 to achieve height H5 (H5 + H6 = H1). In some embodiments, the degree of etching H6 is approximately 10% to approximately 60% of the height H3 of the gate stack 211. For example, the degree of etching H6 is approximately 1 nm to approximately 20 nm. Figure 12 In the depicted embodiment, the degree of etch H6 is approximately 10 nm.

[0080] Reference Figure 1 , Figure 13 ,and Figure 14 In operation 122, a second isolation member 252 is formed on the S / D contact 250. In some embodiments, the dielectric material of the second isolation member 252 comprises silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), other silicon compounds, nitride compounds, oxide compounds, or combinations thereof. The material of the second isolation member 252 should provide good rigidity and good isolation between the conductive materials of different contacts and / or vias, according to the design requirements of the device 200. In some embodiments, the material of the second isolation member 252 may be the same as the material of the first isolation member 246. In some other embodiments, the material of the second isolation member 252 may comprise a different material than the first isolation member 246. The second isolation member 252 can be formed by any suitable process. For example, such as... Figure 13 As depicted, in the first step, an isolation layer 252' is conformally deposited on the substrate 202 using an ALD process, particularly on the S / D contact 250, the first isolation member 246, and the second ILD layer 248. Next, in the second step, as... Figure 14 As depicted, the isolation layer 252' is etched anisotropically, such that only a portion of the isolation layer 252' along the x-direction is removed, leaving a portion along the z-direction. The remaining portion of the isolation layer 252' forms a second isolation member 252. In the depicted embodiment, the second isolation member 252 is disposed above the S / D contact 250, with its outer edge aligned with the sidewall of the S / D contact 250 and its inner edge surrounding a trench formed therein. The second isolation member 252 has a height H6 in the z-direction, which is equal to the degree of etching H6 of the S / D contact 250. In some embodiments, the height H6 is from about 1 nm to about 20 nm, which is from about 10% to about 60% of the height H3 of the gate electrode. Figure 14 In the depicted embodiment, the height H6 is approximately 10 nm. Compared to existing structures that do not provide additional isolation components / layers between various contacts and vias, in this disclosure, the second isolation component 252, independent of or integrated with the first isolation component 246, can be provided between various contacts and vias (e.g., Figure 18 The S / D contact 250 shown provides better isolation between the gate via 290, or the metal gate stack 211 and the S / D contact 280. Therefore, leakage current problems caused by stacking shift during manufacturing can be mitigated, and semiconductor performance can be improved.

[0081] Reference Figure 1 , Figure 15 ,and Figure 16 In operation 124, a second metal layer 254 is deposited in the second isolation member 252 and in the trench formed above the S / D contact 250. In some embodiments, the material of the second metal layer 254 may be the same as or different from the first metal layer 240. In some further embodiments, the material of the second metal layer 254 may be different from the material of the S / D contact 250. In some further embodiments, the material of the second metal layer 254 is different from the material of the S / D contact 250. Figure 18 The material of the second metal layer 254 is the same as that of the first metal layer 240. In some embodiments, the material of the second metal layer 254 comprises W, Co, Al, Zr, Au, Pt, Cu, Ru, metal compounds, or any combination thereof. In some embodiments, the second metal layer 254 may be grown from the S / D contact 250 from bottom to top, or by other suitable processes similar to the fabrication of the first metal layer 240. In some embodiments, the thickness of the second metal layer 254 grown from bottom to top along the z-direction is substantially the same as the thickness H6 of the second isolation member 252, which is about 10% to about 60% of the height H3 of the gate stack 211. For example, the thickness H6 of the second metal layer 254 is about 1 nm to about 20 nm. Figure 15 In the depicted embodiment, the thickness H6 of the second metal layer 254 is approximately 10 nm. Figure 16 As depicted, a second metal layer 254 is deposited between the second isolation members 252 and extends along the entire length of the S / D contact 250 in the y-direction (perpendicular to the gate length direction). In other words, the contact surface between the second metal layer 254 and the second isolation members 252 and the S / D contact 250 is the entire top surface of the S / D contact 250, which is larger than the contact surface between the S / D via and the S / D contact in existing structures. Similar to the first metal layer 240, the second metal layer 254 has the same material as the S / D via and expands the contact surface between the S / D via and the S / D contact. This reduces the contact resistance between the S / D contact and the S / D via, and improves the performance of the semiconductor device.

[0082] Reference Figure 1 and Figure 17 In operation 126, a contact etch stop layer (CESL) 260 is formed on substrate 202. In some embodiments, CESL 260 comprises a dielectric material including silicon and nitrogen (e.g., SiN or SiON). Furthermore, in operation 126, a third ILD layer 270 is formed on CESL 260 and substrate 202. In some embodiments, the third ILD layer 285 comprises a dielectric material including, for example, oxides formed from SiO, SiN, SiON, TEOS, PSG, BPSG, low-k dielectric materials (K < 3.9), other suitable dielectric materials, or combinations thereof. The third ILD layer 270 comprises a dielectric material different from that of CESL 260. In some embodiments, where CESL 260 comprises silicon and nitrogen, the third ILD layer 270 comprises a low-k dielectric material different from the dielectric material of CESL 260. In some embodiments, the third ILD layer 270 may have a multilayer structure having multiple dielectric materials. The third ILD layer 270 and / or CESL 260 are formed on the substrate 202 by, for example, deposition processes (e.g., CVD, FCVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof). After the deposition of CESL 260 and / or the third ILD layer 270, a CMP process and / or other planarization processes are performed to planarize the top surface of the device 200. In some embodiments, the thickness of the CESL layer 260 along the z-direction is from about 1 nm to about 10 nm, and the thickness of the third ILD layer 270 along the z-direction is from about 5 nm to about 30 nm.

[0083] Reference Figure 1 and Figure 18In operation 128, S / D via 280 and gate via 290 are formed on substrate 202 through CESL 260 and third ILD layer 270. The materials of S / D via 280 and gate via 290 may include W, Co, Al, Zr, Au, Pt, Cu, metal compounds, or any combination thereof. To reduce the contact resistance between source / drain via 280 and source / drain contact 250, S / D via 280 contains the same material as the second metal layer 254. To reduce the contact resistance between gate via 290 and gate stack 211, gate via 290 contains the same material as the first metal layer 240.

[0084] The formation of the S / D via 280 and the gate via 290 can include various processes. For example, in a first step, contact openings can be formed by photolithography and / or etching processes. An exemplary photolithography process includes forming a photoresist layer (photoresist) overlying a third ILD layer 270, exposing the photoresist as a pattern, performing a post-exposure bake process, and developing the photoresist to form a masking element containing the photoresist. The masking element is then used to etch contact openings into the third ILD layer 270 and CESL 260, and into the second ILD layer 248 and the first isolation member 246 disposed on the first metal layer 240. The etching process can stop on a metal material, such as the first metal layer 240 and / or the second metal layer 254. The etching process can include dry etching, wet etching, other suitable etching processes, or combinations thereof. The patterned photoresist layer can be removed before or after the etching process. Next, conductive material is deposited in the contact opening to form S / D via 280 and gate via 290.

[0085] Figure 19 A three-dimensional perspective view showing the contact contours between the S / D via 280, the second metal layer 254, and the S / D contact 250. (See attached image.) Figure 19 As depicted, the S / D via 280 and the second metal layer 254 contain the same material (therefore the resistance between the S / D via 280 and the second metal layer 254 can be ignored), and the contact surface between the S / D via 280 and the S / D contact 250 is enlarged by the second metal layer 254 therebetween, thereby reducing the contact resistance between the S / D contact 250 and the S / D via 280.

[0086] Similarly, Figure 20 A three-dimensional perspective view showing the contact contours between the gate via 290, the first metal layer 240, and the gate stack 211. (See attached image.) Figure 20As depicted, the gate via 290 and the first metal layer 240 contain the same material (therefore, the resistance between the gate via 290 and the first metal layer 240 can be ignored), and the contact surface between the gate via 290 and the gate stack 211 is enlarged by the first metal layer 240 therebetween, thus reducing the contact resistance between the metal gate (gate stack 211) and the gate via 290. Therefore, the performance of the device 200 can be improved.

[0087] In addition, such as Figure 18 As shown, various conductive contacts and vias (e.g., gate via 290 and source / drain contact 250, or metal gate stack 211 and S / D via 280) are isolated not only by spacer 214, but also by second ILD layer 248, first isolation member 246, and second isolation member 252. In the depicted embodiment, the top surface of gate stack 211 is lower than the top surface of spacer 214, and the top surface of spacer 214 is lower than the top surface of second metal layer 254 (i.e., the bottom surface of S / D via 280). Therefore, in this disclosure, the distance between gate stack 211 and S / D via 280 is greater than that of existing structures. Furthermore, spacer 214 is etched below the top surface of second metal layer 254 (i.e., the bottom surface of S / D via 280), allowing the top of the T-shaped opening to be filled by second ILD layer 248 and / or first isolation member 246, providing better isolation between various contacts and vias than spacer 214. Furthermore, the second isolation member 252 disposed on the S / D contact 250 and between the second metal layer 254 can further enhance the isolation between various contacts and vias. Therefore, compared with the existing structure, leakage current between the S / D contact and the gate via, as well as between the metal gate and the S / D via, can be reduced. Thus, the performance of the device 200 is improved.

[0088] Reference Figure 1 In operation 130, method 100 performs further processing to complete the fabrication of device 200. For example, other contact openings, contact metals, and various other contacts, vias, wires, and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) may be formed on device 200, configured to connect various components to form a functional circuit containing a semiconductor device.

[0089] Figures 21-23 Various embodiments of the apparatus 200 are provided according to this disclosure. Isolation components 246 and 252 are optional, and one or both of them may be omitted in these various embodiments.

[0090] For example, refer to Figure 21The second isolation component 252 is not disposed on the S / D contact 250, and is removed between the second metal layer 254 and the first isolation component 246, so that the second metal layer 254 directly contacts the first isolation component 246, and the edge of the second metal layer 254 is aligned with the sidewall of the S / D contact 250. Figure 20 As depicted, a first isolation member 246 is disposed on the top surface of the first metal layer 240, extends along the sidewall of the spacer 214 to the top surface of the spacer 214, and further extends along the sidewall of the second metal layer 254. The first isolation member 246 is provided to provide better isolation between the gate via 290 and the S / D contact 250, and between the S / D via 280 and the gate stack 211. Figure 21 In the depicted embodiment, the contact area between the second metal layer 254 and the S / D contact 250 is the entire top surface of the S / D contact 250 along both the x and y directions. Metal layers 240 and 254 (having the same material as the S / D via 280 and gate 290, respectively) are disposed between the contacts (e.g., the S / D contact 250 and gate stack 211) and the vias (e.g., the S / D via 280 and gate via 290), respectively reducing the resistance between the contacts and the vias.

[0091] Reference Figure 22 The first isolation component 246 is not conformally disposed in the T-shaped trench 218 between the gate via 290, the spacer 214, and the S / D contact 250. The top of the T-shaped trench 218 on the spacer 214 is filled only by the second ILD layer 248. The second isolation component 252 is disposed between the second ILD layer 248 and the second metal layer 254 to provide further isolation between the S / D contact 250 and the gate via 290, and between the gate stack 211 and the S / D via 280. The metal layers 240 and 254 are disposed between the contacts (e.g., the S / D contact 250 and the gate stack 211) and the vias (e.g., the S / D via 280 and the gate via 290), respectively, to reduce the resistance between the contacts and the vias.

[0092] Reference Figure 23Both the first isolation member 246 and the second isolation member 252 are removed. In the depicted embodiment, the top of the T-shaped trench 218 on the spacer 214 is filled only by the second ILD layer 248. Isolation between the gate stack 211 and the S / D via 280, and between the S / D contact 250 and the gate via 290, is enhanced by the second ILD layer 248. The contact area between the second metal layer 254 and the S / D contact 250 is the entire top surface of the S / D contact 250 along the x and y directions. The metal layers 240 and 254 are respectively disposed between the contacts (e.g., S / D contact 250 and gate stack 211) and the vias (e.g., S / D via 280 and gate via 290) to reduce the resistance between the contacts and the vias.

[0093] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits to semiconductor devices and their fabrication processes. For example, embodiments of this disclosure provide a semiconductor device comprising a metal layer between contacts and vias (e.g., between S / D contacts and S / D vias, and / or between metal gates and gate vias). The metal layer comprises the same material as the vias and enlarges the contact surface between the contacts and vias, thereby reducing the contact resistance between the contacts and corresponding vias. The semiconductor device of this disclosure may also include isolation components between various contacts and vias, for example, between S / D contacts and gate vias. The isolation components provide further isolation between contacts and vias beyond spacers, mitigating leakage current caused by short paths between various contacts and vias. Therefore, the performance of the semiconductor device can be improved.

[0094] This disclosure provides numerous different embodiments. A semiconductor device having a metal layer and a hard mask layer between contacts and vias, and a method of manufacturing the same, is disclosed herein. An exemplary semiconductor device includes a gate structure disposed on a substrate and on a channel region of the semiconductor device. The gate structure includes a gate stack and spacers disposed along the sidewalls of the gate stack. The gate stack includes a gate dielectric layer and a gate electrode. The semiconductor device further includes a first metal layer disposed on the gate stack, wherein the first metal layer laterally contacts the spacers on the gate dielectric layer and the gate electrode. The semiconductor device further includes a gate via disposed on the first metal layer.

[0095] In some embodiments, the top surface of the first metal layer is located below the top surface of the spacer. In some embodiments, the material of the first metal layer is the same as the material of the gate via.

[0096] In some embodiments, the semiconductor device further includes: a source / drain (S / D) contact disposed on a source / drain region of the semiconductor device; an S / D via disposed on the source / drain contact; and a second metal layer disposed between the S / D contact and the S / D via, wherein the bottom surface of the second metal layer contacts the top surface of the S / D contact, and the area of ​​the bottom surface of the second metal layer is larger than the area of ​​the bottom surface of the S / D via.

[0097] In some embodiments, the material of the second metal layer is the same as the material of the S / D via. In some embodiments, the top surface of the spacer is lower than the top surface of the second metal layer.

[0098] In some embodiments, the semiconductor device further includes a first isolation member formed on the top surface of a first metal layer, extending along the sidewalls of the spacer to the top surface of the spacer, and further along the sidewalls of a second metal layer.

[0099] In some embodiments, the semiconductor device further includes a second isolation member disposed on the S / D contact along the sidewall of the second metal layer, wherein the sidewall of the second dielectric layer opposite to the second metal layer is aligned with the sidewall of the S / D contact, and the sidewall of the second dielectric layer facing the second metal layer surrounds the second metal layer.

[0100] Another exemplary semiconductor device includes a substrate comprising a channel region formed between source / drain (S / D) regions and a gate structure formed on the channel region of the substrate, wherein the gate structure includes a gate stack and spacers disposed along the sidewalls of the gate stack, and the top surface of the spacers is located above the top surface of the gate stack. This other exemplary semiconductor device further includes: source / drain (S / D) contacts disposed on the S / D region of the substrate; a first metal layer disposed on the S / D contacts; an S / D via having the same material as the first metal layer and disposed on the first metal layer, wherein the area of ​​the bottom surface of the S / D via is smaller than the area of ​​the bottom surface of the first metal layer; and an interlayer dielectric (ILD) layer formed on the gate structure, wherein the top of the ILD layer extends over the top surface of the spacers.

[0101] In some embodiments, the height ratio between the gate stack and the spacer is about 20% to about 50%.

[0102] In some embodiments, this other semiconductor device further includes: a second metal layer disposed on the gate structure, wherein the top surface of the second metal layer is lower than the top surface of the spacer; and a gate via disposed on the second metal layer, wherein the material of the gate via is the same as the material of the second metal layer, and the area of ​​the bottom surface of the gate via is smaller than the area of ​​the bottom surface of the second metal layer.

[0103] In some embodiments, this other semiconductor device further includes a first isolation member disposed on a second metal layer, extending along the sidewalls of the spacer to the top surface of the spacer, and further along the sidewalls of the first metal layer.

[0104] In some embodiments, this other semiconductor device further includes a second isolation member disposed on the S / D contact and along the sidewall of the first metal layer, wherein the second isolation member includes a first sidewall facing away from the first metal layer and a second sidewall facing the first metal layer, the first sidewall of the second isolation member being aligned with the sidewall of the S / D contact, and the second sidewall of the second isolation member surrounding the first metal layer.

[0105] In some embodiments, the bottom surface of the first metal layer and the bottom surface of the second isolation member contact the top surface of the S / D contact.

[0106] An exemplary method includes: forming a fin on a substrate; forming a gate structure on a channel region of the fin, wherein the gate structure includes a gate stack and spacers disposed along the sidewalls of the gate stack, the gate stack including a gate dielectric and a gate electrode; epitaxially growing a source / drain (S / D) component on the source / drain region of the fin; forming a first interlayer dielectric (ILD) layer on the S / D component and the substrate; etching the gate structure including the spacers and the gate stack such that the top surface of the spacers is lower than the top surface of the first ILD layer, and the top surface of the gate stack is lower than the top surface of the spacers; and forming a first metal layer on the gate stack by a bottom-up growth process, wherein the first metal layer covers the top surface of the gate stack including the gate dielectric layer and the gate electrode.

[0107] In some embodiments, the recessed gate structure includes: etching a spacer and a gate stack together such that the top surfaces of the spacer and the gate stack are lower than the top surface of the first ILD layer; and further etching the gate stack such that the top surface of the gate electrode is lower than the top surface of the spacer, and a T-shaped trench is formed on the gate stack and the spacer.

[0108] In some embodiments, the method further includes: etching a first ILD layer to form an S / D contact opening; forming an S / D contact in the S / D contact opening; depositing a second ILD layer on the first metal layer and spacers; and forming a gate via through the second ILD layer and in contact with the first metal layer, wherein the gate via contains the same material as the first metal layer, and the area of ​​the bottom surface of the gate via is smaller than the area of ​​the bottom surface of the first metal layer.

[0109] In some embodiments, the method further includes forming a first isolation member after forming the first metal layer and before depositing the second ILD layer, wherein the first isolation member is deposited on the top surface of the first metal layer, extends along the sidewall of the spacer, extends on the top surface of the spacer, and further extends along the sidewall of the S / D contact.

[0110] In some embodiments, the method further includes etching the top of the S / D contact; and forming a second isolation member on the etched S / D contact, wherein the second isolation member includes a first sidewall contacting the first isolation member and a second sidewall facing away from the first isolation member, the first sidewall being aligned with the sidewall of the etched S / D contact, the second sidewall forming a groove therein, and a portion of the top surface of the etched S / D contact being exposed through the groove.

[0111] In some embodiments, the method further includes: forming a second metal layer to cover the top surface of the etched S / D contact exposed in the trench; and forming an S / D via on the second metal layer, wherein the S / D via comprises the same material as the second metal layer.

[0112] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of these embodiments. Those skilled in the art should understand that they can design or modify other processes and structures based on these embodiments to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the concept and scope of the invention, and that various changes, substitutions, and replacements can be made without departing from the concept and scope of the invention.

Claims

1. A semiconductor device, comprising: One substrate; A gate structure is disposed on the substrate and a channel region of the semiconductor device, wherein the gate structure includes a gate stack and a plurality of spacers disposed along a plurality of sidewalls of the gate stack, and the gate stack includes a gate dielectric layer and a gate electrode. A first metal layer is disposed on the gate stack, wherein the first metal layer laterally contacts the plurality of spacers on the gate dielectric layer and the gate electrode, wherein a top surface of the first metal layer is located below a top surface of the plurality of spacers; An interlayer dielectric layer is disposed above the first metal layer and extends between the plurality of spacers, wherein the top surface of the first metal layer and the top surface of the plurality of spacers are lower than the top surface of the interlayer dielectric layer. as well as A gate via is disposed on the first metal layer.

2. The semiconductor device of claim 1, wherein the material of the first metal layer is the same as the material of the gate via.

3. The semiconductor device of claim 1, further comprising: A source / drain contact is disposed on a source / drain region of the semiconductor device; A source / drain via is disposed on the source / drain contact; as well as A second metal layer is disposed between the source / drain contact and the source / drain via, wherein a bottom surface of the second metal layer contacts a top surface of the source / drain contact, and the area of ​​the bottom surface of the second metal layer is larger than the area of ​​the bottom surface of the source / drain via.

4. The semiconductor device of claim 3, wherein the material of the second metal layer is the same as the material of the source / drain via.

5. The semiconductor device of claim 3, wherein the top surface of the spacer is located below the top surface of the second metal layer.

6. The semiconductor device of claim 3, further comprising a first isolation member formed on the top surface of the first metal layer, extending along a plurality of sidewalls of the plurality of spacers to the top surface of the plurality of spacers, and also extending along a sidewall of the second metal layer.

7. The semiconductor device of claim 6, further comprising a second isolation member disposed on the source / drain contact along a plurality of sidewalls of the second metal layer, wherein a sidewall of the second isolation member opposite to the second metal layer is aligned with a sidewall of the source / drain contact.

8. The semiconductor device of claim 1, further comprising: One source / drain component; A source / drain contact is disposed on the source / drain component; as well as A dielectric layer extends continuously from the top surface of the first metal layer to the source / drain contact, wherein the dielectric layer includes the interlayer dielectric layer.

9. A semiconductor device, comprising: A first gate stack is disposed on a substrate, the gate stack including a gate dielectric layer and a gate electrode layer; A first sidewall spacer is disposed along a first sidewall of the first gate stack and a second sidewall spacer is disposed along an opposing second sidewall of the first gate stack, the second sidewall being opposite to the first sidewall of the first gate stack; A first metal layer is directly disposed on the gate electrode layer and extends from the first sidewall spacer to the second sidewall spacer, such that the first metal layer is in solid contact with the first sidewall spacer and the second sidewall spacer, wherein a top surface of the first metal layer is recessed relative to a top surface of the first sidewall spacer, and wherein the top surface of the first metal layer and the first sidewall spacer are respectively facing away from the substrate. An interlayer dielectric layer is disposed above the first metal layer and extends between the first sidewall spacer and the second sidewall spacer, wherein the top surface of the first metal layer, the top surface of the first sidewall spacer and the top surface of the second sidewall spacer are lower than the top surface of the interlayer dielectric layer. A gate via extends between the first sidewall spacer and the second sidewall spacer to intersect with the first metal layer; A source / drain contact is disposed on the substrate; A second metal layer is directly disposed on the source / drain contact; as well as A source / drain via extends into the second metal layer.

10. The semiconductor device of claim 9, wherein the first metal layer and the gate via are formed of the same material, and The second metal layer and the source / drain via are formed of the same material.

11. The semiconductor device of claim 10, further comprising a first insulating material layer compliantly disposed directly on the first metal layer, the first sidewall spacer, and the source / drain contact.

12. The semiconductor device of claim 11, further comprising a second insulating material layer disposed along and bordering one sidewall of the second metal layer, and The first isolation material layer and the second isolation material layer are at the interface.

13. The semiconductor device of claim 9, wherein the interlayer dielectric layer intersects with an inner surface of the first sidewall spacer facing the second sidewall spacer.

14. The semiconductor device of claim 9, further comprising an isolation material layer compliantly disposed directly on the first metal layer, the first sidewall spacer and the source / drain contact, wherein the gate via extends through the isolation material layer to the first metal layer.

15. A semiconductor device, comprising: A first gate stack is disposed on a substrate, the gate stack including a gate dielectric layer and a gate electrode layer; A first sidewall spacer is disposed along a first sidewall of the first gate stack and a second sidewall spacer is disposed along an opposing second sidewall of the first gate stack, the second sidewall being opposite to the first sidewall of the first gate stack; A first metal layer is directly disposed on the gate electrode layer and extends from the first sidewall spacer to the second sidewall spacer, such that the first metal layer is in solid contact with the first sidewall spacer and the second sidewall spacer, wherein the first sidewall spacer extends to a first height above the substrate, and the first metal layer extends to a second height above the substrate, the second height being less than the first height; as well as An interlayer dielectric layer is disposed above the first metal layer and extends between the first sidewall spacer and the second sidewall spacer, wherein the top surface of the first metal layer, the top surface of the first sidewall spacer, and the top surface of the second sidewall spacer are lower than the top surface of the interlayer dielectric layer; and The gate dielectric layer is in contact with the first sidewall spacer and the second sidewall spacer and is located between the gate electrode layer and the first sidewall spacer and the second sidewall spacer, so that the gate dielectric layer prevents the gate electrode layer from intersecting with the first sidewall spacer and the second sidewall spacer.

16. The semiconductor device of claim 15, further comprising a gate via extending between the first sidewall spacer and the second sidewall spacer to intersect with the first metal layer.

17. The semiconductor device of claim 15, wherein the first metal layer has a bottom surface facing the substrate, and The gate dielectric layer and the gate electrode layer are in contact with the bottom surface of the first metal layer.

18. The semiconductor device of claim 15, wherein the gate electrode layer comprises: An activity function layer is disposed on the gate dielectric layer; as well as A metal filler layer is disposed on the work function layer.

19. The semiconductor device of claim 15, further comprising a dielectric material layer disposed on the first metal layer, a first sidewall of the first sidewall spacer, and a second sidewall of the second sidewall spacer, wherein the first sidewall of the first sidewall spacer faces the second sidewall of the second sidewall spacer, and The first metal layer is in contact with the first sidewall of the first sidewall spacer and the second sidewall of the second sidewall spacer.

20. The semiconductor device of claim 19, wherein the dielectric material layer defines a groove disposed on the first metal layer, wherein the interlayer dielectric layer is disposed within the groove, and the semiconductor device further comprises: A via extends through the interlayer dielectric layer to the first metal layer.

21. A method for forming a semiconductor device, comprising: A gate structure is formed on a fin structure. The gate structure includes a gate stack and a first sidewall spacer disposed along one sidewall of the gate stack. The gate stack includes a gate electrode layer and a gate dielectric layer. A first interlayer dielectric layer is formed on the gate structure; The gate stack and the first sidewall spacer are etched in such that the top surfaces of the gate stack and the first sidewall spacer are each lower than a top surface of the first interlayer dielectric layer; A first metal layer is formed directly on the top surface of the gate stack, wherein after the first metal layer is formed directly on the top surface of the gate stack, a top surface of the first metal layer is located below the top surface of the first sidewall spacer, wherein the top surface of the first metal layer is lower than the top surface of the first interlayer dielectric layer. A first isolation layer is formed on the first metal layer and the first sidewall spacer; A first trench is formed through the first insulating layer to expose a portion of the first metal layer; as well as A first conductive component is formed in the first trench on the exposed portion of the first metal layer.

22. The method of forming a semiconductor device as claimed in claim 21, further comprising: Before the first isolation layer is formed on the first metal layer and the first sidewall spacer, a sacrificial layer is formed on the first metal layer and the first sidewall spacer; A second trench is formed that passes through the first interlayer dielectric layer and the sacrificial layer; as well as A second conductive component is formed in the second trench.

23. The method of forming a semiconductor device as claimed in claim 22, further comprising removing the sacrificial layer to expose the top surface of the first metal layer and a sidewall surface of the second conductive member.

24. The method of forming a semiconductor device as claimed in claim 23, wherein the formation of the first isolation layer on the first metal layer and the first sidewall spacer includes directly forming the first isolation layer on the exposed top surface of the first metal layer and the sidewall surface of the second conductive member.

25. The method of forming a semiconductor device as claimed in claim 21, further comprising directly forming a second interlayer dielectric layer on the first isolation layer, wherein the second interlayer dielectric layer extends above the top surface of the first sidewall spacer; and The portion in which the first trench is formed through the first isolation layer to expose the first metal layer includes the formation of the first trench through the second interlayer dielectric layer.

26. The method of forming a semiconductor device as claimed in claim 21, further comprising: A second trench is formed through the first interlayer dielectric layer; A second conductive component is formed in the second trench; Remove a first portion of the first insulating layer to expose a first portion of the second conductive component; as well as Remove the first portion of the second conductive component.

27. The method of forming a semiconductor device as claimed in claim 26, wherein a second portion of the second conductive member is retained after the first portion of the second conductive member is removed, the second portion of the second conductive member having a top surface located above the top surface of the first sidewall spacer.

28. A method for forming a semiconductor device, comprising: A gate structure is formed on a fin, the gate structure including a gate electrode layer, a gate dielectric layer, and a plurality of spacers disposed along the sidewalls of the gate electrode layer and the gate dielectric layer; A source / drain component is formed on this fin; A first interlayer dielectric layer is formed on the gate structure; The gate structure is etched so that one top surface of the gate structure is lower than one top surface of the first interlayer dielectric layer; A first metal layer is formed directly on at least one of the gate electrode layer and the gate dielectric layer, wherein the top surface of the first metal layer and the top surface of the plurality of spacers are lower than the top surface of the first interlayer dielectric layer. A first conductive component is formed that extends through the first interlayer dielectric layer to the source / drain component; A first isolation layer is formed directly on the first metal layer; A second isolation layer is formed directly on the first conductive component and the first isolation layer; Remove a first portion of the second insulating layer to expose a first portion of the first conductive component; and A second metal layer is formed directly on the second part of the first conductive component.

29. The method of forming a semiconductor device as claimed in claim 28, further comprising: A second interlayer dielectric layer is formed on the first isolation layer; as well as A second conductive component is formed that extends through the second interlayer dielectric layer, the first isolation layer, and into the first metal layer.

30. The method of forming a semiconductor device as claimed in claim 29, further comprising: An etch stop layer is formed on the second interlayer dielectric layer; as well as A third interlayer dielectric layer is formed on the etch stop layer, and The formation of the second conductive member extending through the second interlayer dielectric layer, the first isolation layer and to the first metal layer also includes forming the second conductive member to extend through the third interlayer dielectric layer and the etch stop layer.

31. The method of forming a semiconductor device as claimed in claim 30, further comprising forming a third conductive member extending through the third interlayer dielectric layer, the etch stop layer and to the second metal layer.

32. The method of forming a semiconductor device as claimed in claim 28, wherein the first isolation layer is formed of a material different from the second isolation layer.

33. The method of forming a semiconductor device as claimed in claim 28, wherein the first isolation layer is formed of the same material as the second isolation layer.

34. The method of forming a semiconductor device as claimed in claim 28, wherein the formation of the first metal layer on at least one of the gate electrode layer and the gate dielectric layer comprises directly forming the first metal layer on the gate electrode layer and the gate dielectric layer.

35. A method for forming a semiconductor device, comprising: A fin is formed on a substrate; A gate structure is formed on a channel region of the fin, wherein the gate structure includes a gate stack and a plurality of spacers disposed along a plurality of sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; A source / drain component is epitaxially grown on a source / drain region of the fin; A first interlayer dielectric layer is formed on the source / drain component and the substrate; The etch includes the plurality of spacers and the gate structure of the gate stack, such that a top surface of the plurality of spacers is lower than a top surface of the first interlayer dielectric layer, and a top surface of the gate stack is lower than the top surface of the plurality of spacers. as well as A first metal layer is formed on the gate stack using a bottom-up process, wherein the first metal layer covers the top surface of the gate stack, which includes the gate dielectric layer and the gate electrode, and wherein the top surface of the first metal layer is lower than the top surface of the first interlayer dielectric layer.

36. The method of forming a semiconductor device as claimed in claim 35, wherein etching the gate structure comprises: The plurality of spacers and the gate stack are etched together, such that the top surface of the plurality of spacers and the gate stack is lower than the top surface of the first interlayer dielectric layer; as well as The gate stack is further etched so that the top surface of the gate electrode is lower than the top surface of the plurality of spacers, and a T-shaped trench is formed on the gate stack and the plurality of spacers.

37. The method of forming a semiconductor device as claimed in claim 35, further comprising: The first interlayer dielectric layer is etched to form a source / drain contact opening; A source / drain contact is formed in the source / drain contact opening; A second interlayer dielectric layer is deposited on the first metal layer and the plurality of spacers; as well as A gate via is formed that passes through the second interlayer dielectric layer and contacts the first metal layer, wherein the gate via comprises the same material as the first metal layer, and the area of ​​a bottom surface of the gate via is smaller than the area of ​​a bottom surface of the first metal layer.

38. The method of forming a semiconductor device as claimed in claim 37, further comprising: A first isolation member is formed after the formation of the first metal layer and before the deposition of the second interlayer dielectric layer, wherein the first isolation member is deposited on a top surface of the first metal layer, the first isolation member extends along a plurality of sidewalls of the plurality of spacers, extends on the top surface of the plurality of spacers, and further extends along a sidewall of the source / drain contact.

39. The method of forming a semiconductor device as claimed in claim 38, further comprising: The top of the source / drain contact is etched. as well as A second isolation member is formed on the etched source / drain contact, wherein the second isolation member includes a first sidewall that contacts the first isolation member and a second sidewall that faces away from the first isolation member, the first sidewall being aligned with a sidewall of the etched source / drain contact, the second sidewall having a groove formed therein, and a portion of the top surface of the etched source / drain contact being exposed through the groove.

40. The method of forming a semiconductor device as claimed in claim 39, further comprising: A second metal layer is formed to cover the top surface of the etched source / drain contact exposed in the trench; as well as A source / drain via is formed on the second metal layer, wherein the source / drain via comprises the same material as the second metal layer.

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