Semiconductor storage devices

Abstract

A semiconductor memory device is disclosed. The device includes: a peripheral circuit structure on a substrate; a semiconductor layer on the peripheral circuit structure; an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer; a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer; a separation structure penetrating the electrode structure, extending in a first direction and horizontally dividing the electrodes of the electrode structure into a pair of electrodes; an interlayer insulating layer covering the electrode structure; and a through-contact penetrating the interlayer insulating layer and electrically connected to the peripheral circuit structure.

Description

Technical Field

[0001] The example implementation relates to semiconductor devices, and more specifically, to three-dimensional semiconductor memory devices with improved reliability. Background Technology

[0002] The pursuit / demand for higher integration levels in semiconductor devices is driven by consumer demand for superior performance and / or lower prices. Since the integration level of semiconductor devices is a significant factor in determining product price, increased integration is particularly sought after. For two-dimensional (e.g., planar) semiconductor devices, the integration level is primarily determined by the area occupied by a single memory cell, and is therefore heavily influenced by the level of fine patterning technology. However, the very high cost of the process equipment required to increase pattern fineness sets a practical limit on increasing the integration level of two-dimensional or planar semiconductor devices. To overcome this limitation, three-dimensional semiconductor memory devices incorporating three-dimensionally arranged memory cells have recently been proposed. Summary of the Invention

[0003] Some exemplary embodiments of the inventive concept provide three-dimensional semiconductor memory devices with improved reliability.

[0004] According to some exemplary embodiments of the inventive concept, a semiconductor memory device includes: a peripheral circuit structure on a substrate; a semiconductor layer on the peripheral circuit structure; an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer; a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer; a separation structure penetrating the electrode structure, the separation structure extending in a first direction and horizontally dividing at least one electrode of the electrodes of the electrode structure into a pair of electrodes; an interlayer insulating layer covering the electrode structure; and a through contact penetrating the interlayer insulating layer and electrically connected to the peripheral circuit structure. When viewed in a plan view, the sidewalls of the separation structure include protruding portions and recessed portions, the protruding portions projecting in a direction away from the centerline of the separation structure, and the recessed portions recessed towards the centerline.

[0005] According to some exemplary embodiments of the inventive concept, a semiconductor memory device may include: a peripheral circuit structure on a substrate; a semiconductor layer on the peripheral circuit structure; an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer; a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer; a separation structure penetrating the electrode structure and horizontally dividing at least one electrode of the electrodes of the electrode structure into a pair of electrodes; a cell contact plug penetrating the stepped structure of the electrode structure; an interlayer insulating layer covering the electrode structure; and a through contact penetrating the interlayer insulating layer and electrically connected to the peripheral circuit structure. The separation structure includes a lower separation structure and an upper separation structure on the lower separation structure, the upper portion of the lower separation structure having a wider width than the lower portion of the upper separation structure.

[0006] According to some exemplary embodiments of the inventive concept, a semiconductor memory device may include: a peripheral circuit structure on a substrate, the peripheral circuit structure including peripheral transistors on the substrate, peripheral interconnects on the peripheral transistors, and peripheral contacts electrically connecting the peripheral transistors to the peripheral interconnects; a semiconductor layer on the peripheral circuit structure; an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer; a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer; a separation structure penetrating the electrode structure extending in a first direction and horizontally dividing a first electrode in the electrodes into a pair of electrodes; a cell contact plug penetrating the stepped structure of the electrode structure and electrically connected to a second electrode in the electrodes; an interlayer insulating layer covering the electrode structure; a through contact penetrating the interlayer insulating layer and electrically connected to the peripheral interconnects of the peripheral circuit structure; and bit lines and interconnects on the interlayer insulating layer. The vertical channel structure includes: a vertical semiconductor pattern having a tubular shape with an open top; and a vertical insulating pattern including a data storage layer, the data storage layer being interposed between the vertical semiconductor pattern and a third electrode in the electrodes. Bit lines are electrically connected to the vertical semiconductor pattern, connecting lines are electrically connected to the through contact, and the top surfaces of the separation structure, the vertical channel structure, the cell contact plug, and the through contact are coplanar with each other. Attached Figure Description

[0007] The exemplary embodiments will be more clearly understood through the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments as described herein.

[0008] Figure 1 This is a schematic perspective view illustrating some example embodiments of a three-dimensional semiconductor memory device according to the inventive concept.

[0009] Figure 2 This is a plan view illustrating some example embodiments of a three-dimensional semiconductor memory device according to the inventive concept.

[0010] Figure 3 It is along Figure 2 A sectional view taken by line I-I'.

[0011] Figures 4 to 13 It is along Figure 2 The cross-sectional view taken along line I-I' is used to illustrate a method for manufacturing a three-dimensional semiconductor memory device according to some exemplary embodiments of the inventive concept.

[0012] Figure 14A , Figure 14B and Figure 14C It shows the formation Figure 8 A plan view of the trenching method.

[0013] Figure 15 It is along Figure 2 A cross-sectional view taken along line I-I', used to illustrate a three-dimensional semiconductor memory device according to some exemplary embodiments of the inventive concept.

[0014] Figure 16A and Figure 16B They are shown separately. Figure 15 Enlarged sectional views of parts “M” and “N”.

[0015] Figure 17 and Figure 18 It is along Figure 2 The cross-sectional view taken along line I-I' is used to illustrate a method for manufacturing a three-dimensional semiconductor memory device according to some exemplary embodiments of the inventive concept.

[0016] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and are intended to supplement the written description provided below. However, these figures are not necessarily drawn to scale and may not precisely reflect the exact structural and / or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range of values ​​or properties included by the exemplary embodiments. For example, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0017] Figure 1 This is a schematic perspective view illustrating some example embodiments of a three-dimensional semiconductor memory device according to the inventive concept.

[0018] Reference Figure 1A three-dimensional semiconductor memory device according to some exemplary embodiments of the inventive concept may include a peripheral circuit structure PS, a cell array structure CS on the peripheral circuit structure PS, and a through contact (not shown) that vertically connects the cell array structure CS to the peripheral circuit structure PS. When viewed in a plan view, the cell array structure CS may overlap with the peripheral circuit structure PS.

[0019] In some exemplary embodiments of the inventive concept, the peripheral circuit structure PS may include row and / or column decoders, page buffers, control circuitry, and / or peripheral logic circuitry. The peripheral logic circuitry included in the peripheral circuit structure PS may be integrated on a semiconductor substrate.

[0020] A cell array structure CS may include a cell array comprising multiple storage cells arranged in three dimensions. For example, a cell array structure CS may include multiple storage blocks BLK0-BLKn. Each of the storage blocks BLK0-BLKn may include multiple storage cells arranged in three dimensions.

[0021] Figure 2 This is a plan view illustrating some example embodiments of a three-dimensional semiconductor memory device according to the inventive concept. Figure 3 It is along Figure 2 A sectional view taken by line I-I'.

[0022] Reference Figure 2 and Figure 3 The peripheral circuit structure PS, including the peripheral transistor PTR, can be disposed on the substrate SUB. The cell array structure CS, including the electrode structure ST, can be disposed on the peripheral circuit structure PS. The substrate SUB can be or may include a silicon substrate, a silicon-germanium substrate, a germanium substrate, and / or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The substrate SUB may include an active region defined by a device isolation layer DIL.

[0023] The peripheral circuit structure PS may include multiple peripheral transistors PTRs disposed on the active region of the substrate SUB. The peripheral transistors PTRs may constitute the row and column decoders, page buffers, control circuitry, and peripheral logic circuitry described above, or may be included within these components. The peripheral transistors PTRs may include NMOS and / or PMOS transistors with various oxide thicknesses and / or threshold voltages. The peripheral transistors PTRs may include planar transistors; however, the exemplary embodiments are not limited thereto. Peripheral interconnects PILs may be electrically connected to the peripheral transistors PTRs via peripheral contacts PCNTs.

[0024] The first interlayer insulating layer ILD1 can be provided on the substrate SUB to cover the peripheral transistor PTR, peripheral contact PCNT, and peripheral interconnect PIL. The first interlayer insulating layer ILD1 may include multiple stacked insulating layers. For example, the first interlayer insulating layer ILD1 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, and / or a low-k dielectric layer.

[0025] A cell array structure CS can be provided on the peripheral circuit structure PS. The cell array structure CS will be described in more detail below.

[0026] An etch stop layer (ESL) can be provided on the first interlayer insulating layer (ILD1). A second interlayer insulating layer (ILD2) can be provided on the etch stop layer (ESL). A semiconductor layer (SL) can be provided in the second interlayer insulating layer (ILD2). A semiconductor layer (SL) can be provided in the cell array region (CAR) of the cell array structure (CS). A portion of the semiconductor layer (SL) can be provided in the connection region (CNR) of the cell array structure (CS).

[0027] The semiconductor layer SL may include a lower semiconductor layer LSL, a source semiconductor layer SSL on the lower semiconductor layer LSL, and an upper semiconductor layer USL on the source semiconductor layer SSL. The lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may overlap each other perpendicularly. The source semiconductor layer SSL may be inserted between the lower semiconductor layer LSL and the upper semiconductor layer USL. The lower semiconductor layer LSL and the upper semiconductor layer USL may be electrically connected to each other through the source semiconductor layer SSL.

[0028] In detail, the lower semiconductor layer (LSL) may be formed of and / or include at least one semiconductor material (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs), or mixtures thereof). The lower semiconductor layer (LSL) may have at least one of a single-crystal structure, an amorphous structure, and a polycrystalline structure. As an example, the lower semiconductor layer (LSL) may include an n-type doped polycrystalline silicon layer, such as a polycrystalline silicon layer including dopants such as arsenic and / or phosphorus.

[0029] Although not shown, in some example embodiments, a metal-containing conductive layer may be provided below the lower semiconductor layer LSL. This conductive layer can reduce the resistance of the semiconductor layer SL.

[0030] In some example implementations, each of the source semiconductor layer SSL and the upper semiconductor layer USL may comprise the same semiconductor material as the lower semiconductor layer LSL. As an example, the source semiconductor layer SSL may comprise an n-type doped polysilicon layer. The upper semiconductor layer USL may comprise an n-type doped polysilicon layer. The concentration of impurities in the source semiconductor layer SSL may differ from (e.g., may be greater than or less than) the concentration of impurities in the lower semiconductor layer LSL. The concentration of impurities in the upper semiconductor layer USL may differ from (e.g., may be greater than or less than) the concentration of impurities in the lower semiconductor layer LSL.

[0031] An electrode structure ST can be provided on a semiconductor layer SL. The electrode structure ST may include multiple electrodes EL stacked on the upper semiconductor layer USL in a vertical direction (e.g., third direction D3). The electrode structure ST may also include a first insulating layer IL1 separating the stacked electrodes EL from each other. The first insulating layer IL1 and the electrodes EL of the electrode structure ST may be stacked alternately on the third direction D3.

[0032] The electrode structure ST can extend from the cell array region CAR of the cell array structure CS to the connection region CNR of the cell array structure CS. The electrode structure ST can have a stepped structure STS on or within the connection region CNR. For example, as the distance from the cell array region CAR increases, the height of the electrode structure ST on the connection region CNR can decrease in a stepwise manner.

[0033] The electrode structure ST may also include a molded structure MO provided therein. The molded structure MO may be provided in the stepped structure STS and may not be provided within the cell array region CAR. The molded structure MO may include a sacrificial layer HL stacked on a second interlayer insulating layer ILD2 on a third-direction D3. The molded structure MO may also include a first insulating layer IL1 that separates the stacked sacrificial layers HL from each other. The first insulating layer IL1 and the sacrificial layers HL of the molded structure MO may be stacked alternately on the third-direction D3.

[0034] The sacrificial layer HL of the molded structure MO can be provided as having a stepped structure. For example, as the distance from the cell array region CAR increases, the height of the molded structure MO on the connection region CNR can be reduced in a stepwise manner.

[0035] The sacrificial layer HL of the molded structure MO can physically connect the electrodes EL on the cell array region CAR and the connecting region CNR to each other, wherein the electrodes EL on the cell array region CAR and the connecting region CNR are at the same level. For example, the sacrificial layer HL can be inserted between electrodes EL respectively disposed on the cell array region CAR and the connecting region CNR and located at the same level.

[0036] The sacrificial layer HL may be formed of and / or comprise an insulating material (such as silicon nitride and / or silicon nitride). Since both the sacrificial layer HL and the first insulating layer IL1 of the molded structure MO comprise insulating materials, the molded structure MO may be an insulator.

[0037] In electrode structure ST, the bottom electrode in the electrode EL can be used as the bottom select line. The top electrode in the electrode EL of electrode structure ST can be used as the top select line. All electrodes EL except the bottom and top select lines can be used as word lines.

[0038] The electrode EL may include at least one conductive material selected from or including the group consisting of: doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitrides or tantalum nitrides), and transition metals (e.g., titanium or tantalum). The first insulating layer IL1 may be formed of and / or include silicon oxide.

[0039] The electrode structure ST on the cell array region CAR may further include a second insulating layer IL2. The second insulating layer IL2 may be provided only partially on the cell array region CAR and may not be provided on the connection region CNR. The thickness of the second insulating layer IL2 may be greater than the thickness of the first insulating layer IL1. The second insulating layer IL2 may be formed of and / or comprise the same insulating material as the first insulating layer IL1. As an example, the second insulating layer IL2 may be formed of and / or comprise silicon oxide.

[0040] Multiple vertical channel structures VS of the through-electrode structure ST can be provided on the cell array region CAR. When viewed in a plan view, the vertical channel structures VS can be arranged in a specific (e.g., periodic) direction and / or in a zigzag and / or honeycomb pattern. Each vertical channel structure VS may include a vertical insulating pattern VP, a vertical semiconductor pattern SP, and a gap-filling insulating pattern VI.

[0041] A vertical insulating pattern VP can be inserted between the electrode structure ST and the vertical semiconductor pattern SP. The vertical insulating pattern VP extends vertically from the top surface of the electrode structure ST towards the lower semiconductor layer LSL. The vertical insulating pattern VP can be shaped like an open-top tube (e.g., like a PVC pipe). The vertical semiconductor pattern SP can cover the inner surface of the vertical insulating pattern VP. The vertical semiconductor pattern SP can extend towards the lower semiconductor layer LSL together with the vertical insulating pattern VP. The vertical semiconductor pattern SP can also be shaped like an open-top tube (e.g., like a PVC pipe). The internal space of the vertical semiconductor pattern SP can be filled with a gap-filling insulating pattern VI.

[0042] The vertical insulating pattern VP may include one or more layers. In some exemplary embodiments of the inventive concept, the vertical insulating pattern VP may include a data storage layer. For example, the vertical insulating pattern VP may be used as a data storage layer of a NAND FLASH memory device and / or as part of a data storage layer, and may include a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In a NAND FLASH memory device, the charge storage layer between the electrode EL and the vertical semiconductor pattern SP may be used to store data. The data stored in the charge storage layer may vary due to the Fowler-Nordheim (FN) tunneling phenomenon, which can occur when there is a voltage difference (e.g., at least a specific voltage difference) between the electrode EL and the vertical semiconductor pattern SP.

[0043] For example, the charge storage layer may be and / or may include a trap insulating layer, a floating gate electrode, or an insulating layer having conductive nanodots. In some example embodiments, the charge storage layer may include at least one of a silicon nitride layer, a silicon oxide nitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a stacked trap layer. The tunnel insulating layer may be formed of and / or include at least one material whose band gap is larger than that of the charge storage layer. The tunnel insulating layer may be formed of at least one high-k dielectric material (e.g., aluminum oxide and / or hafnium oxide) or silicon oxide, and / or include at least one high-k dielectric material (e.g., aluminum oxide and / or hafnium oxide) or silicon oxide. The barrier insulating layer may be formed of and / or include silicon oxide.

[0044] The vertical semiconductor pattern SP can be formed from and / or include at least one semiconductor material (e.g., silicon (Si), germanium (Ge), or mixtures thereof). Furthermore, the vertical channel structure VS can be formed from and / or include doped semiconductor material or intrinsic semiconductor material. The vertical semiconductor pattern SP containing semiconductor material can be used as the channel region of transistors constituting or corresponding to a cell string of a NAND FLASH memory device.

[0045] Conductive pads (PADs) can be provided in or on the top of each vertical channel structure (VS). The conductive pads (PADs) can cover the top surface of the vertical semiconductor pattern (SP) and the top surface of the gap-filling insulating pattern (VI). The side surfaces of the conductive pads (PADs) can contact the inner surface of the vertical insulating pattern (VP). The conductive pads (PADs) can be formed of and / or include at least one of a doped semiconductor material and a conductive material. Bit line contact plugs (BPLGs) can be electrically connected to the vertical semiconductor pattern (SP) via the conductive pads (PADs).

[0046] Each vertical channel structure VS may have a first diameter DI1. The first diameter DI1 of the vertical channel structure VS may gradually decrease in the downward direction. The first diameter DI1 may have a maximum value at the top horizontal position of the vertical channel structure VS. The cross-section of the vertical channel structure VS may have a tapered shape.

[0047] The source semiconductor layer SSL can contact the lower sidewall of each vertical semiconductor pattern SP, for example, through direct contact. The source semiconductor layer SSL can electrically connect the vertical semiconductor patterns SP to each other. Therefore, the vertical semiconductor patterns SP, the source semiconductor layer SSL, the lower semiconductor layer LSL, and the upper semiconductor layer USL can be electrically connected to each other.

[0048] The three-dimensional semiconductor memory device according to some exemplary embodiments of the inventive concept can be or may include a three-dimensional NAND FLASH memory device. The cell strings of the NAND FLASH memory device can be integrated in an electrode structure ST on a semiconductor layer SL. The electrode structure ST and the vertical channel structure VS penetrating the electrode structure ST can constitute or correspond to memory cells arranged three-dimensionally on the semiconductor layer SL. The electrode EL of the electrode structure ST can be used as the gate electrode of a transistor.

[0049] Multiple discrete structures SPS can be provided as a through electrode structure ST. The discrete structures SPS can extend in a second direction D2 and be parallel to each other. For example, the discrete structures SPS can horizontally divide one electrode EL in the electrode structure ST into multiple electrodes EL. The multiple electrodes EL divided by the discrete structures SPS can be arranged along a first direction D1. The first direction D1 can be horizontal with respect to the surface of the substrate SUB. The multiple electrodes EL divided by the discrete structures SPS can extend in a second direction D2 and can be parallel to each other. The second direction D2 can be horizontal with respect to the surface of the substrate SUB. The discrete structures SPS can be formed of and / or comprise an insulating material (e.g., silicon oxide).

[0050] Return to reference Figure 2 When viewed in a plan view, the sidewalls SW of the split structure SPS can have a wavy and / or uneven shape. Specifically, the sidewalls SW of the split structure SPS can include a protruding portion PP and a recessed portion SS. The protruding portion PP can protrude in a direction away from the centerline CLE of the split structure SPS. For example, the protruding portion PP can protrude from the centerline CLE of the split structure SPS in a first direction D1. The recessed portion SS can be recessed from the protruding portion PP toward the centerline CLE of the split structure SPS.

[0051] The maximum width W1 of the separation structure SPS in the first direction D1 can be defined by a pair of opposing protruding portions PP of the opposing sidewalls SW. The minimum width W2 of the separation structure SPS in the first direction D1 can be defined by a pair of opposing recessed portions SS of the opposing sidewalls SW. The maximum width W1 of the separation structure SPS can be greater than the first diameter DI1 of the upper part of the vertical channel structure VS. The minimum width W2 of the separation structure SPS can be less than, equal to, or greater than the first diameter DI1 of the upper part of the vertical channel structure VS.

[0052] Return to reference Figure 2 and Figure 3 The third interlayer insulating layer ILD3 can be provided on the semiconductor layer SL and the second interlayer insulating layer ILD2. The third interlayer insulating layer ILD3 can cover the stepped structure STS of the electrode structure ST. The fourth interlayer insulating layer ILD4 can be provided on the third interlayer insulating layer ILD3.

[0053] A unit contact plug PLG can be provided on the connection region CNR. The unit contact plug PLG can be provided as an electrode EL penetrating the stepped structure STS and a molded structure MO below the electrode EL. As described above, because the molded structure MO is an insulator or includes an insulator, one unit contact plug PLG can be connected to one electrode EL.

[0054] Each unit contact plug PLG may have a second diameter DI2. The second diameter DI2 of the unit contact plug PLG may gradually decrease in the downward direction. The second diameter DI2 may have a maximum value at the top horizontal position of the unit contact plug PLG. The second diameter DI2 of the upper part of the unit contact plug PLG may be larger than the first diameter DI1 of the upper part of the vertical channel structure VS. The contact plug PLG may have a tapered shape.

[0055] The unit contact plug PLG may include a first unit contact plug PLG1 and a second unit contact plug PLG2. The first unit contact plug PLG1 may be provided as a stepped structure STS that penetrates the electrode structure ST and may extend toward the semiconductor layer SL. An insulating pattern IP may be inserted between the first unit contact plug PLG1 and the upper semiconductor layer USL. The first unit contact plug PLG1 may be separated from the semiconductor layer SL by the insulating pattern IP, for example, through electrical separation.

[0056] The second unit contact plug PLG2 can penetrate the stepped structure STS of the electrode structure ST and extend towards the peripheral circuit structure PS. The second unit contact plug PLG2 can also penetrate the second interlayer insulating layer ILD2 and the etch stop layer ESL, and can be connected to the uppermost peripheral interconnect in the peripheral interconnect PIL. As a result, the electrode EL and the uppermost peripheral interconnect in the peripheral interconnect PIL can be electrically connected to each other through the second unit contact plug PLG2.

[0057] At least one through-contact TVS can be provided on the through-contact region TVR of the substrate SUB. The through-contact TVS can be provided to penetrate the third interlayer insulating layer ILD3, the second interlayer insulating layer ILD2, and the etch stop layer ESL, and can be connected to the uppermost peripheral interconnect in the peripheral interconnect PIL. When viewed in a plan view, the through-contact TVS can be provided in the through-contact region TVR. The through-contact region TVR can be adjacent to the stepped structure STS of the electrode structure ST in the second direction D2.

[0058] The through-contact TVS may have a third diameter DI3. The third diameter DI3 of the through-contact TVS may gradually decrease in the downward direction. The third diameter DI3 may have its maximum value at the highest level of the through-contact TVS. The third diameter DI3 at the upper part of the through-contact TVS may be larger than the first diameter DI1 at the upper part of the vertical channel structure VS. The through-contact TVS may have a tapered shape.

[0059] Multiple bit lines BL and multiple connecting lines CL can be provided on the fourth interlayer insulating layer ILD4. The bit lines BL can extend in the first direction D1 and be parallel to each other.

[0060] Bit line contact plugs (BPLGs) can be provided within the fourth interlayer insulating layer (ILD4), for example, within the fourth interlayer insulating layer (ILD4). The BPLGs can be individually coupled to conductive pads (PADs) on the vertical channel structure (VS). Each bit line (BL) can be electrically connected to the vertical semiconductor pattern (SP) via the BPLGs and conductive pads (PADs).

[0061] The via VIA can be provided in the fourth interlayer insulation layer ILD4. At least one of the connecting wires CL can be electrically connected to the first unit contact plug PLG1 via the via VIA. At least one of the connecting wires CL can be electrically connected to the through contact TVS via the via VIA.

[0062] According to some exemplary embodiments of the present invention, each or at least some of the vertical channel structure VS, the split structure SPS, the unit contact plug PLG, and the through contact TVS may have top surfaces that are coplanar with each other. For example, the top surfaces of each or at least some of the vertical channel structure VS, the split structure SPS, the unit contact plug PLG, and the through contact TVS may be coplanar with the top surface of the third interlayer insulation layer ILD3.

[0063] Figures 4 to 13 It is along Figure 2 The cross-sectional view taken along line I-I' illustrates a method for manufacturing a three-dimensional semiconductor memory device according to some exemplary embodiments of the inventive concept. Figure 14A , Figure 14B and Figure 14C It shows the formation Figure 8 A plan view of the trenching method.

[0064] Reference Figure 2 and Figure 4 A peripheral circuit structure PS can be formed on the substrate SUB. The formation of the peripheral circuit structure PS may include: forming a peripheral transistor PTR on the substrate SUB; forming a peripheral interconnect PIL on the peripheral transistor PTR; forming a peripheral contact PCNT connecting the peripheral transistor PTR to the peripheral interconnect PIL; and forming a first interlayer insulating layer ILD1.

[0065] For example, the formation of a peripheral transistor (PTR) may include: forming a device isolation layer (DIL) on a substrate (SUB) to define an active region; doping a portion of the active region to form a well region; forming a gate insulating layer and a gate electrode on the active region; and / or doping the upper part of the active region to form a source / drain region.

[0066] An etch stop layer (ESL) may be formed on the first interlayer insulating layer (ILD1). A second interlayer insulating layer (ILD2) may be formed on the ESL. A lower semiconductor layer (LSL) may be formed in the second interlayer insulating layer (ILD2). The lower semiconductor layer (LSL) may be formed of at least one semiconductor material (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof), and / or include at least one semiconductor material (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof).

[0067] A third insulating layer IL3, a lower sacrificial layer LHL, and a fourth insulating layer IL4 can be formed on the lower semiconductor layer LSL. When viewed in a plan view, the lower sacrificial layer LHL can overlap with the lower semiconductor layer LSL. For example, the third insulating layer IL3 and the fourth insulating layer IL4 can be formed of and / or include silicon oxide, and the lower sacrificial layer LHL can be formed of and / or include silicon nitride or silicon oxide.

[0068] An upper semiconductor layer USL can be formed on the fourth insulating layer IL4. When viewed in a plan view, the upper semiconductor layer USL can overlap with the lower semiconductor layer LSL. The top surface of the upper semiconductor layer USL can be coplanar with the top surface of the second interlayer insulating layer ILD2. The upper semiconductor layer USL can be formed of and / or include semiconductor material.

[0069] A molded structure MO can be formed on the upper semiconductor layer USL. For example, the molded structure MO can be formed by repeatedly and alternately stacking a first insulating layer IL1 and a sacrificial layer HL on the upper semiconductor layer USL. A second insulating layer IL2 can be formed as the topmost layer of the molded structure MO.

[0070] A first insulating layer IL1, a sacrificial layer HL, and a second insulating layer IL2 can be deposited using at least one of the following processes: thermal or low-pressure chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical chemical vapor deposition, and atomic layer deposition (ALD). The first insulating layer IL1 may be formed of and / or comprise silicon oxide, and the sacrificial layer HL may be formed of and / or comprise silicon nitride or silicon oxide nitride.

[0071] A stepped structure STS can be formed in a molded structure MO. For example, a cell array structure CS on a peripheral circuit structure PS can include a cell array region CAR and a connection region CNR. A cyclic patterning process can be performed on the molded structure MO to form a stepped structure STS on the connection region CNR.

[0072] The formation of the stepped structure STS may include forming a mask pattern (not shown) on the molded structure MO and performing a cyclic patterning process several times using the mask pattern. Each cyclic patterning process may include using the mask pattern as an etching mask to etch a portion of the molded structure MO and performing a trimming process to reduce the size of the mask pattern.

[0073] The third interlayer insulating layer ILD3 can be formed on the molded structure MO. The formation of the third interlayer insulating layer ILD3 may include thickly forming an insulating layer to cover the molded structure MO and performing planarization processes on the insulating layer, such as chemical mechanical planarization (CMP) and / or etch-back processes, to expose the second insulating layer IL2.

[0074] Reference Figure 2 and Figure 5 A patterning process can be performed on a structure having a third interlayer insulating layer (ILD3) to form first to fifth holes HO1-HO5 with high aspect ratios. The patterning process can include forming a hard mask with multiple openings on the molded structure MO and the third interlayer insulating layer ILD3, and using the hard mask as an etching mask to perform anisotropic etching. The anisotropic etching process can be or includes plasma etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), and / or ion beam etching (IBE).

[0075] The first to fifth holes HO1-HO5 can be formed to have the same or similar diameters. Each of the first to fifth holes HO1-HO5 can have a first diameter DI1 at its top horizontal position.

[0076] The first to third holes HO1, HO2, and HO3 can be formed on the upper semiconductor layer USL. The first to third holes HO1, HO2, and HO3 can penetrate the molded structure MO and expose the upper semiconductor layer USL. The first to third holes HO1, HO2, and HO3 can have bottoms located at the same level (e.g., a first height LV1).

[0077] The fourth via HO4 and the fifth via HO5 can be formed on the first interlayer insulating layer ILD1. The fifth via HO5 can be formed in the through-contact region TVR. The fourth via HO4 and the fifth via HO5 can penetrate the molded structure MO, the second interlayer insulating layer ILD2, and the etch stop layer ESL, and can expose the uppermost peripheral interconnect in the peripheral interconnect PIL. The fourth via HO4 and the fifth via HO5 can have a bottom located at the same level (e.g., a second height LV2). The second level LV2 can be lower than the first level LV1.

[0078] By adjusting the etching recipe in the anisotropic etching process forming the first to fifth holes HO1-HO5, it is possible to terminate the etching of the first to third holes HO1, HO2, and HO3 when the upper semiconductor layer USL is exposed. The etching of the fourth hole HO4 and the fifth hole HO5 can be adjusted to terminate when the uppermost peripheral interconnect in the peripheral interconnect PIL is exposed. In other words, it is possible to form holes HO1-HO5 with their bottoms at different levels by performing an anisotropic etching process in one step. The anisotropic etching process can be performed using (e.g., based on) the etch selectivity (i.e., the difference in etch rate) between the upper semiconductor layer USL and the second interlayer insulating layer ILD2. For example, the endpoint of the anisotropic etching process can be determined based on the light emission signal associated with the upper semiconductor layer USL.

[0079] Reference Figure 2 and Figure 6 A sacrificial material SAC can be formed to fill the first to fifth holes HO1-HO5. Subsequently, the first hole HO1 can be vacated by selectively removing the sacrificial material SAC from it. An anisotropic etching process can be further performed on the first hole HO1 from which the sacrificial material SAC has been removed, such that the first hole HO1 has a bottom HO1b located at a third level LV3. The third level LV3 can be lower than the first level LV1. The third level LV3 can be located between the bottom and top levels of the lower semiconductor layer LSL. For example, due to the additional anisotropic etching process, the first hole HO1 can be formed to expose the lower semiconductor layer LSL.

[0080] refer to Figure 2 and Figure 7 A vertical channel structure VS can be formed in the first hole HO1. Specifically, the formation of the vertical channel structure VS may include sequentially forming a vertical insulating layer, a vertical semiconductor layer, and an insulating gap-filling layer on the inner surface of the first hole HO1, followed by a planarization process to expose the top surface of the second insulating layer IL2. The planarization process may include at least one of a CMP process and an etch-back process. The vertical insulating layer and the vertical semiconductor layer may be formed to conformally cover the inner surface of the first hole HO1.

[0081] As a result of the planarization process, the vertical insulating pattern VP can be formed to cover the inner surface of the first hole HO1. The vertical insulating pattern VP can be shaped like a tube (e.g., a PVC pipe) with an open top. The vertical insulating pattern VP may include a data storage layer.

[0082] Similarly, the vertical semiconductor pattern SP can be formed to cover the inner surface of the vertical insulating pattern VP. The vertical semiconductor pattern SP can be shaped like a tube (e.g., a PVC pipe) with an open top. Due to the vertical insulating pattern VP, the vertical semiconductor pattern SP can be spaced apart from the upper semiconductor layer USL and the lower semiconductor layer LSL.

[0083] The gap-filling insulating pattern VI can be formed to fill the internal space of the vertical semiconductor pattern SP. The vertical insulating pattern VP, the vertical semiconductor pattern SP, and the gap-filling insulating pattern VI can be formed or included in the vertical channel structure VS. The conductive pad PAD can be formed in or on the upper part of each vertical channel structure VS.

[0084] Reference Figure 2 , Figure 8 and Figure 14A The second hole HO2 can be made vacant by selectively removing the sacrificial material SAC from it. The second hole HO2 can be arranged in the second direction D2.

[0085] Reference Figure 2 , Figure 8 and Figure 14B An isotropic etching process can be performed on the second hole HO2 to extend the second hole HO2. The second hole HO2 can correspond to the hole from which the sacrificial material SAC has been removed. As a result of the isotropic etching process, the second holes HO2 arranged in the second direction D2 can be connected to each other to form a trench TR that extends in the second direction D2.

[0086] The groove TR can be formed as a through-molded structure MO. The groove TR can extend in the second direction D2 and can be parallel to each other. Due to the groove TR, each sacrificial layer HL of the molded structure MO can be horizontally divided into multiple sacrificial layers HL. When viewed in a plan view, the sidewalls SW of the groove TR can have a wavy or uneven shape. The sidewalls SW of the groove TR can include protruding portions PP and recessed portions SS.

[0087] In some example implementations, in conjunction with Figure 14B Compared to the enhancement method shown, when performing an isotropic etching process on the second hole HO2, the trench TR can be formed as a line shape in the planar view, such as... Figure 14C As shown. For example, the sidewall SW of the trench TR can have a linear shape. Therefore, when viewed in a plan view, the separation structure SPS formed in the trench TR can also have a linear shape.

[0088] refer to Figure 2 and Figure 9Sidewall spacers (SSPs) can be formed on the inner sidewall of the trench TR. The formation of the sidewall spacers (SSPs) may include forming an insulating layer on the inner sidewall of the trench TR and anisotropically etching the insulating layer to expose the bottom of the trench TR.

[0089] An anisotropic etching process can be performed on the trench TR to form a recess RES extending from the trench TR to the lower semiconductor layer LSL. For example, the trench TR can be formed to expose the lower semiconductor layer LSL. The trench TR can expose the inner sidewalls of the third insulating layer IL3, the inner sidewalls of the lower sacrificial layer LHL, and the inner sidewalls of the fourth insulating layer IL4.

[0090] refer to Figure 2 and Figure 10 The lower sacrificial layer LHL exposed through the trench TR can be replaced with the source semiconductor layer SSL. Specifically, the lower sacrificial layer LHL exposed through the trench TR can be selectively removed. The lower sacrificial layer LHL can be removed using a wet etching process; however, the example implementation is not limited to this. Due to the removal of the lower sacrificial layer LHL, the lower portion of the vertical insulating pattern VP of each vertical channel structure VS can be exposed.

[0091] The exposed lower portion of the vertical insulating pattern VP can be selectively removed, for example, by a wet etching process. Therefore, the lower portion of the vertical semiconductor pattern SP can be exposed. During the removal of the lower portion of the vertical insulating pattern VP, the third insulating layer IL3 and the fourth insulating layer IL4 can be removed simultaneously.

[0092] The source semiconductor layer SSL can be formed in the space created by removing the third insulating layer IL3, the lower sacrificial layer LHL, and the fourth insulating layer IL4. The source semiconductor layer SSL can contact (e.g., direct contact) the exposed lower portion of the vertical semiconductor pattern SP. The source semiconductor layer SSL can also directly contact the lower semiconductor layer LSL below it. The source semiconductor layer SSL can also contact (e.g., direct contact) the upper semiconductor layer USL above it. The upper semiconductor layer USL, the source semiconductor layer SSL, and the lower semiconductor layer LSL can be formed within or included in the semiconductor layer SL.

[0093] Subsequently, the sidewall spacers SSP can be selectively removed from the trench TR. Therefore, the inner sidewalls of the sacrificial layer HL can be exposed through the trench TR.

[0094] refer to Figure 2 and Figure 11The sacrificial layer HL exposed through the trench TR can be replaced with electrodes EL. Specifically, the sacrificial layer HL exposed through the trench TR can be selectively removed (e.g., selectively removed using a wet etching process). Electrodes EL can be formed in the empty spaces from which the sacrificial layer HL has been removed. The replaced electrodes EL can form (e.g., correspond to) an electrode structure ST. The unremoved portion of the sacrificial layer HL remaining on the connection region CNR can form or correspond to a molded structure MO.

[0095] Reference Figure 2 and Figure 12 Holes HO3 and HO4 can be vacated by selectively removing the sacrificial material SAC from them. An isotropic etching process can be performed on the holes HO3 and HO4 from which the sacrificial material SAC has been removed to expand each of them (e.g., to expand the diameter of each of them). Therefore, each of the holes HO3 and HO4 can have a second diameter DI2 at its top level. The second diameter DI2 can be larger than the previously referenced diameter. Figure 5 The first diameter DI1 is described. The isotropic etching process may be or may include a wet etching process; however, the example implementation is not limited thereto.

[0096] An oxidation process, such as thermal oxidation, can be performed on the upper semiconductor layer USL exposed through the third hole HO3 to form an insulating pattern IP that fills the lower part of the third hole HO3. The first unit contact plug PLG1 and the second unit contact plug PLG2 can be formed by filling the third hole HO3 and the fourth hole HO4 with conductive materials, respectively.

[0097] Reference Figure 2 and Figure 13 The fifth hole HO5 can be vacated by selectively removing the sacrificial material SAC from it. An isotropic etching process, such as a wet etching process, can be performed on the fifth hole HO5 from which the sacrificial material SAC has been removed to extend the fifth hole HO5. Therefore, the fifth hole HO5 can have a third diameter DI3 at its top horizontal position. The third diameter DI3 can be larger than the previously referenced... Figure 5 The first diameter DI1 is described. A through-contact TVS can be formed by filling the fifth hole HO5 with a conductive material.

[0098] Return to reference Figure 2 and Figure 3A fourth interlayer insulating layer (ILD4) can be formed on the molded structure MO and the third interlayer insulating layer (ILD3). A bit line contact plug (BPLG) and a passage (VIA) can be formed in the fourth interlayer insulating layer (ILD4). A bit line (BL) electrically connected to the bit line contact plug (BPLG) and a connection line (CL) electrically connected to the passage (VIA) can be formed on the fourth interlayer insulating layer (ILD4).

[0099] According to some exemplary embodiments of the present invention, it is possible to simultaneously form the first to fifth holes HO1-HO5 and define the vertical channel structure VS, the split structure SPS, the cell contact plug PLG, and the through contact TVS. The first to fifth holes HO1-HO5 can have a high aspect ratio. Since multiple structures are formed through a single process, the manufacturing process of semiconductor memory devices can be simplified, and / or manufacturing costs can be reduced. Because the first to fifth holes HO1-HO5 are formed simultaneously, the vertical channel structure VS, the split structure SPS, the cell contact plug PLG, and the through contact TVS can have top surfaces that are coplanar with each other.

[0100] Figure 15 It is along Figure 2 A cross-sectional view taken along line I-I' to illustrate a three-dimensional semiconductor memory device according to some exemplary embodiments of the inventive concept. Figure 16A and Figure 16B They are shown separately. Figure 15 Enlarged sectional views of parts "M" and "N". For brevity, refer to the previous reference. Figure 2 and Figure 3 The described elements may be identified by the same reference numerals without having to repeat their description.

[0101] Reference Figure 2 , Figure 15 , Figure 16A and Figure 16B Each vertical channel structure VS may include a lower channel structure VSa and an upper channel structure VSb on the lower channel structure VSa. Each split structure SPS may include a lower split structure SPSa and an upper split structure SPSb on the lower split structure SPSa. Each unit contact plug PLG may include a lower contact plug PLGa and an upper contact plug PLGb on the lower contact plug PLGa. A through contact TVS may include a lower through contact TVSa and an upper through contact TVSb on the lower through contact TVSa.

[0102] The top surfaces of the lower channel structure VSa, the lower separation structure SPSa, the lower contact plug PLGa, and the lower through contact TVSa can be coplanar. For example, the top surfaces of the lower channel structure VSa, the lower separation structure SPSa, the lower contact plug PLGa, and the lower through contact TVSa can be located at the same level (e.g., fourth level LV4).

[0103] The top surfaces of the upper channel structure VSb, the upper separation structure SPSb, the upper contact plug PLGb, and the upper through contact TVSb can be coplanar with each other.

[0104] The upper diameter DI1a of the lower channel structure VSa can be larger than the lower diameter DI1b of the upper channel structure VSb. The diameter of the vertical channel structure VS can change abruptly near the boundary between the lower channel structure VSa and the upper channel structure VSb.

[0105] The width Wla of the upper part of the lower separation structure SPSa can be greater than the width Wlb of the lower part of the upper separation structure SPSb. The width of the separation structure SPS can change abruptly near the boundary between the lower separation structure SPSa and the upper separation structure SPSb.

[0106] The diameter DI2a of the upper part of the lower contact plug PLGa can be larger than the diameter DI2b of the lower part of the upper contact plug PLGb. The diameter of the unit contact plug PLG can change drastically near the boundary between the lower contact plug PLGa and the upper contact plug PLGb.

[0107] Figure 17 and Figure 18 It is along Figure 2 A cross-sectional view taken along line I-I' to illustrate a method for manufacturing a three-dimensional semiconductor memory device according to some exemplary embodiments of the inventive concept. For brevity, previous references... Figure 2 and Figures 4 to 14B The described elements may be identified by the same reference numerals without repeating their descriptions.

[0108] Reference Figure 2 and Figure 17 A first molding structure MO1 can be formed on the upper semiconductor layer USL. Specifically, the first molding structure MO1 can be formed by vertically and alternately stacking a first insulating layer IL1 and a sacrificial layer HL on the upper semiconductor layer USL. A stepped structure STS can be formed in the first molding structure MO1. A third interlayer insulating layer ILD3 can be formed to cover the stepped structure STS of the first molding structure MO1.

[0109] A patterning process can be performed on the structure having a third interlayer insulating layer ILD3 to form the first to fifth holes HO1-HO5 with a high aspect ratio. The first to fourth holes HO1-HO4 can be formed to penetrate the first molded structure MO1.

[0110] Reference Figure 2 and Figure 18 A sacrificial material SAC can be formed to fill the first to fifth holes HO1-HO5. A second molding structure MO2 can be formed on the first molding structure MO1 and the third interlayer insulating layer ILD3. Specifically, the second molding structure MO2 can be formed by vertically and alternately stacking the first insulating layer IL1 and the sacrificial layer HL on the first molding structure MO1. The second insulating layer IL2 can be formed as the uppermost layer of the second molding structure MO2. A stepped structure STS can be formed in the second molding structure MO2. An additional interlayer insulating layer ILD3a can be formed to cover the stepped structure STS of the second molding structure MO2.

[0111] A patterning process can be performed on the structure with an additional interlayer insulating layer ILD3a to additionally form first to fifth holes HO1-HO5 with high aspect ratios. The first to fifth holes HO1-HO5 can be formed as sacrificial material SAC that exposes and fills the first to fifth holes HO1-HO5 of the first molded structure MO1. This can be compared with reference to... Figures 6 to 13 The subsequent processes are performed in essentially the same way as described.

[0112] In a method for manufacturing a semiconductor memory device according to some exemplary embodiments of the present invention, high aspect ratio holes defining vertical channel structures, discrete structures, cell contact plugs, and through contacts can be formed simultaneously. Since multiple structures are formed through a single process, the manufacturing process of the semiconductor memory device can be simplified, and manufacturing costs can be reduced.

[0113] According to the reference Figure 1-18The described example embodiments indicate that the semiconductor device may correspond to a three-dimensional memory device with memory cells above peripheral circuitry. However, the example embodiments are not limited thereto. According to some example embodiments, the semiconductor device may include a semiconductor layer, an electrode structure on the semiconductor layer, an electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and connected to the semiconductor layer, a separation structure penetrating the electrode structure, and an interlayer insulating layer covering the electrode structure. This separation structure extends in a first direction and horizontally divides at least one of the electrodes of the electrode structure into a pair of electrodes. When viewed in a plan view, the sidewalls of the separation structure include protruding portions and recessed portions, the protruding portions projecting in a direction away from the centerline of the separation structure, and the recessed portions recessed towards the centerline. The peripheral circuitry structure may be on a substrate, but the memory cells may not be above the peripheral circuitry.

[0114] Although exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made without departing from the spirit and scope of the appended claims.

[0115] This application claims priority to Korean Patent Application No. 10-2019-0113457, filed with the Korean Intellectual Property Office on September 16, 2019, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: Peripheral circuit structure on the substrate; Semiconductor layer on the peripheral circuit structure; An electrode structure on the semiconductor layer, the electrode structure comprising electrodes stacked on the semiconductor layer; A vertical channel structure that penetrates the electrode structure and connects to the semiconductor layer; A separation structure that penetrates the electrode structure, the separation structure extending in a first direction and horizontally dividing at least one electrode of the electrodes in the electrode structure into a pair of electrodes; Interlayer insulation layer covering the electrode structure; as well as A through-contact that penetrates the interlayer insulation and is electrically connected to the peripheral circuit structure. Wherein, the top surface of the separation structure, the top surface of the vertical channel structure, the top surface of the through contact, and the top surface of the interlayer insulation layer are coplanar with each other, and When viewed in a plan view, the sidewall of the separation structure includes a protruding portion and a recessed portion, the protruding portion protruding in a direction away from the centerline of the separation structure, the recessed portion being recessed toward the centerline, and the sidewall of the separation structure having at least one of a wavy shape and an uneven shape.

2. The semiconductor memory device according to claim 1, wherein, In the second direction, the protruding portion defines the maximum width of the separation structure. In the second direction, the recessed portion defines the minimum width of the separation structure, and The second direction intersects the first direction.

3. The semiconductor memory device according to claim 2, wherein, The maximum width of the separation structure is greater than the diameter of the upper part of the vertical channel structure.

4. The semiconductor memory device according to claim 1, wherein, The vertical channel structure includes: Vertical semiconductor patterns with a tubular shape and open top; and The invention includes a vertical insulating pattern for a data storage layer, the vertical insulating pattern being interposed between the vertical semiconductor pattern and at least one of the electrodes.

5. The semiconductor memory device according to claim 1, wherein, The electrodes of the electrode structure and the vertical channel structure penetrating the electrodes of the electrode structure correspond to a three-dimensionally arranged memory cell.

6. The semiconductor memory device according to claim 1, wherein, The semiconductor layer includes a lower semiconductor layer, an upper semiconductor layer, and a source semiconductor layer interposed between the lower semiconductor layer and the upper semiconductor layer. The vertical channel structure is connected to the source semiconductor layer.

7. The semiconductor memory device according to claim 1, further comprising: The stepped unit contact plug penetrates the electrode structure. The unit contact plug is electrically connected to one of the electrodes of the electrode structure.

8. The semiconductor memory device according to claim 7, wherein, The unit contact plug is connected to the peripheral interconnect of the peripheral circuit structure.

9. The semiconductor memory device according to claim 7, wherein, The unit contact plug extends toward the semiconductor layer, and The semiconductor memory device further includes an insulating pattern inserted between the cell contact plug and the semiconductor layer.

10. A semiconductor memory device, comprising: Peripheral circuit structure on the substrate; Semiconductor layer on the peripheral circuit structure; An electrode structure on the semiconductor layer, the electrode structure comprising electrodes stacked on the semiconductor layer; A vertical channel structure that penetrates the electrode structure and connects to the semiconductor layer; A separation structure that penetrates the electrode structure, the separation structure extending in a first direction and horizontally dividing at least one electrode of the electrodes of the electrode structure into a pair of electrodes; Unit contact plug, which penetrates the stepped structure of the electrode structure; Interlayer insulation layer covering the electrode structure; as well as A through-contact that penetrates the interlayer insulation and is electrically connected to the peripheral circuit structure. The separation structure includes a lower separation structure and an upper separation structure on the lower separation structure, and The width of the upper part of the lower separation structure is greater than the width of the lower part of the upper separation structure, and When viewed in a plan view, the sidewall of the separation structure includes a plurality of protruding portions, each of which protrudes in a second direction intersecting the first direction.

11. The semiconductor memory device according to claim 10, wherein, The vertical channel structure includes a lower channel structure and an upper channel structure on the lower channel structure. The upper width of the lower channel structure is greater than the lower width of the upper channel structure, and The top surface of the lower separation structure and the top surface of the lower channel structure are at the same level.

12. The semiconductor memory device according to claim 11, wherein, The unit contact plug includes a lower contact plug and an upper contact plug on the lower contact plug. The width of the upper part of the lower contact plug is greater than the width of the lower part of the upper contact plug, and The top surface of the lower contact plug is at the same level as the top surface of the lower channel structure.

13. The semiconductor memory device according to claim 10, wherein, The through-contact includes a lower through-contact and an upper through-contact on the lower through-contact, and The width of the upper part of the lower through-contact is greater than the width of the lower part of the lower through-contact.

14. A semiconductor memory device, comprising: A peripheral circuit structure on a substrate, the peripheral circuit structure including a peripheral transistor on the substrate, a peripheral interconnect on the peripheral transistor, and a peripheral contact electrically connecting the peripheral transistor to the peripheral interconnect; Semiconductor layer on the peripheral circuit structure; An electrode structure on the semiconductor layer, the electrode structure comprising electrodes stacked on the semiconductor layer; A vertical channel structure that penetrates the electrode structure and connects to the semiconductor layer; A separation structure that penetrates the electrode structure extending in a first direction, the separation structure extending in the first direction and horizontally dividing the first electrode of the electrodes into a pair of electrodes; A unit contact plug that penetrates the stepped structure of the electrode structure and is electrically connected to a second electrode in the electrode; Interlayer insulation layer covering the electrode structure; A through-contact of the peripheral interconnect that penetrates the interlayer insulation layer and is electrically connected to the peripheral circuit structure; as well as Bit lines and connecting lines on the interlayer insulation layer, The vertical channel structure includes, Vertical semiconductor patterning, having a tubular shape with open tops, and Includes a vertical insulating pattern of a data storage layer, the data storage layer being interposed between the vertical semiconductor pattern and a third electrode in the electrode assembly, wherein... The bit line is electrically connected to the vertical semiconductor pattern. The connecting wire is electrically connected to the through contact, and The top surfaces of the separation structure, the vertical channel structure, the unit contact plug, and the through contact are coplanar. When viewed in a plan view, the sidewall of the separation structure includes a plurality of protruding portions, each of which protrudes in a second direction intersecting the first direction.

15. The semiconductor memory device according to claim 14, wherein, The semiconductor layer includes a lower semiconductor layer, an upper semiconductor layer, and a source semiconductor layer interposed between the lower semiconductor layer and the upper semiconductor layer. The vertical semiconductor pattern is connected to the source semiconductor layer.

16. The semiconductor memory device according to claim 14, wherein, The stepped structure of the electrode structure includes a molded structure below the second electrode. The molded structure includes an insulator, and The unit contact plug penetrates the second electrode and the molded structure.

17. The semiconductor memory device according to claim 14, wherein, The maximum diameter of the unit contact plug is greater than the maximum diameter of the vertical channel structure.

18. The semiconductor memory device according to claim 14, wherein, The maximum diameter of the through contact is greater than the maximum diameter of the vertical channel structure.

Images