Display panel

Abstract

The present disclosure relates to a display panel including: a first substrate including a transmissive area, a display area arranged to at least partially surround the transmissive area, and a first non-display area arranged between the transmissive area and the display area; a display element arranged in the display area; a first bypass line arranged in the first non-display area and arranged to bypass the transmissive area; a second substrate arranged to face the first substrate; a sealing member bonding the first substrate to the second substrate, and the sealing member surrounding a periphery of the transmissive area; and a metal layer arranged in the first non-display area, and the metal layer arranged to be closer to the transmissive area than the first bypass line, wherein the metal layer is arranged in a different layer from the first bypass line, and electrically connected to the first bypass line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0113521, filed on September 16, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display panel. Background Technology

[0004] In recent years, display devices have been used for a wide range of purposes. Furthermore, as display devices have become thinner and lighter, their applications have broadened.

[0005] Since display devices are used in a variety of ways, various methods can be used to design the shape of display devices, and furthermore, more and more functions can be combined with and / or associated with display devices. Summary of the Invention

[0006] One or more aspects of embodiments of this disclosure relate to a display panel including a transmissive region in which a camera and / or sensors, etc., can be arranged within a display area as a method of increasing functionality that can be combined with and / or associated with a display device.

[0007] However, the scope of this disclosure is not limited thereto.

[0008] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments provided in this disclosure.

[0009] According to one or more embodiments, a display panel includes: a first substrate including a transmissive region, a display region at least partially surrounding the transmissive region, and a first non-display region located between the transmissive region and the display region; a display element located in the display region; a first bypass line located in the first non-display region to bypass the transmissive region; a second substrate facing the first substrate; a sealing member bonding the first substrate to the second substrate and the sealing member surrounding the periphery of the transmissive region; and a metal layer located in the first non-display region, wherein the metal layer is more adjacent to the transmissive region than the first bypass line, wherein the metal layer is located in a different layer than the first bypass line and is electrically connected to the first bypass line.

[0010] In an embodiment, the display panel may further include a second bypass line located in the first non-display area to bypass the transmissive area, wherein the second bypass line may be arranged in the same layer as the metal layer.

[0011] In an embodiment, the first bypass route and the second bypass route may intersect or cross each other.

[0012] In one embodiment, the first bypass route may include a connecting portion protruding toward the center of the transmission area, and the metal layer may be connected to the connecting portion through a contact hole.

[0013] In an embodiment, the connection portion may be multiple connection portions.

[0014] In one embodiment, the first bypass line may be part of an electrode voltage line to provide a driving voltage to the display area.

[0015] In one embodiment, the first bypass line may extend from one electrode of the storage capacitor in the display area.

[0016] In one embodiment, the metal layer and the sealing member may surround the transmission region in an annular shape, and the inner diameter of the sealing member may be smaller than the inner diameter of the metal layer.

[0017] In one embodiment, the metal layer and the sealing member may surround the transmission region in an annular shape, and the outer diameter of the sealing member may be equal to the outer diameter of the metal layer.

[0018] In one embodiment, the display panel may further include a touch screen layer located above the second substrate, wherein the touch screen layer may include holes corresponding to the transmissive area.

[0019] According to one or more embodiments, a display panel includes: a first substrate including a first through-hole; a display element located on the first substrate and at least partially surrounding the first through-hole; a first bypass line curved and extending along an edge of the first through-hole; a second substrate facing the first substrate; a first sealing member bonding the first substrate to the second substrate and surrounding the periphery of the first through-hole; and a metal layer located below the first sealing member to surround the first through-hole, wherein the metal layer is located in a different layer from the first bypass line and is electrically connected to the first bypass line.

[0020] In one embodiment, a storage capacitor comprising a first storage capacitor plate and a second storage capacitor plate located above the first storage capacitor plate may be disposed above the first substrate, and the first bypass line may be located in the same layer as the second storage capacitor plate.

[0021] In one embodiment, the second storage capacitor plate can be connected to the drive voltage line via a contact hole, and the metal layer can be located in the same layer as the drive voltage line.

[0022] In one embodiment, a first driving voltage line and a second driving voltage line may be arranged above the first substrate, the first driving voltage line and the second driving voltage line being spaced apart from each other, and the first via being located between the first driving voltage line and the second driving voltage line.

[0023] In one embodiment, the width of the first sealing member may be greater than the width of the metal layer.

[0024] In an embodiment, the display panel may further include: a second sealing member, which bonds the first substrate to the second substrate and surrounds the edge of the first substrate, wherein the width of the second sealing member may be greater than the width of the first sealing member.

[0025] In an embodiment, the second substrate may include a second through hole corresponding to the first through hole.

[0026] In one embodiment, the first bypass route may include a connecting portion protruding toward the center of the transmission region, and the metal layer may be connected to the connecting portion through a contact hole.

[0027] In an embodiment, the connection portion may be multiple connection portions.

[0028] In one embodiment, the metal layer may include a plurality of through holes. Attached Figure Description

[0029] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1A This is a schematic plan view of the display panel according to an embodiment;

[0031] Figure 1B It is along Figure 1A A schematic cross-sectional view of the display panel taken by line I-I';

[0032] Figure 2A and Figure 2B It is an equivalent circuit diagram of a pixel according to one or more embodiments;

[0033] Figure 3 It is a planar layout diagram of pixel circuits according to one or more of this embodiment;

[0034] Figure 4 This is a schematic plan view showing the arrangement of some lines around the transmission area according to an embodiment;

[0035] Figure 5A It is a plan view showing the relationship between the first sealing member and the metal layer in the assembly located around the transmission area;

[0036] Figure 5B yes Figure 4 An enlarged view of region III;

[0037] Figure 6 It is along Figure 4 A schematic cross-sectional view of the display panel taken by line II-II';

[0038] Figure 7 This is a schematic plan view showing the shape of a metal layer according to some embodiments;

[0039] Figure 8 This schematically illustrates a cross-sectional view of a display panel according to some embodiments; and

[0040] Figure 9 This is a schematic cross-sectional view of a display panel according to some embodiments. Detailed Implementation

[0041] Now, reference will be made in more detail to embodiments illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to explain various aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all a, b, and c, or variations thereof. When expressions such as “at least one of…”, “one of…”, and “selected from…” precede a list of elements, the entire list of elements is modified without modifying individual elements within that list. Furthermore, when describing embodiments of the invention, the use of “may” means “one or more embodiments of the invention”.

[0042] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings, and in the following description, the same reference numerals will denote the same elements, and redundant descriptions will not be provided.

[0043] It will be understood that although terms such as “first” and “second” may be used in this document to describe various components, these components should not be limited by these terms, and these terms are only used to distinguish one component from another.

[0044] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0045] It will be understood that terms such as “comprising,” “including,” and “having” as used herein indicate the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0046] It will be understood that when a layer, region, or component is referred to as being “on” another layer, region, or component, that layer, region, or component may be “directly on” the other layer, region, or component (without any intermediate layer, region, or component between them), or may be “indirectly on” the other layer, region, or component, with one or more intermediate layers, regions, or components between the layer, region, or component and the other layer, region, or component.

[0047] For ease of description, the dimensions of the components in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the accompanying drawings are arbitrarily shown for ease of description, this disclosure is not limited thereto.

[0048] When a particular embodiment can be implemented differently, the particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of the described sequence.

[0049] It will be understood that when a layer, region, or component is referred to as being "connected to" another layer, region, or component, that layer, region, or component may be "directly connected to" the other layer, region, or component (without any intermediate layers, regions, or components in between), or may be "indirectly connected to" the other layer, region, or component, with one or more intermediate layers, regions, or components between the layer, region, or component and the other layer, region, or component. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected to" another layer, region, or component, that layer, region, or component may be "directly electrically connected to" the other layer, region, or component (without any intermediate layers, regions, or components in between), or may be "indirectly electrically connected to" the other layer, region, or component, with one or more intermediate layers, regions, or components between the layer, region, or component and the other layer, region, or component.

[0050] Figure 1AThis is a schematic plan view of the display panel according to an embodiment, and Figure 1B It is along Figure 1A A schematic cross-sectional view of the display panel taken by line I-I'.

[0051] Reference Figure 1A and Figure 1B The display panel may include a first base 110 in which a display portion 10 is arranged and a second base 310 arranged facing the first base 110. The first base 110 and the second base 310 may be sealed by a sealing member 500.

[0052] The first substrate 110 and the second substrate 310 may include various suitable materials such as glass materials, ceramic materials, plastic materials and / or metallic materials having SiO2 as the main component.

[0053] The first substrate 110 may include a display area DA and a transmissive area TA at least partially surrounded by the display area DA. Additionally, the first substrate 110 may include a first non-display area NDA1 disposed between the display area DA and the transmissive area TA, and a second non-display area NDA2 located outside the display area DA. The first non-display area NDA1 and the second non-display area NDA2 may be referred to as non-display area NDA.

[0054] Display portion 10 may be arranged in display area DA of first substrate 110. Display portion 10 includes pixels P comprising one or more display elements such as organic light-emitting diodes (OLEDs). Pixel P may include multiple pixels P, and the multiple pixels P may be arranged in various suitable forms such as stripe arrangement, pentile arrangement, and / or mosaic arrangement to realize an image. Each pixel P may emit, for example, red light, green light, blue light, or white light through the display element. Pixel P can be understood as a subpixel that emits light of any color selected from red, green, blue, and white.

[0055] The transmission region TA can be the location where the electronic component 20 is arranged. The transmission region TA can be the area through which light and / or sound emitted from the electronic component 20 to the outside and / or propagated from the outside toward the electronic component 20 can be transmitted. Although in Figure 1A The diagram shows a single transmission region TA, but multiple transmission regions TA can be provided. Furthermore, the shape, size, and position of the transmission region TA can be modified in various appropriate ways.

[0056] The transmissive region TA may be at least partially surrounded by the display region DA. In some embodiments, such as Figure 1AAs shown, the transmissive region TA can be completely surrounded by the display region DA, which includes the display element. In other embodiments, the transmissive region TA can be arranged between the display region DA and the second non-display region NDA2, and in this case, the transmissive region TA can be partially surrounded by the display element.

[0057] In this embodiment, the first substrate 110 may include a first through-hole 110H corresponding to the transmission region TA. Additionally, the second substrate 310 may include a second through-hole 310H corresponding to the first through-hole 110H of the first substrate 110.

[0058] A first non-display area NDA1 can be arranged between the transmissive area TA and the display area DA. The first non-display area NDA1 can be arranged to surround the transmissive area TA. In the first non-display area NDA1, pixels for implementing an image may not be arranged; instead, lines can be arranged to transmit electrical signals to pixels spaced apart from each other, with the transmissive area TA situated between the pixels.

[0059] The second non-display area NDA2 can be arranged to extend along the edge of the display panel to surround the display area DA. In the second non-display area NDA2, pixels for implementing images may not be arranged, but various lines, internal circuit sections and / or drive circuit sections 150, etc., may be arranged.

[0060] In some embodiments, a terminal portion 140 may be disposed on one side of the second non-display area NDA2. The terminal portion 140 may be exposed without being covered by an insulating layer to be electrically connected to a printed circuit board (PCB). A terminal PCB-P of the PCB may be electrically connected to the terminal portion 140 of the display panel. The PCB may be configured to transmit power or signals from the controller 160 to the display panel.

[0061] The pixel P arranged in the display area DA can be connected to the internal circuit section, the driving circuit section 150, and the lines arranged in the second non-display area NDA2 to receive driving voltage and electrical signals.

[0062] The sealing member 500 may include a first sealing member 510 and a second sealing member 520. The sealing member 500 may engage the first substrate 110 and the second substrate 310 with each other to prevent or reduce the inflow of oxygen and / or moisture into the display portion 10 and to improve its mechanical strength.

[0063] A first sealing member 510 may be disposed in a first non-display area NDA1 to surround a transmissive area TA. A second sealing member 520 may be disposed in a second non-display area NDA2 and may be disposed continuously along the edge of the display area DA. In some embodiments, in order to reduce the area of ​​the first non-display area NDA1, the width SW1 of the first sealing member 510 may be smaller than the width SW2 of the second sealing member 520.

[0064] The first sealing member 510 and the second sealing member 520 may each independently comprise inorganic materials and may include, for example, glass frit. The first sealing member 510 and the second sealing member 520 may be applied and formed by a dispenser and / or screen printing method. Glass frit may sometimes refer to powdered glass raw materials; however, in this disclosure, glass frit may also refer to a paste in which a laser or infrared absorber, an organic binder, and / or fillers for reducing the coefficient of thermal expansion are included in a primary material such as SiO2. The paste-like glass frit may be cured by removing the organic binder and moisture via a drying or firing process. The laser or infrared absorber may include transition metal compounds. A laser may be used as a heat source for curing the first sealing member 510 and the second sealing member 520 to bond the first substrate 110 and the second substrate 310 together.

[0065] In the following description, for convenience, display panels comprising organic light-emitting diodes as display elements will be described. However, embodiments of this disclosure can also be applied to various suitable types (or kinds) of display panels, such as inorganic EL display panels, quantum dot display panels, and / or liquid crystal display panels, as well as display devices including such display panels.

[0066] Figure 2A and Figure 2B This is an equivalent circuit diagram of pixel P according to one or more embodiments of the present disclosure.

[0067] Reference Figure 2A Each pixel P may include a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC. The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst.

[0068] The switching thin-film transistor T2 can be connected to the scan line SL and the data line DL, and can be configured to transfer the data voltage input from the data line DL to the driving thin-film transistor T1 according to the switching voltage input from the scan line SL. The storage capacitor Cst can be connected to the switching thin-film transistor T2 and the driving voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the driving voltage ELVDD supplied to the driving voltage line PL.

[0069] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through (towards) the organic light-emitting diode (OLED) in response to the voltage value stored in the storage capacitor Cst. The OLED can emit light with a specific brightness corresponding to the driving current. The opposite electrode (e.g., the cathode) of the OLED can receive a common voltage ELVSS.

[0070] although Figure 2A The pixel circuit PC shown includes two thin-film transistors and one storage capacitor, but this disclosure is not limited thereto. The number of thin-film transistors and the number of storage capacitors can be modified according to the design of the pixel circuit PC.

[0071] Reference Figure 2B The pixel circuit PC may include multiple thin-film transistors and storage capacitors. The thin-film transistors and storage capacitors may be connected to signal lines SL, SIL, EL and DL, initialization voltage line VL, and drive voltage line PL.

[0072] although Figure 2B The illustration shows each pixel P connected to signal lines SL, SIL, EL, and DL, initialization voltage line VL, and drive voltage line PL; however, this disclosure is not limited thereto. In other embodiments, at least one of the signal lines SL, SIL, EL, and DL, initialization voltage line VL, and / or drive voltage line PL may be shared by adjacent pixels.

[0073] The multiple thin-film transistors may include: a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0074] The signal lines may include: a scan line SL configured to transmit a scan signal Sn; a previous scan line SIL transmitting a previous scan signal Sn-1 to a first initialization thin-film transistor T4 and a second initialization thin-film transistor T7; an emit control line EL transmitting an emit control signal En to an operation control thin-film transistor T5 and an emit control thin-film transistor T6; and a data line DL intersecting or crossing the scan line SL and transmitting a data signal Dm. A drive voltage line PL may be configured to transmit a drive voltage ELVDD to a drive thin-film transistor T1, and an initialization voltage line VL may transmit an initialization voltage Vint used to initialize the drive thin-film transistor T1 and the pixel electrode.

[0075] The driving gate electrode G1 of the driving thin-film transistor T1 can be connected to the first storage capacitor plate CE1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin-film transistor T1 can be electrically connected to the driving voltage line PL via the operation control thin-film transistor T5. Furthermore, the driving drain electrode D1 of the driving thin-film transistor T1 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The driving thin-film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin-film transistor T2 and transmit the driving current I... OLED It is supplied to organic light-emitting diodes (OLEDs).

[0076] The switching gate electrode G2 of the switching thin-film transistor T2 can be connected to the scan line SL, the switching source electrode S2 of the switching thin-film transistor T2 can be connected to the data line DL, and the switching drain electrode D2 of the switching thin-film transistor T2 can be connected to the driving source electrode S1 of the driving thin-film transistor T1, and can be connected to the driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 can be turned on according to the scan signal Sn received through the scan line SL to perform a switching operation that transmits the data signal Dm (transmitted to the data line DL) to the driving source electrode S1 of the driving thin-film transistor T1.

[0077] The compensation gate electrode G3 of the compensation thin-film transistor T3 can be connected to the scan line SL, the compensation source electrode S3 of the compensation thin-film transistor T3 can be connected to the driving drain electrode D1 of the driving thin-film transistor T1, and can be connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. Furthermore, the compensation drain electrode D3 of the compensation thin-film transistor T3 can be connected to the first storage capacitor plate CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 can be turned on according to the scan signal Sn received through the scan line SL to electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving thin-film transistor T1, thereby connecting the driving thin-film transistor T1 in a diode manner.

[0078] The first initialization gate electrode G4 of the first initialization thin-film transistor T4 can be connected to the previous scan line SIL. The first initialization source electrode S4 of the first initialization thin-film transistor T4 can be connected to the second initialization drain electrode D7 and the initialization voltage line VL of the second initialization thin-film transistor T7. Furthermore, the first initialization drain electrode D4 of the first initialization thin-film transistor T4 can be connected to the first storage capacitor plate CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin-film transistor T3, and the driving gate electrode G1 of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SIL to perform an initialization operation that initializes the voltage of the driving gate electrode G1 of the driving thin-film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin-film transistor T1.

[0079] The operation control gate electrode G5 of the operation control thin film transistor T5 can be connected to the emitter control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 can be connected to the drive voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 can be connected to the drive source electrode S1 of the drive thin film transistor T1 and the switch drain electrode D2 of the switch thin film transistor T2.

[0080] The emission control gate electrode G6 of the emission control thin film transistor T6 can be connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 can be connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 can be electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0081] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 can be simultaneously (or concurrently) turned on according to the emission control signal En received through the emission control line EL, so that the driving voltage ELVDD can be transmitted to the organic light-emitting diode OLED, and thus the driving current I... OLED It can flow through organic light-emitting diodes (OLEDs).

[0082] The second initialization gate electrode G7 of the second initialization thin-film transistor T7 can be connected to the previous scan line SIL. The second initialization source electrode S7 of the second initialization thin-film transistor T7 can be connected to the emission control drain electrode D6 of the emission control thin-film transistor T6 and the pixel electrode of the organic light-emitting diode (OLED). Furthermore, the second initialization drain electrode D7 of the second initialization thin-film transistor T7 can be connected to the first initialization source electrode S4 of the first initialization thin-film transistor T4 and the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SIL to initialize the pixel electrode of the organic light-emitting diode (OLED).

[0083] although Figure 2B The illustration shows a configuration where the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are connected to the previous scan line SIL, but this disclosure is not limited thereto. In other embodiments, the first initialization thin-film transistor T4 may be connected to the previous scan line SIL to be driven according to the previous scan signal Sn-1, and the second initialization thin-film transistor T7 may be connected to a separate signal line (e.g., a subsequent scan line) to be driven according to the signal transmitted to that separate signal line.

[0084] The second storage capacitor plate CE2 of the storage capacitor Cst can be connected to the driving voltage line PL, and the opposite electrode of the organic light-emitting diode (OLED) can be connected to the common voltage ELVSS. Therefore, the OLED can receive the driving current I from the driving thin-film transistor T1. OLED To emit light in order to display an image.

[0085] although Figure 2B The compensation thin-film transistor T3 and the first initialization thin-film transistor T4 are shown to have dual gate electrodes, but the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 may each have a single gate electrode.

[0086] Figure 3 This is a planar layout diagram of the pixel circuit according to this embodiment.

[0087] Reference Figure 3 The driving thin-film transistor T1, the switching thin-film transistor T2, the compensation thin-film transistor T3, the first initialization thin-film transistor T4, the operation control thin-film transistor T5, the emission control thin-film transistor T6, and the second initialization thin-film transistor T7 can be arranged along the semiconductor layer 1130. The semiconductor layer 1130 can be arranged on a substrate in which a buffer layer of inorganic insulating material is formed.

[0088] Certain regions of semiconductor layer 1130 may correspond to the semiconductor layers of driving thin-film transistor T1, switching thin-film transistor T2, compensation thin-film transistor T3, first initialization thin-film transistor T4, operation control thin-film transistor T5, emission control thin-film transistor T6, and second initialization thin-film transistor T7. For example, the semiconductor layers of driving thin-film transistor T1, switching thin-film transistor T2, compensation thin-film transistor T3, first initialization thin-film transistor T4, operation control thin-film transistor T5, emission control thin-film transistor T6, and second initialization thin-film transistor T7 may be interconnected and may be bent in various suitable shapes.

[0089] The semiconductor layer 1130 may include a channel region and source and drain regions located on and / or on both sides of the channel region, and the source and drain regions can be understood as the source electrode and drain electrode of the corresponding thin-film transistor. Hereinafter, for convenience, the source and drain regions will be referred to as the source electrode and drain electrode, respectively.

[0090] The driving thin-film transistor T1 may include a driving gate electrode G1 overlapping with the driving channel region, and driving source electrodes S1 and driving drain electrodes D1 located on and / or on both sides of the driving channel region. The driving channel region overlapping with the driving gate electrode G1 may have a curved shape, such as an omega shape, to form a long channel length in a narrow space. When the driving channel region is long, the driving range of the gate voltage may become wider, and therefore the color gradation of the light emitted from the organic light-emitting diode OLED can be more finely controlled, thus improving its display quality.

[0091] The switching thin-film transistor T2 may include a switching gate electrode G2 overlapping with the switching channel region, and a switching source electrode S2 and a switching drain electrode D2 located on and / or on both sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0092] The compensation thin-film transistor T3 may be a dual-gate thin-film transistor, which may include a compensation gate electrode G3 overlapping with two compensation channel regions, and may include a compensation source electrode S3 and a compensation drain electrode D3 disposed on and / or disposed on both sides thereof. The compensation thin-film transistor T3 may be connected to the driving gate electrode G1 of the driving thin-film transistor T1 by means of node connection line 1174, which is described in more detail below.

[0093] The first initialization thin-film transistor T4 may be a dual-gate thin-film transistor, which may include a first initialization gate electrode G4 overlapping with two first initialization channel regions, and may include a first initialization source electrode S4 and a first initialization drain electrode D4 disposed on and / or disposed on both sides thereof.

[0094] The operation control thin-film transistor T5 may include an operation control gate electrode G5 overlapping with the operation control channel region, and operation control source electrodes S5 and operation control drain electrodes D5 located on and / or on both sides of it. The operation control drain electrode D5 may be connected to the drive source electrode S1.

[0095] The emitter control thin-film transistor T6 may include an emitter control gate electrode G6 overlapping with the emitter control channel region, and emitter control source electrodes S6 and emitter control drain electrodes D6 located on and / or on both sides of the gate electrode G6. The emitter control source electrode S6 may be connected to the drive drain electrode D1.

[0096] The second initialization thin-film transistor T7 may include a second initialization gate electrode G7 overlapping with the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 located on and / or on both sides of it.

[0097] The aforementioned thin-film transistor can be connected to signal lines SL, SIL, EL and DL, initialization voltage line VL and drive voltage line PL.

[0098] The scan line SL, the previous scan line SIL, the emission control line EL, and the drive gate electrode G1 can be arranged above the semiconductor layer 1130, and one or more insulating layers are located between the scan line SL, the previous scan line SIL, the emission control line EL, and the drive gate electrode G1 and the semiconductor layer 1130.

[0099] The scan line SL can extend along a first direction (e.g., first direction X). The region of the scan line SL can correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, the regions of the scan line SL that overlap with the channel regions of the switching thin-film transistor T2 and the compensation thin-film transistor T3 can be (or correspond to) the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0100] The previous scan line SIL can extend along the first direction X, and certain regions of the previous scan line SIL can correspond to the first initial gate electrode G4 and the second initial gate electrode G7, respectively. For example, the regions of the previous scan line SIL that overlap with the channel regions of the first initial thin film transistor T4 and the second initial thin film transistor T7 can be (or correspond to) the first initial gate electrode G4 and the second initial gate electrode G7, respectively.

[0101] The emitter control line EL can extend along the first direction X. The region of the emitter control line EL can correspond to the operation control gate electrode G5 and the emitter control gate electrode G6, respectively. For example, the region of the emitter control line EL that overlaps with the channel region of the operation control thin film transistor T5 and the channel region of the emitter control thin film transistor T6 can be (or correspond to) the operation control gate electrode G5 and the emitter control gate electrode G6, respectively.

[0102] The driving gate electrode G1 can be a floating electrode and can be connected to the compensation thin film transistor T3 via the node connection line 1174 mentioned above.

[0103] An electrode voltage line HL may be arranged above the scan line SL, the previous scan line SIL, the emission control line EL, and the drive gate electrode G1, with one or more insulating layers between the scan line SL, the previous scan line SIL, the emission control line EL, the drive gate electrode G1, and the electrode voltage line HL.

[0104] The electrode voltage line HL may extend along the first direction X to intersect or cross the data line DL and the drive voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the drive gate electrode G1 and may form a storage capacitor Cst together with the drive gate electrode G1. For example, the drive gate electrode G1 may become the first storage capacitor plate CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may become the second storage capacitor plate CE2 of the storage capacitor Cst.

[0105] The second storage capacitor plate CE2 of the storage capacitor Cst can be electrically connected to the drive voltage line PL. In this regard, the electrode voltage line HL can be connected to the drive voltage line PL arranged on the electrode voltage line HL via the contact hole CNT. Therefore, the electrode voltage line HL can have the same voltage level as the drive voltage line PL (e.g., a constant voltage). For example, the electrode voltage line HL can have a constant voltage of +5V. The electrode voltage line HL can be understood as a horizontal drive voltage line.

[0106] Since the driving voltage line PL extends along the second direction Y, and the electrode voltage line HL electrically connected to the driving voltage line PL extends along the first direction X that intersects or crosses the second direction Y, multiple driving voltage lines PL and multiple electrode voltage lines HL can form a grid structure in the display area DA.

[0107] Data line DL, drive voltage line PL, initialization connection line 1173 and node connection line 1174 can be arranged above electrode voltage line HL, and one or more insulating layers are between data line DL, drive voltage line PL, initialization connection line 1173 and node connection line 1174 and electrode voltage line HL.

[0108] The data line DL may extend in a second direction (e.g., second direction Y) and may be connected to the switching source electrode S2 of the switching thin-film transistor T2 via contact hole 1154. A portion of the data line DL may be understood as (e.g., may correspond to) the switching source electrode S2.

[0109] As described above, the drive voltage line PL can extend in the second direction Y and can be connected to the electrode voltage line HL through the contact hole CNT. Additionally, the drive voltage line PL can be connected to the operation control thin-film transistor T5 through the contact hole 1155. The drive voltage line PL can also be connected to the operation control drain electrode D5 through the contact hole 1155.

[0110] One end of the initialization connection line 1173 can be connected to the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 through the contact hole 1152, and the other end of the initialization connection line 1173 can be connected to the initialization voltage line VL through the contact hole 1151, which will be described in more detail below.

[0111] One end of the node connection line 1174 can be connected to the compensation drain electrode D3 through the contact hole 1156, and the other end of the node connection line 1174 can be connected to the drive gate electrode G1 through the contact hole 1157.

[0112] The initialization voltage line VL can be arranged above the data line DL, the drive voltage line PL, the initialization connection line 1173, and the node connection line 1174, with one or more insulating layers between the initialization voltage line VL and the data line DL, the drive voltage line PL, the initialization connection line 1173, and the node connection line 1174.

[0113] The initialization voltage line VL can extend in the first direction X. The initialization voltage line VL can be connected to the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 via the initialization connection line 1173. The initialization voltage line VL can have a constant voltage (e.g., -2V).

[0114] The initialization voltage line VL can include the same material as the second storage capacitor plate CE2 (e.g., electrode voltage line HL) and can be arranged in the same layer as the second storage capacitor plate CE2 (e.g., electrode voltage line HL). In the display area DA, the pixel electrode of the organic light-emitting diode OLED can be connected to the emission control thin-film transistor T6. The pixel electrode can be connected to the connecting metal 1175 through contact hole 1163, and the connecting metal 1175 can be connected to the emission control drain electrode D6 through contact hole 1153.

[0115] At the same time, Figure 3 In thin-film transistors, the source and drain electrodes can be changed to each other based on the characteristics of the thin-film transistor.

[0116] Figure 4 This is a schematic plan view showing the arrangement of some components around the transmission region TA as an example. Figure 5A This is a plan view showing the relationship between the first sealing member 510 and the metal layer ML in the assembly located around the transmission region TA. Figure 5B yes Figure 4 A magnified view of region III. Figure 6 It is along Figure 4 A schematic cross-sectional view of the display panel taken from line II-II'.

[0117] First, refer to Figure 4 Various lines can be arranged around the transmission area TA. Figure 4 A portion of the scan line SL, a portion of the data line DL, a portion of the drive voltage line PL, and a portion of the electrode voltage line HL are shown around the transmission region TA. Some lines connecting to the pixels are omitted from the illustration in the attached figure.

[0118] The scan line SL and the electrode voltage line HL can extend along the first direction X and can be arranged to bypass the edge of the transmission region TA in the first non-display area NDA1.

[0119] For example, in the first non-display area NDA1, the scan line SL may bypass the transmission area TA. In some embodiments, the scan line SL and the electrode voltage line HL may extend along the first direction X and may be bent and arranged along the edge of the first via 110H.

[0120] For example, some scan lines SL can bend along the upper edge of the transmission region TA, while other scan lines SL can bend along the lower edge of the transmission region TA. Pixels P located on the left and right sides of the transmission region TA can bypass the transmission region TA and be electrically connected to the scan lines SL.

[0121] In the first non-display area NDA1, electrode voltage lines HL can be routed around the transmissive area TA. For example, some electrode voltage lines HL can bend along the upper edge of the transmissive area TA, and others can bend along the lower edge of the transmissive area TA. Pixels P located on the left and right sides of the transmissive area TA can be electrically connected to the electrode voltage lines HL that bypass the transmissive area TA.

[0122] The data lines DL can extend along the second direction Y and can be arranged to bypass the edge of the transmissive region TA in the first non-display area NDA1. For example, some data lines DL can bend along the left edge of the transmissive region TA, while others can bend along the right edge of the transmissive region TA. Pixels P located on the upper and lower sides of the transmissive region TA can be electrically connected to the data lines DL that bypass the transmissive region TA.

[0123] In some embodiments, the driving voltage lines PLA and PLb around the transmission region TA can be disconnected on the transmission region TA. For example, the first driving voltage line PLA and the second driving voltage line PLb, arranged on the same line along the second direction Y, can be spaced apart from each other, with the transmission region TA located between the first driving voltage line PLA and the second driving voltage line PLb. The driving voltage line PL, which does not pass through the transmission region TA, can be arranged continuously in the display region DA.

[0124] The driving voltage lines PLa, PLb, and PL, as well as the electrode voltage lines HL, can be connected to each pixel P through contact holes CNT. Since the driving voltage lines PLa, PLb, and PL extend along the second direction Y, and the electrode voltage lines HL electrically connected to the driving voltage lines PLa, PLb, and PL extend along a first direction X that intersects or crosses the second direction Y, multiple driving voltage lines PLa, PLb, and PL, as well as multiple electrode voltage lines HL, can thus form a grid structure. Therefore, even when the driving voltage lines PLa and PLb around the transmission region TA are disconnected and do not bypass (e.g., pass through) the transmission region TA, the driving voltage ELVDD can be applied substantially uniformly to multiple pixels P.

[0125] The electrode voltage line HL can be referenced as follows Figure 3 The ground extends from the second storage capacitor plate CE2 of the storage capacitor Cst.

[0126] In some embodiments, the wiring that bypasses (e.g., passes through) the periphery of the transmissive region TA may be integrated with the wiring arranged in the display region DA. In other embodiments, the wiring that bypasses the periphery of the transmissive region TA may be provided as connecting lines arranged in the same layer as the wiring arranged in the display region DA or as connecting lines arranged in a different layer than the wiring arranged in the display region DA.

[0127] Reference Figures 4 to 6In this embodiment, the first sealing member 510 can be arranged to surround the transmission region TA, and the metal layer ML can be arranged below the first sealing member 510. The first sealing member 510 and the metal layer ML can be arranged to surround the transmission region TA and can have annular or circular shapes. The shapes of the first sealing member 510 and the metal layer ML can be changed according to the shape of the transmission region TA. For example, when the transmission region TA is elliptical, the first sealing member 510 and the metal layer ML can each be provided as elliptical rings.

[0128] For reference Figure 1B As mentioned above, because the width of the first sealing member 510 is small, the engagement force of the first sealing member 510 may be weak. In this embodiment, the sealing performance of the first sealing member 510 can be improved by introducing a metal layer ML under the first sealing member 510.

[0129] The metal layer ML can be formed of a material with high bonding strength to the first sealing member 510 to improve the sealing performance of the first sealing member 510. In addition, when the first sealing member 510 is cured by laser, the metal layer ML can transfer heat to the first sealing member 510 by absorbing and / or reflecting the laser to assist in the curing process.

[0130] The inner edge of the metal layer ML (facing the transmission region TA) can be covered by the first sealing member 510. For example, the inner diameter d1 of the metal layer ML can be larger than the inner diameter d2 of the first sealing member 510 (d1>d2).

[0131] This is to prevent or reduce the possibility of the metal layer ML being exposed to the transmission region TA. When a portion of the inner edge of the metal layer ML is exposed and not covered by the first sealing member 510, that portion may be corroded by moisture or other substances that may flow out from the transmission region TA. In this embodiment, the inner edge of the metal layer ML may be covered by the first sealing member 510 to prevent or reduce corrosion of the metal layer ML.

[0132] The outer diameter od1 of the metal layer ML can be substantially the same as the outer diameter od2 of the first sealing member 510 (od1 = od2).

[0133] This can be to reduce the area of ​​the first non-display area NDA1, and also to effectively (or appropriately) solidify the first sealing member 510. When the outer diameter od1 of the metal layer ML is greater than the outer diameter od2 of the first sealing member 510, the area of ​​the first non-display area NDA1 may be relatively large when considering the lines arranged in the first non-display area NDA1. On the other hand, when the outer diameter od1 of the metal layer ML is smaller than the outer diameter od2 of the first sealing member 510, the heat energy transferred from the metal layer ML to the first sealing member 510 can be reduced. In this embodiment, the outer diameter od1 of the metal layer ML can be substantially the same as the outer diameter od2 of the first sealing member 510 to minimize or reduce the first non-display area NDA1, and also to effectively (or appropriately) solidify the first sealing member 510.

[0134] In some embodiments, the metal layer ML can be used to bond to the first sealing member 510, and can be disposed only below the first sealing member 510, and the width W1 of the metal layer ML can be smaller than the width W2 of the first sealing member 510 (W1 <W2)。

[0135] In some embodiments, the metal layer may also be disposed below the second sealing member 520.

[0136] Reference Figure 4 and Figure 5B The metal layer ML can be electrically connected to a bypass line that bypasses the transmission region TA. Conversely, when the metal layer ML is electrically levitated, electrostatic charges may accumulate in the metal layer ML, which may cause damage due to electrostatic discharge.

[0137] However, in this embodiment, phenomena caused by electrostatic discharge can be prevented or reduced by electrically connecting the metal layer ML to at least one bypass line. The bypass line can be a line in the electrode voltage line HL adjacent to the metal layer ML. Therefore, the metal layer ML can receive a driving voltage ELVDD as a constant voltage.

[0138] The bypass line and the metal layer ML can be connected by a connecting portion CP. The connecting portion CP can be a conductive layer that extends from the bypass line to the center of the transmission region TA.

[0139] In some embodiments, the connection portion CP may protrude from the electrode voltage line HL, which serves as a bypass line, toward the center of the transmission region TA and extend into the metal layer ML. For example, the connection portion CP may be integrally formed with the electrode voltage line HL. The connection portion CP may overlap with the metal layer ML, and the metal layer ML may be connected to the connection portion CP through a contact hole CNT'.

[0140] Multiple connection portions CP can be provided and can be arranged along the edge of the metal layer ML. Furthermore, multiple bypass lines connected to the metal layer ML can be provided. For example, the metal layer ML can be connected to the line arranged closest to the metal layer ML in the electrode voltage line HL that bypasses the upper side of the transmission region TA, and can also be connected to the line arranged closest to the metal layer ML in the electrode voltage line HL that bypasses the lower side of the transmission region TA.

[0141] In other embodiments, each connection portion CP may be arranged in a different layer than the electrode voltage line HL and the metal layer ML, and may be connected to the electrode voltage line HL and the metal layer ML through contact holes.

[0142] Reference Figure 6 The electronic components 20 can be arranged to correspond to the transmissive area TA of the display panel.

[0143] Electronic component 20 may be positioned within the transmission region TA. In some embodiments, as shown in the figures, electronic component 20 may be arranged to be at least partially inserted into the first through-hole 110H of the first substrate 110. In other embodiments, electronic component 20 may be arranged below the first substrate 110 to correspond to the transmission region TA.

[0144] Electronic component 20 may include electronic components that use light and / or sound. For example, the electronic component may include sensors such as infrared sensors for receiving and using light, cameras for receiving light to capture images, sensors for outputting and detecting light and / or sound to measure distance and / or identify fingerprints, miniature lamps for outputting light, and / or speakers for outputting sound. In the case of electronic components using light, the electronic component may use light of various wavelengths, such as visible light, infrared light, and / or ultraviolet light.

[0145] The display panel according to this embodiment may include: a first substrate 110, including a transmissive region TA, a display region DA in which display elements are disposed, and a first non-display region NDA1; a second substrate 310 facing the first substrate 110; a first sealing member 510 located around the transmissive region TA between the first substrate 110 and the second substrate 310; and a metal layer ML located below the first sealing member 510. The metal layer ML may be electrically connected to at least one bypass line that bypasses the transmissive region TA.

[0146] The first substrate 110 and the second substrate 310 may each independently comprise a glass material or a polymer resin. For example, the first substrate 110 may comprise a glass material having SiO2 as a major component, or may comprise a resin such as a reinforced plastic. The second substrate 310 may be arranged facing the first substrate 110 to cover the display element.

[0147] In the display area DA of the first substrate 110, at least one thin-film transistor (TFT), a storage capacitor (Cst), and an organic light-emitting diode (OLED) can be arranged as display elements.

[0148] A thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode G, a source electrode S, and a drain electrode D. A storage capacitor Cst may include a first storage capacitor plate CE1 and a second storage capacitor plate CE2. An organic light-emitting diode (OLED) may include a pixel electrode 210, an intermediate layer 220 including an organic emitting layer, and a counter electrode 230.

[0149] Its construction will be described below in stacking order.

[0150] A buffer layer 111 may be disposed on the first substrate 110 to reduce or prevent the penetration of foreign matter, moisture and / or outside air from below the first substrate 110 and to provide a flat surface on the first substrate 110. The buffer layer 111 may comprise inorganic materials, organic materials or organic / inorganic composites such as oxides and / or nitrides, and may comprise a single-layer structure or a multi-layer structure of inorganic and organic materials.

[0151] A barrier layer may also be included between the first substrate 110 and the buffer layer 111. The barrier layer can serve to prevent or minimize (or reduce) the penetration of impurities from the first substrate 110 into the semiconductor layer Act. The barrier layer may include inorganic materials, organic materials, or organic / inorganic composites such as oxides and / or nitrides, and may include a single-layer structure or a multi-layer structure of inorganic and organic materials.

[0152] A semiconductor layer Act may be disposed on the buffer layer 111. The semiconductor layer Act may comprise amorphous silicon or may comprise polycrystalline silicon. In other embodiments, the semiconductor layer Act may comprise an oxide selected from at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In some embodiments, the semiconductor layer Act may comprise Zn oxide-based materials such as Zn oxide, In-Zn oxide, and / or Ga-In-Zn oxide. In other embodiments, the semiconductor layer Act may comprise IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), and / or IGTZO (In-Ga-Sn-Zn-O) semiconductors containing metals such as indium (In), gallium (Ga), and / or tin (Sn) in ZnO. The semiconductor layer Act may include a channel region and source and drain regions disposed on both sides of the channel region and / or disposed on both sides of the channel region. The semiconductor layer Act may be a single layer or multiple layers.

[0153] Above the semiconductor layer Act, the gate electrode G may be arranged to at least partially overlap with the semiconductor layer Act, and a first gate insulating layer 112 is disposed between the semiconductor layer Act and the gate electrode G. The gate electrode G may include molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may comprise a single layer or multiple layers. For example, the gate electrode G may comprise a single layer of Mo.

[0154] The first gate insulating layer 112 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2).

[0155] The second gate insulating layer 113 can be provided to cover the gate electrode G. The second gate insulating layer 113 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2).

[0156] The first storage capacitor plate CE1 of the storage capacitor Cst can overlap with the thin-film transistor TFT. For example, the gate electrode G of the thin-film transistor TFT can be used as the first storage capacitor plate CE1 of the storage capacitor Cst.

[0157] The second storage capacitor plate CE2 of the storage capacitor Cst may overlap with the first storage capacitor plate CE1, and the second gate insulating layer 113 is located between the second storage capacitor plate CE2 and the first storage capacitor plate CE1. In this case, the second gate insulating layer 113 can serve as the dielectric layer of the storage capacitor Cst. The second storage capacitor plate CE2 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may comprise a single layer or multiple layers comprising any of the above materials. For example, the second storage capacitor plate CE2 may comprise a single layer of Mo or a multilayer structure of Mo / Al / Mo.

[0158] In the accompanying drawings, the storage capacitor Cst is shown overlapping with the thin-film transistor TFT; however, in other embodiments, as one of various variations, the storage capacitor Cst may be arranged not to overlap with the thin-film transistor TFT.

[0159] An interlayer insulating layer 115 can be provided to cover the second storage capacitor plate CE2 of the storage capacitor Cst. The interlayer insulating layer 115 may comprise silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2).

[0160] The source electrode S and drain electrode D can be disposed on the interlayer insulating layer 115. The source electrode S and drain electrode D can include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can include a single layer or multiple layers comprising any of the above materials. For example, the source electrode S and drain electrode D can include a Ti / Al / Ti multilayer structure.

[0161] The through-layer 117 can be positioned on the source electrode S and the drain electrode D, and the organic light-emitting diode (OLED) can be positioned on the through-layer 117.

[0162] The through-layer 117 may have a flat upper surface, allowing the pixel electrode 210 to be formed flat. In some embodiments, the through-layer 117 may comprise a single layer or multiple layers formed of organic materials. The through-layer 117 may comprise a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyl disiloxane (HMDSO), polymethyl methacrylate (PMMA) and / or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or any mixture thereof.

[0163] In some embodiments, the through-layer 117 may comprise an inorganic material. The through-layer 117 may comprise silicon oxide (SiO2) or silicon nitride (SiN). x The materials used include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2). When the through-layer 117 comprises inorganic materials, chemical planarization polishing may be performed in some cases. In some embodiments, the through-layer 117 may comprise both organic and inorganic materials.

[0164] In the display area DA of the first substrate 110, an organic light-emitting diode (OLED) can be disposed on the through layer 117. The OLED may include a pixel electrode 210, an intermediate layer 220 including an organic emitting layer, and a counter electrode 230.

[0165] Pixel electrode 210 may be a (semi-)transparent electrode or a reflective electrode. In some embodiments, pixel electrode 210 may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or any compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). In some embodiments, pixel electrode 210 may include an ITO / Ag / ITO stacked structure.

[0166] A pixel defining layer 119 may be disposed on the through layer 117, and the pixel defining layer 119 may have an opening portion in the display area DA corresponding to each pixel electrode 210, for example, an opening portion OP for exposing at least the central portion of the pixel electrode 210, thereby defining the emission area of ​​the pixel. Additionally, the pixel defining layer 119 may increase the distance between the edge of the pixel electrode 210 and the opposing electrode 230 located above the pixel electrode 210, to prevent or reduce the generation of electric arcs at the edge of the pixel electrode 210. The pixel defining layer 119 may be formed by spin coating or the like from an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyl disiloxane (HMDSO), and / or phenolic resin.

[0167] The intermediate layer 220 of an organic light-emitting diode (OLED) may include an organic emitting layer. The organic emitting layer may include an organic material comprising a fluorescent or phosphorescent material emitting red, green, blue, or white light. The organic emitting layer may include low-molecular-weight or high-molecular-weight organic materials, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL) may optionally be further disposed below and / or above the organic emitting layer. In some embodiments, the intermediate layer 220 may be disposed corresponding to each of a plurality of pixel electrodes 210. In other embodiments, the intermediate layer 220 may include an integral (common) layer integrated above the plurality of pixel electrodes 210. For example, the organic emitting layer may be disposed corresponding to each of the plurality of pixel electrodes 210, and the functional layers disposed above and / or below the organic emitting layer may be integrally provided above the plurality of pixels. In other embodiments, the intermediate layer 220 may be integrally provided above the plurality of pixel electrodes 210.

[0168] The counter electrode 230 can be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode 230 can be a transparent electrode or a semi-transparent electrode, and can be formed of a thin metal layer having a low work function and comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or any compound or mixture thereof. In some embodiments, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, and / or In2O3 can be further disposed on the thin metal layer. The counter electrode 230 can be disposed above the display area DA and the peripheral area PA, and can be disposed above the intermediate layer 220 and the pixel defining layer 119. The counter electrode 230 can be integrally formed in a plurality of organic light-emitting diodes (OLEDs) to correspond to a plurality of pixel electrodes 210.

[0169] A capping layer and / or a protective layer formed of LiF or the like can be further arranged on the relative electrode 230 to improve light extraction efficiency, so as to protect the organic light-emitting diode (OLED) from the effects of subsequent processes.

[0170] The bypass line portion DWL, the first sealing member 510, and the metal layer ML can be disposed in the first non-display area NDA1 of the first substrate 110. The first sealing member 510 and the metal layer ML can be disposed closer to (e.g., more closely to) the transmission area TA than the bypass line portion DWL.

[0171] The bypass line section DWL may include scan lines SL, electrode voltage lines HL, and data lines DL. In some embodiments, the bypass line section DWL may also include transmit control lines and / or previous scan lines, etc.

[0172] The scan line SL can be arranged on the first gate insulating layer 112, that is, in the same layer as the gate electrode G. The electrode voltage line HL can be arranged on the second gate insulating layer 113, that is, in the same layer as the second storage capacitor plate CE2. The data line DL can be arranged on the interlayer insulating layer 115, that is, in the same layer as the source electrode S and / or the drain electrode D.

[0173] The metal layer ML can be disposed in the same layer as the data line DL, and can be spaced apart from the data line DL. The metal layer ML can be disposed on the interlayer insulating layer 115. The metal layer ML can include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and can include a single layer or multiple layers comprising any of the above materials.

[0174] The metal layer ML can be arranged closer to (e.g., more closely to) the transmission region TA than the bypass line portion DWL. The metal layer ML can be connected to the connection portion CP through a contact hole CNT' passing through the second gate insulating layer 113. The connection portion CP can extend from the electrode voltage line HL. Because the metal layer ML is connected to the electrode voltage line HL, damage due to electrostatic discharge can be prevented or reduced.

[0175] The first sealing member 510 may be arranged to cover the metal layer ML on the interlayer insulation layer 115. The first sealing member 510 may be arranged between the first substrate 110 and the second substrate 310 to seal the first substrate 110 and the second substrate 310 to prevent or reduce the inflow of oxygen and / or moisture into the display area DA.

[0176] The first sealing member 510 may include a material cured by laser. The first sealing member 510 may include glass frit.

[0177] Compared to the bonding force with the interlayer insulation layer 115, which includes inorganic insulating material, the first sealing member 510 can have a stronger bonding force with the metal layer ML, which includes metallic material. In this embodiment, by introducing the metal layer ML between the interlayer insulation layer 115 and the first sealing member 510, the sealing of the first sealing member 510 can be performed more effectively.

[0178] The first substrate 110 may include a first through-hole 110H corresponding to the transmission region TA. Because the first substrate 110 includes the first through-hole 110H, light and / or sound output from and / or received by the electronic element 20 can be used more effectively (appropriately).

[0179] When the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are referred to as the inorganic insulating layer IL, the inorganic insulating layer IL may include a first aperture H1 corresponding to the transmission region TA. The size of the first aperture H1 may be larger than the size of the first via 110H.

[0180] The through layer 117 may include a second hole H2 corresponding to the transmission region TA. The second hole H2 may provide an exposed metal layer ML. For example, the metal layer ML and the first sealing member 510 may be disposed inside the second hole H2.

[0181] The pixel defining layer 119 may include a third aperture H3 corresponding to the transmission region TA. The third aperture H3 may provide an exposed metal layer ML. For example, the metal layer ML and the first sealing member 510 may be disposed inside the third aperture H3.

[0182] The counter electrode 230 may include a fourth hole H4 corresponding to the transmission region TA. The fourth hole H4 may provide an exposed metal layer ML. The edge of the fourth hole H4 may be spaced apart from the metal layer ML. Therefore, an electrical short circuit may not occur between the counter electrode 230 and the metal layer ML.

[0183] The second substrate 310 may include a second through-hole 310H corresponding to the transmission region TA. After the first substrate 110 and the second substrate 310 are joined by the sealing member 500 (see FIG. 1), the first through-hole 110H of the first substrate 110 and the second through-hole 310H of the second substrate 310 can be formed simultaneously (or concurrently) using a laser. Therefore, the size of the second through-hole 310H can be substantially the same as the size of the first through-hole 110H.

[0184] Figure 7 This is a schematic plan view showing the shape of the metal layer ML according to some embodiments.

[0185] Reference Figure 7 The metal layer ML may include multiple through-holes CH. The shape and number of through-holes CH can be modified differently and appropriately. For example, in a planar view, the through-holes CH can have polygonal, circular, elliptical, and / or irregular shapes. Because the through-holes CH are formed in the metal layer ML, the first sealing member 510 can be arranged inside the through-holes CH to achieve three-dimensional coupling. Therefore, the bonding force between the first sealing member 510 and the metal layer ML can be improved.

[0186] Figure 8 This is a schematic cross-sectional view of a display panel according to some embodiments. Figure 8 In, with Figure 6 The same reference numerals in the figures denote the same components, and redundant descriptions will not be provided for the sake of brevity.

[0187] Reference Figure 8 The display panel may include: a first substrate 110 including a transmissive region TA, a display region DA in which display elements are disposed, and a first non-display region NDA1; a second substrate 310 disposed facing the first substrate 110; a first sealing member 510 disposed around the transmissive region TA between the first substrate 110 and the second substrate 310; and a metal layer ML disposed below the first sealing member 510. In some embodiments, the metal layer ML may be electrically connected to at least one bypass line that bypasses the transmissive region TA.

[0188] In this embodiment, a touchscreen layer 700 comprising touch electrodes 710 with various patterns for touchscreen functionality can be provided on the second substrate 310. The touch electrodes 710 can be provided as transparent electrode materials, allowing light from the emitting regions of pixels disposed beneath the touchscreen layer 700 to pass through them. In some embodiments, the touch electrodes 710 can be provided in a grid shape, allowing light from the emitting regions of pixels to pass through them. In this case, the touch electrodes 710 are not limited to transparent electrode materials. For example, the touch electrodes 710 can comprise a single layer or multiple layers formed of conductive materials comprising aluminum (Al), copper (Cu), and / or titanium (Ti).

[0189] The touch electrode 710 may include a first touch conductive layer 711 and a second touch conductive layer 713. The touch screen layer 700 according to the embodiment may have a structure in which the first touch conductive layer 711, the first insulating layer 712, the second touch conductive layer 713 and the second insulating layer 714 are stacked sequentially.

[0190] In some embodiments, the second touch conductive layer 713 can be used as a sensor portion for sensing contact, and the first touch conductive layer 711 can be used as a connection portion for connecting the patterned second touch conductive layer 713 in one direction.

[0191] In some embodiments, both the first touch conductive layer 711 and the second touch conductive layer 713 can serve as sensor portions. For example, the first insulating layer 712 may include a via for exposing the top surface of the first touch conductive layer 711, and the first touch conductive layer 711 and the second touch conductive layer 713 can be connected through the via. Thus, by using the first touch conductive layer 711 and the second touch conductive layer 713, the resistance of the touch electrode 710 can be reduced, thereby improving the response speed of the touchscreen layer 700.

[0192] In some embodiments, the touch electrode 710 may be formed in a mesh structure to allow light emitted from the organic light-emitting diode (OLED) to pass through the touch electrode 710. Therefore, the first touch conductive layer 711 and the second touch conductive layer 713 of the touch electrode 710 may be arranged so as not to overlap with the emission region of the organic light-emitting diode (OLED).

[0193] Each of the first touch conductive layer 711 and the second touch conductive layer 713 may comprise a single layer or multiple layers formed of a conductive material with good conductivity. For example, each of the first touch conductive layer 711 and the second touch conductive layer 713 may comprise a transparent conductive layer or a single layer or multiple layers formed of a conductive material comprising aluminum (Al), copper (Cu), and / or titanium (Ti). The transparent conductive layer may comprise a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium tin zinc oxide (ITZO). In some embodiments, the transparent conductive layer may comprise a conductive polymer such as PEDOT, metal nanowires, and / or graphene. In some embodiments, each of the first touch conductive layer 711 and the second touch conductive layer 713 may have a Ti / Al / Ti stacked structure.

[0194] Each of the first insulating layer 712 and the second insulating layer 714 may include inorganic and organic materials. The inorganic material may include at least one selected from silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The organic material may include at least one selected from acrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, and perylene resin.

[0195] In some embodiments, a touch buffer layer may be further provided between the second substrate 310 and the touchscreen layer 700. The touch buffer layer can serve to block or reduce interference signals that may occur when the touchscreen layer 700 is driven. The touch buffer layer may comprise inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide and / or titanium nitride, or organic materials such as polyimide, polyester and / or acrylic resin, and the touch buffer layer may be formed by any stack of the aforementioned inorganic and organic materials.

[0196] Since the touch buffer layer and / or touch screen layer 700 are formed directly on the second substrate 310 by deposition or the like, a separate adhesive layer may not be required on the second substrate 310. Therefore, the thickness of the display panel can be reduced.

[0197] An optical functional unit 800 and a window 900 may be arranged on the touch screen layer 700. The window 900 may be coupled to components below it, such as the optical functional unit 800, via an adhesive layer such as optically clear adhesive (OCA).

[0198] The optical functional unit 800 may include an anti-reflective layer. The anti-reflective layer reduces the reflectivity of light (external light) incident from the outside through window 900 toward the display panel. The anti-reflective layer may include a phase retarder and a polarizer. The phase retarder may be a film or a liquid crystal coating, and may include a 2 / 2 (half-wave) phase retarder and / or a 4 / 4 (quarter-wave) phase retarder. The polarizer may also be a film or a liquid crystal coating. The film may include a stretched synthetic resin film, and the liquid crystal coating may include liquid crystals arranged in a specific configuration. The phase retarder and polarizer may each further include a protective film independently.

[0199] In other embodiments, the antireflective layer may include a structure of color filters and a black matrix. The color filters can be arranged to take into account the color of light emitted from each pixel in the display panel. In other embodiments, the antireflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, can interfere with each other destructively, and thus can reduce the reflectivity of external light.

[0200] The optical functional unit 800 may include a lens layer. The lens layer can improve the luminous efficiency of light emitted from the display panel and / or reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape, and / or may include multiple layers with different refractive indices. The optical functional unit 800 may include both the anti-reflective layer and the lens layer described above, or may include any one of the anti-reflective layer and the lens layer described above.

[0201] The touch screen layer 700 and the optical functional unit 800 may include holes corresponding to the transmission area TA.

[0202] Window 900 may be disposed above optical functional unit 800 to protect components disposed below it. Window 900 may include transparent glass material and / or polymer resin, etc. When the adhesive layer between window 900 and optical functional unit 800 may include optically transparent adhesive (OCA), the adhesive layer may not include holes corresponding to the transmission area TA.

[0203] Figure 9 This is a schematic cross-sectional view of a display panel according to some embodiments. Figure 9 In, with Figure 6 The same reference numerals in the figures denote the same components, and redundant descriptions will not be provided for the sake of brevity.

[0204] Reference Figure 9 The display panel may include: a first substrate 110 including a transmissive region TA, a display region DA in which display elements are disposed, and a first non-display region NDA1; a second substrate 310 disposed facing the first substrate 110; a first sealing member 510 disposed around the transmissive region TA between the first substrate 110 and the second substrate 310; and a metal layer ML disposed below the first sealing member 510. In some embodiments, the metal layer ML may be electrically connected to at least one bypass line that bypasses the transmissive region TA.

[0205] In this embodiment, the first substrate 110 may be arranged continuously corresponding to the transmission region TA, and may not include through holes. In this case, the electronic component 20 may be arranged below the first substrate 110.

[0206] In some embodiments, the second substrate 310 may be arranged continuously corresponding to the transmission region TA and may not include through holes. In this case, the first sealing member 510 may serve to support the first substrate 110 and the second substrate 310.

[0207] As one of various possible modifications, only one of the first substrate 110 and the second substrate 310 may include a through hole corresponding to the transmission region TA.

[0208] As described above, according to embodiments of the present disclosure, since the metal layer connected to the bypass line is arranged below the sealing member, the adhesion of the sealing member can be enhanced, and the display panel can also be protected from electrostatic discharge. However, these effects are merely examples, and the scope of the present disclosure is not limited thereto.

[0209] As used in this article, the term “use” can be considered synonymous with the term “utilize”.

[0210] In addition, the terms “basically,” “approximately,” and similar terms are used as approximate terms rather than as degree terms, and are intended to explain the inherent biases of the measured or calculated values ​​that would be recognized by a person skilled in the art.

[0211] Furthermore, any numerical range described herein is intended to include all subranges of the same numerical precision that fall within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between the described minimum value of 1.0 and the described maximum value of 10.0 (and including both the described minimum value of 1.0 and the described maximum value of 10.0), that is, all subranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits falling within it, and any minimum numerical limit described herein is intended to include all larger numerical limits falling within it. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges that fall within the range expressly described herein.

[0212] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the following claims and their equivalents.

Claims

1. A display panel, wherein, The display panel includes: A first substrate includes a transmissive region, a display region at least partially surrounding the transmissive region, and a first non-display region located between the transmissive region and the display region; The display element is located in the display area; A first bypass route is located in the first non-display area to bypass the transmission area; The second substrate faces the first substrate; A sealing member that bonds the first substrate to the second substrate, and the sealing member surrounding the periphery of the transmission region; and A metal layer is located in the first non-display area, and the metal layer is closer to the transmissive area than the first bypass line. The metal layer is located in a different layer than the first bypass line and is electrically connected to the first bypass line. The metal layer is bonded to the underside of the sealing member and at least partially overlaps with the sealing member.

2. The display panel as claimed in claim 1, wherein, The display panel further includes a second bypass route located in the first non-display area to bypass the transmissive area. The second bypass line is located in the same layer as the metal layer.

3. The display panel as described in claim 2, wherein, The first side route and the second side route intersect each other.

4. The display panel as claimed in claim 1, wherein, The first bypass line includes a connecting portion protruding toward the center of the transmission area, and The metal layer is connected to the connection portion through a contact hole.

5. The display panel as claimed in claim 4, wherein, The connection portion consists of multiple connection portions.

6. The display panel as claimed in claim 1, wherein, The first bypass line is part of the electrode voltage line to provide a driving voltage to the display area.

7. The display panel as claimed in claim 1, wherein, The first bypass line extends from the electrode of the storage capacitor in the display area.

8. The display panel as claimed in claim 1, wherein, The metal layer and the sealing member surround the transmission area in an annular shape, and The inner diameter of the sealing member is smaller than the inner diameter of the metal layer.

9. The display panel as claimed in claim 1, wherein, The metal layer and the sealing member surround the transmission area in an annular shape, and The outer diameter of the sealing member is equal to the outer diameter of the metal layer.

10. The display panel as claimed in claim 1, wherein, The display panel further includes a touchscreen layer located above the second substrate. The touchscreen layer includes holes corresponding to the transmissive area.

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