Semiconductor package structure and method of manufacturing the same

Abstract

A semiconductor package structure is provided, including a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package structure having metal-metal bonding and metal-solder bonding. Background Technology

[0002] Semiconductor process technology has consistently evolved towards smaller and smaller device geometries, significantly increasing the amount of circuitry that can be placed on a single chip (i.e., increasing circuit density). Integrated circuit technology, typically offered to the public as custom and semi-custom devices, also follows this trend, providing more and more gates on a single chip at increasingly lower costs. A particular type of semi-custom integrated circuit device is called an ASIC (Application-Specific Integrated Circuit), which typically incorporates standard cells and gate array technology. Currently, it is possible to provide ASICs with tens of thousands of gates, even in relatively small sizes.

[0003] To some extent, ASIC technology benefits from advancements in process technology in other areas, such as memory and microprocessor technology. These areas have also been trending towards smaller device geometries and higher circuit densities. Memory technology, particularly DRAM (Dynamic Random Access Memory), now typically provides 4 to 16 million bits of storage on a single memory chip. Microprocessor technology has advanced to the point where million-gate microprocessors are commonly available.

[0004] These trends are typically accompanied by an increased demand for chip-to-chip input / output (I / O) connections. As I / O counts increase, the spacing between contact pads decreases, bridging adjacent solder joint surfaces. Additionally, lower contact resistance is required, especially for products with high I / O counts. Summary of the Invention

[0005] In some embodiments, this disclosure provides a semiconductor package structure comprising a first carrier having a first surface having a first region and a second region. The semiconductor package structure further comprises a second carrier having a second surface opposite to the first surface, the second surface having a third region corresponding to the first region and a fourth region corresponding to the second region. The semiconductor package structure further comprises a plurality of first-type conductive pillars located between the first region of the first surface and the third region of the second surface; and a plurality of second-type conductive pillars located between the second region of the first surface and the fourth region of the second surface. The contact resistance of each of the first-type conductive pillars is lower than the contact resistance of each of the second-type conductive pillars.

[0006] In some embodiments, this disclosure provides a semiconductor package structure comprising: a semiconductor die surface having a narrow pitch region and a wider pitch region adjacent to the narrow pitch region; a plurality of first-type conductive pillars located in the narrow pitch region, each of the first-type conductive pillars having a copper-copper interface; and a plurality of second-type conductive pillars located in the wider pitch region, each of the second-type conductive pillars having a copper-solder interface.

[0007] In some embodiments, this disclosure provides a method for manufacturing a semiconductor package structure, the method comprising: providing a first wafer having a first surface; electroplating a plurality of first conductive pillars in a first region of the first surface and electroplating a plurality of second conductive pillars in a second region of the first surface; planarizing the plurality of first conductive pillars and the plurality of second conductive pillars; and selectively forming solder bumps on each of the plurality of second conductive pillars. Attached Figure Description

[0008] Various aspects of this disclosure can be readily understood from the following detailed description, which is read in conjunction with the accompanying drawings. It should be noted that the various features may not necessarily be drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1A A cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure is shown.

[0010] Figure 1B A cross-sectional view of a semiconductor package structure prior to a bonding operation is shown, according to some embodiments of the present disclosure.

[0011] Figure 2A A cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure is shown.

[0012] Figure 2B A cross-sectional view of a semiconductor package structure prior to a bonding operation is shown, according to some embodiments of the present disclosure.

[0013] Figure 3A A cross-sectional view of a semiconductor package structure according to some embodiments of the present disclosure is shown.

[0014] Figure 3B A cross-sectional view of a semiconductor package structure prior to a bonding operation is shown, according to some embodiments of the present disclosure.

[0015] Figure 3C1 , Figure 3C2 , Figure 3C3 and Figure 3C4 Cross-sectional views of intermediate semiconductor package structures during various manufacturing operations are shown, according to some embodiments of the present disclosure.

[0016] Figure 4A , Figure 4B , Figure 4C and Figure 4D Various manufacturing operations are shown for a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0017] Figure 5A , Figure 5B , Figure 5C and Figure 5D Various manufacturing operations are shown for a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0018] Figure 6A , Figure 6B , Figure 6C and Figure 6D Various manufacturing operations are shown for a portion of a semiconductor package structure according to some embodiments of the present disclosure.

[0019] Figure 7A , Figure 7B and Figure 7C Cross-sectional views of intermediate semiconductor package structures during various manufacturing operations are shown, according to some embodiments of the present disclosure. Detailed Implementation

[0020] Throughout the accompanying drawings and detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0021] Spatial descriptions such as "above," "below," "upward," "left side," "right side," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper part," "above," and "below" are used to specify the orientation of a component or group of components or a plane of a component or group of components with respect to the orientation of said one or more components, as shown in the relevant figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that such arrangement does not depart from the advantages of the embodiments of this disclosure.

[0022] To achieve high I / O count scenarios and reduce contact resistance, hybrid bonding is employed, which includes metal-to-metal bonding and dielectric-to-dielectric bonding on the same surface. However, complex planarization operations are required prior to the bonding operation to control the degree of dishing on the metal surface, thereby facilitating the bonding process. For example, at least three chemical mechanical polishing (CMP) operations are required to polish the electroplated metal, the sputtered seed layer, and the dielectric surface surrounding the metal and seed layer. The surface roughness of the dielectric surface is critical to subsequent bonding operations. Generally, dielectric-to-dielectric bonding occurs before metal-to-metal bonding, and the dielectric bond strength can be difficult to control, potentially affecting the quality of the hybrid bonding. Furthermore, the alignment requirements between the metal-to-metal and dielectric-to-dielectric surfaces in the hybrid bonding are very high, for example, within a 1 μm process window.

[0023] This disclosure provides a semiconductor package structure with the following bonding type: a metal-metal interface in a narrower pitch region and a metal-solder interface in a wider pitch region, which relaxes complex planarization operations, surface roughness control, and precise alignment in hybrid bonding. Using a metal-solder interface in the wider pitch region facilitates alignment of the metal-metal interface in the narrower pitch region. A method for manufacturing a semiconductor package structure with the above-described bonding type is also provided.

[0024] Reference Figure 1A , Figure 1A A cross-sectional view of a semiconductor package structure 10 according to some embodiments of the present disclosure is shown. The semiconductor package structure 10 includes a carrier 101 and a carrier 102 bonded to the carrier. The carrier 101 may include a first surface 1011 facing the carrier 102, and the carrier 102 may include a second surface 1021 facing the carrier 101. At least two regions may be identified on the first surface 1011, for example, a first region 111 connected to a first type conductive post 131 and a second region 112 connected to a second type conductive post 132. The first type conductive post 131 and the second type conductive post 132 have different compositions, and the second type conductive post 132 may laterally surround the first type conductive post 131, such as... Figure 1AAs shown. In some embodiments, the first type of conductive post 131 is closer to the center than the edge of the carrier 101. In some embodiments, the first type of conductive post 131 and the second type of conductive post 132 each comprise a plurality of conductive posts. When referring to the first type of conductive post 131 herein, one or more conductive posts of the same type may be referred to. For example, the spacing of the first type of conductive posts 131 (which is the distance between adjacent first type of conductive posts 131) may be smaller than the spacing of the second type of conductive posts 132 (which is the distance between adjacent second type of conductive posts 132). In other words, the first type of conductive posts 131 are located in a narrower spacing region of the first surface 1011, and the second type of conductive posts 132 are located in a wider spacing region of the first surface 1011. In some embodiments, the spacing of the first type of conductive posts 131 is less than about 20 μm, for example, between 10 μm and 20 μm. In some embodiments, the spacing of the second type of conductive posts 132 is greater than about 20 μm, for example, between 20 μm and 40 μm.

[0025] Similarly, at least two regions can be identified on the second surface 1021, for example, a third region 113 connected to the first type conductive post 131 and a fourth region 114 connected to the second type conductive post 132. The third region 113 of the second surface 1021 corresponds to the first region 111 of the first surface 1011 in such a way that the first region 111 and the third region 113 are connected by the first type conductive post 131. The fourth region 114 of the second surface 1021 corresponds to the second region 112 of the first surface 1011 in such a way that the second region 112 and the fourth region 114 are connected by the second type conductive post 132. In some embodiments, the first type conductive post 131 is closer to the center than the edge of the carrier 101. In some embodiments, the first type conductive post 131 and the second type conductive post 132 each contain a plurality of conductive posts. For example, the spacing of the first type conductive posts 131 (which is the distance between adjacent first type conductive posts 131) can be smaller than the spacing of the second type conductive posts 132 (which is the distance between adjacent second type conductive posts 132). In other words, the first type of conductive post 131 is positioned in a narrower spacing region of the second surface 1021, and the second type of conductive post 132 is positioned in a wider spacing region of the second surface 1021. In some embodiments, the spacing of the first type of conductive posts 131 is less than about 20 μm, for example, between 10 μm and 20 μm. In some embodiments, the spacing of the second type of conductive posts 132 is greater than about 20 μm, for example, between 20 μm and 40 μm. In some embodiments, the distance D between adjacent first type of conductive posts 131 and second type of conductive posts 132 is greater than the spacing of the plurality of first type of conductive posts 131.

[0026] In some embodiments, the carrier 101 may be a semiconductor die with different region I / O densities, such as an application-specific integrated circuit (ASIC) die, a high-bandwidth memory (HBM) die, or a semiconductor wafer having multiple die regions, each die region having a different region I / O density. In some embodiments, the carrier 102 may be a semiconductor die with different region I / O densities or a semiconductor wafer having multiple die regions, each die region having a different region I / O density.

[0027] In some embodiments, the first type of conductive post 131 is made of a single conductive material (e.g., copper). The first type of conductive post 131 may include a copper-copper interface 131A, which is closer to the first surface 1011 than the second surface 1021. In some embodiments, the second type of conductive post 132 is made of more than one conductive material, including but not limited to copper, solder (e.g., SnAg), etc. In some embodiments, the second type of conductive post 132 is made of copper, solder (e.g., SnAg), and nickel. The second type of conductive post 132 may include a copper-solder interface 132A, which is closer to the second surface 1021 than the first surface 1011. Therefore, since there is no heterogeneous interface and the resistance of copper is lower than that of solder, the contact resistance of the first type of conductive post 131 is less than that of the second type of conductive post 132.

[0028] The second type of conductive post 132 may include a first copper segment located near the first surface 1011, a second copper segment located near the second surface 1021, and a solder (e.g., SnAg) segment 1321 located between the first copper segment and the second copper segment. Figure 1A As shown, a copper-solder interface 132A can be observed on the second type of conductive post 132. In some embodiments, an adhesive section 1322, such as a nickel section, is disposed between the first copper section and the solder section 1321. In some embodiments, a third copper section is disposed between the adhesive section 1322 and the solder section 1321.

[0029] exist Figure 1AIn this design, the copper-copper interface 131A on the first type of conductive post 131 may be at a different level from the copper-solder interface 132A on the second type of conductive post 132. For example, the copper-copper interface 131A may be closer to the first surface 1011 than the second surface 1021, and the copper-solder interface 132A may be closer to the second surface 1021 than the first surface 1011. In some embodiments, the first copper segment of the second type of conductive post 132 may have a thickness of about 10 μm. In some embodiments, the second copper segment of the second type of conductive post 132 may have a thickness of about 5 μm (not drawn to scale). In some embodiments, the copper segment of the first type of conductive post 131 located between the first surface 1011 and the copper-copper interface 131A is about 10 μm. In some embodiments, the copper segment of the first type of conductive post 131 located between the second surface 1021 and the copper-copper interface 131A is less than 30 μm, for example, between 28 μm and 30 μm.

[0030] Figure 1B A cross-sectional view of a semiconductor package structure prior to a bonding operation is shown according to some embodiments of the present disclosure. In some embodiments, carrier 101 may be a wafer-level single-cut functional die or die region, and carrier 102 may be a bonding wafer. Prior to the bonding operation, the thickness of the copper segment of the intermediate conductive pillar in the second region 112 of the first surface 1011 is substantially the same as the thickness of the copper segment of the intermediate conductive pillar in the first region 111 of the first surface 1011. The intermediate conductive pillar in the second region 112 further includes an adhesive segment 1322 (e.g., nickel) and a solder segment 1321. On the other hand, prior to the bonding operation, the thickness of the copper segment of the intermediate conductive pillar in the third region 113 of the second surface 1021 is substantially greater than the thickness of the copper segment of the intermediate conductive pillar in the fourth region 114 of the second surface 1021. Figure 1B As shown, a copper-copper interface 131A and a copper-solder interface 132A will be formed after the bonding operation.

[0031] During the bonding operation, solder segment 1321 is brought into contact with copper segments in the fourth region 114 of the second surface 1021, and copper segments in the first region 111 are brought into contact with copper segments in the third region 113 through appropriate alignment and annealing operations. However, when misalignment occurs, for example, when the center of solder segment 1321 does not overlap with the center of copper segments on the second surface 1021, or when the center of copper segments in the first region 111 does not overlap with the center of copper segments in the third region 113, the cohesive force of the molten solder segment 1321 can exert a pulling force on the intermediate conductive post in each region of the two dies, thereby aligning the intermediate conductive post in a self-assembling manner.

[0032] Figure 2AA cross-sectional view of a semiconductor package structure 20 according to some embodiments of the present disclosure is shown. The semiconductor package structure 20 is similar to the semiconductor package structure 10, but has the following differences: The sidewalls of the first type conductive pillar 131 are coated with a solder layer 1311, for example, SnAg. In some embodiments, a copper-solder interface is formed in the first type conductive pillar 131 because the sidewalls of the first type conductive pillar 131 are in contact with the solder layer 1311 and an intermetallic compound may form at the interface. In some embodiments, an additional adhesive layer 1312, for example, nickel, is formed between the first type conductive pillar 131 and the solder layer 1311. In some embodiments, the copper-copper interface 131A on the first type conductive pillar 131 may be flush with other solder-solder interfaces and / or nickel-nickel interfaces on the first type conductive pillar 131.

[0033] Figure 2B A cross-sectional view of a semiconductor package structure prior to a bonding operation is shown according to some embodiments of the present disclosure. In some embodiments, carrier 101 may be a wafer-level single-cut functional die or die region, and carrier 102 may be a bonding wafer. Prior to the bonding operation, the thickness of the copper segment of the intermediate conductive pillar in the second region 112 of the first surface 1011 is substantially the same as the thickness of the copper segment of the intermediate conductive pillar in the first region 111 of the first surface 1011. The intermediate conductive pillar in the second region 112 further includes an adhesive segment 1322 (e.g., nickel) and a solder segment 1321. On the other hand, prior to the bonding operation, the thickness of the copper segment of the intermediate solder-coated conductive pillar in the third region 113 of the second surface 1021 is substantially greater than the thickness of the copper segment of the intermediate conductive pillar in the fourth region 114 of the second surface 1021. Figure 2B As shown, a copper-copper interface 131A and a copper-solder interface 132A will be formed after the bonding operation.

[0034] During the bonding operation, solder segment 1321 is brought into contact with a copper segment in the fourth region 114 of the second surface 1021, and a suitable alignment and annealing process brings the solder-coated copper segment in the first region 111 into contact with the solder-coated copper segment in the third region 113. However, when misalignment occurs, for example, if the center of solder segment 1321 does not overlap with the center of a copper segment on the second surface 1021, or if the center of the solder-coated copper segment in the first region 111 does not overlap with the center of the solder-coated copper segment in the third region 113, the cohesive force of the molten solder segment 1321 and the molten solder layer 1311 can exert a pulling force on the intermediate conductive post in each region of the two dies, thereby aligning the intermediate conductive post in a self-assembly manner. Furthermore, if the copper-copper interface 131A is not formed by electrical connection or even if its contact resistance is not greater than the desired resistance, the solder layer 1311 can provide the necessary electrical connection after bonding.

[0035] Figure 3A A cross-sectional view of a semiconductor package structure 30 according to some embodiments of the present disclosure is shown. The semiconductor package structure 30 is similar to the semiconductor package structure 10, but has the following differences. Copper paste segments 1313 are located between copper segments in a first region 111 of a first surface 1011 and copper segments in a third region 113 of a second surface 1021. Figure 3A This is used to indicate the location of the copper paste and is therefore not drawn to scale. The copper paste can be a thin layer connecting opposing copper sections. In some embodiments, copper paste is applied to reduce contact resistance if opposing copper sections are not properly bonded. Figure 3C1 , Figure 3C2 , Figure 3C3 and Figure 3C4 The above scenario is described in detail.

[0036] Figure 3B A cross-sectional view of a semiconductor package structure prior to a bonding operation is shown according to some embodiments of the present disclosure. In some embodiments, carrier 101 may be a wafer-level single-cut functional die or die region, and carrier 102 may be a bonding wafer. Prior to the bonding operation, the thickness of the copper segment of the intermediate conductive pillar in the second region 112 of the first surface 1011 is substantially the same as the thickness of the copper segment of the intermediate conductive pillar in the first region 111 of the first surface 1011. The intermediate conductive pillar in the second region 112 further includes an adhesive segment 1322 (e.g., nickel) and a solder segment 1321. On the other hand, prior to the bonding operation, the thickness of the copper segment of the intermediate solder-coated conductive pillar in the third region 113 of the second surface 1021 is substantially greater than the thickness of the copper segment of the intermediate conductive pillar in the fourth region 114 of the second surface 1021. Figure 2B As shown, a copper-copper interface 131A and a copper-solder interface 132A will be formed after the bonding operation.

[0037] During the bonding operation, solder segment 1321 is brought into contact with copper segments in the fourth region 114 of the second surface 1021, and copper segments in the first region 111 are brought into contact with copper segments in the third region 113 through appropriate alignment and annealing procedures. However, when misalignment occurs, for example, when the center of solder segment 1321 does not overlap with the center of copper segments on the second surface 1021, or when the center of copper segments in the first region 111 does not overlap with the center of copper paste in the third region 113, the cohesive force of the molten solder segment 1321 can exert a pulling force on the intermediate conductive post in each region of the two dies, thereby aligning the intermediate conductive post in a self-assembling manner.

[0038] Figure 3C1 , Figure 3C2 , Figure 3C3 and Figure 3C4Cross-sectional views of intermediate semiconductor package structures during various manufacturing operations are shown, according to some embodiments of the present disclosure. Figure 3C1 In this process, multiple copper segments 131' are formed on the carrier 301. Figure 3C2 In the process, the plurality of copper segments 131' are immersed in copper paste 300, thereby forming a copper paste segment 313 on each of the copper segments 131'. Then, the carrier 301 is brought into contact with another carrier 302 having a corresponding copper segment 131" and a bonding operation is performed. The bonding operation may include an annealing process to promote copper interdiffusion between the relative copper segments 131', 131" . Misalignment may occur between the relative copper segments 131', 131" because (1) the center of copper segment 131' may be off-center from the center of copper segment 131"; (2) copper segment 131' may not be in contact with copper segment 131" after the annealing process, resulting in a small gap between them; (3) the bonding surface of one of the copper segments 131', 131" may be uneven, resulting in a portion of the bonding surface not being connected to its counterpart; or a combination of the above. In the presence of copper paste, the aforementioned increase in contact resistance can be mitigated by providing additional conductive channels to the relative copper sections for applying the copper paste.

[0039] Figure 4A , Figure 4B , Figure 4C and Figure 4D Various manufacturing operations are illustrated for a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 4A In this context, a first carrier 101 is provided, for example, a first wafer having a first surface 1011. Figure 4B In this design, a plurality of first conductive segments 131B and a plurality of second conductive segments 132B are formed on a first surface 1011. Specifically, conductive segments 131B are formed in a first region 111 on the first surface 1011 at a spacing P1, and second conductive segments 132B are formed in a second region 112 on the first surface 1011 at a spacing P2. The spacing P1 is smaller than the spacing P2. In some embodiments, the first region 111 is a dense region within the die, and the second region 112 is an isolated region within the same die. Figure 4C In this process, a planarization operation is performed to planarize the first conductive segment 131B and the second conductive segment 132B. In some embodiments, the planarization operation includes chemical mechanical polishing (CMP) to flatten the upper surfaces of the first conductive segment 131B and the second conductive segment 132B. Figure 4D In the second region 112, solder sections 1321, such as solder bumps, are selectively formed over the second conductive section 132B. The solder sections 1321 can be formed by electroplating, electroless plating, or printing operations. Figure 2A and Figure 2BIn the semiconductor package structure 20, solder segments 1321 are selectively formed on the second conductive segment 132B in the second region 112, and a solder layer 1311 is formed on the sidewall of the first conductive segment 131B. In some embodiments, the solder segments 1321 and the solder layer 1311 may be formed in a single operation or separately. In some embodiments, an adhesive segment 1322 is formed on the second conductive segment 132B before the solder segments 1321. In some embodiments, a copper segment 1323 is formed on the adhesive segment 1322 before the solder segments 1321.

[0040] Figure 5A , Figure 5B , Figure 5C and Figure 5D Various manufacturing operations are illustrated for a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figure 5A In this context, a second carrier 102 is provided, for example, a second wafer having a second surface 1021. Figure 5B In this design, multiple third conductive segments 131C and multiple fourth conductive segments 132C are formed on the second surface 1021. Specifically, third conductive segments 131C are formed in the third region 113 on the second surface 1021 at a spacing P1, and fourth conductive segments 132C are formed in the fourth region 114 on the second surface 1021 at a spacing P2. The spacing P1 is smaller than the spacing P2. In some embodiments, the third region 113 is a dense region within the die, and the fourth region 114 is an isolated region within the same die. Figure 5C In this process, a planarization operation is performed to selectively planarize the third conductive segment 131C. In some embodiments, the planarization operation includes chemical mechanical polishing (CMP) to flatten the upper surface of the third conductive segment 131C. Figure 5D Optionally, a plasma activation 501 operation is performed on the third conductive segment 131C and the fourth conductive segment 132C on the second wafer 102 to improve the copper-copper bonding strength.

[0041] Figure 6A , Figure 6B , Figure 6C and Figure 6D Various manufacturing operations are shown for a portion of a semiconductor package structure according to some embodiments of the present disclosure. Figures 6A to 6D A method for joining a die from a first carrier 101 and a second carrier 102 is illustrated. Figure 6A In the first carrier 101, a plurality of semiconductor dies 101A are included. Each semiconductor die 101A contains previously... Figure 4B The first region 111 and the second region 112 are described in the text. Figure 6BIn this process, the plurality of semiconductor dies 101A are diced from the first carrier 101 and placed on the third carrier 103. In some embodiments, other types of semiconductor dies 101B diced from another carrier are also placed on the third carrier 103 having semiconductor dies 101A, forming a hybrid die integration. Optionally, in Figure 6C Plasma activation 601 can be performed on the semiconductor die on the third carrier 103. Figure 6D In this process, a semiconductor die 102A diced from the second carrier 102 can be bonded to a semiconductor die on the third carrier 103, completing the die-wafer bonding operation. Each of the second conductive segments 132B on the semiconductor die 101A is bonded to a fourth conductive segment 132C on the semiconductor die 102A via a reflow operation that promotes soldering. Alternatively, the second carrier 102 is bonded to the third carrier 103 having mixed dies before the second carrier 102 is diced into individual semiconductor dies 102A. Alternatively, the first wafer 101 is bonded to the second wafer 12 without dicing any wafers into individual dies. After the reflow operation, each of the first conductive segments 131B on the first surface 1011 is connected to each of the third conductive segments 131C via an annealing operation to promote copper-copper diffusion at the copper-copper interface.

[0042] Figure 7A , Figure 7B and Figure 7C Cross-sectional views of intermediate semiconductor package structures during various manufacturing operations are shown, according to some embodiments of the present disclosure. Figure 7A In this process, each second conductive segment in the second conductive segment 132B is first connected to each fourth conductive segment in the fourth conductive segment 132C via a reflow soldering operation, thereby bonding the first carrier 101 to the second carrier 102. The reflow soldering operation allows the solder segments on the second conductive segment 132B to melt and connect to their counterparts in the fourth conductive segment 132C. For example... Figure 7B As shown, when misalignment occurs between corresponding conductive sections on the first carrier 101 and the second carrier 102, the cohesive force of the molten solder can apply horizontal tensile forces f1 and f2 to the relative carriers and align them in a self-assembly manner. Figure 7C In this process, annealing is performed after self-alignment to promote copper-copper diffusion at the copper-copper interface 131A and to facilitate the bonding process. Figure 7C Then, the first carrier 101 and the second carrier 102 can be cut separately to form multiple semiconductor package structures.

[0043] As used herein and unless otherwise defined, the terms “substantially,” “basically,” “approximately,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may cover instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. For example, when used in conjunction with a numerical value, the terms may cover a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” may refer to two surfaces whose positional difference along the same plane is within a few micrometers, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm.

[0044] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may include plural referents. In the description of some embodiments, the description of another component disposed “on” or “above” a component may cover the case where the preceding component is directly on (e.g., in physical contact with) the following component, as well as the case where one or more intermediate components are positioned between the preceding and following components.

[0045] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the spirit and scope of this disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically shown. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, the order and grouping of operations are not limiting unless expressly indicated herein.

Claims

1. A semiconductor package structure comprising: A first carrier, the first carrier having a first surface, the first surface including a first region and a second region; The second carrier has a second surface opposite to the first surface, and the second surface includes a third region corresponding to the first region and a fourth region corresponding to the second region. A plurality of first-type conductive pillars are located between the first region of the first surface and the third region of the second surface; as well as A plurality of second-type conductive pillars are located between the second region of the first surface and the fourth region of the second surface; The contact resistance of each first-type conductive post in the first type of conductive post is lower than the contact resistance of each second-type conductive post in the second type of conductive post. The spacing between the first type of conductive pillars in the first region is less than the spacing between the second type of conductive pillars in the second region, and the spacing between the first type of conductive pillars in the first region is less than 20 μm.

2. The semiconductor packaging structure according to claim 1, wherein each of the plurality of first-type conductive pillars includes a copper-copper interface.

3. The semiconductor packaging structure according to claim 2, wherein each of the plurality of second-type conductive pillars includes a copper-solder interface.

4. The semiconductor packaging structure according to claim 1, wherein the sidewall of each of the first type of conductive pillars further comprises a solder coating.

5. The semiconductor packaging structure of claim 1, wherein the first carrier comprises a semiconductor die, and the first region of the first surface is closer to the center than the edge of the semiconductor die.

6. A semiconductor package structure comprising: The surface of a semiconductor die has a narrower pitch region and a wider pitch region adjacent to the narrower pitch region; Multiple first-type conductive pillars are located in the narrower spacing region, and each of the first-type conductive pillars has a copper-copper interface. as well as A plurality of second-type conductive posts are located in the wider spacing region, each of the second-type conductive posts having a copper-solder interface, wherein the distance between adjacent first-type conductive posts and second-type conductive posts is greater than the spacing between the plurality of first-type conductive posts.

7. The semiconductor packaging structure according to claim 6, wherein the copper-copper interface and the copper-solder interface are at different levels.

8. The semiconductor packaging structure according to claim 6, wherein the spacing between the plurality of second-type conductive pillars is greater than 20 μm.

9. The semiconductor package structure of claim 6, wherein the sidewall of each of the first type of conductive pillars further comprises a solder coating.

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