Semiconductor device

Abstract

A semiconductor device includes a first diode, a second diode, a clamp circuit, and a third diode. The first diode is coupled between an input / output (I / O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I / O pad, and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are to direct a first portion of electrostatic discharge (ESD) current flowing between the I / O pad and the first voltage terminal. The third diode coupled to the first voltage terminal and the second diode include a first semiconductor structure to direct a second portion of ESD current flowing between the I / O pad and the first voltage terminal. A method of operation of a semiconductor device and a method of manufacturing a semiconductor device are also disclosed.

Description

Technical Field

[0001] This case relates to a semiconductor device and a method of operating and manufacturing the semiconductor device, particularly a semiconductor device having a semiconductor structure for electrostatic discharge between an input / output pad and a voltage terminal, and a method of operating and manufacturing the semiconductor device. Background Technology

[0002] ESD events generate extremely high voltages and result in short-duration high-current pulses, which can damage integrated circuit components. Therefore, diode string-triggered SCRs (DTSCRs) or low-voltage triggered SCRs (LVTSCRs) are widely used for low-capacitance ESD protection. In some cases, DTSCRs suffer voltage overshoot during ESD events, while the performance of LVTSCRs needs to be improved due to their capacitance factor. Summary of the Invention

[0003] According to one embodiment of this invention, a semiconductor device is disclosed including a first diode, a second diode, a clamping circuit, and a third diode. The first diode is coupled between an input / output (I / O) pad and a first voltage terminal. The second diode is coupled to the first diode, the input / output pad, and the second voltage terminal. The clamping circuit is coupled between the first and second voltage terminals. The second diode and the clamping circuit are used to guide a first portion of the electrostatic discharge (ESD) current flowing between the input / output pad and the first voltage terminal. The third diode coupled to the first voltage terminal and the second diode include a first semiconductor structure used to guide a second portion of the ESD current flowing between the input / output pad and the first voltage terminal.

[0004] According to another embodiment of this application, a semiconductor device is disclosed, comprising a substrate, a first well of a first type disposed on the substrate, a first doped region of a first type disposed in the first well, a second doped region of a second type disposed in the first well, a second well of a second type disposed on the substrate and adjacent to the first well, a third doped region of a first type disposed in the second well, and a fourth doped region of a second type disposed in the second well. The first doped region serves as a first terminal of a first diode and is coupled to a first voltage terminal for receiving a first supply voltage. The second doped region serves as a second terminal of the first diode and is coupled to an input / output pad. The third doped region serves as a first terminal of a second diode and is coupled to a second voltage terminal for receiving a second supply voltage. The fourth doped region serves as a second terminal of the second diode and is coupled to the second voltage terminal. The first diode, the first voltage terminal, and a clamping circuit coupled between the first and second voltage terminals constitute a first electrostatic discharge path between the input / output pad and the second voltage terminal. The second doped region, the first well, the substrate, the second well, and the third doped region constitute a second electrostatic discharge path between the input / output pad and the second voltage terminal.

[0005] According to another embodiment of this case, a method of operating a semiconductor device is disclosed, including turning on a first electrostatic discharge path between an input / output pad and a first voltage terminal, the first voltage terminal being used to receive a first supply voltage, wherein in this first electrostatic discharge path, a first diode is coupled between the input / output pad and a second voltage terminal, the second voltage terminal being used to receive a second supply voltage, and a clamping circuit is coupled between the first voltage terminal and the second voltage terminal; and turning on a second electrostatic discharge path between the input / output pad and the first voltage terminal, wherein in this second electrostatic discharge path, the first diode and a second diode having two terminals coupled to the first voltage terminal include a first semiconductor structure, and the first semiconductor structure is used as a first equivalent silicon controlled rectifier circuit.

[0006] According to another embodiment of this application, a semiconductor device is disclosed, comprising a substrate, a first well of a first type, a first doped region of a first type, a second doped region of a second type, a second well of a second type, a third doped region of a first type, and a fourth doped region of a second type. The first well of the first type is disposed on the substrate. The first doped region of the first type is disposed in the first well and is coupled to a first voltage terminal to receive a first supply voltage. The second doped region of the second type is disposed in the first well, the second type being different from the first type, and is coupled to an input / output pad. The second well of the second type is arranged adjacent to the first well and disposed on the substrate. The third doped region of the first type and the fourth doped region of the second type are disposed in the second well and are coupled to a second voltage terminal to receive a second supply voltage different from the first supply voltage. The third doped region is disposed between the second doped region and the fourth doped region. The second doped region, the first well, the substrate, the second well, and the third doped region are used to transmit electrostatic discharge current flowing between the input / output pad and the second voltage terminal.

[0007] According to another embodiment of this application, a semiconductor device is disclosed comprising a plurality of first doped regions and a plurality of second doped regions. The plurality of first doped regions are disposed in a first well and on a substrate, with first and second regions of the first doped regions included in a structure serving as a first diode for receiving a first supply voltage. The plurality of second doped regions are disposed in a second well and on a substrate, each including a first region and a second region. The first region is used to receive a second supply voltage different from the first supply voltage. The second region is coupled to an input / output pad. The first and second regions of the second doped regions are included in a structure serving as a second diode. The first and second regions of the first doped regions and the second regions of the second doped regions are used to transmit a first electrostatic discharge current flowing between the input / output pad and a first voltage terminal providing the first supply voltage.

[0008] According to another embodiment of this application, a semiconductor device is disclosed including a first diode and a second diode. The first diode has a plurality of first doped bands extending in a first direction and serving as a plurality of terminals coupled to a first voltage terminal. The second diode has a second doped band extending in the first direction and separated from the plurality of first doped bands in a second direction different from the first direction. The second doped band serves as a first terminal of the second diode coupled to an I / O pad. The first diode and the second diode are included in a first semiconductor structure, which operates as a first equivalent silicon controlled rectifier circuit between the I / O pad and the first voltage terminal.

[0009] According to another embodiment of this application, a semiconductor device is disclosed, comprising a first doped region of a first conductivity type, a second doped region of a second conductivity type, a first well of a first conductivity type, a third doped region of a first conductivity type, and a second well of a second conductivity type. The first doped region of the first conductivity type serves as a first terminal of a first diode. The second doped region of the second conductivity type serves as a second terminal of the first diode, and the first and second doped regions are coupled to a first voltage terminal. The first well of the first conductivity type surrounds the first and second doped regions in a layout view. The third doped region of the first conductivity type serves as a first terminal of a second diode, and the first terminal is coupled to an I / O pad. The second well of the second conductivity type surrounds the third doped region in a layout view, and the second, third, first, and second wells serve as a first electrostatic discharge path between the I / O pad and the first voltage terminal.

[0010] According to another embodiment of this case, a method of manufacturing a semiconductor device is disclosed, including forming a first well of a first conductivity type, the first well surrounding a first doped region of a second conductivity type in a layout view, wherein the first doped region is coupled to an I / O pad; and forming a second well of the second conductivity type, the second well surrounding a second doped region of the second conductivity type in a layout view, wherein the second doped region is coupled to a first voltage terminal and an isolation region inserted between the first doped region and the second doped region, wherein the first doped region to the second doped region and the first well to the second well form a first electrostatic discharge path between the I / O pad and the second doped region.

[0011] According to another embodiment of this application, a semiconductor device is disclosed, including a first doped region, a second doped region, and a third doped region. The first and second doped regions are disposed in a first well on a substrate and included in a structure operating as a first diode and coupled to a first voltage terminal. The third doped region is disposed in a second well and coupled to an I / O pad. The first and second doped regions have the same conductivity type, and the third doped region has the same conductivity type as the first well. The first and third doped regions transmit a first electrostatic discharge current flowing between the I / O pad and the first voltage terminal, and the first voltage terminal provides a first supply voltage. Attached Figure Description

[0012] The best understanding of this disclosure can be obtained by reading it in conjunction with the accompanying figures, as described in the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0013] Figure 1 An equivalent circuit for a portion of a semiconductor device according to some embodiments;

[0014] Figure 2AAccording to some embodiments, in Figure 1 The layout diagram of a section of the semiconductor device in the plan view, and Figure 2B According to various embodiments, in Figure 2A A cross-sectional view of the layout of semiconductor devices in the diagram;

[0015] Figure 3A The equivalent circuit of a portion of a semiconductor device according to various embodiments, and Figure 3B According to some embodiments, in Figure 3A A layout diagram of a section of a semiconductor device in a plan view;

[0016] Figure 4A This is a layout diagram in a plan view of a segment of a semiconductor device according to various embodiments, and Figure 4B for Figure 4A A cross-sectional view of the layout of semiconductor devices in the diagram; Figure 4C and Figure 4D This is a layout diagram of a semiconductor device according to various embodiments;

[0017] Figure 5A This is a layout diagram in a plan view of a segment of a semiconductor device according to various embodiments, and Figure 5B and Figure 5C for Figure 5A A cross-sectional view of the layout of semiconductor devices in the diagram; Figure 5D and Figure 5E This is a layout diagram of a semiconductor device according to various embodiments;

[0018] Figure 6 Equivalent circuit of a portion of a semiconductor device according to various embodiments;

[0019] Figure 7A According to some embodiments, in Figure 6 A layout diagram of a section of a semiconductor device in a plan view; Figure 7B According to various embodiments, in Figure 7A A cross-sectional view of the layout of semiconductor devices in the diagram;

[0020] Figure 8A The equivalent circuit of a portion of a semiconductor device, and Figure 8B According to some embodiments, in Figure 8A A layout diagram of a section of a semiconductor device in a plan view;

[0021] Figure 9A According to some embodiments, in Figure 6 A layout diagram of a section of a semiconductor device in a plan view, which has another arrangement of doped regions; Figure 9B According to various embodiments, in Figure 9AA cross-sectional view of the layout of semiconductor devices in the diagram; Figure 9C and Figure 9D According to some embodiments, in Figure 9A A layout diagram of a semiconductor device in a plan view;

[0022] Figure 10 Equivalent circuit of a portion of a semiconductor device according to various embodiments;

[0023] Figure 11A According to various embodiments, in Figure 10 A schematic diagram of the operation of the equivalent circuit in the diagram; Figure 11B According to some embodiments, in Figure 11A The layout diagram of a section of the semiconductor device in the plan view, and Figure 11C for Figure 11B A cross-sectional view of the layout of semiconductor devices in the diagram;

[0024] Figure 12A According to various embodiments, in Figure 10 A schematic diagram of another operation of the equivalent circuit in the diagram; Figure 12B According to some embodiments, in Figure 12A The layout diagram of a section of the semiconductor device in the plan view, and Figure 12C for Figure 12B A cross-sectional view of the layout of semiconductor devices in the diagram;

[0025] Figure 13A The equivalent circuit of a portion of a semiconductor device according to various embodiments, and Figure 13B According to some embodiments, in Figure 13A A layout diagram of a section of a semiconductor device in a plan view;

[0026] Figure 14 This is a flowchart of a method for operating a semiconductor device according to various embodiments.

[0027] [Symbol Explanation]

[0028] 100, 300-600, 800, 1000, 1300: Semiconductor devices

[0029] 110: Input / Output (I / O) Pad

[0030] 120: Power clamping circuit

[0031] 130: Internal Circuit

[0032] VDD, VSS: Supply voltage, voltage terminals

[0033] IN: ESD current

[0034] Dp,Dn,Dn',Dp1-Dpm,Dn1-Dnm,Dn'1-Dn'm,Dp', Dp'1-Dp'm: Diodes

[0035] R: Resistance

[0036] ESDP1-ESDP4, ESDP11-ESDP1m, ESDP21-ESDP2m, ESDP31-ESDP3m: ESD path

[0037] CELL1-CELL6,CELL11-CELL1m,CELL21-CELL2m,CELL31-CELL3m,CELL41-CELL4m,CELL51-CELL5m,CELL61-CELL6m:ESD unit

[0038] PW1-PW3: P-trap

[0039] NW1-NW3:N well

[0040] CL1: I / O pad metal connection layer

[0041] CL2: VDD metal interconnect layer

[0042] CL3: VSS metal bonding layer

[0043] VSSP+,DpP+,DnP+,Dn'P+,DnP+1-DnP+p, VSSP+1-VSSP+p,VDDP+,Dp'P+: P+ doped regions, regions

[0044] VSSN+,DnN+,Dn'N+,DpN+,DpN+1-DpN+P,VDDN+,VDDN+1-VDDN+P,Dp'N+1-Dp'N+P,Dp'N+: N+ type doped region, region

[0045] XX': Horizontal line

[0046] P1,P11-P1m: PNP path

[0047] P2, P21-P2m, P3, P31-P3m: NPN path

[0048] SI: Shallow Trench Separation

[0049] R1-R4: Parasitic resistance

[0050] T1, T3, T5, T9: Parasitic PNP transistors

[0051] T2, T4, T6, T10: Parasitic NPN transistors

[0052] T7-T8: Parasitic transistors

[0053] PS: P-type substrate

[0054] 1400: Method

[0055] 1401, 1402: Steps Detailed Implementation

[0056] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify one embodiment of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0057] Additionally, for simplicity, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another (other) element or feature, as illustrated in the figures. These spatial relative terms are intended to cover different orientations of elements in use or operation, in addition to those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0058] For reference Figure 1 . Figure 1 This is an equivalent circuit diagram of a portion of a semiconductor device 100 according to some embodiments. For illustration, the semiconductor device 100 includes an input / output (I / O) pad 110, diodes Dp, Dn, and Dn', a resistor R, a power supply clamping circuit 120, and internal circuitry 130. (See also...) Figure 1As illustrated, the anode of diode Dp is coupled to I / O pad 110, and the cathode of diode Dp is coupled to a voltage terminal used to receive the supply voltage VDD (also referred to as "voltage terminal VDD" in the following paragraphs). A resistor R is coupled between diode Dp and power clamping circuit 120. Power clamping circuit 120 is coupled between voltage terminal VDD and a voltage terminal used to receive the supply voltage VSS (also referred to as "voltage terminal VSS" in the following paragraphs). In some embodiments, power clamping circuit 120 is used to clamp the voltage between voltage terminal VDD and voltage terminal VSS. The anode and cathode of diode Dn' are coupled to voltage terminal VSS. The anode of diode Dn is coupled to voltage terminal VSS. The cathode of diode Dn, I / O pad 110, and anode of diode Dp are coupled to each other.

[0059] like Figure 1 As illustrated, internal circuitry 130 is coupled to I / O pad 110. In some embodiments, internal circuitry 130 is configured to receive signals input via I / O pad 110 or to transmit signals output via I / O pad 110. In some embodiments, internal circuitry 130 includes logic or circuitry for processing signals transmitted via I / O pad 110 or operating in response to signals transmitted via I / O pad 110.

[0060] In some embodiments, diodes Dp, Dn, and Dn' are formed by placing N-type diffusion regions and P-type diffusion regions in an N-type well region or a P-type well region on a substrate. Details of the configuration of diodes Dp, Dn, and Dn' will be discussed in the following paragraphs. However, the scope of one embodiment of this disclosure is not intended to be limited to the above types, and other suitable arrangements of the types of diodes Dp, Dn, and Dn' are within the scope of one embodiment of this disclosure.

[0061] In some embodiments, the resistor R represents the resistance contributed by the metal wiring arranged to couple the power supply clamping circuit 120 to the voltage terminal VDD, diode Dp, or other corresponding element. In various embodiments, the resistor R is omitted, and therefore does not affect the operation of the circuitry in the semiconductor device 100.

[0062] To illustrate, such as Figure 1 As shown, the anode of diode Dn receives the supply voltage VSS. The cathode of diode Dp receives the supply voltage VDD. In some embodiments, the supply voltage VSS is ground voltage, and the supply voltage VDD is power supply voltage.

[0063] During an electrostatic discharge (ESD) event, a large amount of positive potential is momentarily established at I / O pad 110, typically caused by direct or indirect contact with an electrostatic field. When an ESD event occurs, multiple ESD paths are activated in semiconductor device 100 (including, for example, such as...). Figure 1 As shown in ESDP1 and ESDP2, this is used to discharge the ESD current IN. Specifically, as... Figure 1 As shown, a portion of the ESD current IN flows between the I / O pad 110 and the voltage terminal VSS, and is directed through the ESD path ESDP1, which is formed by diode Dp, resistor R, and power supply clamping circuit 120. Another portion of the ESD current IN flows between the I / O pad 110 and the voltage terminal VSS, and is directed through the ESD path ESDP2, wherein diodes Dp and Dn' include semiconductor structures for partially discharging the ESD current IN. Details of the semiconductor structures included in diodes Dp and Dn' are discussed below.

[0064] To further understand Figure 1 The structure of a portion of the semiconductor device 100 shown in the embodiments is now referred to. Figure 2A and Figure 2B . Figure 2A According to some embodiments, in Figure 1 The layout diagram of a section of the semiconductor device 100 in the plan view. Figure 2B According to various embodiments, in Figure 2A The layout of the semiconductor device 100 is a cross-sectional view along the transverse section XX'.

[0065] To illustrate, such as Figure 2A and Figure 2B As shown, the semiconductor device 100 includes P-wells PW1, N-wells NW1, and P-wells PW2 (as shown) disposed on a P-type substrate PS. Figure 2B (As shown), diodes Dp, Dn' and Dn, I / O pad metal connection layer CL1, VDD metal connection layer CL2, and VSS metal connection layer CL3. For simplicity of explanation, Figure 2B The diagram does not show the I / O pad metal connection layer CL1, VDD metal connection layer CL2, and VSS metal connection layer CL3.

[0066] To illustrate, such as Figure 2AAs shown, the I / O pad metal interconnect layer CL1 is disposed on the P+ doped region DpP+ and the N+ doped region DnN+ for connecting regions DpP+, DnN+ and I / O pad 110. The VDD metal interconnect layer CL2 is disposed on the N+ doped region DpN+ for connecting the N+ doped region DpN+ and the voltage terminal VDD. The VSS metal interconnect layer CL3 is disposed on the N+ doped region Dn'N+, P+ doped region Dn'P+, P+ doped region DnP+, N+ doped region DnN+, N+ doped region VSSN+, and P+ doped region VSSP+ for connecting regions Dn'N+, Dn'P+, DnP+, DnN+, VSSN+, VSSP+ and the voltage terminal VSS.

[0067] In some embodiments, diodes Dp, Dn', and Dn, as well as at least a portion of the semiconductor structure described above, are configured as follows: Figure 2A The ESD unit CELL1 shown is an example. However, the scope of this embodiment is not limited to this type of ESD unit, and other suitable types of ESD units are also covered by this embodiment. For example, depending on the current capability required by the semiconductor device 100, the width and length of the doped regions, the spacing between the doped regions, and the arrangement of the interconnect layers can be modified as needed.

[0068] In addition to the above, Figure 2A Beyond the discussed area, the semiconductor device 100 further includes shallow trench isolation (STI) SI. Figure 2B The diagram shows the configuration of the shallow trench isolation SI and the above information. Figure 2A The area discussed. Furthermore, as... Figure 2B As shown, diode Dp includes regions DpP+ and DpN+ formed in N-well NW1. Region DpP+ serves as the anode of diode Dp and is coupled to I / O pad 110. Region DpN+ serves as the cathode of diode Dp and is coupled to voltage terminal VDD to receive supply voltage VDD. Diode Dn' includes a P+-doped region Dn'P+ and an N+-doped region Dn'N+ formed in P-well PW2 adjacent to N-well NW1. Region Dn'P+ serves as the anode of diode Dn'. Region Dn'N+ serves as the cathode of diode Dn'. Regions Dn'P+ and Dn'N+ are coupled to voltage terminal VSS to receive supply voltage VSS. Diode Dn includes regions DnP+ and DnN+ formed in P-well PW2. Region DnP+ serves as the anode of diode Dn and is coupled to voltage terminal VSS to receive supply voltage VSS. Region DnN+ serves as the cathode of diode Dn and is used to couple to I / O pad 110.

[0069] Based on the above... Figure 2B The semiconductor structure, including parasitic PNP transistor T1, parasitic NPN transistor T2, and parasitic resistors R1, R2, and R3, is as follows: Figure 2B The circuit is typically formed and coupled as shown. In some embodiments, the parasitic PNP transistor T1, parasitic NPN transistor T2, and parasitic resistors R1, R2, and R3 together form an equivalent silicon controlled rectifier (SCR) circuit. This is provided for illustrative purposes. Figure 2B The equivalent SCR circuit shown is illustrated. Various equivalent SCR circuits are covered by one embodiment of this disclosure. For example, in various embodiments, at least one of the parasitic resistances R1, R2, or R3 is omitted.

[0070] Parasitic PNP transistor T1 includes an emitter region DpP+, an N-well NW1 as the base, and a P-type substrate PS as the collector. The base of parasitic PNP transistor T1 is coupled to region DpN+ via parasitic resistor R1, which represents the inherent resistance of N-well NW1. The collector of PNP transistor T1 is coupled to region Dn'P+ via parasitic resistors R2 and R3, where parasitic resistor R2 represents the inherent resistance of P-type substrate PS, and parasitic resistor R3 represents the inherent resistance of P-well PW2. Parasitic NPN transistor T2 includes an N-well NW1 as the collector, a P-well PW2 as the base, and an emitter region Dn'N+. The collector of parasitic NPN transistor T2 is coupled to the base of parasitic PNP transistor T1. The base of parasitic NPN transistor T2 is coupled to region Dn'P+ via parasitic resistors R2 and R3. The emitter of the parasitic NPN transistor T2 is coupled to region Dn'N+.

[0071] In some embodiments, regions VSSN+, DpN+, Dn'N+, and DnN+ are doped with n-type dopants, including, for example, phosphorus, arsenic, or combinations thereof. P+ doped regions VSSP+, DpP+, Dn'P+, and DnP+ are doped with p-type dopants, including, for example, boron, indium, aluminum, gallium, or combinations thereof. In some embodiments, unless otherwise stated, the P-wells disclosed herein are formed by doping a substrate with p-type dopants. Similarly, unless otherwise stated, the N-wells disclosed herein are formed by doping a substrate with n-type dopants. In some embodiments, the P-type substrate PS comprises a semiconductor material doped with p-type dopants, such as, but not limited to, silicon, germanium, compound semiconductors (including silicon carbide), and gallium arsenide. In some embodiments, shallow trench isolation SI is formed by forming trenches in N-well NW1 and P-wells PW1, PW2 and filling these trenches with a dielectric material, including, for example, silicon dioxide, high-density plasma (HDP) oxide, or the like.

[0072] Continue to refer to Figure 2B For illustration, the semiconductor structures included in diodes Dp and Dn' are used as ESD path ESD path ESD path ESDP2 (as well as...). Figure 1 As shown in the diagram, it is used as an equivalent silicon controlled rectifier (SCR) circuit as described above. In other words, the regions DpP+, N-well NW1, P-type substrate PS, P-well PW2 of diode Dp, and the regions Dn'N+ and Dn'P+ of diode Dn' are used as the SCR circuit. For example, in some embodiments, a portion of the ESD current IN injected from I / O pad 110 flows through the regions DpP+, N-well NW1, P-type substrate PS, P-well PW2, and the regions Dn'N+ and Dn'P+ of diode Dn', and flows to the voltage terminal VSS.

[0073] During operation, during ESD-to-VSS (Positive-to-VSS, hereinafter referred to as "PS" mode) or positive electrostatic discharge events, Figure 1 The diode Dp and the power clamping circuit 120 are turned on to further trigger... Figure 2B The SCR circuit. At least a portion of the ESD current IN flows from I / O pad 110 through... Figure 1 The ESD path ESDP1 leads to the voltage terminal VDD. This ESD path ESDP1 includes the region DpP+ of diode Dp, the N-well NW1, and the region DpN+ of diode Dp. Furthermore, parasitic transistors T1 and T2 are turned on during PS mode. Therefore, another portion of the ESD current IN flows from I / O pad 110 through the ESD path ESDP2 to the voltage terminal VSS. This ESD path ESDP2 includes parasitic transistor T1 (corresponding to the region DpP+ of diode Dp, the N-well NW1, and the P-type substrate PS), parasitic resistor R2 (corresponding to the P-type substrate PS), parasitic transistor T2 (corresponding to the N-well NW1, the P-well PW2, and the region Dn'N+), and parasitic resistor R3, flowing to the voltage terminal VSS. Regarding... Figure 1 , Figure 2A and Figure 2B The configuration shown in the diagram, except for the ESD path ESD P1 (where the ESD current IN flows through diode Dp, ...), Figure 1 In addition to the resistor R and the power clamping circuit 120, a portion of the ESD current IN is further shunted to ground via the ESD path ESDP2.

[0074] In some embodiments, the semiconductor device 100 further includes regions VSSP+ and VSSN+ formed in the P-well PW1, such as Figure 2BAs shown in the diagram. For illustration, region VSSN+ is doped with an n-type dopant as described above. In some embodiments, the ESD path ESDP3 is also conducted through the semiconductor structure including region VSSN+ in the P-well PW1. In various embodiments, the ESD path ESDP3 also implements another equivalent SCR circuit; for simplicity of explanation, Figure 2B This other equivalent SCR circuit is not illustrated. Another portion of the ESD current IN flows from I / O pad 110 through the ESD path ESDP3 (including the area DpP+ of diode Dp and the area VSSN+), to the voltage terminal VSS.

[0075] For illustrative purposes, the following is given: Figure 2A and Figure 2B The above configuration. Figure 2A and Figure 2B The various configurations of the elements mentioned herein are within the scope of one embodiment of this disclosure. For example, in various embodiments, the semiconductor structure including the P-well PW1 and regions VSSP+ and VSSN+ is omitted.

[0076] For reference Figure 3A . Figure 3A This is an equivalent circuit diagram of a portion of a semiconductor device 300 according to various embodiments. Regarding... Figure 1 For ease of understanding, the embodiments are represented by the same element symbols. Figure 3A The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 3A The cooperative relationship of the components shown.

[0077] and Figure 1 Compared to the embodiments shown, Figure 3A The semiconductor device 300 in the illustrated embodiment includes a plurality of diodes Dp1 to Dpm coupled in parallel between the I / O pad 110 and the voltage terminal VDD, a plurality of diodes Dn1 to Dnm coupled in parallel between the I / O pad 110 and the voltage terminal VSS, and a plurality of diodes Dn'1 to Dn'm coupled in parallel to the voltage terminal VSS. In some embodiments, each of diodes Dp1 to Dpm is coupled to the voltage terminal VSS as shown in the figure. Figures 1 to 2B The diode Dp discussed is equivalent. In some embodiments, each of diodes Dn1 to Dnm is as described above. Figures 1 to 2B The diode Dn discussed is equivalent. In some embodiments, each of diodes Dn'1 to Dn'm is as described above. Figures 1 to 2BThe diodes Dn' discussed are equivalent. Furthermore, in some embodiments, the number of diodes Dp1 to Dpm, diodes Dn1 to Dnm, and diodes Dn'1 to Dn'm are different from each other. In other words, in some embodiments, the semiconductor device 300 includes at least one diode among diodes Dp2 to Dpm coupled to diode Dp1, at least one diode among diodes Dn2 to Dnm coupled to diode Dn1, and at least one diode among diodes Dn'2 to Dn'm coupled to diode Dn'1.

[0078] For reference Figure 3B . Figure 3B According to some embodiments, in Figure 3A The semiconductor device 300 is shown in a plan view of a section. For illustration, the semiconductor device 300 includes a plurality of ESD cells CELL11 to CELL1m arranged in an array. Each of the ESD cells CELL11 to CELL1m has a [missing information - likely related to a specific feature or characteristic]. Figure 2A The ESD unit CELL1 in the illustrated embodiment has the same configuration. Figure 3B As shown, ESD cell CELL 12 is adjacent to ESD cell CELL 11, ESD cell CELL 13 is adjacent to ESD cell CELL 12, and so on. However, the scope of one embodiment of this disclosure is not intended to be limited to the aforementioned arrangement of multiple ESD cells in an array, and other suitable arrangements of multiple ESD cells are within the scope of one embodiment of this disclosure. For example, the number of ESD cells included in the array can be modified as needed, depending on the current capability required by the semiconductor device 300.

[0079] Specifically Figure 3B The diagram illustrates that the semiconductor device 300 provides multiple ESD paths ESDP11 to ESDP1m, multiple ESD paths ESDP21 to ESDP2m, and multiple ESD paths ESDP31 to ESDP3m provided by ESD units CELL11 to CELL1m. In some embodiments, each of the ESD paths ESDP11 to ESDP1m has a... Figure 2A and Figure 2BThe ESD path ESDP1 in the illustrated embodiment has the same configuration. Similarly, each of the ESD paths ESDP21 to ESDP2m has the same configuration as ESD path ESDP2, and each of the ESD paths ESDP31 to ESDP3m has the same configuration as ESD path ESDP3. In other words, ESD paths ESDP11 to ESDP1m cooperate to discharge a portion of the ESD current IN between I / O pad 110 and voltage terminal VSS. ESD paths ESDP21 to ESDP2m cooperate to discharge another portion of the ESD current IN via the semiconductor structures included in diodes Dp1 to Dpm and diodes Dn'1 to Dn'm. ESD paths ESDP31 to ESDP3m cooperate to discharge another portion of the ESD current IN from the anode of diodes Dp1 to Dpm to voltage terminal VSS.

[0080] For illustrative purposes, the configurations of diodes Dp1 to Dpm, Dn1 to Dnm, Dn'1 to Dn'm, and ESD cells CELL11 to CELL1m are given. Various configurations of the above components are all within the scope of one embodiment of this disclosure. For example, in various embodiments, the ESD cells CELL11 to CELL1m are arranged in a column or matrix, rather than as shown... Figure 3B The arrangement shown is in rows.

[0081] For reference Figure 4A and Figure 4B . Figure 4A This is a layout diagram of a section of a semiconductor device 400 according to various embodiments. Figure 4B According to various embodiments, in Figure 4A The layout of semiconductor device 400 is shown in a cross-sectional view along the cross section XX'. Regarding... Figure 4A and Figure 4B For ease of understanding, the embodiments are represented by the same element symbols. Figure 2A and Figure 2B The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 4A and Figure 4B The cooperative relationship of the components shown.

[0082] and Figure 2A and Figure 2B Compared to the embodiments shown, for the purpose of illustration, in Figure 4A and Figure 4BIn the illustrated embodiment, the regions Dn'P+ and Dn'N+ of diode Dn' are disposed in P-well PW2 on one side of N-well NW1, while the doped region of diode Dn is disposed in P-well PW1 on the other side of N-well NW1. P-wells PW1 and PW2 are adjacent to N-well NW1. Furthermore, a plurality of P+ doped regions DnP+1 to DnP+p (each having as shown in the figure) are arranged in P-well PW1 along the direction of the transverse section XX'. Figure 4A (As shown in the strip configuration). Region DnP+1 serves as the anode of diode Dn. Each of the P+ doped regions DnP+1 to DnP+p is coupled to the voltage terminal VSS via a VSS metal interconnect layer CL3 disposed thereon. In some embodiments, the aforementioned diodes Dn', Dp, and Dn, as well as at least a portion of the semiconductor structure described above, are formed as follows. Figure 4A The ESD cell CELL2 is shown. It should be noted that in some other embodiments, the P+ doped region ( Figure 4B (Not shown in the diagram) It is located next to the region Dn'N+ in the P-well PW2. Each region in the P+ doped region is coupled to the voltage terminal VSS via the VSS metal interconnect layer CL3 disposed thereon.

[0083] Based on the above... Figure 4B The semiconductor structure discussed, such as the parasitic PNP transistor T3, is as follows: Figure 4B The diagram shows a typical configuration and coupling. For illustration, region DpP+ serves as the emitter of the parasitic PNP transistor T3 coupled to I / O pad 110, N-well NW1 serves as the base of the parasitic PNP transistor T3, and the P-type substrate PS serves as the collector of the parasitic PNP transistor T3. The parasitic PNP transistor T3, the P-type substrate PS, the P-well PW, and regions DnP+1 to DnP+p are configured as a PNP path P1 for shunting positive latch-up current to the voltage terminal VSS. For example, in some embodiments, during an ESD PS mode event, diode Dp and power clamping circuit 120 are turned on, and external latch-up holes caused by positive noise are injected into diode Dp at region DpP+. Subsequently, the latching hole flows through the parasitic PNP transistor T3, the P-type substrate PS, the P-well PW1, and regions VSSP+1 to VSSP+p to the voltage terminal VSS, which in some embodiments is coupled to ground voltage.

[0084] For reference Figure 4C . Figure 4C This is a layout diagram in a plan view of a semiconductor device 400 according to various embodiments. For illustration, the semiconductor device 400 includes a plurality of ESD cells CELL21 to CELL2m arrayed together. Each of the ESD cells CELL21 to CELL2m has a... Figure 4AThe ESD unit CELL2 in the illustrated embodiment has the same configuration. Figure 4C As shown, ESD cell CELL 22 is adjacent to ESD cell CELL 21, ESD cell CELL 23 is adjacent to ESD cell CELL 22, and so on. However, the scope of one embodiment of this disclosure is not intended to be limited to the aforementioned arrangement of multiple ESD cells, and other suitable arrangements of the array are within the scope of one embodiment of this disclosure. For example, the number of ESD cells included in the array may be modified as needed, depending on the current capability required by the semiconductor device 400.

[0085] Specifically Figure 4C The diagram illustrates that the semiconductor device 400 provides a plurality of ESD paths ESDP11 to ESDP1m and a plurality of ESD paths ESDP21 to ESDP2m provided by ESD cells CELL21 to CELL2m. In some embodiments, each of the ESD paths ESDP11 to ESDP1m has a... Figure 2A and Figure 2B The ESD path ESDP1 in the illustrated embodiment has the same configuration. Similarly, each of the ESD paths ESDP21 to ESDP2m has the same configuration as ESD path ESDP2. In other words, ESD paths ESDP11 to ESDP1m cooperate to discharge a portion of the ESD current IN between I / O pad 110 and voltage terminal VSS. ESD paths ESDP21 to ESDP2m cooperate to discharge another portion of the ESD current IN via the semiconductor structures included in diodes Dp1 to Dpm and diodes Dn'1 to Dn'm. Semiconductor device 400 also provides a plurality of PNP paths P11 to P1m (not shown for brevity). Figure 4C (as shown in the diagram), which work together to shunt the positive latch-up current to the voltage terminal VSS.

[0086] For reference Figure 4D . Figure 4D This is a layout diagram in a plan view of a semiconductor device 400 according to various embodiments. For illustration, the semiconductor device 400 includes arrayed ESD cells CELL11 to CELL1m and ESD cells CELL21 to CELL2m. Figure 4DAs shown, ESD cells CELL11 and CELL21 are adjacent. The same configuration of ESD cells CELL11 and CELL21 can be repeated many times. However, the scope of this embodiment is not intended to be limited to the aforementioned array arrangement, and other suitable array arrangements are within the scope of this embodiment. For example, depending on the current capability required by the semiconductor device 400, the number of multiple ESD cells CELL11 to CELL1m and multiple ESD cells CELL21 to CELL2m included in the array can be modified as needed.

[0087] Specifically Figure 4D The diagram illustrates that the semiconductor device 400 provides multiple ESD paths ESDP11 to ESDP1m and multiple ESD paths ESDP21 to ESDP2m in ESD cells CELL21 to CELL2m; multiple ESD paths ESDP11 to ESDP1m, multiple ESD paths ESDP21 to ESDP2m, and multiple ESD paths ESDP31 to ESDP3m in ESD cells CELL11 to CELL1m. In other words, the ESD paths ESDP11 to ESDP1m in ESD cells CELL11 to CELL1m and the ESD paths ESDP11 to ESDP1m in ESD cells CELL21 to CELL2m cooperate to discharge a portion of the ESD current IN between the I / O pad 110 and the voltage terminal VSS. The ESD paths ESDP21 to ESDP2m in ESD cells CELL11 to CELL1m and ESDP21 to ESDP2m in ESD cells CELL21 to CELL2m cooperate to discharge another portion of the ESD current IN through the semiconductor structure included in diodes Dp1 to Dpm and Dn'1 to Dn'm in the ESD cells CELL11 to CELL1m and ESD cells CELL21 to CELL2m. The ESD paths ESDP31 to ESDP3m in ESD cells CELL11 to CELL1m cooperate to discharge another portion of the ESD current IN from the anode to the voltage terminal VSS of diodes Dp1 to Dpm in the ESD cells CELL11 to CELL1m. Semiconductor device 400 also provides PNP paths P11 to P1m in ESD cells CELL21 to CELL2m (not shown in the diagram for brevity). Figure 4D (as shown in the diagram), which work together to shunt the positive latch-up current to the voltage terminal VSS.

[0088] The configurations of ESD cells CELL11 to CELL1m and ESD cells CELL21 to CELL2m are given for illustrative purposes. Various configurations of the above-described components are all within the scope of one embodiment of this disclosure. For example, in some embodiments, two adjacent ESD cells CELL11 to CELL1m are arranged next to three of the ESD cells CELL21 to CELL2m. In other words, in some embodiments, at least one of the plurality of ESD cells CELL11 to CELL1m and at least one of the plurality of ESD cells CELL21 to CELL2m are arranged in an array. The combination of ESD cells CELL11 to CELL1m and ESD cells CELL21 to CELL2m in the array can be modified according to the application.

[0089] In some embodiments, the semiconductor structures of diodes Dp and Dn are designed to be close to each other to further reduce the input parasitic capacitance of the semiconductor device in one embodiment of the present disclosure, but one embodiment of the present disclosure is not limited thereto.

[0090] For reference Figure 5A , Figure 5B and Figure 5C According to various embodiments, Figure 5A This is a layout diagram of a section of a semiconductor device 500 in a plan view, and Figure 5B and Figure 5C for Figure 5A A cross-sectional view of semiconductor device 500 along transverse section XX'. Regarding... Figure 2A and Figure 2B For ease of understanding, the embodiments are represented by the same element symbols. Figure 5A , Figure 5B and Figure 5C The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 5A , Figure 5B and Figure 5C The cooperative relationship of the components shown.

[0091] and Figure 2A and Figure 2B Compared to the embodiments shown, for the purpose of illustration, in Figure 5A and Figure 5B In the embodiment shown, a plurality of N+ doped regions DpN+1 to DpN+P (each having as shown) are arranged in the N-well NW1 along the direction of the transverse section XX'. Figure 5A(as shown in the strip configuration). Region DpN+1 serves as the cathode of diode Dp. Each of the N+ doped regions DpN+1 to DpN+P is coupled to the voltage terminal VDD via a VDD metal interconnect layer CL2 disposed thereon. In some embodiments, the aforementioned diodes Dn', Dp, and Dn, as well as at least a portion of the semiconductor structure described above, are formed as follows. Figure 5A The ESD unit CELL3 shown in the figure.

[0092] Based on the above... Figure 5C The semiconductor structure discussed, such as the parasitic NPN transistor T4, is as follows: Figure 5C The diagram shows a typical configuration and coupling. For illustration, region DnN+ serves as the emitter of the parasitic NPN transistor T4 coupled to I / O pad 110, P-well PW2 serves as the base of the parasitic transistor T4, and regions DpN+1 to DpN+p serve as the collector of the parasitic NPN transistor T4. The parasitic NPN transistor T4 forms an NPN path P2 for shunting negative latch-up current to the voltage terminal VDD. For example, in some embodiments, negative noise occurs at I / O pad 110, and external electrons are injected into diode Dn at region DnN+ (the arrows in the NPN path indicate the direction of the current, while the electrons flow in the opposite direction). Subsequently, the latch-up electrons flow through region DnN+, P-well PW2, and N-well NW2, and regions DpN+1 to DpN+p, to the voltage terminal VDD, which in some embodiments is coupled to ground.

[0093] For reference Figure 5D . Figure 5D This is a layout diagram in a plan view of a semiconductor device 500 according to various embodiments. For illustration, the semiconductor device 500 includes a plurality of ESD cells CELL31 to CELL3m arrayed together. Each of the ESD cells CELL31 to CELL3m has a... Figure 5A The ESD unit CELL3 in the illustrated embodiment has the same configuration. Figure 5D As shown, ESD cell CELL 32 is adjacent to ESD cell CELL 31, ESD cell CELL 33 is adjacent to ESD cell CELL 32, and so on. However, the scope of one embodiment of this disclosure is not intended to be limited to the aforementioned arrangement of multiple ESD cells, and other suitable arrangements of the array are within the scope of one embodiment of this disclosure. For example, the number of ESD cells included in the array may be modified as needed, depending on the current capability required by the semiconductor device 500.

[0094] Specifically Figure 5DThe diagram illustrates that the semiconductor device 500 provides a plurality of ESD paths ESDP11 to ESDP1m and a plurality of ESD paths ESDP21 to ESDP2m provided by ESD cells CELL31 to CELL3m. In some embodiments, each of the ESD paths ESDP11 to ESDP1m has a... Figure 2A and Figure 2B The ESD path ESDP1 in the illustrated embodiment has the same configuration. Similarly, each of the ESD paths ESDP21 to ESDP2m has the same configuration as ESD path ESDP2. In other words, ESD paths ESDP11 to ESDP1m cooperate to discharge a portion of the ESD current IN between I / O pad 110 and voltage terminal VSS. ESD paths ESDP21 to ESDP2m cooperate to discharge another portion of the ESD current IN via the semiconductor structures included in diodes Dp1 to Dpm and diodes Dn'1 to Dn'm. Semiconductor device 500 also provides a plurality of NPN paths P21 to P2m (not shown for brevity). Figure 5D (As shown in the diagram), they work together to shunt the negative latch-up current to the voltage terminal VDD.

[0095] For reference Figure 5E . Figure 5E This is a layout diagram in a plan view of a semiconductor device 500 according to various embodiments. For illustration, the semiconductor device 500 includes an array of multiple ESD cells CELL31 to CELL3m and multiple ESD cells CELL11 to CELL1m. Figure 5E As shown, ESD cells CELL11 and CELL31 are adjacent. The same configuration of ESD cells CELL11 and CELL31 can be repeated many times. However, the scope of this embodiment is not intended to be limited to the aforementioned array arrangement, and other suitable array arrangements are within the scope of this embodiment. For example, depending on the current capability required by the semiconductor device 500, the number of multiple ESD cells CELL11 to CELL1m and multiple ESD cells CELL31 to CELL3m included in the array can be modified as needed.

[0096] Specifically Figure 5EThe diagram illustrates that the semiconductor device 500 provides multiple ESD paths ESDP11 to ESDP1m and multiple ESD paths ESDP21 to ESDP2m in ESD cells CELL31 to CELL3m; and multiple ESD paths ESDP11 to ESDP1m, multiple ESD paths ESDP21 to ESDP2m and multiple ESD paths ESDP31 to ESDP3m in ESD cells CELL11 to CELL1m. In other words, the ESD paths ESDP11 to ESDP1m in ESD cells CELL31 to CELL3m and the ESD paths ESDP11 to ESDP1m in ESD cells CELL11 to CELL1m cooperate to discharge a portion of the ESD current IN between the I / O pad 110 and the voltage terminal VSS. The ESD paths ESDP21 to ESDP2m in ESD cells CELL31 to CELL3m and the ESD paths ESDP21 to ESDP2m in ESD cells CELL11 to CELL1m cooperate to discharge another portion of the ESD current IN through the semiconductor structure included in the diodes Dp1 to Dpm and Dn'1 to Dn'm in ESD cells CELL31 to CELL3m and ESD cells CELL11 to CELL1m. The ESD paths ESDP31 to ESDP3m in ESD cells CELL11 to CELL1m cooperate to discharge another portion of the ESD current IN from the anode to the voltage terminal VSS of the diodes Dp1 to Dpm in ESD cells CELL11 to CELL1m. Semiconductor device 500 also provides NPN paths P21 to P2m in ESD cells CELL31 to CELL3m (not shown in the diagram for brevity). Figure 5E (As shown in the diagram), they work together to shunt the negative latch-up current to the voltage terminal VSS.

[0097] The configurations of ESD units CELL11 to CELL1m and ESD units CELL31 to CELL3m are given for illustrative purposes. Various configurations of the above-described components are all within the scope of one embodiment of this disclosure. For example, in some embodiments, ESD units CELL31 to CELL3m are formed together with ESD units CELL21 to CELL2m in the semiconductor device 500.

[0098] For reference Figure 6 . Figure 6 This is an equivalent circuit diagram of a portion of a semiconductor device 600 according to various embodiments. Regarding... Figure 1 For ease of understanding, the embodiments are represented by the same element symbols. Figure 6The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 6 The cooperative relationship of the components shown.

[0099] and Figure 1 In comparison, such as Figure 6 As shown, semiconductor device 600 does not include diode Dn'. Semiconductor device 600 includes diode Dp'. The anode and cathode of diode Dp' are used to receive supply voltage VDD. In some embodiments, supply voltage VDD is ground voltage.

[0100] Continue to refer to Figure 6 During an ESD negative-to-VDD (hereinafter referred to as "ND mode") or negative electrostatic discharge event, a large amount of negative potential is instantaneously established at I / O pad 110. Diode Dn and power clamping circuit 120 are turned on to further trigger the established SCR circuit (including diodes Dn and Dp'). To illustrate, multiple ESD paths are conducted in semiconductor device 600 (including, for example, such as...). Figure 6 As shown in ESDP1 and ESDP2, this is used to discharge the ESD current IN. Specifically, as... Figure 6 As shown, a portion of the ESD current IN flows between I / O pad 110 and voltage terminal VDD, and is directed through ESD path ESDP1, which is formed by diode Dn, resistor R, and power supply clamping circuit 120. Another portion of the ESD current IN flows between I / O pad 110 and voltage terminal VDD, and is directed through ESD path ESDP2, where diodes Dn and Dp' include semiconductor structures for partially discharging the ESD current IN. Details of the semiconductor structures included in diodes Dp' and Dn are discussed below.

[0101] To further understand Figure 6 The structure of the semiconductor device 600 shown in the embodiments is now referred to Figure 7A and Figure 7B . Figure 7A According to some embodiments, in Figure 6 The layout diagram of a section of the semiconductor device 600 in the plan view. Figure 7B According to various embodiments, in Figure 7A The layout of the semiconductor device is shown in a cross-sectional view along the transverse section XX'. Regarding... Figure 2A and Figure 2B For ease of understanding, the embodiments are represented by the same element symbols. Figure 7A and Figure 7BThe same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 7A and Figure 7B The cooperative relationship of the components shown.

[0102] and Figure 2A and Figure 2B Compared with the embodiments in, such as Figure 7A and Figure 7B As shown, the semiconductor device 600 further includes an N-well NW2 and a diode Dp' disposed next to a P-well PW2 on a P-type substrate PS, wherein a VDD metal interconnect layer CL2 is further disposed on the diode Dp'. Figure 7A In the illustrated embodiment, N-well NW1, N-well NW2, P-well PW2, diodes Dp, Dp', and Dn, and at least a portion of the semiconductor structure as described above, are used to form an ESD cell CELL4, as shown. Figure 7A As shown in the illustration. However, the scope of this disclosure is not limited to this type of ESD unit, and other suitable types of ESD units are also covered by this disclosure. For example, depending on the current capability required by the semiconductor device 600, the width and length of the doped regions, the spacing between the doped regions, and the arrangement of the interconnect layers can be modified as needed. For simplicity of explanation, Figure 7B The diagram does not show the I / O pad metal connection layer CL1, VDD metal connection layer CL2, and VSS metal connection layer CL3.

[0103] and Figure 2B Compared with the embodiments in the example, for the purpose of illustration, as shown Figure 7B As shown, diode Dp' includes a P+ doped region Dp'P+ and an N+ doped region Dp'N+ formed in an N-well NW1. Region Dp'P+ serves as the anode of diode Dp'. Region Dp'N+ serves as the cathode of diode Dp'. Regions Dp'P+ and Dp'N+ are coupled to a voltage terminal VDD to receive a supply voltage VDD.

[0104] Based on the above... Figure 7B The semiconductor structure, including parasitic PNP transistor T5, parasitic NPN transistor T6, and parasitic resistors R1, R2, and R3, is as follows: Figure 7B The circuit is typically formed and coupled as shown. In some embodiments, parasitic transistors T5 and T6, along with parasitic resistors R1, R2, and R3, together form an equivalent silicon controlled rectifier (SCR) circuit. This is provided for illustrative purposes. Figure 7B The equivalent SCR circuit shown is illustrated. Various equivalent SCR circuits are covered by one embodiment of this disclosure. For example, in various embodiments, at least one of the parasitic resistances R1, R2, or R3 is omitted.

[0105] Parasitic PNP transistor T5 includes a P+ doped region Dp'P+ as the emitter, an N-well NW1 as the base, and a P-type substrate PS as the collector. The base of PNP transistor T5 is coupled to the N+ doped region Dp'N+ via parasitic resistor R1. The collector of PNP transistor T5 is coupled to the P+ region DnP+ via parasitic resistors R2 and R3. Parasitic NPN transistor T6 includes an N-well NW1 as the collector, a P-well PW2 as the base, and an N+ doped region DnN+ as the emitter. The collector of NPN transistor T6 is coupled to the base of PNP transistor T5. The base of NPN transistor T6 is coupled to the P+ doped region DnP+ via parasitic resistors R2 and R3.

[0106] Continue to refer to Figure 7B For illustration, the semiconductor structures included in diodes Dp' and Dn are used as ESD path ESD path ESD path ESDP2 (as well as...). Figure 6 As shown in the diagram, it is used as the SCR circuit as described above. In other words, the regions Dp'P+, N-well NW1, P-type substrate PS, P-well PW2 of diode Dp', and the regions DnN+ and DnP+ of diode Dn are used as the SCR circuit. For example, in some embodiments, a portion of the ESD current IN from the voltage terminal VDD flows through the regions Dp'N+ and Dp'P+, N-well NW1, P-type substrate PS, P-well PW2, and region DnN+ of diode Dp', and flows to I / O pad 110 (the arrow of ESD path ESDP2 indicates the direction of ESD current IN, while electrons flow in the opposite direction).

[0107] During operation, during ESD ND mode events, Figure 6 The diode Dn and the power clamping circuit 120 are turned on to further trigger... Figure 7B The SCR circuit. Specifically, as shown... Figure 7B As shown, at least a portion of the ESD current IN flows from the voltage terminal VSS through... Figure 6 The ESD path ESDP1 leads to I / O pad 110. This ESD path ESDP1 includes region DnP+ of diode Dn, P-well PW2, and region DnN+ of diode Dn. Furthermore, parasitic PNP transistor T5 and parasitic NPN transistor T6 are turned on during ND mode. Therefore, another portion of the ESD current IN flows from the voltage terminal VDD through ESD path ESDP2 (including parasitic resistor R1, parasitic PNP transistor T5, parasitic resistor R2, and parasitic NPN transistor T6) to I / O pad 110 (the arrow in ESD path ESDP2 indicates the direction of the ESD current IN, while electrons flow in the opposite direction).

[0108] In some embodiments, the semiconductor device 600 further includes VDDP+ and VDDN+ formed in the N-well NW2, such as Figure 7B As shown in the diagram. For illustration, region VDDP+ is doped with a p-type dopant as described above. In some embodiments, the ESD path ESDP3 is also conducted through the semiconductor structure including region VDDP+ in the N-well NW2. In various embodiments, the ESD path ESDP3 also implements another equivalent SCR circuit; for simplicity of explanation, Figure 7B This other equivalent SCR circuit is not shown in the diagram. Another portion of the ESD current IN flows from the voltage terminal VDD through the ESD path ESDP3 (including the region VDDP+ and the region DnN+ of diode Dn) to I / O pad 110.

[0109] For illustrative purposes, the following is given: Figure 7A and Figure 7B The above configuration. Figure 7A and Figure 7B The various configurations of the elements mentioned herein are within the scope of one embodiment of this disclosure. For example, in various embodiments, the semiconductor structure including the N-well NW2 and regions VDDP+ and VDDN+ is omitted.

[0110] For reference Figure 8A . Figure 8A This is an equivalent circuit diagram of a portion of a semiconductor device 800 according to various embodiments. Regarding... Figure 3A and Figure 6 For ease of understanding, the embodiments are represented by the same element symbols. Figure 8A The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 8A The cooperative relationship of the components shown.

[0111] and Figure 3A and Figure 6 Compared to the embodiments shown, Figure 8AThe semiconductor device 800 in the illustrated embodiment further includes a plurality of diodes Dp'1 to Dp'm coupled in parallel to the voltage terminal VDD, but excludes a plurality of diodes Dn'1 to Dn'm. Each of diodes Dp'1 to Dp'm is equivalent to diode Dp'. Furthermore, in some embodiments, the number of diodes Dp1 to Dpm, diodes Dn1 to Dnm, and diodes Dp'1 to Dp'm are different from each other. In other words, in some embodiments, the semiconductor device 800 includes at least one diode among diodes Dp2 to Dpm coupled to diode Dp1, at least one diode among diodes Dn2 to Dnm coupled to diode Dn1, and at least one diode among diodes Dp'2 to Dp'm coupled to diode Dp'1.

[0112] For reference Figure 8B . Figure 8B According to some embodiments, in Figure 8A The semiconductor device 800 is shown in a plan view of a section. For illustration, the semiconductor device 800 includes a plurality of ESD cells CELL41 to CELL4m arranged in an array. Each of the plurality of ESD cells CELL41 to CELL4m has a [missing information - likely related to a specific feature or characteristic]. Figure 7A The ESD unit CELL4 in the illustrated embodiment has the same configuration. For example... Figure 8B As shown, ESD cell CELL42 is adjacent to ESD cell CELL41, ESD cell CELL43 is adjacent to ESD cell CELL42, and so on. However, the scope of one embodiment of this disclosure is not intended to be limited to the aforementioned arrangement of multiple ESD cells in an array, and other suitable arrangements of multiple ESD cells are within the scope of one embodiment of this disclosure. For example, the number of ESD cells included in the array can be modified as needed, depending on the current capability required by the semiconductor device 800.

[0113] Specifically Figure 8B The diagram illustrates that the semiconductor device 800 provides multiple ESD paths ESDP11 to ESDP1m, multiple ESD paths ESDP21 to ESDP2m, and multiple ESD paths ESDP31 to ESDP3m provided by ESD units CELL41 to CELL4m. In some embodiments, each of the ESD paths ESDP11 to ESDP1m has a... Figure 7A and Figure 7BThe ESD path ESDP1 in the illustrated embodiment has the same configuration. Similarly, each of the ESD paths ESDP21 to ESDP2m has the same configuration as ESD path ESDP2, and each of the ESD paths ESDP31 to ESDP3m has the same configuration as ESD path ESDP3. In other words, ESD paths ESDP11 to ESDP1m cooperate to discharge a portion of the ESD current IN between I / O pad 110 and voltage terminal VDD. ESD paths ESDP21 to ESDP2m cooperate to discharge another portion of the ESD current IN via the semiconductor structures included in diodes Dn1 to Dnm and diodes Dp'1 to Dp'm. ESD paths ESDP31 to ESDP3m cooperate to discharge another portion of the ESD current IN from voltage terminal VDD to the anode of diodes Dn1 to Dnm.

[0114] For illustrative purposes, the configuration of diodes Dp1 to Dpm, Dn1 to Dnm, and Dp'1 to Dp'm, and ESD cells CELL41 to CELL4m are given. Various configurations of the above components are all within the scope of one embodiment of this disclosure. For example, in various embodiments, the ESD cells CELL41 to CELL4m are arranged in a column or matrix, rather than as shown in the example. Figure 8B The arrangement shown is in rows.

[0115] For reference Figure 9A and Figure 9B . Figure 9A According to some embodiments, in Figure 6 The layout diagram of a section of the semiconductor device 600 in the plan view, which has another arrangement of doped regions. Figure 9B According to various embodiments, in Figure 9A The layout of semiconductor device 600 is shown in the cross-sectional view along the transverse section XX'. Regarding... Figure 7A and Figure 7B For ease of understanding, the embodiments are represented by the same element symbols. Figure 9A and Figure 9B The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 9A and Figure 9B The cooperative relationship of the components shown.

[0116] and Figure 7A and Figure 7B Compared to the embodiments shown, for the purpose of illustration, in Figure 9A and Figure 9B In the embodiment shown, a plurality of N+ doped regions Dp'N+1 ​​to Dp'N+p (each having as shown) are arranged in the N-well NW1 along the direction of the transverse section XX'. Figure 9A (As shown in the strip configuration). Region Dp'N+1 ​​serves as the cathode of diode Dp'. Each of the N+ doped regions Dp'N+1 ​​to Dp'N+p is coupled to the voltage terminal VDD via a VDD metal interconnect layer CL2 disposed thereon. In some embodiments, the aforementioned diodes Dp', Dp, and Dn, and at least a portion of the semiconductor structure described above, are formed as follows. Figure 7A The ESD cell CELL5 is shown. It should be noted that in some embodiments, a plurality of N+ doped regions VDDN+1 to VDDN+p are disposed in the N-well NW2 adjacent to the region VDDP+. Each of the N+ doped regions VDDN+1 to VDDN+p is coupled to the voltage terminal VDD via a VDD metal interconnect layer CL2 disposed thereon.

[0117] Based on the above... Figure 9B The semiconductor structure discussed includes parasitic transistors T7 and T8, as follows: Figure 9B The configuration shown is generally formed and coupled. For illustration, region DnN+ serves as the emitter of parasitic transistors T7 and T8, which are coupled to I / O pad 110. P-well PW2 serves as the base of parasitic transistors T7 and T8. Multiple regions Dp'N+1 ​​to Dp'N+p serve as the collector of transistor T7. Multiple regions VDDN+1 to VDDN+p serve as the collector of transistor T8. The bases of parasitic transistors T7 and T8 are coupled to voltage terminal VSS via region DnP+.

[0118] For illustration, parasitic transistors T7 and T8 are used to form an NPN path P3 for shunting negative latch-up current to the voltage terminal VDD. For example, in some embodiments, negative noise occurs at I / O pad 110, and external electrons are injected into diode Dn at region DnN+ (the arrows in the NPN path indicate the direction of the current, while the electrons flow in the opposite direction). Subsequently, latch-up electrons flow from region DnN+, P-well PW2 and N-wells NW1 and NW2, regions Dp'N+1 ​​to Dp'N+p, and multiple regions VDDN+1 to VDDN+p through NPN path P3 to the voltage terminal VDD, which in some embodiments is coupled to ground.

[0119] For reference Figure 9C and Figure 9D . Figure 9C and Figure 9D According to some embodiments, in Figure 9A The semiconductor device 600 is shown in a plan view. For illustration, the semiconductor device 600 includes an array of multiple ESD cells CELL51 to CELL5m. Each of the ESD cells CELL51 to CELL5m has a... Figure 9AThe ESD unit CELL5 in the illustrated embodiment has the same configuration. Figure 9C As shown, one of the ESD cells CELL51 to CELL5m is positioned adjacent to another of the ESD cells CELL51 to CELL5m. However, the scope of this embodiment is not intended to be limited to the aforementioned arrangement of the array, and other suitable arrangements of the array are within the scope of this embodiment. For example, the number of ESD cells included in the array may be modified as needed, depending on the current capability required by the semiconductor device 600.

[0120] Continue to refer to Figure 9C The semiconductor device 600 provides a plurality of ESD paths ESDP11 to ESDP1m, a plurality of ESD paths ESDP21 to ESDP2m, and a plurality of ESD paths ESDP31 to ESDP3m provided by ESD units CELL51 to CELL5m. In some embodiments, each of the ESD paths ESDP11 to ESDP1m has a... Figure 7A and Figure 7B The ESD path ESDP1 in the illustrated embodiment has the same configuration. Similarly, each of the ESD paths ESDP21 to ESDP2m has the same configuration as ESD path ESDP2, and each of the ESD paths ESDP31 to ESDP3m has the same configuration as ESD path ESDP3. In other words, ESD paths ESDP11 to ESDP1m cooperate to discharge a portion of the ESD current IN between I / O pad 110 and voltage terminal VDD. ESD paths ESDP21 to ESDP2m cooperate to discharge another portion of the ESD current IN via the semiconductor structures included in diodes Dn1 to Dnm and diodes Dp'1 to Dp'm. ESD paths ESDP31 to ESDP3m cooperate to discharge another portion of the ESD current IN from the anode of diodes Dn1 to Dnm to voltage terminal VDD. Semiconductor device 600 also provides a plurality of NPN paths P31 to P3m (not shown for brevity). Figure 9C (As shown in the diagram), they work together to shunt the negative latch-up current to the voltage terminal VDD.

[0121] Provided for illustrative purposes Figures 9A to 9C The configuration of the above-mentioned components is within the scope of one embodiment of this disclosure.

[0122] For reference Figure 9D . Figure 9DThis is a layout diagram in a plan view of a semiconductor device 600 according to various embodiments. For illustration, the semiconductor device 600 includes an array of ESD cells CELL41 to CELL4m and ESD cells CELL51 to CELL5m. Figure 9D As shown, ESD cells CELL41 and CELL51 are adjacent. The same configuration of ESD cells CELL41 and CELL51 can be repeated many times. However, the scope of this embodiment is not intended to be limited to the aforementioned array arrangement, and other suitable types of array arrangements are within the scope of this embodiment. For example, depending on the current capability required by the semiconductor device 600, the number of multiple ESD cells CELL41 to CELL4m and multiple ESD cells CELL51 to CELL5m included in the array can be modified as needed.

[0123] Specifically Figure 9DThe diagram illustrates that semiconductor device 600 provides ESD paths ESDP11 to ESDP1m, ESDP21 to ESDP2m, and ESDP31 to ESDP3m in ESD cells CELL41 to CELL4m; and ESD paths ESDP11 to ESDP1m, ESDP21 to ESDP2m, and multiple ESD paths ESDP31 to ESDP3m in ESD cells CELL51 to CELL5m. In other words, the ESD paths ESDP11 to ESDP1m in ESD cells CELL41 to CELL4m and the ESD paths ESDP11 to ESDP1m in ESD cells CELL51 to CELL5m cooperate to discharge a portion of the ESD current IN between I / O pad 110 and voltage terminal VSS. The ESD paths ESDP21 to ESDP2m in ESD cells CELL41 to CELL4m and ESDP21 to ESDP2m in ESD cells CELL51 to CELL5m cooperate to discharge another portion of the ESD current IN through the semiconductor structure included in diodes Dn1 to Dnm and Dp'1 to Dp'm in ESD cells CELL41 to CELL4m and ESD cells CELL51 to CELL5m. The ESD paths ESDP31 to ESDP3m in ESD cells CELL41 to CELL4m and ESD paths ESDP31 to ESDP3m in ESD cells CELL51 to CELL5m cooperate to discharge another portion of the ESD current IN from the cathode to the voltage terminal VDD of diodes Dn1 to Dn'm in ESD cells CELL41 to CELL4m and ESD cells CELL51 to CELL5m. Semiconductor device 600 also provides multiple NPN paths P31 to P3m in ESD cells CELL51 to CELL5m (not listed for brevity) Figure 9D (As shown in the diagram), they work together to shunt the negative latch-up current to the voltage terminal VDD.

[0124] The configurations of ESD units CELL41 to CELL4m and ESD units CELL51 to CELL5m are given for illustrative purposes. Various configurations of the above components are all within the scope of one embodiment of this disclosure.

[0125] For reference Figure 10 . Figure 10 This is an equivalent circuit diagram of a portion of a semiconductor device 1000 according to various embodiments. Regarding... Figure 1 and Figure 6 For ease of understanding, the embodiments are represented by the same element symbols. Figure 10The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 10 The cooperative relationship of the components shown.

[0126] and Figure 1 and Figure 6 Compared to the embodiments shown, such as Figure 10 As shown, the semiconductor device 1000 includes both diodes Dp' and Dn'. The anode and cathode of diode Dp' are coupled to voltage terminal VDD. The anode and cathode of diode Dn' are coupled to voltage terminal VSS. The cooperative relationship between diodes Dp' and Dn' will be discussed in detail below.

[0127] For reference Figure 11A . Figure 11A According to various embodiments, in Figure 10 A schematic diagram of the operation of the equivalent circuit in [the diagram]. Regarding... Figure 11A For ease of understanding, the embodiments are represented by the same element symbols. Figure 1 The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 11A The cooperative relationship of the components shown.

[0128] To illustrate, during the ESD PS mode event at I / O pad 110, and Figure 1 Compared to the embodiments shown, multiple ESD paths are enabled in the semiconductor device 1000, including (for example) such as Figure 11A The diagram shows the ESD path ESDP4 between voltage terminals VDD and VSS. Alternatively, a portion of the ESD current IN between I / O pad 110 and voltage terminal VSS can be discharged via ESD path ESDP4. Specifically, diodes Dp' and Dn' include a semiconductor structure designed to guide a portion of the ESD current IN from voltage terminal VDD to voltage terminal VSS when the voltage level of I / O pad 110 is highest, the supply voltage VDD is higher than the supply voltage VSS, and voltage terminal VSS is coupled to ground.

[0129] To further understand Figure 11A The structure of the semiconductor device 1000 shown in the embodiments is now referred to Figure 11B and Figure 11C . Figure 11B According to some embodiments, in Figure 11A The layout diagram of a section of the semiconductor device 1000 in the plan view. Figure 11C for Figure 11BThe layout diagram of semiconductor device 1000 is shown as a cross-sectional view along the transverse section XX'. Regarding... Figure 2A and Figure 2B For ease of understanding, the embodiments are represented by the same element symbols. Figure 11A and Figure 11B The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 11B and Figure 11C The cooperative relationship of the components shown.

[0130] and Figure 2A and Figure 2B Compared to the embodiments shown, such as Figure 11B and Figure 11C As shown, the semiconductor device 1000 further includes an N-well NW3 adjacent to the P-well PW2, and an N-well NW3 disposed on a P-type substrate PS (such as...). Figure 11C As shown in the diagram, the N-well NW3 is adjacent to the P-well PW3. The regions Dp'N+ and Dp'P+ of diode Dp' are located within the N-well NW3. The regions DnN+ and DnP+ of diode Dn are located within the P-well PW3, not within the P-well PW2. Figure 11B In the illustrated embodiment, N-wells NW1, NW2, and NW3, P-wells PW1, PW2, and PW3, diodes Dp, Dp', Dn, and Dn', and at least a portion of the semiconductor structure as described above are used to form an ESD cell CELL6, as shown. Figure 11B As shown in the image. For the sake of simplicity, Figure 11C The I / O pad metal interconnect layer CL1, VDD metal interconnect layer CL2, and VSS metal interconnect layer CL3 are not illustrated. However, the scope of this embodiment is not limited to this type of ESD unit, and other suitable types of ESD units are covered by this embodiment. For example, depending on the current capability required by the semiconductor device 1000, the width and length of the doped regions, the spacing between the doped regions, and the arrangement of the interconnect layers can be modified as needed.

[0131] To illustrate, such as Figure 11C As shown, region Dp'N+ of diode Dp' serves as the cathode of diode Dp'. Region Dp'P+ of diode Dp' serves as the anode of diode Dp'. Regions Dp'P+ and Dp'N+ are coupled to the voltage terminal VDD to receive the supply voltage VDD. Region DnN+ of diode Dn serves as the cathode of diode Dn and is coupled to I / O pad 110. Region DnP+ of diode Dn serves as the anode of diode Dn and is coupled to the voltage terminal VSS.

[0132] Based on the above... Figure 11CThe semiconductor structure, including the parasitic PNP transistor T9, the parasitic NPN transistor T10, and the parasitic resistor R4, is further described as follows: Figure 11C The circuit shown is generally formed and coupled. In some embodiments, the parasitic PNP transistor T9, the parasitic NPN transistor T10, and the parasitic resistor R4 together form an equivalent silicon controlled rectifier (SCR) circuit. This is given for illustrative purposes. Figure 11C The equivalent SCR circuit shown is illustrated. Various equivalent SCR circuits are covered by one embodiment of this disclosure. For example, in various embodiments, the parasitic resistance R4 is omitted.

[0133] Parasitic PNP transistor T9 includes an emitter region Dp'P+, an N-well NW3 as the base, and a P-type substrate PS as the collector. The collector of parasitic PNP transistor T9 is coupled to the base of parasitic NPN transistor T10 via parasitic resistor R4. Parasitic NPN transistor T10 includes an N-well NW3 as the collector, a P-well PW2 as the base, and an emitter region Dn'N+. The collector of parasitic NPN transistor T10 is coupled to the base of parasitic PNP transistor T9.

[0134] Continue to refer to Figure 11C For illustration, region Dp'P+, N-well NW3, P-type substrate PS, P-well PW2, and region Dn'N+ of diode Dp' are used as the ESD path ESDP4 between voltage terminals VSS and VDD. Figure 2A and Figure 2B Compared to the embodiments shown, in Figure 11C In the embodiment shown, during the ESD PS mode event, Figure 11A The diode Dp and power clamping circuit 120 are turned on to further trigger the ESD path ESDP4. Alternatively, besides a portion of the ESD current IN discharging through ESD paths ESDP1, ESDP2, and ESDP3, another portion of the ESD current IN flows from the voltage terminal VDD through the ESD path ESDP4 (including the parasitic PNP transistor T9, parasitic resistor R4, and parasitic NPN transistor T10) to the voltage terminal VSS. Figures 11A to 11C The configuration shown in the diagram, in addition to ESD paths ESDP1, ESDP2, and ESDP3, also provides a bidirectional SCR circuit. During an ESD PS mode event, a portion of the ESD current IN is further shunt to ground via ESD path ESDP4.

[0135] For reference Figure 12A , Figure 12B and Figure 12C . Figure 12A According to various embodiments, in Figure 10 A schematic diagram of another operation of the equivalent circuit in the diagram. Figure 12B According to some embodiments, in Figure 12A The layout diagram of a section of the semiconductor device 1000 in the plan view. Figure 12C for Figure 12B The layout diagram of semiconductor device 1000 is shown as a cross-sectional view along the transverse section XX'. Regarding... Figure 11A , Figure 11B and Figure 11C For ease of understanding, the embodiments are represented by the same element symbols. Figure 12A , Figure 12B and Figure 12C The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 12A , Figure 12B and Figure 12C The cooperative relationship of the components shown.

[0136] To illustrate, during an ESD ND mode event at I / O pad 110, the ESD path ESDP4 between the on-voltage terminals VDD and VSS in semiconductor device 1000 is described. Specifically... Figure 12A The description states that diode Dn and power clamping circuit 120 are turned on, further triggering ESD path ESDP4. Alternatively, besides a portion of the ESD current IN discharging via ESD paths ESDP1, ESDP2, and ESDP3, another portion of the ESD current IN flows from voltage terminal VDD through ESD path ESDP4 (including parasitic PNP transistor T9, parasitic resistor R4, and parasitic NPN transistor T10) to voltage terminal VSS (the arrow in ESD path ESDP4 indicates the direction of current, while electrons flow in the opposite direction). Figures 12A to 12C The configuration shown in the diagram, in addition to ESD paths ESDP1, ESDP2, and ESDP3, also provides a bidirectional SCR circuit. During an ESD ND mode event, a portion of the ESD current IN is further shunt to ground via ESD path ESDP4.

[0137] For reference Figure 13A and Figure 13B . Figure 13A The equivalent circuit for a portion of the semiconductor device 1300. Figure 13B According to some embodiments Figure 13A The layout diagram of a section of the semiconductor device 1300 in the plan view. Regarding... Figure 3A , Figure 3B , Figure 8A , Figure 8B , Figure 10 and Figure 11B For ease of understanding, the embodiments are represented by the same element symbols. Figure 13A and Figure 13B The same components. For the sake of brevity, specific operations of similar components that have been discussed in detail in the preceding paragraphs are omitted here unless it is necessary to introduce them. Figure 13A and Figure 13B The cooperative relationship of the components shown.

[0138] and Figure 10 Compared to the embodiments shown, Figure 13A The semiconductor device 1300 in the illustrated embodiment includes diodes Dp1 to Dpm coupled in parallel between I / O pad 110 and voltage terminal VDD, diodes Dn1 to Dnm coupled in parallel between I / O pad 110 and voltage terminal VSS, diodes Dn'1 to Dn'm coupled in parallel to voltage terminal VSS, and diodes Dp'1 to Dp'm coupled in parallel to voltage terminal VDD. Furthermore, in some embodiments, the number of diodes Dp1 to Dpm, diodes Dn1 to Dnm, diodes Dn'1 to Dn'm, and diodes Dp'1 to Dp'm are different from each other. In other words, in some embodiments, the semiconductor device 1300 includes at least one diode among diodes Dp2 to Dpm coupled to Dp1, at least one diode among diodes Dn2 to Dnm coupled to Dn1, at least one diode among diodes Dn'2 to Dn'm coupled to Dn'1, and at least one diode among diodes Dp'2 to Dp'm coupled to Dp'1.

[0139] For reference Figure 13B . Figure 13B According to various embodiments, in Figure 13A The semiconductor device 1300 is shown in a plan view of a section. For illustration, the semiconductor device 1300 includes a plurality of ESD cells CELL61 to CELL6m arranged in an array. Each of the ESD cells CELL61 to CELL6m has a... Figure 11B The ESD unit CELL6 in the illustrated embodiment has the same configuration. For example... Figure 13B As shown, ESD cell CELL 62 is adjacent to ESD cell CELL 61, and so on. However, the scope of one embodiment of this disclosure is not intended to be limited to the aforementioned arrangement of multiple ESD cells in an array, and other suitable arrangements of multiple ESD cells are within the scope of one embodiment of this disclosure. For example, the number of ESD cells included in the array may be modified as needed depending on the current capability required by the semiconductor device 1300. For the sake of brevity, [details omitted]. Figure 13A and Figure 13B The specific operation of similar elements in the embodiments has been described. Figures 11A to 11C and Figures 12A to 12C This is discussed in detail in the text.

[0140] For reference Figure 14 . Figure 14 This is a flowchart of a method 1400 for operating semiconductor devices 100, 300, 400, 500, 800, 1000 and 1300 according to various embodiments.

[0141] Will Figure 11A , Figure 11B and Figure 11C The embodiments illustrated herein are used as examples to illustrate method 1400. In step 1401, in some embodiments, during an ESD PS mode event, the ESD path ESDP1 between I / O pad 110 and voltage terminal VSS is turned on, the voltage terminal VSS being used to receive the supply voltage VSS. In the ESD path ESDP1, diode Dp is coupled between I / O pad 110 and voltage terminal VDD to receive the supply voltage VDD, and power clamping circuit 120 is coupled between voltage terminals VDD and VSS.

[0142] In step 1402, the ESD path ESDP2 between I / O pad 110 and voltage terminal VSS is turned on. In ESD path ESDP2, diode Dp and diode Dn' having two terminals coupled to voltage terminal VSS comprise a semiconductor structure. This semiconductor structure is used as an equivalent silicon controlled rectifier (SCR) circuit.

[0143] In some embodiments, method 1400 further includes an ESD path ESDP4 between the voltage terminals VDD and VSS. In the ESD path ESDP4, diode Dn' and diode Dp' having two terminals coupled to the voltage terminal VDD comprise another semiconductor structure. This other semiconductor structure serves as another SCR circuit.

[0144] In some embodiments, method 1400 further includes forming a diode Dn on one side of diode Dp. Diode Dn includes a P-well PW3, an N+ doped region DnN+ coupled to I / O pad 110, and at least one P+ doped region DnP+ coupled to voltage terminal VSS. Furthermore, in some embodiments, forming diode Dn further includes forming a plurality of P+ doped regions DnP+1 to DnP+N. Each of the plurality of P+ doped regions DnP+1 to DnP+N has a strip configuration in a planar view, and the plurality of P+ doped regions DnP+1 to DnP+N are as follows: Figure 4B The embodiments shown are generally arranged along the direction of the transverse section XX'.

[0145] In some embodiments, closer spacing between two doped regions of a semiconductor structure including diodes Dp and Dn', diodes Dn and Dp', or diodes Dp' and Dn' results in a better ability to shunt the ESD current IN to ground, wherein the semiconductor structure serves as an SCR circuit. For example, such as Figure 2B As shown, the closer the spacing between the region DpP+ of diode Dp and the region Dn'N+ of diode Dn', the higher the effectiveness of the SCR circuit included in diodes Dp and Dn'.

[0146] In some methods, semiconductor devices as described above include power supply clamping circuitry for providing ESD protection to internal circuitry. However, in semiconductor structures without dummy diodes (such as diodes Dn' and Dp' provided in one embodiment of this disclosure), internal circuitry can experience high voltage drops when ESD current flows through pull-up diodes, metal wiring, and power supply clamping circuitry.

[0147] Compared to the methods described above, one embodiment of this disclosure provides a semiconductor device including at least one newly created SCR circuit to discharge ESD current from the I / O pad to ground, further reducing voltage drop across internal circuitry. Therefore, compared to previous methods, the semiconductor device provided in one embodiment of this disclosure allows for greater ESD robustness of integrated circuit elements. Furthermore, lower parasitic capacitance from the I / O pad is achieved for use in high-speed applications.

[0148] The above description includes exemplary operations, but these operations may not be performed in the order shown. Operations may be appropriately added, replaced, reordered, and / or eliminated according to the spirit and scope of various embodiments of one embodiment of this disclosure.

[0149] In some embodiments, a semiconductor device is disclosed, comprising a first diode, a second diode, a clamping circuit, and a third diode. A first terminal of the first diode is coupled to a first voltage terminal for receiving a first supply voltage. A first terminal, an input / output (I / O) pad, and a second terminal of the first diode of the second diode are coupled to each other, and a second terminal of the second diode is coupled to a second voltage terminal for receiving a second supply voltage. The clamping circuit is coupled between the first and second voltage terminals. The second diode and the clamping circuit are used to guide a first portion of an electrostatic discharge (ESD) current to flow between the I / O pad and the first voltage terminal. The first and second terminals of the third diode are coupled to the first voltage terminal. The second and third diodes include a first semiconductor structure for guiding a second portion of the ESD current to flow between the I / O pad and the first voltage terminal.

[0150] In one embodiment, the first semiconductor structure in the second and third diodes is used as an equivalent silicon controlled rectifier (SCR) circuit.

[0151] In one embodiment, the first semiconductor structure in the second and third diodes includes: a substrate, a first well of a first type, a first doped region of a first type, a second doped region of a second type, a second well of a second type, a third doped region of a first type, and a fourth doped region of a second type. The first well of the first type is disposed on the substrate. The first doped region of the first type is disposed in the first well and serves as a second terminal of the second diode. The second doped region of the second type is disposed in the first well and serves as a first terminal of the second diode. The second well of the second type is disposed on the substrate and adjacent to the first well. The third doped region of the first type is disposed in the second well and serves as a first terminal of the third diode. The fourth doped region of the second type is disposed in the second well and serves as a second terminal of the third diode. The second doped region, the first well, the substrate, the second well, and the third doped region are used as an equivalent silicon controlled rectifier (SCR) circuit.

[0152] In one embodiment, it further includes at least one of: a fourth diode coupled in parallel to the first diode between the I / O pad and the first voltage terminal, a fifth diode coupled in parallel to the second diode between the I / O pad and the second voltage terminal, or a sixth diode coupled in parallel to the third diode.

[0153] In one embodiment, a fourth diode is further included, wherein a first terminal and a second terminal of the fourth diode are coupled to a second voltage terminal. The fourth diode and the third diode include a second semiconductor structure for guiding a third portion of the ESD current from the second voltage terminal to the first voltage terminal or from the first voltage terminal to the second voltage terminal.

[0154] In one embodiment, the third and fourth diodes are used as an equivalent silicon controlled rectifier (SCR) circuit.

[0155] In one embodiment, the first semiconductor structure includes: a substrate, a first well of a first type, a first doped region of a first type, a second doped region of a second type, a second well of a second type, a third doped region of a first type, and a fourth doped region of a second type. The first well of the first type is disposed on the substrate. The first doped region of the first type is disposed in the first well and serves as a second terminal of a second diode. The second doped region of the second type is disposed in the first well and serves as a first terminal of a second diode. The second well of the second type is disposed on the substrate and adjacent to the first well. The third doped region of the first type is disposed in the second well and serves as a first terminal of a third diode. The fourth doped region of the second type is disposed in the second well and serves as a second terminal of a third diode. The second doped region, the first well, the substrate, the second well, and the third doped region are used as an equivalent silicon controlled rectifier (SCR) circuit.

[0156] In one embodiment, it further includes at least one of a fourth diode coupled in parallel to the first diode between the I / O pad and the first voltage terminal, a fifth diode coupled in parallel to the second diode between the I / O pad and the second voltage terminal, or a sixth diode coupled in parallel to the third diode.

[0157] In one embodiment, a fourth diode is further included, wherein a first terminal and a second terminal of the fourth diode are coupled to a second voltage terminal. The fourth diode and the third diode include a second semiconductor structure for guiding a third portion of the ESD current from the second voltage terminal to the first voltage terminal or from the first voltage terminal to the second voltage terminal.

[0158] In one embodiment, the third and fourth diodes are used as an equivalent silicon controlled rectifier (SCR) circuit.

[0159] In one embodiment, the first semiconductor structure includes a substrate, a first well of a first type, a first doped region of a first type, a second doped region of a second type, a second well of a second type, a third doped region of a first type, and a fourth doped region of a second type. The first well of the first type is disposed on the substrate. The first doped region of the first type is disposed in the first well and serves as a second terminal of a second diode. The second doped region of the second type is disposed in the first well and serves as a first terminal of a second diode. The second well of the second type is disposed on the substrate and adjacent to the first well. The third doped region of the first type is disposed in the second well and serves as a first terminal of a third diode. The fourth doped region of the second type is disposed in the second well and serves as a second terminal of the third diode. The second doped region, the first well, the substrate, the second well, and the third doped region are used as an equivalent silicon controlled rectifier (SCR) circuit.

[0160] In one embodiment, the second semiconductor structure includes a substrate, a third doped region, a fourth doped region, a third well of a first type, a fifth doped region of a first type, and a sixth doped region of a second type. The third well of the first type is disposed on the substrate and adjacent to the second well. The fifth doped region of the first type is disposed in the third well and serves as a first terminal of the fourth diode. The sixth doped region of the second type is disposed in the third well and serves as a second terminal of the fourth diode. The third doped region, the second well, the substrate, the third well, and the sixth doped region are used as a second equivalent silicon controlled rectifier circuit.

[0161] Also disclosed is a semiconductor device including a substrate, a first well of a first type disposed on the substrate, a first doped region of a first type disposed in the first well, a second doped region of a second type disposed in the first well, a second well of a second type disposed on the substrate and adjacent to the first well, a third doped region of a first type disposed in the second well, and a fourth doped region of a second type disposed in the second well. The first doped region serves as a first terminal of a first diode and is coupled to a first voltage terminal for receiving a first supply voltage. The second doped region serves as a second terminal of the first diode and is coupled to an input / output (I / O) pad. The third doped region serves as a first terminal of a second diode and is coupled to a second voltage terminal for receiving a second supply voltage. The fourth doped region serves as a second terminal of the second diode and is coupled to the second voltage terminal. The first diode, the first voltage terminal, and a clamping circuit coupled between the first and second voltage terminals constitute a first electrostatic discharge (ESD) path between the I / O pad and the second voltage terminal. The second doped region, the first well, the substrate, the second well, and the third doped region constitute a second ESD path between the I / O pad and the second voltage terminal.

[0162] In some embodiments, the system further includes a third well of a second type, a fifth doped region of a first type, and at least one sixth doped region of a second type. The second-type third well is disposed on a substrate and adjacent to the first well. The fifth doped region of the first type is disposed in the third well, wherein the fifth doped region serves as a first terminal of the third diode and is coupled to an I / O pad. At least one sixth doped region of the second type is disposed in the third well, wherein the at least one sixth doped region serves as a second terminal of the third diode and is coupled to a second voltage terminal.

[0163] In some embodiments, the first to third wells, the first to fifth doped regions, and at least one sixth doped region are used in the units of the layout of the semiconductor device, and the semiconductor device further includes: a plurality of units arranged in an array.

[0164] In some embodiments, at least one sixth doped region includes a plurality of sixth doped regions, each having a strip configuration in a plan view, wherein the sixth doped regions are arranged along a first direction.

[0165] In some embodiments, the first to third wells, the first to fifth doped regions, and the sixth doped region are used in the cells of the layout of the semiconductor device, and the semiconductor device further includes a plurality of cells arranged in an array.

[0166] In some embodiments, a sixth doped region, including the first to third wells, the first to fifth doped regions, and the sixth doped region, is used in a first unit of the semiconductor device layout, and the first to third wells, the first to fifth doped regions, and the sixth doped region are used in a second unit of the semiconductor device layout. The semiconductor device further includes at least one of the plurality of first units and at least one of the plurality of second units arranged in an array.

[0167] In some embodiments, the system further includes a third well of a first type, a fifth doped region of a first type, a sixth doped region of a second type, a fourth well of a second type, a seventh doped region of a first type, and an eighth doped region of a second type. The third well of the first type is disposed on the substrate and adjacent to the second well. The fifth doped region of the first type is disposed in the third well, wherein the fifth doped region serves as a first terminal of the third diode and is coupled to a first voltage terminal, the first voltage terminal being used to receive a first supply voltage. The sixth doped region of the second type is disposed in the third well, wherein the sixth doped region serves as a second terminal of the third diode and is coupled to the first voltage terminal. The fourth well of the second type is disposed on the substrate and adjacent to the third well. The seventh doped region of the first type is disposed in the fourth well, wherein the seventh doped region serves as a first terminal of the fourth diode and is coupled to an I / O pad. The eighth doped region of the second type is disposed in the fourth well, wherein the eighth doped region serves as a second terminal of the fourth diode and is coupled to a second voltage terminal, the second voltage terminal being used to receive a second supply voltage.

[0168] In some embodiments, the third doped region, the second well, the substrate, the third well, and the sixth doped region serve as a third ESD path between the first voltage terminal and the second voltage terminal.

[0169] In some embodiments, the first to fourth wells and the first to eighth doped regions are used in a unit of a layout of a semiconductor device, and the semiconductor device further includes a plurality of units arranged in an array.

[0170] A method is also disclosed, comprising: conducting a first electrostatic discharge (ESD) path between an input / output (I / O) pad and a first voltage terminal for receiving a first supply voltage, wherein in the first ESD path a first diode is coupled between the I / O pad and a second voltage terminal for receiving a second supply voltage, and a clamping circuit is coupled between the first voltage terminal and the second voltage terminal; and conducting a second ESD path between the I / O pad and the first voltage terminal, wherein in the second ESD path the first diode and a second diode having two terminals coupled to the first voltage terminal include a first semiconductor structure, and the first semiconductor structure serves as a first equivalent silicon controlled rectifier (SCR) circuit.

[0171] In some embodiments, a third ESD path is further included, connecting the first voltage terminal and the second voltage terminal. In the third ESD path, the second diode and the third diode having two terminals coupled to the second voltage terminal include a second semiconductor structure, and the second semiconductor structure serves as a second equivalent SCR circuit.

[0172] In some embodiments, a third diode is disposed on one side of a first diode, wherein the third diode includes a first type of well, a first doped region of a second type coupled to an I / O pad, and at least one second doped region of a first type coupled to a first voltage terminal.

[0173] In some embodiments, at least one second doped region includes a plurality of second doped regions, each having a strip configuration in a plan view, wherein the second doped regions are arranged along a first direction.

[0174] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the appearance of an embodiment of this disclosure. Those skilled in the art should understand that they can readily use an embodiment of this disclosure as the basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of an embodiment of this disclosure, and that various changes, substitutions, and replacements can be made herein without departing from the spirit and scope of an embodiment of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first diode, wherein a first terminal of the first diode is coupled to a first voltage terminal, the first voltage terminal being used to receive a first supply voltage; A second diode, wherein a first terminal, an input / output pad, and a second terminal of the first diode are coupled to each other, and the second terminal of the second diode is coupled to a second voltage terminal for receiving a second supply voltage; A clamping circuit is coupled between the first voltage terminal and the second voltage terminal, wherein the second diode and the clamping circuit are used to guide a first portion of an electrostatic discharge current to flow between the input / output pad and the first voltage terminal; as well as A third diode, wherein a first terminal and a second terminal of the third diode are coupled to the first voltage terminal; The second diode and the third diode include a first semiconductor structure for guiding a second portion of the electrostatic discharge current to flow between the input / output pad and the first voltage terminal.

2. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure in the second diode and the third diode is used as an equivalent silicon controlled rectifier circuit.

3. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure in the second diode and the third diode includes: One substrate; A first well of the first type is disposed on the substrate; A first doped region of the first type is disposed in the first well and serves as the second terminal of the second diode; A second doped region of a second type is disposed in the first well and serves as the first terminal of the second diode; The second type of second well is disposed on the substrate and adjacent to the first well; The third doped region of the first type is disposed in the second well and serves as the first terminal of the third diode; The second type of fourth doped region is disposed in the second well and serves as the second terminal of the third diode; The second doped region, the first well, the substrate, the second well, and the third doped region are used as an equivalent silicon controlled rectifier circuit.

4. The semiconductor device according to claim 1, characterized in that, Further includes: At least one of a fourth diode, a fifth diode, and a sixth diode, wherein the fourth diode is coupled in parallel to the first diode between the input / output pad and the first voltage terminal, the fifth diode is coupled in parallel to the second diode between the input / output pad and the second voltage terminal, and the sixth diode is coupled in parallel to the third diode.

5. The semiconductor device according to claim 1, characterized in that, Further includes: A fourth diode, wherein a first terminal and a second terminal of the fourth diode are coupled to the second voltage terminal. The fourth diode and the third diode include a second semiconductor structure, which is used to guide a third portion of the electrostatic discharge current from the second voltage terminal to the first voltage terminal or from the first voltage terminal to the second voltage terminal.

6. The semiconductor device according to claim 5, characterized in that, The third diode and the fourth diode are used as an equivalent silicon controlled rectifier circuit.

7. The semiconductor device according to claim 5, characterized in that, The first semiconductor structure includes: One substrate; A first well of the first type is disposed on the substrate; A first doped region of the first type is disposed in the first well and serves as the second terminal of the second diode; A second doped region of a second type is disposed in the first well and serves as the first terminal of the second diode; The second type of second well is disposed on the substrate and adjacent to the first well; The third doped region of the first type is disposed in the second well and serves as the first terminal of the third diode; The second type of fourth doped region is disposed in the second well and serves as the second terminal of the third diode; The second doped region, the first well, the substrate, the second well, and the third doped region are used as an equivalent silicon controlled rectifier circuit. The second semiconductor structure includes: The substrate; This third doped region; This fourth doped region; A third well of the first type is disposed on the substrate and adjacent to the second well; The fifth doped region of the first type is disposed in the third well and serves as the first terminal of the fourth diode; and The sixth doped region of this second type is disposed in the third well and serves as the second terminal of the fourth diode; The third doped region, the second well, the substrate, the third well, and the sixth doped region are used as a second equivalent silicon controlled rectifier circuit.

8. A semiconductor device, characterized in that, include: One substrate; A first well of the first type is disposed on the substrate; The first type of first doped region is disposed in the first well, wherein the first doped region serves as a first terminal of a first diode and is coupled to a first voltage terminal, the first voltage terminal being used to receive a first supply voltage; A second doped region of a second type is disposed in the first well, wherein the second doped region serves as a second terminal of the first diode and is coupled to an input / output pad; The second type of second well is disposed on the substrate and adjacent to the first well; The third doped region of the first type is disposed in the second well, wherein the third doped region serves as a first terminal of a second diode and is coupled to a second voltage terminal, the second voltage terminal being used to receive a second supply voltage; as well as The second type of fourth doped region is disposed in the second well, wherein the fourth doped region serves as a second terminal of the second diode and is coupled to the second voltage terminal; The first diode, the first voltage terminal, and a clamping circuit coupled between the first voltage terminal and the second voltage terminal serve as a first electrostatic discharge path between the input / output pad and the second voltage terminal. The second doped region, the first well, the substrate, the second well, and the third doped region are connected by a second electrostatic discharge path between the input / output pad and the second voltage terminal.

9. The semiconductor device according to claim 8, characterized in that, Further includes: The third well of the second type is disposed on the substrate and adjacent to the first well; The first type of fifth doped region is disposed in the third well, wherein the fifth doped region serves as a first terminal of a third diode and is coupled to the input / output pad; as well as At least one sixth doped region of the second type is disposed in the third well, wherein the at least one sixth doped region serves as a second terminal of the third diode and is coupled to the second voltage terminal.

10. The semiconductor device according to claim 9, characterized in that, The first to the third wells, the first to the fifth doped regions, and the at least one sixth doped region are used in a unit of a layout of the semiconductor device, and the semiconductor device further includes: Multiple units arranged in an array.

11. The semiconductor device according to claim 9, characterized in that, The at least one sixth doped region includes: Multiple sixth doped regions, each having a strip configuration in a planar view, wherein the multiple sixth doped regions are arranged along a first direction.

12. The semiconductor device according to claim 11, characterized in that, The first to the third wells, the first to the fifth doped regions, and the plurality of sixth doped regions are used in a unit of a layout of the semiconductor device, and the semiconductor device further includes: Multiple units arranged in an array.

13. The semiconductor device according to claim 11, characterized in that, The first to the third wells, the first to the fifth doped regions, and one of the plurality of sixth doped regions are used in a first unit of a layout of the semiconductor device, and The first to the third wells, the first to the fifth doped regions, and the plurality of sixth doped regions are used in a second unit of the layout of the semiconductor device, and The semiconductor device further includes: At least one of the multiple first units and at least one of the multiple second units are arranged in an array.

14. The semiconductor device according to claim 8, characterized in that, Further includes: The third well of the first type is disposed on the substrate and adjacent to the second well; A fifth doped region of the first type is disposed in the third well, wherein the fifth doped region serves as a first terminal of a third diode and is coupled to the first voltage terminal, the first voltage terminal being used to receive the first supply voltage; The sixth doped region of the second type is disposed in the third well, wherein the sixth doped region serves as a second terminal of the third diode and is coupled to the first voltage terminal; The second type of fourth well is disposed on the substrate and adjacent to the third well; The first type of seventh doped region is disposed in the fourth well, wherein the seventh doped region serves as a first terminal of a fourth diode and is coupled to the input / output pad; as well as The second type of eighth doped region is disposed in the fourth well, wherein the eighth doped region serves as a second terminal of the fourth diode and is coupled to the second voltage terminal, the second voltage terminal being used to receive the second supply voltage.

15. The semiconductor device according to claim 14, characterized in that, The third doped region, the second well, the substrate, the third well, and the sixth doped region serve as a third electrostatic discharge path between the first voltage terminal and the second voltage terminal.

16. The semiconductor device according to claim 14, characterized in that, The first to fourth wells and the first to eighth doped regions are used in a unit of a layout of the semiconductor device, and the semiconductor device further includes: Multiple units arranged in an array.

17. A semiconductor device, characterized in that, include: One substrate; A first well of the first type is disposed on the substrate; A first doped region of the first type and a second doped region of a second type different from the first type are disposed in the first well, wherein the first doped region is used to be coupled to a first voltage terminal to receive a first supply voltage, and the second doped region is used to be coupled to an input / output pad, wherein the first doped region serves as a first terminal of a first diode, and the second doped region serves as a second terminal of the first diode; The second type of second well is arranged adjacent to the first well and disposed on the substrate; as well as A third doped region of the first type and a fourth doped region of the second type are disposed in the second well, wherein the third doped region and the fourth doped region are coupled to a second voltage terminal to receive a second supply voltage different from the first supply voltage, wherein the third doped region serves as a first terminal of a second diode, and the fourth doped region serves as a second terminal of the second diode. The third doped region is positioned between the second doped region and the fourth doped region, and The second doped region, the first well, the substrate, the second well, and the third doped region are used to transmit an electrostatic discharge current flowing between the input / output pad and the second voltage terminal.

18. The semiconductor device according to claim 17, characterized in that, Also includes: A shallow trench isolation region is configured between the second doped region and the third doped region.

19. The semiconductor device according to claim 17, characterized in that, Also includes: The first type of third well, wherein the second well is arranged between the first well and the third well; and A fifth doped region of the first type and a sixth doped region of the second type are disposed in the third well, wherein the fifth doped region and the sixth doped region are used to be coupled to the first voltage terminal; The sixth doped region, the substrate, the third well, the second well, and the third doped region are used to transmit an electrostatic discharge current flowing between the first voltage terminal and the second voltage terminal.

20. The semiconductor device according to claim 17, characterized in that, Also includes: The second type of third well, wherein the first well is arranged between the second well and the third well; and The first type of fifth doped region and a plurality of sixth doped regions are disposed in the third well, wherein the fifth doped region is used to be coupled to the input / output pad; and the plurality of sixth doped regions are used to be coupled to the second voltage terminal; The second doped region, the first well, the substrate, the third well, and the plurality of sixth doped regions are included in a structure to shunt a latch-up current from the input / output pad to the second voltage terminal.

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