Integrated circuit devices and their manufacturing methods

Abstract

An integrated circuit device includes: a fin-type active region protruding from a substrate and extending along a first direction; a plurality of semiconductor patterns disposed separately from the upper surface of the fin-type active region, each of the plurality of semiconductor patterns including a channel region; a gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction perpendicular to the first direction, and including a main gate electrode and a sub-gate electrode, wherein the main gate electrode is disposed on the uppermost semiconductor pattern among the plurality of semiconductor patterns and extends in the second direction, and the sub-gate electrode is disposed between the plurality of semiconductor patterns; a first spacer structure disposed on two sidewalls of the main gate electrode; and a source / drain region connected to the plurality of semiconductor patterns, disposed on both sides of the gate electrode, and contacting the bottom surface of the spacer structure.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0114366, filed on September 17, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to integrated circuit devices and methods of manufacturing the same, and more specifically, to integrated circuit devices including transistors having a multi-gate structure and methods of manufacturing the integrated circuit device. Background Technology

[0004] To provide good performance and economical prices, it is necessary / desirable to increase the integration density of integrated circuit devices. Due to this requirement, the size of integrated circuit devices has been reduced; however, the short-channel effect of transistors has emerged, leading to a decrease in the reliability of integrated circuit devices. Therefore, to reduce the short-channel effect, integrated circuit devices with multi-gate structures, such as nanosheet or nanowire transistors, have been proposed. Summary of the Invention

[0005] The inventive concept provides an integrated circuit device and / or a method for manufacturing an integrated circuit device, which prevents or reduces the likelihood of defects such as undesirable connections between the source / drain region and the gate electrode, and reduces / minimizes the spacing between adjacent source and drain regions.

[0006] The purpose of the inventive concept is not limited to the above-described purposes, but other purposes not described herein will be clearly understood by those skilled in the art from the following description.

[0007] According to some exemplary embodiments of the inventive concept, an integrated circuit device is provided, comprising: a fin-type active region protruding from a substrate and extending along a first direction; a plurality of semiconductor patterns separated from the upper surface of the fin-type active region; a gate electrode surrounding the plurality of semiconductor patterns, the gate electrode extending in a second direction perpendicular to the first direction, the gate electrode including a main gate electrode and a sub-gate electrode, wherein the main gate electrode is disposed on the uppermost semiconductor pattern among the plurality of semiconductor patterns and extends in the second direction, and the sub-gate electrode is between two semiconductor patterns among the plurality of semiconductor patterns; the integrated circuit includes a spacer structure on a first sidewall and a second sidewall of the main gate electrode, and source / drain regions at corresponding sides of the plurality of semiconductor patterns, and the source / drain regions are respectively located on a first side and a second side of the gate electrode, the source / drain regions contacting the bottom surface of the spacer structure. The middle portion of the main gate electrode has a first width in a first direction, the bottom portion of the main gate electrode has a second width in a first direction that is less than the first width, and the spacing between the middle portions of adjacent source / drain regions in the source / drain regions has a third width in the first direction that is less than the second width.

[0008] According to some exemplary embodiments of the inventive concept, an integrated circuit device is provided, comprising: a fin-type active region protruding from a substrate and extending along a first direction; a plurality of semiconductor patterns separated from an upper surface of the fin-type active region; a gate electrode surrounding the plurality of semiconductor patterns, the gate electrode extending in a second direction perpendicular to the first direction, the gate electrode including a main gate electrode and a sub-gate electrode, wherein the main gate electrode is disposed on the uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and the sub-gate electrode is located between two semiconductor patterns of the plurality of semiconductor patterns. The integrated circuit includes: a spacer structure disposed on a first sidewall and a second sidewall of the main gate electrode; and source / drain regions at corresponding sides of the plurality of semiconductor patterns, the source / drain regions being located on a first side and a second side of the gate electrode, respectively, and contacting a bottom surface of the spacer structure, the main gate electrode including a circularly inclined surface inclined from a lower portion of the main gate electrode toward at least one of the first sidewall or the second sidewall of the main gate electrode, the circularly inclined surface being inclined relative to a third direction perpendicular to the upper surface of the substrate.

[0009] According to some exemplary embodiments of the inventive concept, an integrated circuit device is provided, comprising: a fin-shaped active region protruding from a substrate and extending along a first direction; a plurality of semiconductor patterns separated from an upper surface of the fin-shaped active region; a gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction perpendicular to the first direction, the gate electrode including a main gate electrode and a sub-gate electrode, wherein the main gate electrode is disposed on the uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and the sub-gate electrode is between two semiconductor patterns of the plurality of semiconductor patterns; the integrated circuit includes: a gate dielectric layer between the plurality of semiconductor patterns and the gate electrode; a spacer structure disposed on a first sidewall and a second sidewall of the main gate electrode; a pair of source / drain regions at corresponding sides of the plurality of semiconductor patterns, the pair of source / drain regions being located on a first side and a second side of the gate electrode, respectively, the pair of source / drain regions contacting a bottom surface of the spacer structure; and a contact plug electrically connected to the pair of source / drain regions. The main gate electrode has a first width in the middle of a first direction, a second width in the first direction that is less than the first width, and a third width in the first direction that is less than the second width between the middle portions of the pair of source / drain regions; and the main gate electrode includes a circular inclined surface that is inclined from the bottom of the main gate electrode toward at least one of the first sidewall or the second sidewall of the main gate electrode, the circular inclined surface being inclined relative to a third direction perpendicular to the upper surface of the substrate. Attached Figure Description

[0010] Embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This illustrates the layout of an integrated circuit device according to an embodiment;

[0012] Figure 2A It is along Figure 1 A cross-sectional view taken from line A1-A1′. Figure 2B It is along Figure 1 A cross-sectional view taken from line B1-B1′. Figure 2C yes Figure 2A A magnified view of region CC;

[0013] Figure 3 This is a cross-sectional view showing an integrated circuit device according to an embodiment;

[0014] Figure 4 This is a cross-sectional view showing an integrated circuit device according to an embodiment;

[0015] Figure 5 This is a cross-sectional view showing an integrated circuit device according to an embodiment;

[0016] Figures 6 to 15B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment; and

[0017] Figure 16 This is a perspective view showing an integrated circuit device according to an embodiment. Detailed Implementation

[0018] In the following description, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0019] Figure 1 This illustrates the layout of the integrated circuit device 10 according to an embodiment. Figure 2A It is along Figure 1 A cross-sectional view taken from line A1-A1′. Figure 2B It is along Figure 1 A cross-sectional view taken from line B1-B1′. Figure 2C yes Figure 2A A magnified view of region CC.

[0020] Reference Figures 1 to 2C In the integrated circuit device 10, the substrate 110 may include a fin-type active region FA disposed in the device region DR.

[0021] The fin-type active region FA can be configured to correspond to or be associated with the transistor TR, and for example, the transistor TR can be / correspond to an NMOS transistor or a PMOS transistor.

[0022] Substrate 110 may include a semiconductor such as silicon (Si) or germanium (Ge), or a compound semiconductor such as at least one of SiGe, SiC, GaAs, InAs, or InP. In some example embodiments, substrate 110 may include at least one of group III-V materials and group IV materials. Each group III-V material may be a binary, ternary, or quaternary compound comprising at least one group III element and at least one group V element. Each group III-V material may be a compound comprising at least one element from group III (In), gallium (Ga), and aluminum (Al) and at least one element from group V (As), phosphorus (P), and antimony (Sb). For example, group III-V materials may be derived from InP, In... z Ga 1-z AS(0≤z≤1), and Al z Ga 1-zThe selection is made from As (0≤z≤1). Binary compounds can be, for example, one of InP, GaAs, InAs, InSb, and GaSb. Ternary compounds can be, for example, one of InGaP, InGaAs, AlInAs, InGaSb, GaAsSb, and GaAsP. Group IV materials can be Si or Ge.

[0023] In some example embodiments, group III-V materials and group IV materials such as Ge can be used as channel materials for fabricating high-speed transistors. High-performance complementary metal-insulator-semiconductor (CMOS) transistors can be formed using semiconductor substrates comprising group III-V materials (e.g., GaAs) and semiconductor substrates comprising semiconductor materials (e.g., Ge), wherein the group III-V material has higher electron mobility than a Si substrate, and the semiconductor material has higher hole mobility than a Si substrate. In some example embodiments, when an NMOS transistor is formed on substrate 110, substrate 110 may comprise one of the aforementioned group III-V materials. Alternatively, when a PMOS transistor is formed on substrate 110, at least a portion of substrate 110 may comprise Ge.

[0024] Furthermore, the substrate 110 may have a semiconductor-on-insulator (SOI) structure, such as silicon-on-insulator and / or silicon-on-sapphire. The substrate 110 may include conductive regions, such as doped wells and / or doped structures.

[0025] The fin-type active region FA can extend on the substrate 110 along a first direction (X direction) and can protrude from the upper surface of the substrate 110 along a vertical direction (Z direction). An isolation trench 114T for confining the fin-type active region FA can be formed in the substrate 110, and an isolation layer 114 can be formed in the isolation trench 114T. In some example embodiments, the isolation layer 114 may include an isolation liner (not shown) conformally disposed on the inner wall of the isolation trench 114T, and may include a gap-filling insulating layer (not shown) filling the interior of the isolation trench 114T on the isolation liner.

[0026] exist Figure 2A In the diagram, the upper surface of the isolation layer 114 is shown as being at the same horizontal level as the upper surface of the fin-type active region FA, but is not limited thereto. Alternatively, the upper surface of the isolation layer 114 may be positioned at a lower horizontal level than the upper surface of the fin-type active region FA, and only the lower portion of the sidewalls of the fin-type active region FA may be surrounded by the isolation layer 114. Both the isolation liner and the gap-filling insulating layer may comprise silicon oxide, silicon nitride, or combinations thereof.

[0027] In the finned active region FA, multiple semiconductor patterns NS can be disposed separately from each other in the vertical direction (Z direction) from the upper surface 110M of the substrate 110. The multiple semiconductor patterns NS can include the same material as the substrate 110. For example, the multiple semiconductor patterns NS can include semiconductors such as Si or Ge, or compound semiconductors such as SiGe, SiC, GaAs, InAs, or InP. Furthermore, each of the multiple semiconductor patterns NS can include a channel region.

[0028] The plurality of semiconductor patterns NS may include a first semiconductor pattern NS1, a second semiconductor pattern NS2, and a third semiconductor pattern NS3, which are arranged in the aforementioned order from the upper surface 110M of the substrate 110. The plurality of semiconductor patterns NS may have a relatively large width in the second direction (Y direction) and a relatively small thickness in the vertical direction (Z direction), and may, for example, have a nanosheet shape.

[0029] For example, the first semiconductor pattern NS1 may have a first thickness t11 of about 1 nm to about 10 nm, the second semiconductor pattern NS2 may have a second thickness t12 of about 1 nm to about 10 nm, and the third semiconductor pattern NS3 may have a third thickness t13 of about 1 nm to about 10 nm or about 1 nm to about 20 nm.

[0030] like Figure 2B As shown, the third thickness t13 of the third semiconductor pattern NS3 can be greater than the first thickness t11 of the first semiconductor pattern NS1 and the second thickness t12 of the second semiconductor pattern NS2, but the inventive concept is not limited thereto. In some embodiments, each of the plurality of semiconductor patterns NS can have a width of about 5 nm to about 100 nm in a first direction (X direction) or a second direction (Y direction), but the example embodiments are not limited thereto.

[0031] like Figure 2A As shown, multiple semiconductor patterns NS can be arranged to be spaced apart from each other by the same distance. However, the inventive concept is not limited to this, and the spacing between two adjacent semiconductor patterns NS in the multiple semiconductor patterns NS can be varied. Furthermore, the number of semiconductor patterns NS is not limited to this. Figures 2A to 2C An instance of a number, and it can be an integer greater than three, such as four, five, six or seven, or an integer less than three, such as one or two.

[0032] The gate electrode 120 may extend in a second direction (Y direction) on the fin active region FA. The gate electrode 120 may surround multiple semiconductor patterns NS and may extend on the fin active region FA and the isolation layer 114.

[0033] The gate electrode 120 may include a main gate electrode 120M and a plurality of sub-gate electrodes 120S. The main gate electrode 120M may cover the upper surface of the uppermost semiconductor pattern NS (e.g., the third semiconductor pattern NS3). The plurality of sub-gate electrodes 120S may be disposed between the fin-type active region FA and the lowermost semiconductor pattern NS, and each may be disposed between two adjacent semiconductor patterns NS.

[0034] For example, multiple sub-gate electrodes 120S can be disposed between the finned active region FA and the first semiconductor pattern NS1, between the first semiconductor pattern NS1 and the second semiconductor pattern NS2, and between the second semiconductor pattern NS2 and the third semiconductor pattern NS3. The main gate electrode 120M can be disposed on the upper surface of the third semiconductor pattern NS3 and the isolation layer 114, and can be connected to the multiple sub-gate electrodes 120S.

[0035] The main gate electrode 120M may include a circularly inclined surface 120SI, which is inclined in a third direction (Z direction) perpendicular to the upper surface 110M of the substrate 110. For example, the circularly inclined surface 120SI may not be perpendicular to the upper surface 110M of the substrate 110 and may be inclined relative to the bottom of the main gate electrode 120M. The circularly inclined surface 120SI may be connected to / be connected to the vertical sidewall 120SW of the main gate electrode 120M and may extend a certain height from the bottom of the main gate electrode 120M. For example, the height of the circularly inclined surface 120SI in the third direction (Z direction) may be from about 1% to about 20% of the height of the main gate electrode 120M, but the example embodiment is not limited thereto.

[0036] The gate electrode 120 may include a work function control layer (not shown) and / or a buried conductive layer (not shown). The work function control layer may be disposed on the upper surface of each of the plurality of semiconductor patterns NS, and the buried control layer may be disposed on the work function control layer. In some example embodiments, both the work function control layer and the buried conductive layer may include Al, copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlC, TiAlN, TaCN, TaC, TaSiN, or combinations thereof and / or may include materials different from each other, but the example embodiments are not limited thereto.

[0037] A gate dielectric layer 128 may be disposed between the gate electrode 120 and the plurality of semiconductor patterns NS. The gate dielectric layer 128 may, for example, be conformally disposed on the upper surface and sidewalls of each of the plurality of semiconductor patterns NS.

[0038] The gate dielectric layer 128 may be disposed within a stacked structure including an interface layer (not shown) and / or a high-k dielectric layer (not shown). The interface layer may repair or help repair interface defects between the high-k dielectric layer in the upper surface of the fin active region FA and the surface of each of the plurality of semiconductor patterns NS.

[0039] In some example embodiments, the interface layer may include a low-dielectric material layer (e.g., silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, or combinations thereof) having a dielectric constant of about 9 or less. Alternatively or additionally, the interface layer may include silicates, combinations of silicates and silicon oxide, or combinations of silicates and silicon oxynitride. However, the interface layer may be omitted.

[0040] The high-k dielectric layer may include materials having a dielectric constant greater than that of silicon oxide. For example, the high-k dielectric layer may have a dielectric constant of about 10 to about 25. The high-k dielectric layer may include materials selected from the following: hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, and combinations thereof, but the materials included in the high-k dielectric layer are not limited to these.

[0041] The spacer structure 130 may be disposed on each of the two sidewalls of the gate electrode 120. The gate dielectric layer 128 may be disposed between the gate electrode 120 and the spacer structure 130. The spacer structure 130 may include a first spacer portion 132 and a second spacer portion 134, which are sequentially disposed on the sidewalls of the main gate electrode 120M.

[0042] like Figure 2C As shown, the first spacer 132 may be conformally disposed on the sidewall of the main gate electrode 120M, and the third semiconductor pattern NS3 is adjacent to it. The bottom of the first spacer 132 may extend horizontally and may be disposed on the upper surface of the third semiconductor pattern NS3 and between the second spacer 134 and the third semiconductor pattern NS3. Each of the first spacer 132 and the second spacer 134 may comprise silicon nitride or silicon oxynitride and / or may comprise materials different from each other; however, the exemplary embodiment is not limited thereto.

[0043] A recessed region RS1 can be provided in the fin-type active region FA on both sides of each of the multiple semiconductor patterns NS, and the source / drain region 140 can fill the interior of the recessed region RS1. The source / drain region 140 can be connected to both ends of the multiple semiconductor patterns NS.

[0044] The source / drain region 140 may include a first semiconductor layer 142 and a second semiconductor layer 144, which are sequentially disposed on the inner wall of the recessed region RS1. The first semiconductor layer 142 and the second semiconductor layer 144 may be grown from the fin-type active region FA and multiple semiconductor patterns NS by a selective epitaxial growth (SEG) process, for example, epitaxial growth. The SEG process may include a homoepitaxial process; alternatively or additionally, the SEG process may include a heteroepitaxial process. Furthermore, the source / drain region 140 may include a dopant, such as at least one of boron, phosphorus, arsenic, or carbon. The dopant may be implanted into the source / drain region 140, and / or may be included in the source / drain region 140 during the SEG process.

[0045] In some example embodiments, the first semiconductor layer 142 may be formed on the inner wall of the recessed region RS1 to have a specific thickness and may be in contact with a plurality of semiconductor patterns NS and the gate dielectric layer 128.

[0046] The first semiconductor layer 142 may include a tilted surface 142SI disposed along a direction from the upper portion to the middle portion of the first semiconductor layer 142. At least a portion of the tilted surface 142SI of the first semiconductor layer 142 may vertically overlap with the vertical sidewall 120SW of the main gate electrode 120M, and another portion of the tilted surface 142SI of the first semiconductor layer 142 may be arranged to vertically overlap with the bottom of the main gate electrode 120M. For example, the upper surface of the first semiconductor layer 142 may contact, for example, the bottom surface of the spacer structure 130.

[0047] The second semiconductor layer 144 can be formed to fill the recessed region RS1 on the first semiconductor layer 142. A portion of the upper surface of the second semiconductor layer 144 can contact, for example, directly contact, the bottom surface of the spacer structure 130. Another portion of the upper surface of the second semiconductor layer 144 can protrude upwards to a level higher than the bottom surface of the spacer structure 130. Therefore, the second semiconductor layer 144 can fill the recessed region RS1, and the edge of the second semiconductor layer 144 can extend to the portion below the spacer structure 130 and can vertically overlap with the spacer structure 130.

[0048] The first semiconductor layer 142 and the second semiconductor layer 144 may each include at least one of the following: an epitaxially grown Si layer (i.e., an epitaxial Si layer), an epitaxially grown SiC layer (i.e., an epitaxial SiC layer), an epitaxially grown SiGe layer (i.e., an epitaxial SiGe layer), or an epitaxially grown SiP layer (i.e., an epitaxial SiP layer).

[0049] In some example embodiments, both the first semiconductor layer 142 and the second semiconductor layer 144 may include a Si layer, and the concentrations of impurities doped on the first semiconductor layer 142 and the second semiconductor layer 144 may be different.

[0050] Alternatively or additionally, both the first semiconductor layer 142 and the second semiconductor layer 144 may comprise a SiGe layer, and the content of Ge included in the first semiconductor layer 142 may differ from the content of Ge included in the second semiconductor layer 144. For example, the concentration of Ge included in the first semiconductor layer 142 may be different from (e.g., greater than or less than) the concentration of Ge included in the second semiconductor layer 144. Furthermore, impurities such as carbon (C) may also be included / contained in the first semiconductor layer 142.

[0051] Alternatively or additionally, one of the first semiconductor layer 142 and the second semiconductor layer 144 may include a Si layer, and the other of the first semiconductor layer 142 and the second semiconductor layer 144 may include a SiGe layer. However, the inventive concept is not limited thereto. Alternatively or additionally, at least one additional semiconductor layer may be disposed between the first semiconductor layer 142 and the second semiconductor layer 144.

[0052] like Figure 2C As shown, the width of the recessed region RS1 in its middle portion can be greater than its width at its uppermost portion. Therefore, the width of the source / drain region 140 filling the recessed region 140 in its middle portion can be greater than its width at its uppermost portion, and at least a portion of each of the plurality of semiconductor patterns NS in contact with the source / drain region 140 can include inclined sidewalls.

[0053] like Figure 2C As shown, the middle portion of the main gate electrode 120M may have a first width W1 in the first direction (X direction), and the bottom of the main gate electrode 120M may have a second width W2 in the first direction (X direction) that is smaller than the first width W1. A circular inclined surface 120SI may be formed at the bottom of the main gate electrode 120M, and the first spacing portion 132 of the spacing structure 130 may fill the space defined by the circular inclined surface 120SI and the upper surface of the uppermost semiconductor pattern NS.

[0054] For example, the first spacer 132 may include a circular protrusion 132P disposed at its bottom, and the circular protrusion 132P may fill the space defined by the circular inclined surface 120SI and the upper surface of the uppermost semiconductor pattern NS. A gate dielectric layer 128 may be disposed between the circular inclined surface 120SI and the circular protrusion 132P. The circular inclined surface 120SI of the main gate electrode 120M may vertically overlap with a portion of the spacer structure 130 (e.g., the circular protrusion 132P of the first spacer 132).

[0055] like Figure 2C As shown, the upper portion of the source / drain region 140 may include a sloping surface 142SI, and the uppermost semiconductor pattern NS (e.g., a third semiconductor pattern NS3) connected to the source / drain region 140 may include a pair of sloping sidewalls conforming to the shape of the sloping surface 142SI of the source / drain region 140. For example, each sidewall in the pair of sloping sidewalls may contact the first semiconductor layer 142 of the source / drain region 140. The upper portion of the uppermost semiconductor pattern NS may have a top width WT in a first direction (X direction), and the bottom of the uppermost semiconductor pattern NS may have a bottom width WB in the first direction (X direction) that is smaller than the top width WT. For example, the uppermost semiconductor pattern NS may include a pair of sloping sidewalls.

[0056] The middle portion of the source / drain region 140 may include a vertical surface 142SW connected from its upper inclined surface 142SI. The spacing between the middle portions of adjacent source / drain regions 140 may have a third width W3 in a first direction (X direction). For example, the distance between the vertical surfaces 142SW of adjacent source / drain regions 140 may be the third width W3, and the third width W3 may be substantially the same as the bottom width WB of the uppermost semiconductor pattern NS. Additionally or alternatively, the third width W3 of the source / drain region 140 may be smaller than the second width W2 of the bottom of the main gate electrode 120M.

[0057] like Figure 2C As shown, the uppermost semiconductor pattern NS may include a cross-section with an inverted trapezoidal shape, and the top width WT of the uppermost semiconductor pattern NS may be greater than the second width W2 of the bottom of the main gate electrode 120M. Alternatively or additionally, the circular protrusion 132P of the first spacing portion 132 may be disposed between the bottom of the main gate electrode 120M and the source / drain region 140, so that the spacing between the main gate electrode 120M and the source / drain region 140 can be relatively large compared to the case where the main gate electrode 120M includes a vertical sidewall disposed at its bottom.

[0058] As described above, since the spacing between the main gate electrode 120M and the source / drain region 140 is relatively large, leakage current, such as gate-induced leakage current (GIDL), between the bottom of the main gate electrode 120M and the source / drain region 140 can be prevented or reduced. Furthermore, this leakage current can be reduced during the process of forming the source / drain region 140 or during the removal of the dummy gate structure DG (see [link to documentation]). Figure 13A In the process of forming the gate electrode 120, measures are taken to prevent issues such as the presence of a dummy gate structure DG (see [link to relevant documentation]). Figure 13A This reduces the likelihood of process errors such as undesired connections between the gate electrode 120 and the source / drain region 140 or undesired connections between the gate electrode 120 and the source / drain region 140.

[0059] An insulating liner 152 and an inter-gate insulating layer 154 may be sequentially formed on the two sidewalls of the spacer structure 130, the source / drain region 140, and the isolation layer 114. An upper insulating layer 162 may be disposed on the gate electrode 120 and the inter-gate insulating layer 154. A contact plug 166 may be disposed in a contact hole 166H that passes through the upper insulating layer 162 and exposes the upper surface of the source / drain region 140, and a metal silicide layer 168 may be disposed between the contact plug 166 and the source / drain region 140. For example, the metal silicide layer 168 may include titanium silicide and / or cobalt silicide, but the example embodiment is not limited thereto.

[0060] Although not shown, a wiring layer (not shown) and a via (not shown) connected to the contact plug 166 and the gate electrode 120 may also be provided on the upper insulating layer 162.

[0061] Typically, dummy gate structures can be formed on multiple semiconductor patterns. Recessed regions can be formed by removing portions of the semiconductor patterns on either side of the dummy gate structure, and source / drain regions can be formed within these recessed regions. However, at the edge portions of each semiconductor pattern, the spacing between the recessed regions and the dummy gate structures may be relatively small, reducing process margins and potentially causing process errors such as unwanted connections between the dummy gate structures and the source / drain regions, and / or unwanted connections between the gate electrode and the source / drain regions. Furthermore, due to the relatively small spacing between the recessed regions and the dummy gate structures at the edge portions of each semiconductor pattern, relatively large leakage currents, such as GIDL currents, may occur between the gate electrode and the source / drain regions.

[0062] However, in the integrated circuit device 10 according to some example embodiments, the circularly tilted surface 120SI can be disposed at the bottom of the main gate electrode 120M, thus ensuring the dummy gate structure DG (see Figure 13AA relatively large spacing between the gate electrode 120 and the source / drain region 140, or between the gate electrode 120 and the source / drain region 140. Therefore, it can greatly prevent phenomena such as dummy gate structures (DG) (see...). Figure 13A Process errors such as undesired connections between the source / drain region 140 and the gate electrode 120 and the source / drain region 140. Alternatively or additionally, leakage current between the source / drain region 140 and the main gate electrode 120M can be greatly prevented.

[0063] Furthermore, in the integrated circuit device 10 according to some example embodiments, the middle portion of the source / drain region 140 may include a vertical surface 142SW connected from its upper inclined surface 142SI, and the spacing between the middle portions of adjacent source / drain regions 140 may be less than the width of the bottom of the main gate electrode 120M. Therefore, since the spacing between adjacent source / drain regions 140 is reduced, the operating voltage can be relatively reduced, and the operating current can be relatively increased. For example, the electrical characteristics of the integrated circuit device 10 can be enhanced.

[0064] Therefore, in the integrated circuit device 10 according to some example embodiments, defects such as undesirable connections between the gate electrode 120 and the source / drain region 140 can be prevented or their likelihood of occurrence can be reduced, and the spacing between adjacent source / drain regions 140 can be reduced, thereby enhancing electrical characteristics and / or improving productivity.

[0065] Figures 3 to 5 This is a cross-sectional view of an integrated circuit device according to some example embodiments.

[0066] Most elements and the material of each of the integrated circuit devices 20, 30 and 40 described below are similar to those described below. Figures 1 to 2C The descriptions are substantially the same or similar. Therefore, for ease of description, the differences from the aforementioned integrated circuit device 10 will be mainly described below.

[0067] Reference Figure 3 In the integrated circuit device 20 according to some example embodiments, a circular inclined surface 120SI may be provided at the bottom of the main gate electrode 120M.

[0068] The first spacer 132 may include a circular protrusion 132P disposed at its bottom, and the circular protrusion 132P may fill the space defined by the circular inclined surface 120SI and the upper surface of the uppermost semiconductor pattern NS. A gate dielectric layer 128 may be disposed between the circular inclined surface 120SI and the circular protrusion 132P. The circular inclined surface 120SI of the main gate electrode 120M may vertically overlap with a portion of the spacer structure 130 (e.g., the circular protrusion 132P of the first spacer 132).

[0069] like Figure 3 As shown, the upper portion of the source / drain region 140A may include a sloped surface 142ASI, and the semiconductor pattern NS connected to the uppermost part of the source / drain region 140A may include a pair of sloped sidewalls conforming to the shape of the sloped surface 142ASI of the source / drain region 140A. For example, each sidewall in the pair of sloped sidewalls may contact the first semiconductor layer 142A of the source / drain region 140A.

[0070] The middle portion of the source / drain region 140A may include a vertical surface 142ASW connected from its upper inclined surface 142ASI. The spacing between the middle portions of adjacent source / drain regions 140A may have a third width W3 in a first direction (X direction). For example, the distance between the vertical surfaces 142ASW of adjacent source / drain regions 140A may be the third width W3, and the third width W3 may be substantially the same as the bottom width WB of the uppermost semiconductor pattern NS. Furthermore, the third width W3 of the source / drain region 140A may be smaller than the second width W2 of the bottom of the main gate electrode 120M.

[0071] The endpoint of the inclined surface 142ASI of the source / drain region 140A can contact the endpoint of the circular protrusion 132P of the first spacer 132. For example, the vertex portion / vertex of the upper surface of the first semiconductor layer 142A can contact the portion protruding in the direction from the circular protrusion 132P of the first spacer 132 to the main gate electrode 120M. Therefore, the lower surface of the first spacer 132 can contact the upper surface of the second semiconductor layer 144A.

[0072] In the integrated circuit device 20 according to some example embodiments, the middle portion of the source / drain region 140A may include a vertical surface 142ASW connected from its upper inclined surface 142ASI, and the spacing between the middle portions of adjacent source / drain regions 140A can be much smaller than the width of the bottom of the main gate electrode 120M. Therefore, due to the reduced spacing between adjacent source / drain regions 140A, the operating voltage can be relatively reduced, and / or the operating current can be relatively increased. For example, the electrical characteristics of the integrated circuit device 20 can be enhanced.

[0073] Reference Figure 4 In an integrated circuit device 30 according to some example embodiments, the spacing structure 130A may include a first spacing portion 132A and a second spacing portion 134A, which are sequentially disposed on the sidewall of the gate electrode 120, and the bottom of the first spacing portion 132A and the bottom of the second spacing portion 134A may extend horizontally on the upper surface of each of the plurality of semiconductor patterns NS.

[0074] The second spacing portion 134A may include a lateral extension portion 134W, and the bottom of the first spacing portion 132A may be disposed between the lateral extension portion 134W and the uppermost semiconductor pattern NS.

[0075] In the integrated circuit 30 according to some example embodiments, because the spacing between the source / drain region 140 and the main gate electrode 120M is relatively large due to the increased width of the spacing structure 130A at its bottom, leakage current such as GIDL between the source / drain region 140 and the main gate electrode 120M can be prevented or reduced.

[0076] Reference Figure 5 In an integrated circuit device 40 according to some example embodiments, a plurality of semiconductor patterns NW may include a first semiconductor pattern NW1, a second semiconductor pattern NW2 and a third semiconductor pattern NW3, which are arranged in the order described above from the upper surface 110M of the substrate 110.

[0077] Multiple semiconductor patterns NW can each include a circular cross-section and / or an elliptical cross-section, and may each have a nanowire shape, for example. Furthermore, the first semiconductor pattern NW1 may have a diameter r11 of about 1 nm to about 10 nm, the second semiconductor pattern NW2 may have a diameter r12 of about 1 nm to about 10 nm, and the third semiconductor pattern NW3 may have a diameter r13 of about 1 nm to about 20 nm.

[0078] like Figure 5As shown, the diameter r13 of the third semiconductor pattern NW3 can be larger than the diameter r11 of the first semiconductor pattern NW1 and the diameter r12 of the second semiconductor pattern NW2; however, the example embodiment is not limited thereto.

[0079] Figures 6 to 15B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some example embodiments.

[0080] Specifically, Figure 6 , Figure 7A , Figure 8A , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 13A , Figure 14A and Figure 15A Shown in the order of processes and along Figure 1 The vertical cross-section diagram corresponding to the section intercepted by line A1-A1′ in the diagram. Figure 7B , Figure 8B , Figure 14B and Figure 15B Shown in the order of processes and along Figure 1 The vertical cross-section diagram corresponding to the section intercepted by line B1-B1′ in the diagram, and Figure 12B and Figure 13B Show Figure 12A and Figure 13A A cross-sectional view at the first level LV1.

[0081] Reference Figure 6 A sacrificial layer 210 and a channel semiconductor layer PNS can be alternately and sequentially formed on the upper surface 110M of the substrate 110, thereby forming a sacrificial layer stack 210S.

[0082] The sacrificial layer 210 and the channel semiconductor layer PNS can be formed by an epitaxial process. In some example embodiments, both the sacrificial layer 210 and the channel semiconductor layer PNS may comprise materials that are etch-selective relative to each other. For example, each of the sacrificial layer 210 and the channel semiconductor layer PNS may comprise a single-crystal layer comprising at least one of a group IV semiconductor and a group IV-IV compound semiconductor or a group III-V compound semiconductor, and the sacrificial layer 210 and the channel semiconductor layer PNS may comprise different materials. For example, the sacrificial layer 210 may comprise SiGe, and the channel semiconductor layer PNS may comprise crystalline silicon (e.g., single-crystal silicon without any other germanium).

[0083] In some example embodiments, the epitaxial process may be or may include molecular beam epitaxy and / or chemical vapor deposition (CVD) processes (e.g., vapor phase epitaxy (VPE) or ultra-high vacuum chemical vapor deposition (UHV-CVD), or combinations thereof). In the epitaxial process, liquid and / or gaseous precursors may be used as precursors required to form the sacrificial layer 210 and the channel semiconductor layer PNS.

[0084] Reference Figure 7A and Figure 7B A hard mask pattern (not shown) extending a specific length in a first direction (X direction) can be formed on the channel semiconductor layer PNS. Then, the sacrificial layer pattern 210P and the isolation trench 114T can be formed by etching the sacrificial layer 210, the channel semiconductor layer PNS and the substrate 110 using the hard mask pattern as an etching mask.

[0085] Subsequently, insulating material can be filled into the isolation trench 114T, and then an isolation layer 114 filled into the isolation trench 114T can be formed by planarizing the upper part of the insulating material, for example by using a chemical mechanical planarization (CMP) process and / or an etch-back process. The fin-type active region FA can be defined in the substrate 110 by the isolation layer 114.

[0086] Subsequently, the hard mask pattern retained on the sacrificial layer pattern 210P can be removed, and then a recessed process can be performed to remove a portion of the isolation layer 114 by a certain thickness from its upper surface. In some example embodiments, the recessed process can be performed on the upper surface of the isolation layer 114 such that the upper surface of the isolation layer 114 is arranged at the same horizontal line as the upper surface 110M of the substrate 110. Alternatively or additionally, a portion of the sidewalls of the fin-type active region FA can be exposed by performing the recessed process such that the upper surface of the isolation layer 114 is arranged at a lower horizontal line than the upper surface 110M of the substrate 110.

[0087] refer to Figure 8A and Figure 8B The dummy gate structure DG can be formed on the sacrificial layer pattern 210P and the isolation layer 114. The dummy gate structure DG may include a dummy gate dielectric layer DGI, a dummy gate line DGL, and a dummy gate capping layer DGC.

[0088] For example, the dummy gate line DGL may include doped or undoped polysilicon, and the dummy gate capping layer DGC may include silicon nitride. The dummy gate dielectric layer DGI may include a material having an etch selectivity corresponding to the dummy gate line DGL, and may include, for example, at least one material selected from thermal oxides, silicon oxide, or silicon nitride.

[0089] The dummy gate dielectric layer (DGI) may include a protruding sidewall (DGI_OS) that protrudes beyond the sidewall of the dummy gate structure (DG). For example, when the height of the dummy gate structure (DG) is relatively large, a portion of the dummy gate dielectric layer (DGI) may be retained without being removed in the etching environment, and therefore, the protruding sidewall (DGI_OS) of the dummy gate dielectric layer (DGI) may protrude further outward than the sidewall of the dummy gate line (DGL).

[0090] Reference Figure 9 By performing the removal of the protruding sidewalls DGI_OS of the dummy gate dielectric layer DGI (see...) Figure 8A With the additional etching process, the dummy gate dielectric layer DGI can be formed to include recessed sidewall DGI_IS.

[0091] The recessed sidewall DGI_IS may include a portion that is recessed further inward than the sidewall of the dummy gate line DGL. In some example embodiments, the protruding sidewall DGI_OS of the dummy gate dielectric layer DGI is removed (see [link to example]). Figure 8A The additional etching process may include and / or utilize a wet etching process, which may be an isotropic etching process. Therefore, the recessed sidewall DGI_IS can have a circular shape. The wet etching process can be controlled to limit etching to areas outside the dummy gate dielectric layer DGI.

[0092] Reference Figure 10 The first spacer layer 132L, the second spacer layer 134L, and the cover spacer layer 136L can be sequentially formed on the dummy gate structure DG. The first spacer layer 132L, the second spacer layer 134L, and the cover spacer layer 136L can be formed using a chemical vapor deposition (CVD) process such as plasma-enhanced chemical vapor deposition (PECVD).

[0093] Each of the first spacer layer 132L and the second spacer layer 134L may comprise silicon nitride or silicon oxynitride, and the covering spacer layer 136L may comprise silicon oxide. However, the inventive concept is not limited thereto.

[0094] The first spacer layer 132L can be conformally formed on the recessed sidewall DGI_IS of the dummy gate dielectric layer DGI (see [link]). Figure 9 Therefore, the first spacer layer 132L and the recessed sidewall DGI_IS of the dummy gate dielectric layer DGI (see...) Figure 9 The contact portion can correspond to the circular protrusion 132P (see...) Figure 2C ).

[0095] Reference Figure 11 It can be achieved through the first spacer layer 132L (see Figure 10), second spacer layer 134L (see Figure 10 ), and covering spacer layer 136L (see Figure 10 An isotropic etching process is performed on the dummy gate structure DG to form a spacer structure 130 on both sides of the dummy gate structure DG.

[0096] In an isotropic etching process, the covering spacer layer 136L disposed on the upper surface of the dummy gate structure DG and the upper surface of the sacrificial layer pattern 210P can be removed together (see [link to original text]). Figure 10 The spacer structure 130 may include a first spacer portion 132 and a second spacer portion 134, which are sequentially disposed on the sidewall of the dummy gate structure DG, and the bottom surface of the second spacer portion 134 may be surrounded by the first spacer portion 132.

[0097] The accompanying drawings show the covering spacer layer 136L (see attached drawings). Figure 10 The second spacer 134 is completely removed and its sidewalls are not covered, but the inventive concept is not limited thereto. For example, a portion of the spacer layer 136L may be covered (see [link to documentation]). Figure 10 The covering spacer 136L can be retained on at least a portion of the sidewall of the second spacer 134. In this case, removal of the covering spacer 136L (see...) can also be performed. Figure 10 Additional etching process is required. Alternatively, removal of the cover spacer layer 136L (see [reference]) may be omitted. Figure 10 The additional etching process can remove the remaining portion of the covering spacer layer 136L together with the subsequent process that forms the recessed region RS1 (see [link]). Figure 10 ).

[0098] Reference Figure 12A and Figure 12B This can be achieved by etching the substrate 110 and the sacrificial layer pattern 210P (see...). Figure 11 A recessed region RS1 is formed on both sides of the dummy gate structure DG, at a portion of the spacer structure 130 and the dummy gate structure DG.

[0099] When the recessed region RS1 is formed, the sacrificial layer pattern 210P (see...) Figure 11 The semiconductor pattern NS can be separated into multiple semiconductor patterns NS. For example, the multiple semiconductor patterns NS may include a first semiconductor pattern NS1 to a third semiconductor pattern NS3 separated from each other by the sacrificial layer 210.

[0100] In some example embodiments, during the process of forming the recessed region RS1, instead of removing the portion of the uppermost semiconductor pattern NS (e.g., the third semiconductor pattern NS3) that overlaps with the spacer structure 130, the portion of another semiconductor pattern NS (e.g., the second semiconductor pattern NS2 and / or the first semiconductor pattern NS1) that overlaps with the spacer structure 130 can be removed. The center width of the recessed region RS can be greater than the top width of the recessed region RS1, and the plurality of semiconductor patterns NS and the plurality of sacrificial layers 210 can all include inclined surfaces disposed at the portions overlapping with the spacer structure 130.

[0101] In the process of forming the spacer structure 130, the second spacer layer 134L (see...) Figure 10 The upper surface of the ) can be covered with a spacer layer 136L (see Figure 10 Therefore, the width d11 of the spacer structure 130 retained in the anisotropic etching process in the first direction (X direction) can be relatively large (see...). Figure 12B For example, when the width d11 of the second spacer 134 in the first direction (X direction) is relatively large, the portion of the sacrificial layer 210 adjacent to the spacer structure 130 may be less exposed to the etching environment during the process of forming the recessed region RS1. Therefore, an inclined surface of the sacrificial layer 210 can be formed. In addition, since the first spacer 132 may include a circular protrusion 132P, the spacing distance between the recessed region RS1 and the dummy gate structure DG can be increased relatively more.

[0102] Reference Figure 13A and Figure 13B The source / drain region 140 can be formed by sequentially forming a first semiconductor layer 142 and a second semiconductor layer 144 in the recessed region RS1.

[0103] The first semiconductor layer 142 and the second semiconductor layer 144 can be formed by epitaxially growing semiconductor material from the surface of the substrate 110, the sacrificial layer 210, and a plurality of semiconductor patterns NS exposed at the inner wall of the recessed region RS1. The first semiconductor layer 142 and the second semiconductor layer 144 may include at least one of an epitaxially grown Si layer, an epitaxially grown SiC layer, an epitaxially grown SiGe layer, or an epitaxially grown SiP layer. During the epitaxial process, other dopants such as boron can be incorporated into the first semiconductor layer 142 and the second semiconductor layer 144.

[0104] like Figure 13B As shown, the first width WE of the first semiconductor layer 142 in the second direction (Y direction) can be greater than or equal to the second width WC of the middle portion of the first semiconductor layer 142 in the first direction (X direction). This can be obtained as a result of epitaxial growth, but the inventive concept is not limited thereto.

[0105] Subsequently, a gate insulating liner 152 and an inter-gate insulating layer 154 can be sequentially formed on the sidewalls of the spacer structure 130 and the source / drain region 140. The gate insulating liner 152 and the inter-gate insulating layer 154 can be formed by a CVD process such as PECVD. However, the example embodiment is not limited thereto. By planarizing the upper portion, gate insulating liner 152, and inter-gate insulating layer 154 of each dummy gate structure DG in the dummy gate structure DG, for example, using a CMP process and / or an etch-back process, the dummy gate capping layer DGC of the dummy gate structure DG can be removed (see...). Figure 12A It can also expose the upper surface of the dummy gate line DGL.

[0106] Reference Figure 14A and Figure 14B This can be achieved by removing the dummy gate lines DGL, which are all exposed via the inter-gate insulating layer 154 (see [link]). Figure 13A ) and Dummy Gate Dielectric Layer (see Figure 13A To form the main gate electrode space GS.

[0107] Subsequently, the multiple sacrificial layers 210 retained in the finned active region FA can be removed by passing through the main gate electrode space GS (see...). Figure 13A This exposes a portion of the upper surface of each of the multiple semiconductor patterns NS and a portion of the upper surface of the fin active region FA. Therefore, a sub-gate electrode space GSS can be formed between adjacent semiconductor patterns NS and between the lowermost semiconductor pattern NS and the fin active region FA. The process of removing the multiple sacrificial layers 210 can be achieved by using sacrificial layers 210 (see...) Figure 13A A wet etching process or including the etching selectivity difference between each semiconductor pattern NS in a plurality of semiconductor patterns NS.

[0108] Because the width d11 of the spacer structure 130 in the first direction (X direction) is relatively large and the first spacer portion 132 includes a circular protrusion 132P, the upper surface of the source / drain region 140 may not be exposed at the main gate electrode space GS during the removal of the dummy gate line DGL (see...). Figure 13A ).

[0109] For example, when the source / drain region 140 and the dummy gate line DGL (see...) Figure 13A When the spacing between them is relatively small, the dummy gate line DGL is removed (see...). Figure 13AIn the process, the edge portion of the source / drain region 140 may also be exposed to the etching environment, and errors may occur in removing or partially removing the source / drain region 140 and / or filling the removed portion with gate electrode material.

[0110] However, since the width d11 of the spacer structure 130 in the first direction (X direction) is relatively large and the first spacer portion 132 includes a circular protrusion 132P, the removal of the dummy gate line DGL (see...) Figure 13A In the process of ), defects can be greatly prevented from occurring.

[0111] Reference Figure 15A and Figure 15B It can be exposed in the main gate electrode space GS (see Figure 14A ) and sub-gate electrode space GSS (see Figure 14A A gate dielectric layer 128 is formed on each surface of the gate dielectric layer.

[0112] Subsequently, a space GS filled into the main gate electrode space can be formed on the gate dielectric layer 128 (see...). Figure 14A ) and sub-gate electrode space GSS (see Figure 14A The gate electrode 120 is located in the main gate electrode space GS. For example, a work function control layer (not shown) can be located in the main gate electrode space GS (see [reference]). Figure 14A ) and sub-gate electrode space GSS (see Figure 14A Each of the layers is conformally formed on its inner wall, and then a buried conductive layer (not shown) can be formed on the work function control layer to fill the main gate electrode space GS (see [link to main gate electrode space]). Figure 14A ) and sub-gate electrode space GSS (see Figure 14A ).

[0113] Subsequently, the gate electrode 120 can be formed by planarizing the upper part of the buried conductive layer to expose the upper surface of the inter-gate insulating layer 154. Planarization may include at least one of a CMP process or an etch-back process.

[0114] Refer again Figure 2A An upper insulating layer 162 can be formed, and a contact hole 166H can then be formed through the upper insulating layer 162. A contact plug 166 can then be formed by filling the contact hole 166H with a conductive material. By performing such a process, an integrated circuit device 10 according to the embodiment can be manufactured.

[0115] Figure 16 This is a perspective view showing an integrated circuit device 50 according to some example embodiments.

[0116] Reference Figure 16The integrated circuit device 50 may include a source / drain region 140 and a gate structure 120GS, which are formed as heterogeneous and / or homogeneous epitaxial growth layers disposed on the upper surface of the fin-type active region FA in the substrate 110.

[0117] The integrated circuit device 50 may include a field-effect transistor with a fin structure. Unlike a field-effect transistor with a two-dimensional structure, such as a planar structure, a field-effect transistor with a fin structure may have the characteristic that the source / drain region 140 is not limited by the isolation layer 114.

[0118] The gate structure 120GS may include a gate electrode 120 and a gate dielectric layer 128. The middle portion of the gate electrode 120 may have a first width W1 in a first direction (X direction), and the bottom of the gate electrode 120 may have a second width W2 in the first direction (X direction) that is smaller than the first width W1.

[0119] A circular inclined surface 120SI may be formed at the bottom of the gate electrode 120, and the first spacer portion 132 of the spacer structure 130 may fill the space defined by the circular inclined surface 120SI and the upper surface of the isolation layer 114. For example, the first spacer portion 132 may include a circular protrusion 132P disposed at its bottom, and the circular protrusion 132P may fill the space defined by the circular inclined surface 120SI and the upper surface of the isolation layer 114.

[0120] The gate dielectric layer 128 may be disposed between the circular inclined surface 120SI and the circular protrusion 132P. The circular inclined surface 120SI of the gate electrode 120 may vertically overlap with a portion of the spacer structure 130 (e.g., the circular protrusion 132P of the first spacer 132).

[0121] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: The fin-shaped active region protrudes from the substrate and extends in the first direction; Multiple semiconductor patterns are separated from the upper surface of the fin-shaped active region; A gate electrode, surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, the gate electrode comprising: The main gate electrode extends on the uppermost semiconductor pattern of the plurality of semiconductor patterns and in the second direction. Sub-gate electrode, located between two semiconductor patterns in the plurality of semiconductor patterns; A gate dielectric layer is formed between the plurality of semiconductor patterns and the gate electrode, the gate dielectric layer being formed to include recessed sidewalls; Spacing structures are provided on the first sidewall and the second sidewall of the main gate electrode; and The source / drain regions are located at corresponding sides of the plurality of semiconductor patterns, respectively, on the first and second sides of the gate electrode, and are in contact with the bottom surface of the spacer structure. Wherein, the middle portion of the main gate electrode has a first width in the first direction. The bottom of the main gate electrode has a second width in the first direction that is smaller than the first width. The spacing between the middle portions of adjacent source / drain regions in the first direction has a third width that is smaller than the second width. The sub-gate electrode has a fourth width in the first direction that is smaller than the first width. The spacing structure includes a first spacing portion and a second spacing portion. The first spacing portion is disposed on each of the first sidewall and the second sidewall of the main gate electrode. The second spacing portion is disposed on the sidewall of the first spacing portion and its bottom surface is surrounded by the first spacing portion. The first spacing portion includes a protrusion that protrudes away from the first sidewall and the second sidewall in the first direction. The portion of the first spacer that contacts the recessed sidewall of the gate dielectric layer corresponds to the protrusion.

2. The integrated circuit device according to claim 1, wherein, The main gate electrode includes a circular inclined surface extending from the bottom of the main gate electrode to at least one of the first sidewall or the second sidewall of the main gate electrode, the circular inclined surface being inclined relative to a third direction perpendicular to each of the first and second directions.

3. The integrated circuit device according to claim 2, wherein, The circular inclined surface of the main gate electrode vertically overlaps with a portion of the spacing structure.

4. The integrated circuit device according to claim 3, wherein, The first gap fills the space defined by the circular inclined surface of the main gate electrode and the upper surface of the uppermost semiconductor pattern.

5. The integrated circuit device according to claim 1, wherein, The source / drain region includes: A first semiconductor layer on the inner wall of the recessed region, the recessed region being located within the fin-type active region, the recessed region being located on both sides of the gate electrode; and A second semiconductor layer is placed on the first semiconductor layer, the second semiconductor layer filling the recessed region, and The upper surface of the first semiconductor layer is in contact with the bottom surface of the spacer structure.

6. The integrated circuit device according to claim 5, wherein, Each of the first and second semiconductor layers comprises epitaxial silicon-germanium (SiGe), and The concentration of germanium (Ge) in the first semiconductor layer is lower than the concentration of Ge in the second semiconductor layer.

7. The integrated circuit device according to claim 6, wherein, The first semiconductor layer also includes impurities not present in the second semiconductor layer.

8. The integrated circuit device according to claim 5, wherein, The first semiconductor layer includes a third upward inclined surface perpendicular to each of the first and second directions, the inclined surface being inclined from the upper surface of the first semiconductor layer toward the middle of the first semiconductor layer.

9. The integrated circuit device according to claim 8, wherein, At least a portion of the inclined surface of the first semiconductor layer vertically overlaps with at least one sidewall of the first sidewall or the second sidewall of the main gate electrode, and A portion of the inclined surface of the first semiconductor layer vertically overlaps with the bottom of the main gate electrode.

10. The integrated circuit device according to claim 5, wherein, In the plan view, the first width of the first semiconductor layer in the second direction is greater than or equal to the second width of the middle portion of the first semiconductor layer in the first direction.

11. An integrated circuit device, comprising: The fin-shaped active region protrudes from the substrate and extends in the first direction; Multiple semiconductor patterns are separated from the upper surface of the fin-shaped active region; A gate electrode, surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, the gate electrode comprising: The main gate electrode extends on the uppermost semiconductor pattern of the plurality of semiconductor patterns and in the second direction. Sub-gate electrode, located between two semiconductor patterns in the plurality of semiconductor patterns; A gate dielectric layer is formed between the plurality of semiconductor patterns and the gate electrode, the gate dielectric layer being formed to include recessed sidewalls; A spacer structure is disposed on the first and second sidewalls of the main gate electrode; and The source / drain regions are located at corresponding sides of the plurality of semiconductor patterns, respectively, on the first and second sides of the gate electrode, and are in contact with the bottom surface of the spacer structure. The main gate electrode includes a circular inclined surface that slopes from the lower part of the main gate electrode toward at least one of the first sidewall or the second sidewall of the main gate electrode, the circular inclined surface being inclined relative to a third direction perpendicular to the upper surface of the substrate. The spacing structure includes a first spacing portion and a second spacing portion. The first spacing portion is disposed on each of the first sidewall and the second sidewall of the main gate electrode. The second spacing portion is disposed on the sidewall of the first spacing portion and its bottom surface is surrounded by the first spacing portion. The first spacing portion includes a protrusion that protrudes away from the first sidewall and the second sidewall in the first direction. The portion of the first spacer that contacts the recessed sidewall of the gate dielectric layer corresponds to the protrusion.

12. The integrated circuit device according to claim 11, wherein, The middle portion of the main gate electrode has a first width in the first direction. The bottom of the main gate electrode has a second width in the first direction that is smaller than the first width, and The spacing between the middle portions of adjacent source / drain regions has a third width in the first direction that is smaller than the second width.

13. The integrated circuit device according to claim 12, wherein, The uppermost semiconductor pattern has a top width in the first direction, and the lower part of the uppermost semiconductor pattern has a bottom width in the first direction. The second width is less than the top width but greater than the bottom width.

14. The integrated circuit device according to claim 11, wherein, The first spacing portion is conformal along the sidewall of the main gate electrode, the circular inclined surface of the main gate electrode, and the upper surface of the uppermost semiconductor pattern.

15. The integrated circuit device according to claim 11, wherein, The source / drain region includes: A first semiconductor layer on the inner wall of the recessed region, the recessed region being located on the first side and the second side of the gate electrode in the fin-type active region; and A second semiconductor layer is placed on the first semiconductor layer, the second semiconductor layer filling the recessed region, and The first semiconductor layer includes a third-side-up inclined surface that slopes from the upper surface of the first semiconductor layer toward the middle of the first semiconductor layer.

16. An integrated circuit device, comprising: The fin-shaped active region protrudes from the substrate and extends in the first direction; Multiple semiconductor patterns are separated from the upper surface of the fin-shaped active region; A gate electrode, extending around the plurality of semiconductor patterns and in a second direction perpendicular to the first direction, comprises: The main gate electrode extends on the uppermost semiconductor pattern of the plurality of semiconductor patterns and in the second direction. Sub-gate electrode, located between two semiconductor patterns in the plurality of semiconductor patterns; A gate dielectric layer is formed between the plurality of semiconductor patterns and the gate electrode, the gate dielectric layer being formed to include recessed sidewalls; A spacing structure is disposed on the first sidewall and the second sidewall of the main gate electrode; A pair of source / drain regions at corresponding sides of the plurality of semiconductor patterns, the pair of source / drain regions being located on a first side and a second side of the gate electrode, respectively, and the pair of source / drain regions contacting the bottom surface of the spacer structure; and Contact plugs are electrically connected to the pair of source / drain regions. Wherein, the middle portion of the main gate electrode has a first width in the first direction. The bottom of the main gate electrode has a second width in the first direction that is smaller than the first width. The spacing between the middle portions of the pair of source / drain regions has a third width in the first direction that is smaller than the second width. The main gate electrode includes a circular inclined surface that slopes from the bottom of the main gate electrode toward at least one of the first sidewall or the second sidewall of the main gate electrode, the circular inclined surface being inclined relative to a third direction perpendicular to the upper surface of the substrate. The spacing structure includes a first spacing portion and a second spacing portion. The first spacing portion is disposed on each of the first sidewall and the second sidewall of the main gate electrode. The second spacing portion is disposed on the sidewall of the first spacing portion and its bottom surface is surrounded by the first spacing portion. The first spacing portion includes a protrusion that protrudes away from the first sidewall and the second sidewall in the first direction. The portion of the first spacer that contacts the recessed sidewall of the gate dielectric layer corresponds to the protrusion.

17. The integrated circuit device according to claim 16, wherein, Each of the pair of source / drain regions includes: A first semiconductor layer on the inner wall of the recessed region, the recessed region being located on both sides of the gate electrode in the fin-type active region; and A second semiconductor layer is placed on the first semiconductor layer, the second semiconductor layer filling the recessed region, and The upper surface of the first semiconductor layer is in contact with the bottom surface of the spacer structure.

18. The integrated circuit device according to claim 17, wherein, Each of the first and second semiconductor layers comprises epitaxial silicon-germanium (SiGe). The concentration of germanium (Ge) in the first semiconductor layer is lower than the concentration of Ge in the second semiconductor layer, and The first semiconductor layer also includes impurities not present in the second semiconductor layer.

19. The integrated circuit device according to claim 17, wherein, The second semiconductor layer is in contact with the contact plug.

20. The integrated circuit device according to claim 17, wherein, In the plan view, the first width of the first semiconductor layer in the second direction is greater than or equal to the second width of the middle portion of the first semiconductor layer in the first direction.

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