IGBT power semiconductor devices

Abstract

This invention discloses a novel IGBT power semiconductor device, comprising: a substrate; a buffer zone disposed on the substrate; a base region disposed on the buffer zone; and a plurality of true gate units disposed on the base region, wherein each true gate unit has dummy trench units on both sides, and the contact holes of each true gate unit are connected to the contact holes of the adjacent dummy trench units on both sides. This invention can increase the source region width, improve process consistency, and enhance the consistency and uniformity of device characteristics such as threshold voltage within the wafer, thereby solving the device manufacturability problem.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a novel IGBT power semiconductor device. Background Technology

[0002] With technological advancements, IGBTs have undergone numerous iterations. For instance, the back surface of the IGBT has evolved from a thick PT (potentially parabolic) sheet to a thin NPT (non-potentially parabolic) sheet, and then further upgraded to an ultra-thin FS (field termination) sheet. Similarly, the front surface of the IGBT has evolved from a planar structure to a trench type, and then further upgraded to... Figure 1 The microtrench structure is shown. However, as the unit cell size of the trench structure shrinks to less than 2 μm and the current density per unit area increases significantly, its short-circuit and RBSOA capabilities weaken.

[0003] To solve the above problems, some people have proposed using Figure 2 The pseudo-groove structure shown, even Figure 3 The structure shown is a hybrid of dummy trench and dummy gate to replace part of the real gate to reduce the effective channel and improve short-circuit and RBSOA capabilities. However, due to its small unit cell size, the distance between its contact hole and gate trench is also very small, generally less than 0.5um. In addition, the drift of the hole photolithography process and the loading effect of the etching process can further lead to poor device consistency and uniformity, posing a challenge to the manufacturability of the device. Summary of the Invention

[0004] The present invention aims to at least partially solve one of the technical problems in the aforementioned technologies. Therefore, the object of the present invention is to propose a novel IGBT power semiconductor device that can increase the source region width, improve process consistency, and enhance the consistency and uniformity of device characteristics such as threshold voltage within the wafer, thereby solving the device's manufacturability problem.

[0005] To achieve the above objectives, this invention proposes a novel IGBT power semiconductor device, comprising: a substrate; a buffer zone disposed on the substrate; a base region disposed on the buffer zone; and a plurality of true gate units disposed on the base region, wherein each true gate unit has dummy trench units on both sides, and the contact hole of each true gate unit is connected to the contact holes of the adjacent dummy trench units on both sides.

[0006] The novel IGBT power semiconductor device proposed in this embodiment of the invention, by setting a substrate and sequentially setting a buffer zone, a base region and a plurality of true gate units on the substrate, wherein each true gate unit has dummy trench units on both sides, and the contact hole of each true gate unit is connected to the contact hole of the adjacent dummy trench units on both sides, thereby increasing the source region width, improving the consistency of the process, and improving the consistency and uniformity of the device's threshold voltage and other characteristics within the wafer, thus solving the manufacturability problem of the device.

[0007] In addition, the novel IGBT power semiconductor device proposed according to the above examples of the present invention may also have the following additional technical features:

[0008] According to one embodiment of the present invention, the contact hole of each true gate unit is not discontinuously connected to the contact holes of the adjacent two sides of the dummy trench units, so as to form a plurality of equally spaced merged contact holes on both sides of each true gate unit.

[0009] According to one embodiment of the present invention, a well region is further provided between each true gate cell and the adjacent two dummy trench cells, and the well region is disposed on the base region.

[0010] According to one embodiment of the present invention, each of the true gate cells is further provided with source regions on both sides, and the source regions are disposed on the well region.

[0011] According to one embodiment of the present invention, the source region is connected to the dummy trench unit through the merged contact hole.

[0012] According to one embodiment of the present invention, each of the true gate units is further provided with an emitter, and the emitter is connected to a plurality of equally spaced merging contact holes formed on both sides of each true gate unit.

[0013] According to one embodiment of the present invention, the substrate is an N-type substrate.

[0014] According to one embodiment of the present invention, the well region is a P-type well region.

[0015] According to one embodiment of the present invention, the source region is N. + Source region. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a micro-groove IGBT in the prior art;

[0017] Figure 2 This is a schematic diagram of the structure of a pseudo-groove IGBT in the prior art;

[0018] Figure 3This is a schematic diagram of the structure of a micro-trench IGBT that combines dummy trenches and dummy gates in the prior art;

[0019] Figure 4 This is a schematic diagram of the structure of the novel IGBT power semiconductor device according to an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of the structure of a novel IGBT power semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Figure 4 This is a schematic diagram of the structure of a novel IGBT power semiconductor device according to an embodiment of the present invention.

[0023] like Figure 4 As shown, the novel IGBT power semiconductor device of this invention includes: a substrate 10; a buffer zone 20 disposed on the substrate 10; a base region 30 disposed on the buffer zone 20; and a plurality of true gate units 40 disposed on the base region 30, wherein each true gate unit 40 has a dummy trench unit 50 on both sides, and the contact hole of each true gate unit 40 is connected to the contact hole of the adjacent dummy trench unit 50 on both sides.

[0024] Specifically, such as Figure 5 As shown, the contact holes of each true gate cell 40 are not discontinuously connected to the contact holes of the adjacent dummy trench cells 50 on both sides, so as to form a plurality of equally spaced merged contact holes 100 on both sides of each true gate cell 40. This increases the source region width, improves process consistency, and enhances the consistency and uniformity of device characteristics such as threshold voltage within the wafer, thereby solving the device manufacturability problem. Each true gate cell 40 includes a gate contact hole 200 and a gate.

[0025] In one embodiment of the present invention, the substrate 10 may be an N-type substrate, specifically, an N-type single-crystal silicon substrate. Furthermore, in other embodiments of the present invention, the substrate 10 may be other semiconductor materials, such as polycrystalline silicon or amorphous silicon. Additionally, it may be a hybrid semiconductor structure, such as silicon carbide, alloy semiconductors, or combinations thereof, without limitation herein.

[0026] In another embodiment of the present invention, the contact holes of each true gate unit 40 are not discontinuously connected to the contact holes of the adjacent two-sided dummy trench units 50. Multiple non-equally spaced merged contact holes 100 can be formed on both sides of each true gate unit 40. This increases the distance from the plug holes on both sides of each true gate unit 40 to the gate, thereby ensuring the threshold voltage characteristics of the device and ensuring the consistency and uniformity of the wafer in the device.

[0027] In one embodiment of the present invention, the buffer 20 may be a SiC buffer, epitaxially formed on the substrate 10. Further, a base region 30 may be epitaxially formed on the buffer 20. The buffer 20 may be an N-type SiC buffer, and the base region 30 may be an N-type base region. In other embodiments of the present invention, the buffer and base region may be configured as other types; for example, the buffer 20 may be a P-type SiC buffer, which is not limited here.

[0028] Furthermore, such as Figure 4 As shown, each true gate cell 40 is further provided with a well region 60 between it and the adjacent two dummy trench cells 50, and the well region 60 is disposed on the base region 30. The well region 60 may be a P-type well region.

[0029] Furthermore, such as Figure 4 As shown, each true gate cell 40 is further provided with source regions 70 on both sides, and the source regions 70 are disposed on the well region 60. The source regions 70 can be N + The source region can be specifically located in the well region 60 between the true gate cell 40 and the adjacent dummy trench cell 50, for example, on a P-type well region. Further, as... Figure 4 As shown, the source region 70 can be connected to the dummy trench unit 50 through the merging contact hole 100, thereby increasing the width of the source region, which can ensure the threshold voltage characteristics of the device and ensure the consistency and uniformity of the wafer in the device.

[0030] Furthermore, such as Figure 4 As shown, each true gate cell 40 is also provided with an emitter 80, which is connected to multiple equally spaced merged contact holes 100 formed on both sides of each true gate cell 40. It should be further noted that, as... Figure 5 As shown, the width of each merged contact hole 100 and the spacing between adjacent merged contact holes 100 are not unique and can be adjusted according to actual production conditions. For example, the width a of the merged contact holes 100 arranged at equal intervals on both sides of each true gate unit 40, the longitudinal spacing b between the equally spaced merged contact holes 100, and the diagonal spacing c between the staggered merged contact holes 100 can all be adjusted according to actual production conditions.

[0031] It should be further noted that the fabrication process of the novel IGBT power semiconductor device proposed in this invention is consistent with that of the existing micro-trench gate IGB, and no additional process is required, thereby avoiding the increase in production costs caused by process improvements.

[0032] For example, the fabrication process of the novel IGBT power semiconductor device proposed in this invention is as follows: 1. Implanting and pushing junctions to form a P-type PW conductive layer; 2. Implanting and pushing junctions on both sides of the true gate cell to form an N-type conductive layer. + Source region, the rest are without N + 3. The true gate cell is connected to the emitter through a contact hole; 4. The dummy trench cell is connected to the emitter through a contact hole connected to the true gate cell.

[0033] The novel IGBT power semiconductor device proposed in this embodiment of the invention, by setting a substrate and sequentially setting a buffer zone, a base region and a plurality of true gate units on the substrate, wherein each true gate unit has dummy trench units on both sides, and the contact hole of each true gate unit is connected to the contact hole of the adjacent dummy trench units on both sides, thereby increasing the source region width, improving the consistency of the process, and improving the consistency and uniformity of the device's threshold voltage and other characteristics within the wafer, thus solving the manufacturability problem of the device.

[0034] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0035] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0036] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0037] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0038] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An IGBT power semiconductor device, characterized by, The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions. The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions. The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions. The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions. The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions. The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions.

2. The IGBT power semiconductor device according to claim 1, characterized in that, The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions.

3. The IGBT power semiconductor device according to claim 2, characterized in that, The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions.

4. The IGBT power semiconductor device according to claim 3, characterized in that The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions. The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions.

5. The IGBT power semiconductor device according to claim 4, characterized in that, The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions.

6. The IGBT power semiconductor device according to claim 5, characterized in that The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions.

7. The IGBT power semiconductor device according to claim 6, characterized in that, The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions. The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions. The application relates to a substrate, a buffer region, a base region, a plurality of true gate units, a plurality of false trench units, a plurality of merged contact holes, a plurality of source regions, a plurality of emitter regions, and a plurality of well regions 8. The IGBT power semiconductor device according to claim 7, characterized in that, The source region is N + Source region.

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