Semiconductor device

Abstract

This disclosure relates to semiconductor devices. The provided fin field-effect transistor device includes a channel region comprising a constituent element and excess atoms, wherein the constituent element belongs to a group of the periodic table, and the excess atoms are nitrogen or belong to that group of the periodic table, and the concentration of excess atoms in the channel region is between about 10. 19 cm ‑3 To about 10 20 cm ‑3 between.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to semiconductor manufacturing, and more particularly to apparatus and manufacturing methods employing ion implantation. Background Technology

[0002] In recent developments in the semiconductor industry, fin field-effect transistors (FETs) have replaced planar transistors. In a fin field-effect transistor, the transistor channel is essentially formed within a structure with a high aspect ratio (often called a fin). The gate of the fin field-effect transistor covers not only the top of the fin but also its sides. This configuration offers several advantages over planar transistors, including higher reliability at the same performance and better control over channel reversal. Summary of the Invention

[0003] In one embodiment, the semiconductor device includes a transistor and an isolation region adjacent to the transistor. The transistor has a channel region containing a constituent element and excess atoms, wherein the constituent element belongs to a group of the periodic table, and the excess atom is nitrogen, or belongs to that group of the periodic table. The concentration of excess atoms in the channel region is between approximately 10⁻⁶. 19 cm -3 To about 10 21 cm -3 Between. The isolation region also contains excess atoms, and the concentration of excess atoms in the isolation region is between approximately 10. 20 cm -3 To about 10 21 cm -3 between.

[0004] In one embodiment, the semiconductor device includes a gate, wherein the upper width of the gate is greater than 1 nm than the lower width of the gate, a channel region comprising a constituent element and excess atoms, the constituent element belonging to a group of the periodic table, and the excess atoms being nitrogen or belonging to that group of the periodic table, and the excess atom concentration in the channel region being between about 10. 19 cm -3 To about 10 21 cm -3 between.

[0005] In one embodiment, the channel region of the fin field-effect transistor includes constituent elements belonging to a group of the periodic table, and the method of fabricating the fin field-effect transistor includes: placing a channel masking structure on a first portion of the fin to cover the first portion of the fin, the channel masking structure not covering a second portion of the fin, and the first portion of the fin including at least a portion of the channel region, performing a first ion implantation of nitrogen or an element belonging to that group of the periodic table, and annealing the first ion implantation. Attached Figure Description

[0006] Figure 1This is a simplified perspective view of a selected cell in a structure containing two fin field-effect transistors during a stage of the fin field-effect transistor manufacturing process.

[0007] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B This is a simplified cross-sectional view of a selected fin field-effect transistor structure during various stages of the fin field-effect transistor manufacturing process.

[0008] Figure 5A and Figure 5B This is a simplified cross-sectional view of a selected structure prior to the lightly doped drain process sequence in the fabrication process of a fin field-effect transistor.

[0009] Figure 6A and Figure 6B This is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after strain implantation in a p-type lightly doped drain process sequence.

[0010] Figure 7 This is a plane diagram of the stress components in the p-type fin field-effect transistor structure after strain injection in the p-type lightly doped drain process sequence.

[0011] Figure 8A and Figure 8B It is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after the source / drain is recessed in the manufacturing process of the fin field-effect transistor, and the manufacturing process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence.

[0012] Figure 9A and Figure 9B This is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after the deposition of the first interlayer dielectric layer in the manufacturing process of the fin field-effect transistor, and the manufacturing process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence.

[0013] Figure 10A and Figure 10B This is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after removing the gate stack in the manufacturing process of the fin field-effect transistor, and the manufacturing process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence.

[0014] Figure 11A and Figure 11B It is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after the replacement gate is formed in the manufacturing process of the fin field-effect transistor, and the manufacturing process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence.

[0015] Figure 12A and Figure 12B It is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after the junction is formed in the manufacturing process of the fin field-effect transistor, and the manufacturing process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence.

[0016] Figure 13 This is a table of injection parameters for strain injection in fin field-effect transistors in some embodiments.

[0017] Figure 14 This is a flowchart of a strain injection method in one embodiment.

[0018] Figure 15 This is a flowchart of a method for strain implantation during the lightly doped drain stage in one embodiment.

[0019] Explanation of reference numerals in the attached figures:

[0020] AA, BB, CC: Section lines

[0021] 110: Fin-like structures

[0022] 120: Substrate

[0023] 130: Quarantine Zone

[0024] 140: Dummy Gate Stack

[0025] 510: Dummy Gate

[0026] 520: Silicon nitride layer

[0027] 530: Oxide layer

[0028] 540: First spacer

[0029] 550: Passage Area

[0030] 560: Channel length direction

[0031] 565, 575: Inclination angle

[0032] 570: Width direction of the fin

[0033] 610: Upper fin area

[0034] 625: Compressive strain

[0035] 630: Upper Isolation Zone

[0036] 633, 635, 638: Strain components; 640: Upper stacking area

[0037] 655: Lower fin-like portion

[0038] 710: Corner

[0039] 810: Area

[0040] 820: Concave Horizontal

[0041] 830: Second spacer

[0042] 840: Free Fully Finned Region

[0043] 850: Sidewall

[0044] 910: Source / Drain Structure

[0045] 920: Air gap

[0046] 930: Contact Etching Stop Layer

[0047] 940: First interlayer dielectric layer

[0048] 1010: Hollow

[0049] 1020: Top width

[0050] 1030: Bottom width

[0051] 1110: Second gate dielectric layer

[0052] 1120: Gate Displacement

[0053] 1210: Second interlayer dielectric layer

[0054] 1220: Source / Drain Contact

[0055] 1230: Gate contact

[0056] 1240: Top width

[0057] 1250: Bottom width

[0058] 1400, 1500: Method

[0059] 1410, 1420, 1430, 1510, 1520, 1530, 1540, 1550: Steps Detailed Implementation

[0060] The different embodiments or examples provided below can implement different structures of the present invention. The specific components and configurations described below are intended to simplify the content of the present invention and not to limit it. For example, the description of forming a first component on a second component includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by other additional components and are not in direct contact. Furthermore, multiple embodiments of the present invention may use the same reference numerals repeatedly for brevity, but elements with the same reference numerals in various embodiments and / or configurations do not necessarily have the same correspondence.

[0061] In addition, spatial relative terms such as "below," "under," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90° or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0062] The term "Group IV semiconductor element" here essentially refers to any semiconductor element composed of a single element from Group IVB of the periodic table, such as silicon or germanium. Similarly, the term "Group IV semiconductor compound" essentially refers to any semiconductor compound composed of elements from Group IVA of the periodic table, including silicon-germanium, silicon-germanium carbide, or silicon carbide, regardless of whether the composition of the compound is fixed or varies with position. Furthermore, the term "Group III-V semiconductor compound" essentially refers to any semiconductor compound composed of elements from Groups IIIA and VA of the periodic table, including gallium arsenide, indium gallium arsenide, or the like. Additionally, the chemical formula Si... 1- x Ge x This indicates pure or substantially pure silicon, pure or substantially pure germanium, or silicon-germanium of any composition, regardless of whether its composition is fixed or varies with position. When the germanium content x is zero, Si... 1-x Ge x It is pure silicon or substantially pure silicon. When the germanium content x is 1 or 100%, Si... 1-x Ge x It is pure germanium or substantially pure germanium.

[0063] The terms "p-FinFET" and "n-FinFET" refer to n-type and p-type fin field-effect transistors, respectively. Furthermore, the term "source-drain" is intended to refer to the source or drain. For example, the source-drain region is, or is intended to be, the region of the transistor's source or drain. The term "implanted species" refers to the implanted element, while the term "implanted gas" refers to the gas used in an ion implanter to implant the species. For example, silicon tetrafluoride (Si) can be used as the implanted gas to implant the species Si. Strain or stress can be represented by arrows in the accompanying drawings. However, the length or width of the arrows is not intended to indicate the absolute or relative intensity of stress or strain unless otherwise explicitly stated in the specification.

[0064] In semiconductor manufacturing processes, one or more annealing steps can be performed after the ion implantation step. Here, an annealing step that occurs after the ion implantation step but earlier than any other annealing step can be considered as annealing the ion implantation.

[0065] Some embodiments disclosed herein illustrate the fabrication process of fin field-effect transistors, but the disclosed process can also be applied to other structures. Figure 1 This is a simplified perspective view of a selected cell in a structure containing two fin field-effect transistor channels during a stage of the fin field-effect transistor manufacturing process. Figure 1 In the illustrated manufacturing process stage, fins 110 are formed on substrate 120, and isolation regions 130 separate the fins 110 from each other and from other fins (not shown). Furthermore, a dummy gate stack 140 runs along the sidewalls of the fins 110 and is located on the upper surface of the fins 110. Two transistor channel regions may be formed in the portion of the fins 110 covered by the dummy gate stack 140. Figure 1 As shown, section line AA in any manufacturing process stage is along a plane perpendicular to substrate 120. Similarly, section line BB in any manufacturing process stage is along a plane perpendicular to substrate 120. Similarly, section line CC in any manufacturing process stage is along a plane perpendicular to substrate 120. Figures 2A to 6A References 8A to 12A Figure 1 The section line AA shown is... Figures 2B to 6B References 8B to 12B Figure 1 The section line BB is shown.

[0066] Figures 2A to 4B This is a simplified cross-sectional view of a selected fin field-effect transistor structure during various stages of the fin field-effect transistor manufacturing process. (Example:) Figure 2A and 2BAs shown, an example of the manufacturing process begins with substrate 120. Substrate 120 may be a substrate semiconductor substrate, a semiconductor-on-insulator substrate, an insulating substrate, or the like. The substrate semiconductor substrate may be silicon or a semiconductor compound, which may be doped or undoped. The semiconductor-on-insulator substrate may include a semiconductor material layer formed on an insulating layer, which may be a buried oxide layer, a silicon oxide layer, or the like, and the insulating layer may be located on an underlying substrate such as a silicon substrate or a glass substrate.

[0067] exist Figure 2A and 2B In the manufacturing process shown, the material layer used for fin 110 may be located on substrate 120. In various embodiments, the material used for fin 110 may comprise one or more semiconductor layers deposited on substrate 120, and the deposition method may be epitaxy. The composition of the material used for fin 110 may differ from the underlying substrate material, and it may be undoped or doped during or after growth. For example, the material used for fin 110 may be or include silicon, silicon germanium, pure or substantially pure germanium, silicon carbide, group III-V semiconductor compounds, group II-VI semiconductor compounds, or the like.

[0068] It is anticipated here that in other manufacturing processes, no special material is deposited for the fin 110, and the fin 110 can be produced from the substrate 120. In these processes, the lines between the fin 110 and the material used for the substrate 120 in various figures do not represent a change in material properties, but rather represent the approximate bottom of the fin 110 after its fabrication is complete.

[0069] exist Figure 3A and 3B In this embodiment, fins 110 are located on substrate 120. The fins can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fins, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, resulting in a pattern pitch smaller than that obtained using a single direct photolithography process. For example, a sacrificial layer can be formed on the substrate and patterned using photolithography. Spacers can be formed along the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer can then be removed, and the remaining spacers can be used to pattern the fins.

[0070] Fins can be produced by various methods, including etching areas of the layered structure on a substrate or depositing fin material into narrow trenches. During the process, areas of the layered structure can be etched to create fins, and the fin pattern can be transferred to one or more underlying masking layers. These masking layers can be or include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof. Anisotropic etching can then be used to remove material outside the fin areas.

[0071] exist Figure 4A and Figure 4B In this configuration, isolation regions 130 are located between fins 110. Isolation regions 130 may comprise or be an insulating material such as silicon oxide, silicon nitride, the like, or a combination thereof, and may be formed using a suitable deposition process. For example, isolation regions 130 may comprise silicon oxide formed by a flowable chemical vapor deposition process. Other insulating materials formed using any acceptable process may also be used. A planarization process, such as chemical mechanical polishing, may be used to remove excess material, making the insulating material coplanar with the upper surface of the fins 110. The insulating material may then be recessed to form isolation regions 130, causing the fins 110 to protrude from between the isolation regions 130. The recessing method for the insulating material may employ any acceptable etching process, such as a selective etching process for the insulating material. The upper surface of isolation regions 130 may be flat as illustrated, raised, recessed, or have more complex shapes, depending on the process details.

[0072] In other manufacturing processes, fins are formed by depositing fin material into narrow trenches, which is more complex than the processes described above and involves additional structures not shown. In one example of the process, a dielectric layer can be formed on the upper surface of a semiconductor substrate 120, trenches can be formed by etching through the dielectric layer, fin material can be epitaxially grown in the trenches, and the dielectric layer can be recessed to allow the fin material to protrude from the dielectric layer and form fins. The epitaxial material can be the same as or different from the substrate, and it can be undoped or doped during or after growth. In these processes, using different materials for growing n-type and p-type fin field-effect transistors is particularly advantageous, for example, as it can maximize carrier mobility in each device configuration. For example, the composition of the fin or a portion thereof can be silicon-germanium, silicon carbide, pure or substantially pure germanium, group III-V semiconductor compounds, group II-VI semiconductor compounds, or the like. Potential materials used to form III-V semiconductor compounds include, but are not limited to, gallium arsenide, indium arsenide, indium gallium arsenide, aluminum arsenide, indium aluminum arsenide, indium phosphide, gallium nitride, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, or the like.

[0073] Suitable well regions (not shown) can be formed in the fin 110 and / or substrate 120. For example, a p-type well can be formed where an n-type fin field-effect transistor is about to be formed, an n-type well can be formed where a p-type fin field-effect transistor is about to be formed, or both p-type and n-type wells can be formed. The doping used for the p-type and n-type wells can be provided by ion implantation. In summary, the fin 110, isolation region 130, substrate 120, and any other structures present on the substrate may contain dopants from the well implantation during well implantation. The dopants used to form the n-type wells may be phosphorus, arsenic, antimony, or the like. The dopants used to form the p-type wells may be boron, boron difluoride, indium, or the like. One or more annealing steps can be performed to activate the implanted dopants. In some processes, the substrate and / or fin material can be doped during crystal growth or deposition, and well implantation may not be necessary.

[0074] Figure 5A and Figure 5B The following is a simplified cross-sectional view of a selected structure prior to the lightly doped drain process sequence in the fabrication process of a fin field-effect transistor. Figure 1 The illustrated dummy gate stack 140 may include a dummy gate 510 and one or more additional layers such as a silicon nitride layer 520 and an oxide layer 530. Furthermore, a first gate dielectric layer (not shown) may be located between the fin 110 and the dummy gate 510. The first gate dielectric layer may comprise or be silicon oxide, silicon nitride, a high-dielectric-constant dielectric layer, the like, or multiple layers as described above, and its formation method may be thermal growth and / or chemical or compliant deposition (by a suitable deposition technique). Once the fabrication process is complete, the channel region 550 of the fin 110 may serve as a channel for the fin field-effect transistor. In some examples of the fabrication process, a first spacer 540 may be located on the side of the fin 110 and the dummy gate stack 140. The first spacer 540 may be or comprise silicon nitride, silicon oxide, silicon oxynitride, or the like. In one embodiment, the first spacer 540 is silicon nitride.

[0075] exist Figure 5A In this example, the fin field-effect transistor has a channel length direction of 560°. Furthermore, the tilt angle of 565° refers to the tilt angle along the channel length direction of the fin field-effect transistor. Figure 5B The width direction of the fin is also shown as 570°. The tilt angle of 575° refers to the tilt angle in the width direction of the fin. Ion implantation can be performed at an angle, producing a symmetrical implantation profile on both sides of the symmetrical structure, and is typically performed in two steps. With respect to a plane perpendicular to the substrate, the total dose is implanted at positive and negative tilt angles, respectively. In ion implantation without a tilt angle, the total dose is implanted in a single step.

[0076] The lightly doped drain process can include an n-type lightly doped drain process sequence and / or a p-type lightly doped drain process sequence. In an example of an n-type lightly doped drain process sequence, a mask layer, such as a photoresist layer, can be deposited and patterned according to an n-type lightly doped drain pattern to cover the p-type fin field-effect transistor structure and expose the n-type fin field-effect transistor structure. Next, n-type dopants are implanted to form the n-type lightly doped drain region used in the n-type fin field-effect transistor, which can serve as a precursor. For example, one or more of phosphorus, arsenic, antimony, or other n-type dopants can be implanted as the n-type lightly doped drain dopants to form the n-type lightly doped drain region. This implantation can be considered as n-type lightly doped drain implantation. After n-type lightly doped drain implantation, the patterned photoresist layer can be removed and n-type lightly doped drain annealing can be performed to activate the dopants. In a p-type lightly doped drain process, a patterned masking layer (e.g., a patterned photoresist layer deposited according to a p-type lightly doped drain pattern) covers the n-type fin field-effect transistor structure and exposes the p-type fin field-effect transistor structure. Next, p-type dopants are implanted to form the p-type lightly doped drain region used in the p-type fin field-effect transistor, which can act as acceptors. For example, boron, boron difluoride, indium, or one or more other p-type dopants can be implanted as p-type lightly doped drain dopants to form the p-type lightly doped drain region. This implantation can be considered as p-type lightly doped drain implantation. After p-type lightly doped drain implantation, the patterned photoresist layer can be removed and p-type lightly doped drain annealing can be performed to activate the dopants. Without lightly doped drain implantation, the doping concentration change between the transistor channel and the source / drain region is drastic, generating harmful hot electrons. Lightly doped drain implantation is typically used to smooth out the doping concentration change between the channel and the source / drain region. The n-type lightly doped drain process can be performed before or after the p-type lightly doped drain process sequence. Furthermore, other process steps can be performed between the n-type and p-type lightly doped drain processes. For example, sidewalls can be formed after the n-type lightly doped drain process sequence and before the p-type lightly doped drain process sequence to advantageously influence the position of the p-type lightly doped drain doping value. Additionally, instead of separate n-type and p-type lightly doped drain annealing steps, a single lightly doped drain annealing can be used to activate the dopants in both the p-type and n-type lightly doped drains. In examples of various processes, one or more annealing steps can be rapid thermal annealing, peak annealing, laser annealing, or similar steps. The terms moderately doped drain, n-type moderately doped drain, and p-type moderately doped drain are sometimes used instead of lightly doped drain, n-type lightly doped drain, and p-type lightly doped drain to indicate that the doping concentration used in a given process is slightly higher than the historically low levels used in previous technology generations. Other terms, such as drain extension, may also be used.

[0077] In the embodiments described herein, ion implantation can advantageously influence the strain in the channel region of the fin field-effect transistor. This implantation can be considered here as strain implantation.

[0078] Figure 6A and Figure 6B This is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after strain implantation in a p-type lightly doped drain process sequence. In this embodiment, strain implantation is performed in the presence of a p-type lightly doped drain photoresist pattern. Therefore, the advantage of this embodiment is that no additional patterning step is required, reducing cost and process complexity. Furthermore, the combination of the dummy gate stack 140 and the first spacer 540 can serve as a mask structure for implantation. In various embodiments, strain implantation can be performed before or after any of one or more p-type lightly doped drain implantations in the p-type lightly doped drain process sequence. In one embodiment, the material used for the fin 110 is silicon, and the implantation species used for strain implantation is also silicon. For example, silicon tetrafluoride can be used as the implantation gas to implant silicon. The implantation species enters some of the upper fin regions 610 of the fin 110, some of the upper isolation regions 630 of the isolation region 130, and the upper stack region 640 of the dummy gate stack 140. Any injected species entering the portion of the first spacer 540 on the sidewalls of the dummy gate stack 140 and the sidewalls of the fin 110 are not illustrated here for simplicity of the figures.

[0079] In one embodiment, a single annealing step is used to anneal the p-type lightly doped drain and strain implantation. This embodiment has the advantage of eliminating the need for an additional annealing step for strain implantation. In one embodiment, a single-peak rapid thermal annealing at 850°C can be used as the general annealing for p-type lightly doped drain and strain implantation. The annealing step has several effects. First, the implanted species diffuse outward from the implanted region to adjacent regions during annealing. If strain implantation is not tilted during the process... Figure 6A and 6B As shown by the vertical arrow, the implanted species will be partially blocked from entering the channel region 550 by the dummy gate stack 140 and the first spacer 540 located on the sidewall of the dummy gate stack 140, unless laterally dispersed. During annealing, the implanted species can diffuse toward and into the channel region 550. If the strain implantation adopts an angled approach in the direction of the channel length, a larger amount of implanted species can enter the deeper channel region 550 before annealing, and then further diffuse into the channel region during annealing. Therefore, the amount of implanted species entering the channel region 550 depends on parameters such as the implantation angle and the annealing time and temperature. Similarly, silicon atoms implanted into the upper portion of the isolation region 130 diffuse toward the lower fin portion 655 of the fin 110. In addition, silicon atoms implanted into the upper portion of the isolation region 130 can diffuse into the gate stack (not shown in the diagram). Figure 6A and 6BThe unimplanted region of isolation zone 130 (as shown in the cross-sectional view). Furthermore, many implanted species occupy interstitial sites before annealing and bonding to adjacent atoms, thus allowing them to integrate into the crystalline structure during annealing, thereby increasing the strain level in the implanted region and consequently increasing the stress level applied to adjacent regions. Thirdly, the annealing step can partially repair the significant crystalline damage caused by strain implantation.

[0080] Strain injection of silicon generates compressive strain in channel region 550 of the p-type fin field-effect transistor. This compressive strain 625 is generated in... Figure 6A In the cross-section, the intensity decreases below the upper fin region 610, and is substantially along the channel length direction. One advantage of this strain is improved performance of the p-type fin field-effect transistor, as the compressive strain along the channel length direction increases hole mobility. Strain injection in the upper isolation region 630 also produces strain, but this strain mainly occurs in the region below the channel region 550. Since the main current occurs in the channel region, the strain injection in the upper isolation region 630 has a smaller impact on transistor performance. However, the strain components caused by strain injection in the upper isolation region 630 will be briefly described here. In a simplified two-dimensional illustration, these two strain components can be distinguished. The direction of the first compressive strain component is substantially along the width of the fin, and it reduces hole mobility in the region where it exists. Strain components (such as...) Figure 6B The strain component 633 shown is... Figure 6A The strain component 635 shown exists in Figure 6B In the cross-section, and exists Figure 6A Before and after the cross-section. Furthermore, the fin material was... Figure 6A Compression inwards and outwards originates from... Figure 6A The upper isolation zone 630 after the cross-section Figure 6A The upper isolation zone 630 before the cross-section. The direction of the second compressive strain component is substantially along the channel length, and it increases the hole mobility in the region where it exists to cancel out the first component. Figure 6A The strain component 638 shown exists in Figure 6A Before and after the cross-section.

[0081] The stress components described above will be further illustrated in a plan view. Figure 7 This is a planar view of the stress components in the p-type fin field-effect transistor structure after strain implantation in the p-type lightly doped drain process sequence. The isolation region 130 isolates the fin 110, which is sequentially covered by the dummy gate stack 140. Figure 7 The section lines AA and CC correspond to respectively Figure 1 The cross-sections AA and CC are shown in the diagram. The compressive strain 625 in the transistor channel originates from strain injection in the upper region of the fin 110, which can increase hole mobility and improve transistor performance. It is worth noting... Figure 7 The compressive strain 625 is represented by a dashed line in the plan view. It should be understood that the strain occurs in the channel region of fin 110, not on top of the dummy gate stack 140. The compressive strain components 633 and 638 occur in the region below channel 550, but have a smaller impact on transistor performance. It should be understood that at the corner 710 of the injection region near isolation region 130, the directions of the total strain components, such as strain components 633 and 638, reflect the bidirectional simplified nature described herein.

[0082] like Figure 6A As shown, another advantage of strain injection in one embodiment is the increased size of the upper stack region 640. For example, in some embodiments, the top width of the gate stack can be increased by approximately 6% to approximately 10%. Under the stress applied by strain injection in the upper stack region 640, the portion of the first spacer 540 located on the sidewall of the dummy gate stack 140 tilts outward. Although Figure 6A The tilt of the first spacer 540 is substantially linear, but it can be a non-linear shape. Increasing the size of the upper stacking area 640 offers several advantages. These advantages will be combined with… Figure 11A and Figure 12A The explanation is as follows.

[0083] Figure 8A and Figure 8B This is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after the source / drain is recessed during the fabrication process of the fin field-effect transistor, and the fabrication process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence. Prior to this stage of the fabrication process, a second spacer 830 may be placed on top of the first spacer 540 and the fin on the sidewall of the dummy gate stack 140. Since the second spacer 830 is located on the first spacer 540, the portion of the second spacer 830 on the sidewall of the dummy gate stack 140 in this strain implantation embodiment may be tilted outward.

[0084] Because the masking sequence covers the n-type fin field-effect transistor and exposes the p-type fin field-effect transistor, region 810 of the fin 110 is removed downwards to the recess level 820. Parts of the first spacer 540 and the second spacer 830 can also be removed. After subsequent process steps, region 810 can serve as the source or drain for the p-type fin field-effect transistor. An advantage of this embodiment is that the source / drain recessing step removes crystal damage in region 810 that originates from strain implantation and is retained after annealing.

[0085] During the implantation and annealing process, implanted species enter the channel region 550, while implanted species in any portion of the fin 110 remain between region 810 and the channel region. The source / drain recess process does not remove these implanted species. The implanted species provide compressive strain, thus increasing mobility in the channel region. In some manufacturing processes, the gate stack does not cover the free fully fin region 840 of the fin 110, and the source / drain recess step does not remove the free fully fin region 840. This region is considered a free fully fin region, which contains substantially all of the implanted species implanted therein during the strain implantation step. With this manufacturing process, a portion of the upper isolation region 630 may be removed, resulting in a reduction in the strain component in the region below the channel region 550. In some embodiments, the upper isolation region 630 may be substantially or completely removed.

[0086] Figure 9A and Figure 9B This is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after the deposition of the first interlayer dielectric layer in the manufacturing process of the fin field-effect transistor, and the manufacturing process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence. The source / drain structure 910 of the p-type fin field-effect transistor is formed in... Figure 8A In region 810, its generation method can be extensional growth. For example... Figure 9B As shown, the epitaxial source / drain structures growing on adjacent fins 110 can merge to form an interconnected structure, with the air gap 920 formed beneath the interconnected structure. During or after growth, the source / drain regions can be doped, with a dopant concentration ranging from approximately 10-1. 19 cm -3 To about 10 21 cm -3 Between. The dopants used to form the source / drain regions of an n-type fin field-effect transistor can be phosphorus, arsenic, antimony, or similar substances, while the dopants used to form the source / drain regions of a p-type fin field-effect transistor can be boron, boron difluoride, indium, or similar substances.

[0087] In some embodiments, the material used for the source / drain structure 910 may be substantially the same as the material used for the fin 110. In other embodiments, different materials may be selected to apply compressive stress to the channel region 550. In summary, if the fin 110 is silicon, the source / drain structure 910 may comprise silicon, silicon germanium, germanium, silicon germanium boride, germanium tin, or the like. In these embodiments, the total strain in the channel region 550 may originate from strain injection and the source / drain structure 910. Therefore, strain injection can enhance the improved mobility resulting from stress applied to the source / drain region.

[0088] The source / drain structure used in n-type fin field-effect transistors can be generated using similar methods. In some embodiments, the material used for the source / drain structure may be substantially the same as the material of the fin. In other embodiments, different materials may be selected to apply tensile stress to the channel region of the n-type fin field-effect transistor. In summary, if the fin is silicon, the source / drain region may comprise silicon, silicon carbide, silicon phosphide, silicon carbide, or the like. In embodiments containing strain injection for n-type fin field-effect transistors, the total strain in the channel region of the n-type fin field-effect transistor may originate from strain injection and the source / drain region of the n-type fin field-effect transistor. Therefore, strain injection can enhance the improved mobility resulting from stress applied to the source / drain region.

[0089] After fabricating the source / drain regions, a first interlayer dielectric layer 940 may be deposited on the fin field-effect transistor structure. The first interlayer dielectric layer 940 may be or comprise phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. In some embodiments, a contact etch stop layer 930 is deposited on the fin field-effect transistor structure prior to the deposition of the first interlayer dielectric layer. The contact etch stop layer 930 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and its etch rate differs from that of the material of the overlying first interlayer dielectric layer 940. In a strain-implanted embodiment, a portion of the contact etch stop layer 930 located on the sidewall of the dummy gate stack 140 may be tilted outwards.

[0090] Figure 10A and Figure 10B This is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after the removal of the gate stack in the fabrication process of the fin field-effect transistor, and the fabrication process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence. A planarization process, such as chemical mechanical polishing, can be performed to planarize the upper surface of the wafer and prepare for the removal of the dummy gate stack 140. The planarization process can stop at the upper surface of the dummy gate stack 140, leaving the dummy gate stack 140 substantially intact, or it can remove the upper portion of the dummy gate stack 140 and the upper portions of the first spacer 540 and the second spacer 830 along the sidewalls of the dummy gate stack 140. Any material remaining in the dummy gate stack 140 after the planarization step can then be removed to leave a void 1010 defined by the first spacer 540 on its side, and the removal method can be selective etching. For all transistors or transistors intended to operate within a specific voltage range, the first gate dielectric layer (not shown) on the fin 110 may be retained, or the first gate dielectric layer may be completely or partially removed from the cavity 1010. In one embodiment of strain injection, the top width 1020 of the cavity 1010 is greater than the bottom width 1030.

[0091] Figure 11A and Figure 11B This is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after forming a replaced gate in the fabrication process of a fin field-effect transistor, and the fabrication process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence. The second gate dielectric layer 110 may be located in the void 1010. The second gate dielectric layer 1110 may be compliantly deposited on the wafer and may comprise silicon oxide, silicon nitride, or multiple layers thereof. In some fabrication processes, the second gate dielectric layer 1110 may comprise a dielectric material with a high dielectric constant greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or combinations thereof. The deposition method of the second gate dielectric layer 1110 may be molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods. The advantage of strain implantation in this embodiment is that the tilted profile of the first spacer 540 facilitates compliant deposition of the second gate dielectric layer 1110. The second gate dielectric layer 1110 is also tilted outward.

[0092] In the filling process, a replacement gate 1120 may be deposited on the second gate dielectric layer 1110, which may include a metal material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or a multilayer thereof. Although Figure 11A Details of the replacement gate 1120 are not shown. The replacement gate 1120 may include any number of pad layers and work function adjustment layers. Figure 10A As shown, another advantage of strain implantation in the p-type lightly doped drain process sequence is the increased top width 1020 of the void 1010, which increases the overall volume of the replacement gate 1120 of the same depth, thereby helping to reduce the resistance of the replacement gate. Reduced gate resistance increases circuit speed. Another advantage is that the increased top width 1020 facilitates the fill process, reducing the likelihood of voids of any size forming in the replacement gate. Voids are detrimental because they increase gate resistance and degrade circuit speed.

[0093] After depositing the material used for the replacement gate 1120, the second gate dielectric layer 1110 and portions of the replacement gate 1120 deposited on the upper surface of the first interlayer dielectric layer 940 can be removed by a planarization step to obtain... Figure 11A and Figure 11B The structure is shown. It is anticipated that in some manufacturing processes, the substituted gate and associated dielectric layer used in n-type and p-type fin field-effect transistors may differ. In these processes, suitable masking methods can be employed to deposit the different materials used in n-type and p-type fin field-effect transistors.

[0094] Figure 12A and Figure 12B This is a simplified cross-sectional view of a selected p-type fin field-effect transistor structure after the formation of contacts in the manufacturing process of the fin field-effect transistor, and the manufacturing process of the fin field-effect transistor includes strain implantation in the p-type lightly doped drain process sequence. A second interlayer dielectric layer 1210 is deposited on the first interlayer dielectric layer 940. The second interlayer dielectric layer 1210 can be a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and can be flowable. Its deposition method can be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The opening used for the source / drain contact 1220 can pass through the second interlayer dielectric layer 1210, the first interlayer dielectric layer 940, and the contact etch stop layer 930. In some manufacturing processes, a gate cap (not shown) may be present on the replaced gate 1120. The opening used for gate contact 1230 passes through the second interlayer dielectric layer 1210 and through the gate cap (if present). The opening can be formed using acceptable photolithography and etching techniques. One or more pad layers (not shown), such as diffusion barrier layers, adhesive layers, or similar layers, can be formed in the opening. The pad layers may contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material used for source / drain contacts 1220 and gate contact 1230 can be located in individual openings. The conductive material used for the contacts can be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, can then be performed to remove excess material from the surface of the second interlayer dielectric layer 1210. An annealing process can be performed to form a silicide interface between the source / drain structure 910 and the source / drain contact 1220. The source / drain contacts 1220 and the gate contacts 1230 can be formed in separate process sequences, or in the same process sequence.

[0095] Although both the source / drain contact 1220 and the gate contact 1230 exist Figure 12A In the cross-section shown, nitrogen should be understood to be present at some or all of the junctions in some manufacturing processes. Figure 12A In the cross-section, but in Figure 12A Before or after the cross-section. Furthermore, Figure 12A and 12B The sloping sidewalls of the source / drain contact 1220 and gate contact 1230 shown do not imply any equal or unequal relationship between them and the sloping sidewalls of other structures in the figures (such as the sidewall of the replacement gate 1120).

[0096] The strain injection in this embodiment can have two additional advantages, which will be combined with Figure 12AExplanation. First, the upper width 1240 of the replaced gate 1120 is greater than the lower width 1250. The larger upper width 1240 can be used for the electrical connection between the replaced gate 1120 and the gate contact 1230. If the gate contact 1230 also has a corresponding size, it is beneficial to reduce the connection resistance. Furthermore, the interconnect layer (not shown) is typically deposited on the second interlayer dielectric layer 1210, allowing interconnects with multiple ends to form circuits. Because this embodiment is advantageous for the fill process used for the replaced gate 1120, it can produce a higher gate and thus increase the vertical distance between the interconnect layer on one side and the substrate and fin field-effect transistor structure on the other side. The larger vertical distance can reduce the capacitance between structures. In some cases, taking advantage of this opportunity to reduce capacitance can increase the net circuit speed.

[0097] Since the process steps after the junction formation mainly concern the formation of the structure on the second interlayer dielectric layer 1210, Figure 12A and Figure 12B This is a cross-sectional view of a selected p-type fin field-effect transistor structure after the circuit manufacturing process is completed. For example... Figure 12B As shown, stress-injected atoms can be located in the channel region 550, the free fully finned region 840, or any part (not shown) of the fin retained between the source / drain structure 910 and the channel region 550. Figure 12B As shown, the stress-injected atoms can be located in the upper isolation region 630. The constituent element atoms of the region are located therein. The constituent elements of the material are defined here as any element present in the material with an atomic concentration of approximately 20% or more. The atoms of the material's composition can be considered as constituent atoms here. For example, if the channel region 550 is Si... 0.8 Ge 0.2 The silicon and germanium atoms in the channel are located in a ratio of approximately 4:1. If the composition of the channel region is not constant in the vertical direction, the vertical concentration profile of the silicon and germanium atoms will reflect the vertical profile of the composition. Similarly, in an isolation region composed of substantially stoichiometric silicon dioxide, the ratio of silicon to oxygen atoms in the isolation region is approximately 1:2. Furthermore, dopants or acceptors can be located in these regions. For example, in the channel region of a p-type fin field-effect transistor, dopants such as boron or indium can be located therein. As emphasized above, in strain-implanted embodiments, atoms from strain-implanted atoms can also be located in various regions. These atoms enter the region during strain implantation or diffuse into the region during subsequent annealing and are considered redundant atoms here. Redundant atoms can be interstitial or bonded to other atoms. In embodiments where the strain-implanted species and compositional elements differ, such as nitrogen stress implantation and Si… 0.8 Ge 0.2Excess atoms can be distinguished by chemical species, concentration profiles, or the presence of any interstitial atoms. The concentration profile of the implantation profile depends on the implanted species, the material into which the implanted species are implanted, the implantation energy, the implantation dose, and the implantation tilt angle. These concentration profiles typically have peaks (considered ranges) at specific depths and sometimes approximate Gaussian functions in a laterally consistent manner. The annealing step can alter the implantation concentration profile via diffusion, depending on the annealing temperature-time profile and the diffusion coefficient of the diffusing species in the host material. Numerical modules and simulations are generally used to calculate the implantation profiles and annealed profiles for various implantations. Measurement techniques such as secondary ion mass spectrometry and nano-secondary ion mass spectrometry are generally used to measure these profiles. Implanted atoms are typically interstitial; although it is assumed that implanted atoms are located at lattice sites during annealing, some implanted atoms remain interstitial. Therefore, the presence of any interstitial atom may indicate the presence of excess atoms. In embodiments where the stress-implanted species and compositional elements are the same, such as silicon stress implantation into silicon or Si... 0.8 Ge 0.2 In the channel, extra atoms can be distinguished by the concentration profile or the presence of any interstitial atoms.

[0098] In various embodiments of strain injection, the concentration of excess atoms in channel region 550 is between approximately 10. 19 cm -3 To about 10 20 cm -3 Between. In other embodiments, the concentration of excess atoms in the upper isolation region 630 is between 10. 20 cm -3 To about 10 21 cm -3 Between. In other embodiments, the concentration of excess atoms per unit area in the free fully finned region 840 is approximately equal to the strain injection dose. For example, in one embodiment, the concentration per unit area for a p-type fin field-effect transistor is between 10. 15 cm -2 To about 10 17 cm -2 between.

[0099] Figure 13 This is a table of injection parameters for strain injection in fin field-effect transistors in some embodiments. Figure 13 The illustrated embodiments can be applied to fin field-effect transistors, wherein the fin material is any group IV semiconductor element or group IV semiconductor compound, such as Si. 1-x Ge x (Germanium content x is between 0 and 100%, including silicon and germanium), Si 1-x-y Ge x C yOr similar substances. In one embodiment of a p-type fin field-effect transistor, silicon tetrafluoride gas is used to inject silicon into the p-type fin field-effect transistor, with a dosage between approximately 10... 15 cm -2 Up to 10 17 cm -2 The tilt angle is between 0 and 30 degrees, and the implantation energy is between approximately 5 keV and approximately 30 keV. In another embodiment, silicon tetrafluoride is used for silicon implantation, with a dosage between approximately 10 keV and 10 keV. 15 cm -2 To about 10 17 cm -2 The tilt angle is between 0 degrees and about 30 degrees, and the injected energy causes the injected range R to be between about 20 nm and about 40 nm. In other embodiments of the p-type fin field-effect transistor, germanium tetrafluoride gas or nitrogen gas is used for injecting germanium or nitrogen, respectively.

[0100] In other embodiments, strain injection is used to increase electron mobility in the channels of the n-type fin field-effect transistor. In one embodiment, carbon dioxide is used as a carbon-containing gas to inject carbon into the n-type fin field-effect transistor, with a doping dose exceeding 10. 17 cm -2 The tilt angle is between 0 and 30 degrees, and the injected energy is less than about 15 keV. In another embodiment, carbon dioxide is used as a carbon-containing gas to inject carbon into the n-type fin field-effect transistor, with a dose exceeding about 10 keV. 17 cm -2 The tilt angle is between 0 degrees and about 30 degrees, and the injected energy causes the injection range R to be between about 20 nm and about 40 nm. In other embodiments, nitrogen is used to inject nitrogen into the n-type fin field-effect transistor.

[0101] exist Figure 6A In the illustrated embodiment, the first spacer 540 during strain implantation is present on the fin 110 and on the sidewalls of the dummy gate stack 140. In various embodiments, the first spacer 540, multiple spacers, or other layers may or may not be present on the fin 110 or on the sidewalls of the dummy gate stack 140 during strain implantation. In some embodiments, the strain implantation parameters, such as the dose, energy, and tilt angle described below, can be appropriately adjusted to ensure that the implanted species after the annealing step are located in the channel region 550 and have the aforementioned favorable concentration.

[0102] In some embodiments, the fin material is a group III-V semiconductor compound, and one or more elements from groups IIIA and VA of the periodic table can be used as implanted species. For example, the fin material may be gallium arsenide, and the implanted species may be nitrogen, phosphorus, arsenic, aluminum, gallium, and / or indium. In some embodiments, approximately equal doses of group IIIA and group VA elements may be implanted to approximately the same implantation range to maintain the stoichiometry of the fin. For example, the fin material may be gallium arsenide, and group VA elements (such as nitrogen, phosphorus, or arsenic) and group IIIA elements (such as aluminum, gallium, or indium) may be implanted to approximately the same doses and implantation ranges.

[0103] In various embodiments, the annealing step for strain implantation is any annealing process compatible with the fin field-effect transistor manufacturing process, including rapid thermal annealing, peak annealing, laser annealing, or similar processes. In one embodiment, a single annealing step can be used for strain implantation and p-type lightly doped drain implantation. In other embodiments, separate strain annealing steps can be performed for strain implantation. For example, if the p-type lightly doped drain annealing used in the fin field-effect transistor manufacturing process has a lower temperature, shorter time, or both (compared to strain implantation annealing), then strain annealing is performed first. In one embodiment, the p-type lightly doped drain process, after patterning photoresist, can include strain implantation for a p-type fin field-effect transistor, photoresist removal, strain annealing, applying and patterning photoresist for the p-type lightly doped drain, p-type lightly doped drain implantation, removal of a second photoresist, and p-type lightly doped drain annealing. In another embodiment, a hard mask is used to avoid a second patterning step: photoresist for a lightly doped p-type drain is used to pattern the hard mask, followed by strain implantation for a p-type fin field-effect transistor, strain annealing, lightly doped p-type drain implantation, and lightly doped p-type drain annealing, after which the hard mask is removed. Similar embodiments can be used for n-type fin field-effect transistors. Other embodiments are also possible. For example, strain implantation for one or both of the p-type and n-type fin field-effect transistors can be performed before the lightly doped drain process sequence, and one or more strain annealing steps can be performed to anneal the strain implantation for one or both of the p-type and n-type fin field-effect transistors separately or together.

[0104] In some embodiments, the strain injection may be angled in the direction of the fin width and may or may not be angled in the direction of the channel length. For example... Figure 6BAs shown, there is no tilted injection in the fin width direction, and the injected atoms cannot reach the region of fin 110 below the upper fin region 610. However, if the injection is tilted in the fin width direction, the injected atoms will reach the region of fin 110 below the upper fin region 610, which helps to mitigate any strain reduction below the channel region 550. In some embodiments, a portion of the total strain injection dose is injected tilted in the fin width direction. In some embodiments, the strain injection is not tilted in the channel length direction, but tilted in the fin width direction. In this embodiment, strain injection is performed in three steps. In the first step, a portion of the total dose may be injected without tilting. Then the remaining portion of the total dose is divided into two halves and injected in two steps with positive and negative tilt values ​​in the fin width direction. In other embodiments, strain injection may be performed in the direction of both channel length and fin width. In this embodiment, a portion of the total dose is injected in two steps along the channel length direction with positive and negative tilt values, while the remainder of the total dose is injected in two additional steps along the fin width direction with positive and negative tilt values. In some embodiments, the tilt angle in the fin width direction is between 0 degrees and about 30 degrees.

[0105] In some embodiments, strain implantation used for p-type fin field-effect transistors can be performed during the fabrication process of the fin field-effect transistor, rather than during the p-type lightly doped drain or n-type lightly doped drain stages. For example, in one embodiment, strain implantation can be performed after source / drain recessing and before source / drain epitaxy. Figure 8A As shown, the source / drain recess directly exposes the sidewalls 850 of the channel region 550. Strain implantation is angled along the channel length to implant the implanted species into the channel region 550. Furthermore, a lower implantation dose can be used compared to strain implantation in a lightly doped drain process sequence. An annealing step is then performed before source / drain epitaxy to enhance strain and repair implantation damage. In other embodiments, strain implantation can be performed after source / drain epitaxy.

[0106] Figure 14 This is a flowchart of strain implantation method 1400 in one embodiment. In step 1410, a channel masking structure is located on a first portion of the fin but not on a second portion of the fin structure, and the first portion is located on at least a portion of the channel region. The channel masking structure may or may not include a gate, such as a dummy gate or a replaced gate, and may or may not include one or more sidewalls. The channel masking structure may be or include photoresist, silicon nitride, silicon oxide, or the like. The width of the channel masking structure may differ from the width of the channel region; for example, the structure may extend beyond the channel region or may not mask all of the channel region. In step 1420, strain implantation is performed. The channel masking structure at least blocks some of the implanted species from entering the channel region. In step 1430, annealing is performed.

[0107] Figure 15 This is a flowchart of a method 1500 for strain implantation in a lightly doped drain stage, as described in one embodiment. The lightly doped drain stage can be an n-type or p-type lightly doped drain stage, and the method can be applied to an n-type lightly doped drain stage for an n-type fin field-effect transistor, a p-type lightly doped drain stage for a p-type fin field-effect transistor, or a lightly doped drain stage for both n-type and p-type fin field-effect transistors. In step 1510, the gate is located on the channel region of the fin. The gate can be a dummy gate or a substituted gate. In step 1520, a patterned mask layer can be placed on the wafer according to the lightly doped drain pattern. The mask layer can be photoresist. In step 1530, strain implantation is performed. In step 1540, one or more lightly doped drain implantations are performed, and in step 1550, annealing is performed. If the mask layer is photoresist, it can be removed before the annealing step 1550.

[0108] In other embodiments of the method, the order of steps 1530 and 1540 may be reversed. A more common practice is to perform strain implantation after implantation of one or more lightly doped drains. In other embodiments of the method, an anti-reflective coating or planarization layer may be used in conjunction with photoresist. In other embodiments, one or more hard masking layers, such as oxide or nitride layers, may be used for mask implantation, and the photoresist may or may not be removed after patterning one or more masking layers. Any masking layer may be removed before or after annealing step 1550.

[0109] In one embodiment, the semiconductor device includes a transistor and an isolation region adjacent to the transistor. The transistor has a channel region containing a constituent element and excess atoms, wherein the constituent element belongs to a group of the periodic table, and the excess atom is nitrogen, or belongs to that group of the periodic table. The concentration of excess atoms in the channel region is between approximately 10⁻⁶. 19 cm -3 To about 10 21 cm -3 Between. The isolation region also contains excess atoms, and the concentration of excess atoms in the isolation region is between approximately 10. 20 cm -3 To about 10 21 cm -3In one embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is a p-type fin field-effect transistor, and the excess atoms are silicon. In another embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is a p-type fin field-effect transistor, and the excess atoms are germanium. In yet another embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is a p-type fin field-effect transistor, and the excess atoms are nitrogen. In yet another embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is an n-type fin field-effect transistor, and the excess atoms are carbon. In yet another embodiment, the channel region is a group IV semiconductor element or a group IV semiconductor compound, the transistor is an n-type fin field-effect transistor, and the excess atoms are nitrogen. In yet another embodiment, the channel region is a group III-V semiconductor compound, and the excess atoms are nitrogen or elements belonging to group III or V of the periodic table.

[0110] In one embodiment, the semiconductor device includes a gate, wherein the upper width of the gate is greater than 1 nm than the lower width of the gate, a channel region comprising a constituent element and excess atoms, the constituent element belonging to a group of the periodic table, and the excess atoms being nitrogen or belonging to that group of the periodic table, and the excess atom concentration in the channel region being between about 10. 19 cm -3 To about 10 21 cm -3 In one embodiment, the semiconductor device is a fin field-effect transistor and further includes an isolation region adjacent to the fin field-effect transistor. The isolation region includes excess atoms, and the concentration of excess atoms in the isolation region is between about 10. 20 cm -3 To about 10 21 cm -3 Between. In one embodiment, the fins extend above the topmost surface of the isolation region. In one embodiment, the concentration of excess atoms per unit area in the free, fully finned region is at least 10. 15 cm -2 .

[0111] In one embodiment, the channel region of the fin field-effect transistor comprises elements belonging to a group of the periodic table, and the method of fabricating the fin field-effect transistor includes: placing a channel masking structure on a first portion of a fin to cover the first portion of the fin, the channel masking structure not covering a second portion of the fin, and the first portion of the fin including at least a portion of the channel region; performing a first ion implantation of nitrogen or an element belonging to that group of the periodic table; and annealing the first ion implantation. In one embodiment, the fin field-effect transistor is p-type, the channel masking structure includes a gate, the fin is a group IV semiconductor element or a group IV semiconductor compound, the ion implantation gas is silicon hexafluoride, germanium tetrafluoride, or nitrogen, and the ion implantation dose is between approximately 10. 15 cm -2 To about 10 17 cm -2 The ion implantation energy is between approximately 5 keV and approximately 30 keV, and the tilt angle of the ion implantation along the length of the channel region is between 0 degrees and approximately 30 degrees. In one embodiment, the fin field-effect transistor is p-type, the channel masking structure includes a gate, the fin is a group IV semiconductor element or a group IV semiconductor compound, the gas used for ion implantation is silicon hexafluoride, germanium tetrafluoride, or nitrogen, and the ion implantation dose is between approximately 10 keV and approximately 30 keV. 15 cm -2 To about 10 17 cm -2 The ion implantation energy is between about 5 keV and about 30 keV, the tilt angle of the ion implantation along the length of the channel region is between 0 degrees and about 30 degrees, and the tilt angle of the ion implantation along the width of the fin is between 0 degrees and about 30 degrees. In one embodiment, the fin field-effect transistor is n-type, the channel masking structure includes a gate, the fin is a group IV semiconductor element or a group IV semiconductor compound, the gas used for ion implantation is carbon dioxide or nitrogen, and the ion implantation dose is greater than about 10. 17 cm -2 The ion implantation energy is less than about 15 keV, and the tilt angle of the ion implantation along the length of the channel region is between 0 degrees and about 30 degrees. In one embodiment, the fin field-effect transistor is n-type, the channel masking structure includes a gate, the fin is a group IV semiconductor element or a group IV semiconductor compound, the gas used for ion implantation is carbon dioxide or nitrogen, and the ion implantation dose is greater than about 10. 17 cm -2The ion implantation energy is less than about 15 keV, the tilt angle of the ion implantation along the length of the channel region is between 0 degrees and about 30 degrees, and the tilt angle of the ion implantation along the width of the fin is between 0 degrees and about 30 degrees. In one embodiment, the method further includes performing a second ion implantation, wherein the second ion implantation is a lightly doped drain implantation to form a lightly doped drain region, and an annealing step to anneal the first ion implantation and the second ion implantation. In one embodiment, the fin field-effect transistor is a p-type fin field-effect transistor located on a wafer, the channel mask structure includes a gate, and the method further includes: placing a patterned mask layer on the wafer before the first ion implantation, wherein the patterned mask layer covers the n-type fin field-effect transistor but does not cover the p-type fin field-effect transistor, and performing the second ion implantation while the patterned mask layer is on the wafer, wherein the second ion implantation is a p-type lightly doped drain implantation to form a p-type lightly doped drain region. In one embodiment, the fin field-effect transistor is an n-type fin field-effect transistor located on a wafer, the channel masking structure includes a gate, and the method further includes: placing a patterned masking layer on the wafer prior to a first ion implantation, wherein the patterned masking layer covers the p-type fin field-effect transistor but not the n-type fin field-effect transistor; and performing a second ion implantation while the patterned masking layer is on the wafer, wherein the second ion implantation is an n-type lightly doped drain implantation to form an n-type lightly doped drain region. In one embodiment, the method further includes forming an isolation region adjacent to the fin, wherein a first ion implantation step of nitrogen or an element belonging to that group of the periodic table is performed, including implanting nitrogen or an element belonging to that group of the periodic table into the isolation region. In one embodiment, the channel region is a group III-V semiconductor compound, and the implanted species is nitrogen or an element belonging to group III or group V of the periodic table.

[0112] Those skilled in the art will readily understand that materials and methods can be modified without departing from the scope of the embodiments of the present invention. It should also be understood that, in addition to the specific content describing the embodiments, the embodiments of the present invention provide many applicable inventive concepts. Therefore, the appended claims are intended to include such processes, machines, manufacturing methods, compositions, means, methods, or steps within their scope.

Claims

1. A semiconductor device, comprising: A transistor has a channel region comprising a constituent element and a plurality of excess atoms. The constituent element belongs to a group of elements in the periodic table, and the excess atoms are atoms introduced into the channel region by strain injection and annealing. The strain injection of these excess atoms applies stress to the channel region. These extra atoms are nitrogen or elements belonging to Group III of the periodic table, silicon, germanium, carbon, or elements belonging to Group III of the periodic table, and The concentration of the excess atoms in the channel region is between 10 19 cm -3 and 10 21 cm -3 ; and An isolation region adjacent to the transistor, the isolation region also containing the excess atoms, and the concentration of the excess atoms in the isolation region is between 10 20 cm -3 and 10 21 cm -3 .

2. The semiconductor device of claim 1, wherein: This channel region is composed of group IV semiconductor elements or group IV semiconductor compounds. The transistor is a p-type fin field-effect transistor, and These extra atoms are silicon, germanium, or nitrogen.

3. The semiconductor device of claim 1, wherein: This channel region is composed of group IV semiconductor elements or group IV semiconductor compounds. The transistor is an n-type fin field-effect transistor, and These extra atoms are carbon or nitrogen.

4. The semiconductor device of claim 1, wherein: This channel region is a III-V group semiconductor compound, and These extra atoms are nitrogen or belong to group III or group III of the periodic table.

5. The semiconductor device of claim 1, wherein the isolation region is at least partially a portion of an insulating material surrounding the transistor.

6. The semiconductor device of claim 1, wherein the isolation region is stressed below the channel region.

7. A semiconductor device, comprising: A gate, wherein the upper width of the gate is greater than 1 nm than the lower width of the gate. A channel region comprising a constituent element and multiple excess atoms. The constituent element belongs to a group of elements in the periodic table, while the excess atoms are nitrogen or belong to that group. These excess atoms originate from atoms introduced into the channel region through strain injection and annealing. The strain injection of these excess atoms applies stress to the channel region. The concentration of these excess atoms in the channel region is between 10. 19 cm -3 Up to 10 21 cm -3 between, in: The semiconductor device is a fin field-effect transistor having a fin, and further includes an isolation region adjacent to the fin field-effect transistor, the isolation region including the excess atoms, and the concentration of the excess atoms in the isolation region being between 10. 20 cm -3 Up to 10 21 cm -3 between.

8. The semiconductor device of claim 7, wherein: The fin extends above the topmost surface of the isolation zone.

9. The semiconductor device of claim 7, wherein: The concentration of these extra atoms per unit area in a free, fully finned region is at least 10. 15 cm -2 The gate does not cover the free fully finned region, and the free fully finned region is separated from the channel region by a source / drain structure.

10. A semiconductor device, comprising: A transistor has a channel region having a constituent element and a plurality of excess atoms. The constituent element belongs to a group IV semiconductor element or a group IV semiconductor compound of the periodic table. The excess atoms are germanium, carbon, or nitrogen. These excess atoms are atoms driven into the channel region by strain injection and annealing. The excess atoms injected by strain injection apply stress to the channel region, and the concentration of these excess atoms in the channel region is between 10. 19 cm -3 Up to 10 21 cm -3 between; A gate is located on the channel region, and the upper width of the gate is at least 1 nm larger than the lower width of the gate; and An isolation region adjacent to the transistor, and the isolation region contains the excess atoms at a concentration between 10 20 cm -3 and 10 21 cm -3 .

11. The semiconductor device of claim 10, wherein the gate extends over the channel region and further extends over at least one additional channel region.

12. The semiconductor device of claim 10, wherein the transistor further includes a source region and a drain region, and the semiconductor device further includes an air gap under the source region, the drain region, or the source region and the drain region.

13. The semiconductor device of claim 10, wherein the transistor is a fin field-effect transistor having a fin, and wherein the isolation region applies stress to the lower portion of the fin.

14. A method for forming a finned field-effect transistor, wherein the finned field-effect transistor contains elements belonging to a group of elements in the periodic table, and the method includes: A channel shielding structure is placed on a first portion of a fin to cover that first portion of the fin, the channel shielding structure not covering a second portion of the fin, and the first portion of the fin includes at least a portion of a channel region. To form an isolation zone adjacent to the fin, Perform first ion implantation of multiple redundant atoms, and After the first ion implantation, the channel region is annealed to drive the excess atoms implanted by the first ion into the channel region, thereby introducing the excess atoms implanted by the first ion into the channel region, wherein the excess atoms implanted by the first ion implantation exert stress on the channel region. These extra atoms are nitrogen or elements belonging to that group of the periodic table, silicon, germanium, carbon, or elements belonging to Group III of the periodic table. wherein the concentration of the excess atoms of the isolation region is between 10 20 cm -3 and 10 21 cm -3 .

15. The method for forming a finned field-effect transistor as described in claim 14, wherein: This fin field-effect transistor is p-type. The channel mask structure includes a gate. The fin is a group IV semiconductor element or a group IV semiconductor compound. The first ion implantation is performed using silicon tetrafluoride, germanium tetrafluoride, or nitrogen gas. The dose of the first ion implantation is between 10 15 cm -2 Up to 10 17 cm -2 between, The energy of the first ion implantation is between 5 keV and 30 keV, and The tilt angle of the first ion implanted along the length of the channel region is between 0 and 30 degrees.

16. The method of forming a finned field-effect transistor as described in claim 15, wherein: The first ion is implanted at an angle between 0 and 30 degrees in the width direction of the fin.

17. The method of forming a finned field-effect transistor as described in claim 14, wherein: This fin field-effect transistor is n-type. The channel mask structure includes a gate. The fin is a group IV semiconductor element or a group IV semiconductor compound. The first ion implantation is performed using either carbon dioxide or nitrogen gas. The first ion implantation has a dose greater than 10 17 cm -2 , The energy of the first ion implantation was less than 15 keV, and The tilt angle of the first ion implanted along the length of the channel region is between 0 and 30 degrees.

18. The method of forming a finned field-effect transistor as described in claim 17, wherein: The first ion is implanted at an angle between 0 and 30 degrees in the width direction of the fin.

19. The method of forming a fin field-effect transistor as described in claim 14, further comprising: A second ion implantation is performed, wherein the second ion implantation is a lightly doped drain implantation to form a lightly doped drain region in the fin, and The annealing step anneals the first ion implantation and the second ion implantation.

20. The method for forming a finned field-effect transistor as described in claim 14, wherein: This fin field-effect transistor is a p-type fin field-effect transistor located on a wafer. The channel mask structure includes a gate, and The methods also include: Prior to the first ion implantation, a patterned masking layer is placed on the wafer, and the patterned masking layer covers an n-type fin field-effect transistor but not the p-type fin field-effect transistor. A second ion implantation is performed when the patterned masking layer is located on the wafer, and the second ion implantation is a p-type lightly doped drain implantation to form a p-type lightly doped drain region.

21. The method for forming a finned field-effect transistor as described in claim 14, wherein: This fin field-effect transistor is an n-type fin field-effect transistor located on a wafer. The channel mask structure includes a gate, and The methods also include: Prior to the first ion implantation, a patterned masking layer is placed on the wafer, and the patterned masking layer covers a p-type fin field-effect transistor but does not cover the n-type fin field-effect transistor. A second ion implantation is performed when the patterned masking layer is located on the wafer, and the second ion implantation is an n-type lightly doped drain implantation to form an n-type lightly doped drain region.

22. A method for forming a semiconductor device, comprising: A channel region is formed in a substrate structure, the channel region containing a constituent element that belongs to a group of elements in the periodic table. An isolation layer is deposited around the substrate structure; Multiple excess atoms are implanted into the substrate structure and the insulating layer. These excess atoms are nitrogen or elements belonging to the same group of the periodic table, silicon, germanium, or carbon. The substrate structure is annealed to drive the excess atoms into the channel region, thereby introducing the implanted excess atoms into the channel region, wherein the implanted excess atoms create stress in the channel region. wherein the concentration of the excess atoms of the isolation layer is between 10 20 cm -3 and 10 21 cm -3 .

23. The method of forming a semiconductor device as claimed in claim 22, further comprising: Multiple lightly doped drain dopants are implanted into the substrate structure; as well as After implanting the lightly doped drain dopants and the excess atoms into the substrate structure, the substrate structure is annealed.

24. The method of forming a semiconductor device as claimed in claim 22, further comprising: A patterned masking layer is used to selectively implant lightly doped drain dopants into the substrate structure; as well as The same patterned mask is used to selectively inject these excess atoms into the substrate structure.

25. The method of forming a semiconductor device as claimed in claim 22, wherein the stress is compressive stress.

26. A method for forming a semiconductor device, comprising: A transistor structure is formed having a channel region containing a constituent element that belongs to a group of elements in the periodic table. An isolation region is formed adjacent to the transistor structure; Multiple excess atoms are injected into the transistor structure and the isolation region, and these excess atoms are nitrogen or atoms of the constituent element; as well as Annealing is used to drive at least some of the excess atoms into the channel region to introduce the injected excess atoms into the channel region, to achieve 19 19 cm -3 Up to 10 21 cm -3 Concentration between The excess atoms injected during this process create stress in the channel region. wherein the concentration of the excess atoms of the isolation region is 10 20 cm -3 to 10 21 cm -3 between.

27. The method of forming a semiconductor device as claimed in claim 26, further comprising: A mask is used to inject multiple dopants into the transistor structure; as well as This mask is used to inject these excess atoms into the transistor structure.

28. The method of forming a semiconductor device as claimed in claim 26, wherein the excess atoms are implanted at an angle that is not perpendicular to (a) the longitudinal axis of the transistor structure, (b) the channel length of the transistor structure, or (c) both of the above.

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