System and method for storage instruction fusion in a microprocessor

Abstract

The present invention relates to a technology for executing storage and load instructions in a processor. The instructions are acquired, decoded and renamed. A storage instruction is acquired and decomposed into two operation codes. The first operation code is a storage address and the second operation code is storage data. When a fusion condition is detected, since the source register of the storage instruction matches the destination register of the arithmetic operation instruction, the second operation code is fused or merged with the arithmetic operation instruction. Then, the first operation code is distributed / issued to a first issue queue, and the second operation code is fused with the arithmetic operation instruction and distributed / issued to a second issue queue.

Description

[0001] Cross-application of related applications

[0002] This application claims priority to U.S. non-provisional patent application No. 16 / 054,413, filed on August 3, 2018, entitled “SYSTEM AND METHOD FOR STORAGE INSTRUCTION FUSION IN A MICROPROCESSOR,” the contents of which are incorporated herein by reference. Technical Field

[0003] The present invention generally relates to pipelined computer instruction processing in a microprocessor. Background Art

[0004] Instruction pipelining in computer architecture improves the utilization of CPU resources, making the execution time of computer applications shorter. Instruction pipelining is a technique used in the design of microprocessors, microcontrollers and CPUs to increase instruction throughput (i.e., the number of instructions that can be executed per unit time).

[0005] The main idea is to divide (or decompose) the processing of a CPU instruction defined by the instruction microcode into a series of independent micro-operation steps (also called "microinstructions", "micro-ops" or "μ-ops"), and store them at the end of each step. This allows the CPU control logic to process instructions at the maximum processing rate of the steps, which is less time than it would take to process the instructions as a single step. Therefore, during each CPU clock cycle, the steps of multiple instructions can be evaluated in parallel. The CPU can use multiple processor pipelines to further improve performance and fuse instructions (such as micro-ops) into a single macro-operation. Summary of the invention

[0006] According to one aspect of the present invention, there is provided a computer-implemented method for executing instructions in a processor, comprising: in an instruction fusion stage, in response to a source register of a storage instruction that matches a destination register of an arithmetic operation instruction, detecting an existing fusion condition; decomposing the storage instruction into two opcodes, wherein a first opcode includes a storage address and a second opcode includes storage data; distributing the first opcode to a first issue queue, and distributing the second opcode to a second issue queue after being fused with the arithmetic operation instruction.

[0007] Optionally, in any of the above aspects, the computer-implemented method further includes: retrieving one or more instructions from a memory based on a current address stored in an instruction point register, wherein the one or more instructions include at least one of the storage instruction and the arithmetic operation instruction.

[0008] Optionally, in any of the above aspects, the computer implementation method also includes: the decoder decodes the one or more instructions obtained into at least one execution operation; issues the first opcode stored in the first issue queue, thereby executing in the load / store stage; and issues the second opcode stored in the second issue queue and fused with the arithmetic operation instruction, thereby executing in an arithmetic logic unit (ALU).

[0009] Optionally, in any of the above aspects, the computer-implemented method further includes: when a corresponding one of the first issue queue and the second issue queue is issued, executing the first opcode and the second opcode fused with the arithmetic operation instruction respectively.

[0010] Optionally, in any one of the above aspects, the first opcode is executed in the load / store stage, and the second opcode fused with the arithmetic operation instruction is executed in the arithmetic logic unit (ALU).

[0011] Optionally, in any of the above aspects, the second opcode fused with the arithmetic operation instruction is stored in a single physical entry of the second issue queue.

[0012] Optionally, in any of the above aspects, the computer-implemented method further comprises: completing the storage instruction when all instructions before the storage instruction are completed, and when all instructions in the instruction group including the storage instruction are completed.

[0013] Optionally, in any one of the above aspects, the first opcode and the second opcode are micro-operation instructions.

[0014] Optionally, in any of the above aspects, the arithmetic operation instruction is one of addition, subtraction, multiplication, division or logical operators.

[0015] According to another aspect of the present invention, a processor for executing instructions is provided, comprising: fusion logic, for detecting the existence of a fusion condition in response to a source register of a storage instruction that matches a destination register of an arithmetic operation instruction; decomposition logic, for decomposing the storage instruction into two opcodes, wherein a first opcode includes a storage address and a second opcode includes storage data; a distributor, for distributing the first opcode to a first issue queue, and distributing the second opcode to a second issue queue after merging it with the arithmetic operation instruction.

[0016] According to another aspect of the present invention, a non-transitory computer-readable medium for storing computer instructions is provided, and when one or more processors execute the computer instructions, the one or more processors perform the following steps: detecting an existing fusion condition in response to a source register of a storage instruction that matches a destination register of an arithmetic operation instruction; decomposing the storage instruction into two opcodes, wherein a first opcode includes a storage address and a second opcode includes storage data; distributing the first opcode to a first issue queue, and distributing the second opcode to a second issue queue after merging it with the arithmetic operation instruction.

[0017] This summary is provided to introduce a selection of concepts in a simplified form that will be further described in the following detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor to help determine the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that address any or all of the disadvantages mentioned in the background. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The various aspects of the present invention are illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements.

[0019] Figure 1 An example of a pipeline of a processor provided according to an embodiment is shown;

[0020] Figure 2 It is a block diagram of temporary storage in a reorder buffer (ROB);

[0021] Figure 3 An example of a pipeline of a processor provided according to an embodiment is shown;

[0022] Figure 4A and Figure 4B It is a flow chart of how the instruction acquisition and execution process is implemented;

[0023] Figure 5A An example of the processing flow of instructions in a processing pipeline is shown;

[0024] Figure 5B shows an example of instructions stored in the scheduler;

[0025] FIG. 5C to FIG. 5E Shows Figure 4A and Figure 4B cycle in the process flow.

[0026] Figure 6 is a block diagram of a network device 800 that can be used to implement various embodiments. DETAILED DESCRIPTION

[0027] The present invention will now be described with reference to the accompanying drawings.The present invention generally relates to executing instructions in a microprocessor.

[0028] Processors typically include support for load memory operations and store memory operations to facilitate data transfers between the processor and a memory to which the processor may be coupled. A load memory operation (or load operation or load) is an operation that specifies the transfer of data from main memory to the processor (although the transfer may be performed in a cache). A store memory operation (or store operation or store) is an operation that specifies the transfer of data from the processor to the memory. In various implementations, the load operation and the store operation may be an implicit part of an instruction that includes a memory operation, or may be an explicit instruction.

[0029] A given load / store specifies the transfer of one or more bytes starting from a memory address calculated during the execution of the load / store. The memory address is called the data address of the load / store. The load / store itself (or the instruction derived from the load / store) is located by the instruction address used to fetch the instruction, also known as the program counter address. The data address is typically calculated by adding one or more address operands specified by the load / store to produce an effective address or virtual address.

[0030] In order to increase the operating speed of the microprocessor, some architectures are designed and implemented so that instructions in the microprocessor can be executed out of order. For example, a storage instruction can be decomposed into two parts: storage data and storage address, and then each part can be executed separately. The storage address part can be executed in a load store, and the storage data part can be executed in other execution resources. However, before execution, each execution resource has a corresponding scheduler, which holds the instruction before the source register is ready. Once the source register is ready, the corresponding instruction can be transferred to the execution resource for execution. When both parts have been executed, the storage instruction is completed.

[0031] The cracked storage instruction occupies additional scheduler entries, thereby reducing the efficiency of the use of the scheduler entries, and the number of scheduler entries directly limits the out-of-order instruction window. In order to address this inefficiency, the disclosed technology fuses two or more separate instructions (e.g., storage data and arithmetic operations) into a single fused instruction, which can then be stored and processed by the microprocessor. In this way, the two instructions are fused and the fused instruction is stored in a single (shared) table entry of the memory (e.g., scheduler), thereby shortening the wake-up delay by at least one cycle. In one embodiment, the fusion condition is detected in the mapping (renaming) stage of the pipeline without generating additional detection / comparison logic.

[0032] It is to be understood that embodiments of the present invention can be implemented in many different forms, and the scope of the claims should not be regarded as limiting the embodiments described herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the concepts of the embodiments of the present invention to those skilled in the art. In fact, the present invention is intended to cover substitutes, modifications and equivalents of these embodiments included in the spirit and scope of the present invention disclosed as defined by the appended claims. Further, for a clearer understanding, many specific details are provided in the following detailed description of the embodiments of the present invention. However, it will be clear to those skilled in the art that the subject matter of the present claim can be practiced without such specific details.

[0033] Figure 1 An example of a pipeline of a processor provided according to an embodiment is shown. In particular, the pipeline shows a storage instruction, which is passed down the pipeline by adding an instruction, thereby generating a fusion instruction. As shown in the figure, the processor 100 includes an instruction acquisition 102, a decoder 104, a mapper 106, a distributor 108, an arithmetic logic unit (ALU) scheduler 110, a load / store (LS) scheduler 112, an executor 114, a cache / memory interface 116, and a register file 118.

[0034] The instruction fetch 102, including the instruction cache 102A, is coupled to an exemplary instruction processing pipeline. The pipeline starts from the decoder 104 and passes through the mapper 106 and the distributor 108. The distributor and the issuer 108 are coupled to issue instructions to the executor 114, which may include any number of instruction execution resources, such as LS 114A, ALU 114B, floating-point (FP) 114C, and encryption 114D. The executor 114 is coupled to the register file 118. In addition, the ALU scheduler 110 and the LS scheduler 112 are coupled to the cache / memory interface 116.

[0035] The instruction fetch 102 may provide instructions (or instruction streams) to the pipeline for execution. Execution may be broadly defined as, but not limited to, processing instructions throughout the execution pipeline (e.g., by fetching, decoding, and executing), processing instructions by the instruction execution resources of the executor (e.g., LS and ALU), retrieving the value of a load target location (i.e., reading the location of a load instruction or writing to the location of a load instruction), or all operations in the entire pipeline resulting from a load instruction. In one embodiment, the instruction fetch 102 may also include forward-looking operations for conditional branches, where branch prediction logic (not shown) predicts the outcome of decisions that affect the flow of program execution, which at least helps to allow the processor 100 to speculatively execute instructions out of order.

[0036] In one embodiment, the instruction fetch 102 may fetch instructions from the instruction cache 102A and cache these instructions for downstream processing, and in response to an instruction cache miss, request data from a cache or memory through the cache / memory interface 116. Although not shown, the instruction fetch 102 may include a plurality of data structures in addition to the instruction cache 102A, such as an instruction buffer and / or structure for storing states related to thread selection and processing.

[0037] The decoder 104 may prepare the fetched instructions for further processing. The decoder 104 may include: a decoder circuit 104A for decoding the received instructions; a decode queue 104B for queuing the instructions to be decoded. The decoder 104 may also identify specific properties of the instruction (e.g., as specified by the instruction opcode) and determine the source register and destination register (if any) encoded in the instruction. In one embodiment, the decoder 104 is used to detect instruction dependencies and / or convert complex instructions into two or more simpler instructions for execution. For example, the decoder 104 may decode the instruction into one or more micro-operations (micro-operations), which may also be referred to as "instructions" when the micro-operations specify operations to be performed by the processor pipeline.

[0038] The mapper 106 renames the architectural purpose registers specified by the instruction by mapping the architectural purpose registers into the physical register space. Typically, register renaming can eliminate certain dependencies between instructions (e.g., read-before-write or "false" dependencies), thereby preventing unnecessary serialization of instruction execution. In one embodiment, the mapper 106 may include a reorder buffer (ROB) 106A that stores instructions being decoded and renamed. The relationship between architectural registers and physical registers may be described in detail in a mapping table (or mapping) 106B maintained in the mapper 106 to track the name mapping of each register. Below Figure 2 An example of an out-of-order processor implementation including renaming via the ROB 106A is described in detail in . In one embodiment, the ROB 106A and / or the mapping table 106B are provided independently from the mapper 106 .

[0039] When the instruction is a storage (or load) instruction, the mapper 106 is also responsible for using the decomposition logic to decompose (divide) the received instruction into two internal micro-operations. First, determine whether the received instruction is a storage instruction. If not, the instruction can be processed and executed down the pipeline. However, if the received instruction is determined to be a storage instruction, the instruction is decomposed into two internal micro-operations. The first micro-operation is a storage address sent to the LS scheduler 112, and the second micro-operation is the storage data sent to the ALU scheduler 110. It should be understood that although the ALU scheduler is described in the disclosed embodiment, the processing pipeline is not limited to such an embodiment. Other or additional schedulers, such as a floating point scheduler or an encryption scheduler, may also be used in the processing pipeline. It should also be understood that although the decomposition logic shown is in the mapper, the decomposition logic may also be included in other independent stages of the pipeline.

[0040] In one embodiment, the mapper 106 is also responsible for detecting a fusion condition and fusing instructions when a fusion condition is detected. It is also understood that although the fusion condition discussed is in the mapper, the fusion condition detection may also be included in other independent stages of the pipeline. Figure 3 Describes detection of fusion conditions and instruction fusion.

[0041] Once decoded and renamed, the instruction can be scheduled for distribution and subsequent execution. As shown in the figure, the distributor and issuer 108 are used to schedule (i.e., distribute and issue) instructions that can be distributed and subsequently executed. Instructions are queued in the distributor 108 and sent to schedulers, such as the ALU scheduler 110 and the LS scheduler 112, while waiting for operands to become available from, for example, early instructions. The schedulers 110 and / or 112 can receive instructions in program order, but the instructions can be issued without being executed in the program order (out of order). In one embodiment, the distributor 108 distributes instructions to a scheduling queue, such as the ALU scheduler 110 and the LS scheduler 112, wherein the scheduling queue stores decoded and renamed instructions. The scheduler can be a part of the distributor 108 or separated from the distributor 108. In one embodiment, the schedulers 110 and 112 represent any number of different schedulers, including reserved sites and central instruction windows, etc. The schedulers 110 and 112 are also coupled to a physical register file 118 .

[0042] Instructions issued from the ALU scheduler 110 and the LS scheduler 112 may be transmitted to any one or more executors (e.g., the LS 114A and the ALU 114B) for execution (execution). In one embodiment, architectural and non-architectural register files are physically implemented within or near the executors 114. It should be understood that in some embodiments, the processor 100 may include any number of executors, and the executors may or may not have similar or identical functionality.

[0043] The LS 114A can perform load and store operations on a data buffer or memory. Although not shown, the LS 114A may include a data cache, a load queue, and a store queue (not shown). In one embodiment, the load queue and the store queue are used to queue load instructions and store instructions, respectively, until the results can be submitted to the architecture state of the processor. The instructions in the queue can be executed speculatively, non-speculatively, or waiting to be executed. Each queue may include multiple entries, which may store load instructions / store instructions in program order.

[0044] The ALU 114B may perform arithmetic operations, such as addition, subtraction, multiplication, division, or other logical operations (e.g., AND, OR, or shift operations). In one embodiment, the ALU 114B may be an integer ALU that performs integer operations on 64-bit data operands. Alternatively, in an embodiment, the ALU 114B may be implemented to support multiple data bits including 16, 32, 128, and 256.

[0045] The floating point 114C can execute floating point and graphics-oriented instructions and provide results. For example, in one embodiment, the floating point 114C implements single-precision and double-precision floating point arithmetic instructions that conform to the IEEE floating point standard, such as addition, subtraction, multiplication, division, and certain transcendental functions.

[0046] In the above discussion, exemplary embodiments of each structure of the illustrated embodiment of the processor 100 are described. However, it should be noted that the illustrated embodiment is only one example of how the processor 100 may be implemented. Other configurations and variations are possible and contemplated.

[0047] Figure 2 A block diagram of temporary storage in a reorder buffer (ROB) is shown. As shown, at block 202, instructions are fetched and placed in an instruction fetch queue 204. In one example, the instructions are primitive combined instructions included in an executable program, and the primitive combined instructions reference registers (e.g., 32 and 64) defined in the architecture. These registers are the above-mentioned architectural registers, stored in an architectural register file 212 (registers R1 to R32 are shown).

[0048] In block 202, the fetched instructions may be executed in an out-of-order manner. To prevent the contents of the architecture register file 212 from being modified, the instructions may be executed in an out-of-order manner. Figure 1 The ROB 208 provides temporary registers for each instruction in the pipeline architecture to store results. The temporary results are ultimately written to the architecture register file 118 in program order. By tracking the program order in which instructions enter the pipeline, the ROB 208 is able to perform out-of-order processing. For each instruction received into the pipeline, the ROB 208 maintains temporary register storage.

[0049] exist Figure 2In the example of FIG. 2 , the ROB 208 stores six entries according to temporary register storage names P1 to P6. This example does not consider load / store instructions, which will be further discussed below in conjunction with Table I. The instructions acquired in box 202 and placed in the instruction acquisition queue 204 are decoded and renamed in box 205 and then placed in the ROB 208. For example, the first instruction (R1<-R1+R2) is renamed P1<-R1+R2. A table in the ROB 208 maintains and tracks the mapping of each register, where R1 is renamed to P1. When the next instruction (R2<-R1+R3) is received, the reference R1 is now P1, and the result is written to P2 (P2<-P1+R3), where R2 is renamed to P2. These renamed instructions are stored in the ROB 208 and the issue queue 210. The register mapping table 206 identifies how registers are mapped during renaming.

[0050] After the instructions are renamed and placed in the issue queue 210, the issue queue 210 determines which instructions can be executed in the next cycle. For each instruction, the issue queue 210 tracks whether the input operands of the instruction are available. In this case, the instructions can be executed in an execution resource, such as ALU 214A, 214B or 214C. For example, if six instructions are renamed and placed in the issue queue 210 at the same time in the first cycle, the issue queue 210 realizes that registers R1, R2, R4 and R5 are available in the architecture register file 212. Therefore, the first instruction and the sixth instruction have their operands ready and can begin execution. Each other instruction depends on at least one temporary register value that has not yet been generated. When the first instruction and the sixth instruction are executed, the results are written to P1 and P6 and broadcast to the issue queue 210. When the issue queue 210 knows that register R3 is ready, the result is written to P1 (now available in the issue queue) to prompt the execution of the second instruction in the next cycle. Upon completion, the availability of P2 is broadcast to the issue queue, and the third and fourth instructions are prompted to begin execution. Thus, when information is available in the issue queue 210, instructions are executed (e.g., in ALUs 214A to 214C) and completed (out of order).

[0051] Since the oldest instruction in the ROB 208 produces a valid result, the instruction can be made permanent (or committed), so that the result is written to the architectural register file 212. For example, P1 is a temporary storage for register R1, so the value P1 is copied to R1. The ROB 208 also sends a message to the issue queue 210 to suggest a name change. As will be appreciated, temporary storage P1 to P6 is also referred to as a rename register. At the same time, because it has not yet been committed, the instructions in the pipeline are referred to as speculative instructions.

[0052] Figure 3 FIG. 1 shows an example of a pipeline of a processor according to an embodiment. In the described embodiment, a portion 100A of the processor 100 includes a mapper 106 (including a fusion detector 106B), a distributor and issuer 108, an ALU scheduler 110, an LS scheduler 112, and an executor 114. Although only the portion 100A and the pipeline of the processor 100 are shown, it should be understood that the processor 100 may be combined with the pipeline of the processor 100. Figure 1 Each component discussed with respect to processor 100 is also shown as part of a complete processor pipeline in this embodiment.

[0053] like Figure 1 As described in the example architecture of , in order to increase the operating speed of the microprocessor, the microprocessor is allowed to execute instructions "out of order" inside. When a load or store instruction is received, the instruction is decomposed into two parts, storage data (STD) and storage address (STA), for execution in corresponding execution resources (such as LS 114A and ALU 114B) respectively. For ease of discussion, the following example will discuss storage instructions, although the discussion is also applicable to load instructions.

[0054] Once decomposed, the storage address portion is executed in LS 114A, while the storage data portion is executed in a separate execution resource (e.g., ALU 114B). Before execution, each storage instruction (e.g., storage address and storage data) is stored in a corresponding scheduler (e.g., the LS scheduler 112 and the ALU scheduler 110). Until execution can be performed, the two storage instructions are kept in their respective schedulers. For example, until the operand (e.g., from an earlier instruction) becomes available, the instructions are kept in their respective schedulers. At this point, the instructions can be sent to a suitable execution resource (in this case, LS 114A or ALU 114B). When both instruction decomposition parts have been executed, the storage instruction is completed.

[0055] exist Figure 1In the illustrated embodiment, as described above, the decomposed store instruction occupies additional scheduler entries: one LS scheduler 112 entry and one ALU scheduler 110 entry. Occupying additional entries in both schedulers reduces the efficiency of the use of the scheduler entries, and the number of scheduler entries directly limits the out-of-order instruction window.

[0056] exist Figure 3 In the illustrated embodiment, when a fusion condition is detected (i.e., if an early instruction generates data for storage), the decomposed storage data portion is fused with the operand (early instruction). For example, the mapper 106 may include a fusion detector (or fusion condition detector) 106B. When a fusion condition is detected, the fusion detector 106B is responsible for detecting the fusion condition and the fusion instruction. As shown in the decomposition diagram of the fusion detector 106B, the fusion detector 106B may set and store one or more conditions indicating the fusion condition. In the described example, the condition is set so that if the destination register of the operand instruction (early instruction) matches the source register of the storage data instruction, the two instructions are fused. Therefore, for storage instructions, no additional table entries are used, thereby more efficiently using scheduler resources and improving processing performance.

[0057] In this case, for the purposes of this discussion, the early instructions are ALU instructions. Therefore, if an ALU instruction (ADD) generates data for a data store (STD), then the data store and the ALU instruction are fused. Once fused, the store data and the ALU instruction can be stored as a single entry in the scheduler (ADD+STD), as shown in the ALU scheduler 110. This is similar to Figure 1 This is different from the ALU instruction (add) stored in a single entry of the ALU scheduler 110 in the storage data (STD) of the embodiment, which requires two ALU scheduler entries. Figure 1 In an embodiment, the storage address (STA) portion is stored in the LS scheduler 112.

[0058] More specifically, the following 4A to 5D ALU instructions that recognize architectural registers are described in more detail. Since ALU instructions generate data for store data, this renames its destination register to a new physical register, which the store instruction uses as its source register. The store data is then merged with the ALU instruction in the mapping (renaming) stage.

[0059] Once entering the scheduler, the instruction waits for the operand to be ready, and then is scheduled to execute. The distributor 108 is used to distribute the instructions ready to be executed, and sends the instructions to the corresponding scheduler. For example, as shown by the dotted arrow, the fusion instruction (ADD+STD) is sent to the ALU scheduler 110, and the storage address (STA) is sent to the LS scheduler 112. Once each source register is ready, the storage address and the fusion instruction can be issued independently. As mentioned above, in the case of the fusion instruction, whether the source register is ready depends on the ALU instruction source register. Therefore, after the issuance and execution of the ALU instruction, the data will be forwarded to the storage data for execution, without the need to additionally wake up the storage data.

[0060] In one embodiment, a scheduler (e.g., ALU scheduler 110 or scheduler 112) is used to maintain a scheduling queue, wherein the scheduling queue stores decoded renamed instructions and information about the various stages and states of storage instructions. For example, taking into account instruction dependencies and stage information, the scheduler can be used to select one or more instructions ready for execution. In another embodiment, the scheduler can be used to provide instruction sources and data to various execution resources in the executor 114 for the selected (i.e., scheduled) instructions. Instructions issued from the scheduler can be transmitted to one or more execution resources in the executor 114 to be executed. For example, as shown by the dotted line from the scheduler to the executor 114, a fused instruction (ADD+STD) can be sent to the ALU scheduler 114B, and the storage address (STA) can be sent to the LS 114A for execution.

[0061] Figure 4A and Figure 4B Shown according to Figure 3 The process disclosed in the figure can be found in Figure 3 For ease of discussion, reference will be made to FIG. 5A to FIG. 5D , FIG. 5A to FIG. 5D Shows the processor executing instructions and memory at various stages of the pipeline.

[0062] Figure 4A Step 402 in the embodiment involves the microprocessor 100A fetching program instructions from the instruction cache (or memory) 102A in block 502. Figure 5A In the example of , instructions (instr) 1 to 4 are fetched from instruction cache 102A at instruction fetch 102. In step 404, decoder 104 receives the fetched instructions 1 to 4 and decodes them by decoder circuit 104A. Figure 5AAn example instruction decode is shown in block 504 of , where each of instructions 1 to 4 has been decoded to display the respective instruction. For example, instructions 1 and 2 display write (ADD) instructions to architectural registers r1 and r2, respectively, while instructions 3 and 4 display store (STR) and load (LDR) instructions to architectural registers, respectively.

[0063] Once the instruction is decoded, it is sent to the mapper (or renamer) 106 stage of the pipeline for renaming in step 406. The mapper 106 is responsible for mapping and renaming the architectural (or logical) registers of the instruction to physical registers using a mapping table. The mapping table in box 506A is responsible for tracking where the architectural registers of the program can be found. For example, the architectural source register r3 can currently be found in physical register p3, the architectural source register r2 can be found in physical register p2, and so on. After executing the write instruction (ADD), the architectural destination register r1 can be found in physical register p4. A similar process also maps and renames the registers of instruction 2. In one embodiment, when an instruction is renamed, the speculative mapping table can track the latest mapping of the architectural registers, and the mapping table can be updated to indicate more current mappings.

[0064] In one embodiment, in step 408, the mapper 106 determines whether a store instruction (STR) is received in the fetched instructions. If a store instruction is not detected, the process proceeds to step 411, where the instruction is dispatched and issued to be stored in the ALU scheduler (or a scheduler corresponding to the type of instruction). When the stored instruction is ready, the instruction is issued to the execution resources in the executor 114 and executed to complete the instruction. If the mapper 106 determines that a store instruction has been received, the process proceeds to step 409, where the store instruction is decomposed into two micro-operations. Figure 5A As described, instruction 3 includes a store instruction (STR). As a result, the decoder circuit 106A in the mapper 106 recognizes instruction 3 as a store instruction and decomposes the instruction into two micro-operations: store address (STA) and store data (STD).

[0065] In step 410, the fusion detector 106B of the mapper 106 determines whether a fusion condition is detected. As described above, when the destination register of the operand instruction (early instruction) matches the source register of the store data instruction, it can be said that the fusion condition exists. If the fusion detector 106B determines that there is no fusion condition, the process proceeds to step 413, in which the decomposed storage address and storage data are distributed and issued to be stored in the LS scheduler 112 and the ALU scheduler 110 respectively. When the storage instruction is ready, the storage instruction is issued to the execution resources in the executor 114 for execution and completion of the instruction.

[0066] according to Figure 5A In the example of, in step 410, the fusion detector 106B detects that the fusion condition exists because instruction 3 is a storage instruction and has a source register that matches each earlier ALU instruction in the group (i.e., instruction 1 and instruction 2). For example, rename instruction 3 has a source register P1 that matches the destination register (i.e., P1) of instruction 2 (i.e., the earlier instruction). Since the source register matches the destination register, in step 414, the fusion condition is detected and the store data and ALU instructions can be fused into a single fused instruction. Instruction 2 (ADD_STD P1, P8, and P4) in the distribution and release block 508 is an example of a fused instruction. In step 414, the storage address and the fused instruction are distributed and released by the distributor 508 to the LS scheduler 112 and the ALU scheduler 110 (e.g., Figure 4B 415 and 424).

[0067] Continue to refer Figure 5A , the LS scheduler 112 and the ALU scheduler 110 are shown as instructions that were distributed in box 508 and are now issued to the corresponding schedulers. As shown, instruction 1 and instruction 2 are issued to the ALU scheduler 110 because both instructions include operation instructions, such as addition. In this example, instruction 1 (ADD) shows sources src1 (P2) and src2 (P3) in a ready state (indicated by "1") and the destination (dst) is P4. Instruction 2 (ADD_STD) is a fusion instruction of the previous step, indicating that the source src1 (P8) is in a read state, src2 (P4) is in a non-ready state (indicated by "0"), and the destination (dst) is P1.

[0068] Instruction 3 and instruction 4 include a store instruction and a load instruction. Since instruction 3 and instruction 4 are read-only instructions, instruction 3 and instruction 4 are issued to the LS scheduler 112. As shown in the distribution and issuance block 508, because the instructions are decomposed in the previous step, instruction 3 shows the storage address (STA) portion of the store instruction, and instruction 4 shows the load instruction (LDR). The LS scheduler 112 stores the load instruction, where the source src1 (P1) is in the not ready state and the destination is P5; and stores the address instruction, where the source src1 (P4) is in the not ready state.

[0069] Go to Figure 5B , which shows the scheduling allocation between the fused condition detection technique and the more traditional technique of not fusing instructions. Figure 5B In the embodiment of the present invention, during the instruction pipeline, the store data (STD) and the ALU instruction (ADD) are not fused together. Accordingly, the ALU scheduler requires additional entries to store the store data portion of the decomposed store instruction, and an additional wake-up cycle is required for the store data. Figure 5A In an embodiment of the present invention, the fused instruction (ADD_STD) uses a single entry in the ALU scheduler 110, thereby saving additional wake-up cycles.

[0070] exist Figure 4B , the process of implementing the microprocessor 100A continues, continuing to implement the fused instruction from step 414. It should be understood that, as described above, the store instruction or the decomposed store instruction (without the fused instruction) can also be implemented by the microprocessor 100A, as understood by those skilled in the art.

[0071] Once ready, the store address instruction stored in the LS scheduler 112 and the fused instruction (store data and ALU instruction) in the ALU scheduler 110 can be issued and executed. The process of storing and executing the store address (STA) portion is shown on the far left of the flowchart, starting from step 415 and continuing to step 422. The process of storing and executing the store data (STD) portion and the ALU instruction (ADD) is shown on the far right of the flowchart, starting from step 424 and continuing to step 422.

[0072] As described above, at step 415, the store address has been stored in the LS scheduler 112, and at step 424, the fused instruction (fused data store) has been stored in the ALU scheduler 110. When the registers associated with the store address instruction (and the load address instruction) are ready in the LS scheduler 112, the instruction is issued to the LS 114A of the executor 114 at step 416 for execution at step 418. Similarly, when the registers associated with the fused data store are ready in the ALU scheduler 110, the instruction is issued to the ALU 114B of the executor 114 at step 426 for execution at step 428.

[0073] FIG. 5C to FIG. 5E An example of issuing instructions from the scheduler for execution in corresponding execution resources is shown. During the first cycle (cycle X) of the microprocessor 100A, Figure 5C In the example embodiment of , instruction 1 (ADD) is selected to be issued to the execution resource (ALU 114B) because the source register is ready. The result of execution in destination P4 is then broadcast to all other entries in the scheduler. As shown, since instruction 2 and instruction 3 have source registers (P4) that match the destination register (P4) of instruction 1, the microprocessor 100A wakes up instruction 2 and instruction 3. After execution is complete, the address can be written to the load / store queue (not shown), and a signal can be sent to the completion stage (not shown) in step 422.

[0074] As used herein, the completion stage can be coupled to the mapper 106. In one embodiment, the completion stage can include the ROB 106A and coordinate the transfer of the speculative results to the architectural state of the microprocessor 100A. The completion stage can include other elements for handling instruction completion / disablement and / or storage history (including register values, etc.). Instruction completion refers to the guarantee of the result of the instruction to the architectural state of the microprocessor. For example, in one embodiment, the completion of the add instruction includes writing the result of the add instruction to the destination register. Similarly, as described above, the completion of the load instruction includes writing a value (e.g., a value retrieved from a cache or memory) to the destination register.

[0075] In the second cycle (cycle X+1), combined Figure 5DIn the example embodiment of , the microprocessor 100A selects instruction 2 and instruction 3 to be issued to the execution resource of the executor 114. In this case, instruction 2 is a fused instruction (including a storage data portion and an ALU instruction) and is sent to the ALU 114B for execution. Once executed, the result of execution in the destination P1 is broadcast to all remaining entries. Instruction 3 is the storage address portion of the storage instruction and is sent to the LS 114A for execution. Since instruction 3 has no destination address (instruction 3 is a storage address instruction), instruction 3 is not broadcast. As shown in the figure, since instruction 4 has a source register (P1) that matches the destination register (P1) of instruction 2, the microprocessor 100A wakes up instruction 4. After execution is completed, the data in the storage data can be written to the load / store queue, and the data in the ALU instruction can be written to the ALU114B. Then, a signal can be sent to the completion stage (not shown) in step 422.

[0076] In the last cycle (cycle X+2) of the microprocessor 100A, combined with Figure 5E , select instruction 4 to issue to the execution resource of executor 114. Instruction 4 is a load register instruction, which is sent to LS 114A for execution, and the execution result of the destination register (P5) is broadcasted. Since there are no remaining instructions in this stage, the address can be loaded into the load / store queue and a signal is sent to the completion stage in step 422.

[0077] Figure 6 6 is a block diagram of a network device 600 that can be used to implement various embodiments. A particular network device may utilize all of the components shown or only a subset of the components, and the degree of integration between devices may vary. In addition, the network device 600 may include multiple instances of components, such as multiple processing units, processors, memories, transmitters, receivers, and the like. The network device 600 may include a processing unit 601 equipped with one or more input / output devices (such as a network interface, a storage interface, etc.). The processing unit 601 may include a central processing unit (CPU) 610, a memory 620, a mass storage device 630, and an I / O interface 660 connected to a bus 670. The bus 670 may be one or more of several bus architectures of any type, including a memory bus or a memory controller, a peripheral bus, and the like.

[0078] The CPU 610 may include any type of electronic data processor. The memory 620 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), or a combination thereof.

[0079] In an embodiment, the memory 620 may include a ROM used at boot time and a DRAM used when executing a program to store programs and data. In an embodiment, the memory 620 is non-transitory. In one embodiment, the memory 620 includes: a detection module 620A, used to: detect the existence of a fusion condition in response to a source register of a storage instruction matching a destination register of an arithmetic operation instruction; a decomposition module 620B, used to decompose the storage instruction into two opcodes, wherein the first opcode includes a storage address and the second opcode includes storage data; a distribution module 620C, used to distribute the first opcode to a first issue queue, and to distribute the second opcode to a second issue queue after merging it with the arithmetic operation instruction; a fetch module 620D, used to fetch one or more instructions from the memory based on a current address stored in an instruction point register, wherein the one or more instructions include at least one of the storage instruction and the arithmetic operation instruction; an issue module 620E, used to issue the first opcode stored in the first issue queue so as to be executed in a load / store phase; and to issue the second opcode stored in the second issue queue and fused with the arithmetic operation instruction so as to be executed in an arithmetic logic unit (ALU) unit, referred to as ALU); an execution module 620F, used to execute the first opcode and the second opcode fused with the arithmetic operation instruction respectively when a corresponding one of the first issue queue and the second issue queue is issued.

[0080] The mass storage device 630 may include any type of storage device for storing data, programs, and other information and making them accessible via the bus 670. The mass storage device 630 may include one or more of the following: a solid-state disk, a hard disk drive, a magnetic disk drive, an optical disk drive, etc.

[0081] The processing unit 801 also includes one or more network interfaces 850, which may include wired links such as Ethernet cables or the like, and / or wireless links for accessing nodes or different networks. The network interface 650 allows the processing unit 601 to communicate with remote units via a network. For example, the network interface 650 may provide wireless communication via one or more transmitters / transmit antennas and one or more receivers / receive antennas. In one embodiment, the processing unit 601 is coupled to a local area network or a wide area network for data processing and communication with remote devices, such as other processing units, the Internet, remote storage facilities, or the like.

[0082] It should be understood that the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the subject matter more thorough and complete, and to fully convey the present invention to those skilled in the art. In fact, this subject matter is intended to cover substitutes, modifications and equivalents of these embodiments included in the spirit and scope of the subject matter disclosure defined by the appended claims. In addition, in the following detailed description of this subject matter, many specific details are set forth in order to provide a thorough understanding of this subject matter. However, it will be clear to those of ordinary skill in the art that the subject matter of this claim can be practiced without such specific details.

[0083] According to an embodiment of the present invention, various aspects of the present invention are described herein in conjunction with the flow chart and / or block diagram of the method, device (system) and computer program product. It should be understood that each frame of the flow chart and / or block diagram and the combination of frames in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to generate a mechanism so that these instructions executed by the processor of the computer or other programmable instruction execution device create a mechanism for implementing the function / action specified by one or more frames in the flow chart and / or block diagram.

[0084] The non-transitory computer-readable medium includes all types of computer-readable media, including magnetic storage media, optical storage media, and solid-state storage media, and specifically does not include signals. It should be understood that the software can be installed on the device and can be sold with the device. Alternatively, the software can be obtained and loaded into the device, including obtaining the software through optical disk media or in any way through a network or distribution system, for example, including obtaining the software from a server owned by the software developer or from a server not owned by the software developer but used by the software developer. For example, the software can be stored on a server for distribution over the Internet.

[0085] Computer-readable storage media excludes the propagated signal itself, can be accessed by a computer and / or processor, and includes removable and / or non-removable volatile and non-volatile internal and / or external media. For computers, various types of storage media accommodate the storage of data in any suitable digital format. Those skilled in the art will appreciate that other types of computer-readable media, such as zip drives, solid-state drives, tapes, flash cards, flash drives, ink cartridges, etc., can be used to store computer-executable instructions for executing the novel methods (actions) of the disclosed architecture.

[0086] The terms used herein are only for the purpose of describing specific aspects and are not intended to limit the present invention. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" used herein include their plural forms. It should be further understood that the term "comprising" used in this specification is used to illustrate the presence of the features, integers, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or combinations thereof.

[0087] What is presented in the description of the present invention is for explanation and illustration, not for exhaustive or limiting the present invention in the disclosed manner. Various modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. Various aspects of the present invention are selected and described in order to better explain the principles and practical applications of the present invention and to enable those skilled in the art to understand the various modifications to which the present invention is suitable for the intended specific use.

[0088] For the purposes of this document, each process associated with the disclosed technology can be performed serially and by one or more computing devices. Each step in the process can be performed by the same or different computing devices used in other steps, and each step is not necessarily performed by a single computing device.

[0089] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the claims is not necessarily limited to the specific features or acts described above. Instead, the specific features and acts described above are disclosed as exemplary ways of implementing the claims.

Claims

1. A computer-implemented method for executing instructions in a processor, characterized in that: include: In an instruction fusion stage, in response to a source register of a store instruction matching a destination register of an arithmetic operation instruction, detecting the presence of a fusion condition; Decomposing the storage instruction into two operation codes, wherein the first operation code includes the storage address and the second operation code includes the storage data; Distributing the first opcode to a first issue queue, and distributing the second opcode fused with the arithmetic operation instruction that generates data for the second opcode to a second issue queue; wherein the second opcode fused with the arithmetic operation instruction is stored in a single physical entry of the second issue queue; The decoder decodes the acquired one or more instructions into at least one execution operation; issuing the first opcode stored in the first issue queue for execution in a load / store phase; issuing the second opcode fused with the arithmetic operation instruction stored in the second issue queue for execution in an arithmetic logic unit; When a corresponding one of the first issue queue and the second issue queue is issued, the first opcode and the second opcode fused with the arithmetic operation instruction are respectively executed.

2. The computer-implemented method of claim 1, wherein: Also includes: Based on the current address stored in the instruction-point register, one or more instructions are retrieved from the memory, wherein the one or more instructions include at least one of the storage instruction and the arithmetic operation instruction.

3. The computer-implemented method of claim 1, wherein: The first operation code is executed in the load / store stage, and the second operation code fused with the arithmetic operation instruction is executed in the arithmetic logic unit.

4. The computer-implemented method according to any one of claims 1 to 3, characterized in that: Also includes: The store instruction is completed when all instructions preceding the store instruction are completed and when all instructions in the instruction group including the store instruction are completed.

5. The computer-implemented method according to any one of claims 1 to 3, characterized in that: The first operation code and the second operation code are micro-operation instructions.

6. The computer-implemented method according to any one of claims 1 to 3, characterized in that: The arithmetic operation instruction is one of addition, subtraction, multiplication, division or a logical operator.

7. A processor for executing instructions, characterized in that include: a fusion logic unit for: detecting the presence of a fusion condition in response to a source register of a store instruction matching a destination register of an arithmetic operation instruction; A decomposition logic unit, used to: decompose the storage instruction into two operation codes, wherein the first operation code includes a storage address and the second operation code includes storage data; a distributor, configured to: distribute the first opcode to a first issue queue, and distribute the second opcode fused with the arithmetic operation instruction generating data for the second opcode to a second issue queue; wherein the second opcode fused with the arithmetic operation instruction is stored in a single physical entry of the second issue queue; a decoder, the decoder decoding the acquired one or more instructions into at least one execution operation; an issue logic unit, configured to issue the first opcode stored in the first issue queue for execution in a load / store phase; an issue logic unit, configured to issue the second opcode fused with the arithmetic operation instruction stored in the second issue queue, so as to be executed in an arithmetic logic unit; An execution logic unit is used to: when a corresponding one of the first issue queue and the second issue queue is issued, respectively execute the first operation code and the second operation code fused with the arithmetic operation instruction.

8. The processor according to claim 7, characterized in that Also includes: The acquisition logic unit is used to: acquire one or more instructions from the memory based on the current address stored in the instruction point register, wherein the one or more instructions include at least one of the storage instruction and the arithmetic operation instruction.

9. The processor according to claim 7, characterized in that: The first operation code is executed in the load / store stage, and the second operation code fused with the arithmetic operation instruction is executed in the arithmetic logic unit.

10. A non-transitory computer-readable medium storing computer instructions, characterized in that: When one or more processors execute the computer instructions, the one or more processors are caused to perform the following steps: responsive to a source register of a store instruction matching a destination register of an arithmetic operation instruction, detecting the presence of a fusion condition; Decomposing the storage instruction into two operation codes, wherein the first operation code includes the storage address and the second operation code includes the storage data; Distributing the first opcode to a first issue queue, and distributing the second opcode fused with the arithmetic operation instruction that generates data for the second opcode to a second issue queue; wherein the second opcode fused with the arithmetic operation instruction is stored in a single physical entry of the second issue queue; The decoder decodes the acquired one or more instructions into at least one execution operation; issuing the first opcode stored in the first issue queue for execution in a load / store phase; issuing the second opcode fused with the arithmetic operation instruction stored in the second issue queue for execution in an arithmetic logic unit; When a corresponding one of the first issue queue and the second issue queue is issued, the first opcode and the second opcode fused with the arithmetic operation instruction are respectively executed.

11. The non-transitory computer readable medium of claim 10, wherein: It is also used to enable the one or more processors to perform the following steps: based on the current address stored in the instruction point register, obtain one or more instructions from the memory, wherein the one or more instructions include at least one of the storage instruction and the arithmetic operation instruction.

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