Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for preparing the same. In the semiconductor device, the aperture of a second contact hole extending to the active pattern, the isolation pattern and the inside of the trench gate structure along the direction of the trench gate structure is larger than the aperture of a first contact hole penetrating the first interlayer insulating layer, so that there is enough space between the bit line structure and the side walls of the contact holes on both sides thereof to form spacers, and the bit line has a larger line width, thereby reducing the process difficulty and the generation of device defects.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] In recent years, the design of electronic products generally has multifunctional and fast processing capabilities. In order to increase processing capabilities, such as computer systems or multifunctional electronic products, they all require large-capacity dynamic random access memory (DRAM). In order to increase memory capacity, the storage unit of the memory needs to be more integrated. However, in highly integrated semiconductor memory devices, in order to prevent the bit line from contacting other components on both sides, there needs to be enough space between the bit line and the side walls of the contact holes on both sides to form a spacer. In this case, the line width of the bit line needs to be designed to be smaller in size to meet the requirements of high integration, but this will increase the difficulty of the process, and the defects of the prepared device will also increase, and problems such as broken lines may occur. Summary of the invention

[0003] In view of the above problems, the present disclosure provides a semiconductor device and a method for manufacturing the same, which solves the technical problems in the prior art of high-integration semiconductor memory devices, such as small line width of bit lines leading to greater process difficulty and increased product defects.

[0004] In a first aspect, the present disclosure provides a semiconductor device, comprising:

[0005] Semiconductor substrate;

[0006] A plurality of active patterns arranged at intervals along a first direction on the substrate; wherein each of the active patterns is isolated by an isolation pattern;

[0007] A plurality of trench gate structures disposed at intervals along a second direction on the substrate; wherein each of the trench gate structures intersects with at least one of the active patterns;

[0008] a first interlayer insulating layer located above the substrate and covering the active pattern and the trench gate structure;

[0009] A contact hole penetrating the first interlayer insulating layer and extending to the active pattern, the isolation pattern and the inside of the trench gate structure; wherein the contact hole is arranged at a middle position of the active pattern, and the contact hole comprises a first contact hole penetrating the first interlayer insulating layer, and a second contact hole extending to the active pattern, the isolation pattern and the inside of the trench gate structure; the aperture of the second contact hole along the second direction is larger than the aperture of the first contact hole along the second direction;

[0010] A plurality of bit line structures are arranged at intervals along a third direction above the first interlayer insulating layer; wherein the bit line structure intersects the trench gate structure vertically, each of the bit line structures is connected to at least one of the active patterns through the corresponding contact hole, and the line width of the bit line structure along the second direction is smaller than the aperture of the first contact hole along the second direction.

[0011] According to an embodiment of the present disclosure, preferably, in the above-mentioned semiconductor device, in the second direction and at the corresponding contact hole position, the distance between the bit line structure and the side wall of the second contact hole is greater than the distance between the bit line structure and the side wall of the first contact hole.

[0012] According to an embodiment of the present disclosure, preferably, in the above-mentioned semiconductor device, in the second direction and at the corresponding contact hole position, the depth of the second contact hole on both sides of the bit line structure is greater than the depth of the second contact hole at the bit line structure position.

[0013] According to an embodiment of the present disclosure, preferably, in the above semiconductor device, the second contact hole is located between two adjacent trench gate structures.

[0014] According to an embodiment of the present disclosure, preferably, in the above-mentioned semiconductor device, the first interlayer insulating layer is a two-layer stacked structure, including an upper dielectric layer and a lower dielectric layer;

[0015] Wherein, the first contact hole comprises an upper contact hole penetrating the upper dielectric layer and a lower contact hole penetrating the lower dielectric layer;

[0016] The aperture of the lower contact hole along the second direction is larger than the aperture of the upper contact hole along the second direction;

[0017] The aperture of the upper contact hole along the second direction is the aperture of the first contact hole along the second direction.

[0018] According to an embodiment of the present disclosure, preferably, in the above-mentioned semiconductor device, the first interlayer insulating layer is a three-layer stacked structure, including an upper dielectric layer, a middle dielectric layer and a lower dielectric layer;

[0019] Wherein, the first contact hole comprises an upper contact hole penetrating the upper dielectric layer, a middle contact hole penetrating the middle dielectric layer, and a lower contact hole penetrating the lower dielectric layer;

[0020] The apertures of the upper contact hole and the lower contact hole along the second direction are both larger than the aperture of the middle contact hole along the second direction;

[0021] The aperture of the middle contact hole along the second direction is the aperture of the first contact hole along the second direction.

[0022] According to an embodiment of the present disclosure, preferably, the semiconductor device further comprises:

[0023] A spacer layer is located at the bottom and sidewalls of the contact hole and covers the bit line structure; wherein in the second direction, the spacer layer isolates the bit line structure from the sidewalls of the contact hole.

[0024] According to an embodiment of the present disclosure, preferably, in the above semiconductor device, the bit line structure includes:

[0025] a first conductive layer located above the first interlayer insulating layer and within the contact hole;

[0026] a metal barrier layer located above the first conductive layer;

[0027] A second conductive layer is located above the metal barrier layer.

[0028] According to an embodiment of the present disclosure, preferably, in the above-mentioned semiconductor device, the trench gate structure includes a trench, a gate insulating layer arranged on the sidewall and bottom of the trench, and a gate and a second interlayer insulating layer respectively filled in the lower and upper parts of the trench.

[0029] In a second aspect, the present disclosure provides a method for preparing a semiconductor device, comprising:

[0030] providing a semiconductor substrate;

[0031] Forming a plurality of active patterns spaced apart along a first direction on the substrate; wherein each of the active patterns is isolated by an isolation pattern;

[0032] Forming a plurality of trench gate structures spaced apart along a second direction on the substrate; wherein each of the trench gate structures intersects with at least one of the active patterns;

[0033] forming a first interlayer insulating layer over the substrate;

[0034] A contact hole is formed on the first interlayer insulating layer at a position corresponding to the middle position of the active pattern by a dry etching process, and the contact hole penetrates the first interlayer insulating layer and extends to the active pattern, the isolation pattern and the inside of the trench gate structure; wherein the contact hole includes a first contact hole penetrating the first interlayer insulating layer, and a second contact hole extending to the active pattern, the isolation pattern and the inside of the trench gate structure;

[0035] forming a bit line stack filled in the contact hole above the first interlayer insulation;

[0036] The bit line stack is patterned by a wet etching process to form a plurality of bit line structures arranged at intervals along the third direction above the first interlayer insulating layer, and the second contact hole is etched again at the same time, so that the aperture of the second contact hole after the second etching along the second direction is larger than the aperture of the first contact hole along the second direction;

[0037] The bit line structure intersects the trench gate structure vertically, each bit line structure is connected to at least one active pattern through the corresponding contact hole, and the line width of the bit line structure along the second direction is smaller than the aperture of the first contact hole along the second direction.

[0038] According to an embodiment of the present disclosure, preferably, in the method for preparing the above-mentioned semiconductor device, in the second direction and at the corresponding contact hole position, the distance between the bit line structure and the side wall of the second contact hole after re-etching is greater than the distance between the bit line structure and the side wall of the first contact hole.

[0039] According to an embodiment of the present disclosure, preferably, in the method for preparing the above-mentioned semiconductor device, in the second direction and at the corresponding contact hole position, the depth of the second contact hole on both sides of the bit line structure after re-etching is greater than the depth of the second contact hole at the position of the bit line structure.

[0040] According to an embodiment of the present disclosure, preferably, in the method for preparing the semiconductor device, the second contact hole is located between two adjacent trench gate structures.

[0041] According to an embodiment of the present disclosure, preferably, in the method for manufacturing the semiconductor device, the first interlayer insulating layer is a two-layer stacked structure, including an upper dielectric layer and a lower dielectric layer;

[0042] Wherein, the wet etching rate of the lower dielectric layer is greater than the wet etching rate of the upper dielectric layer.

[0043] According to an embodiment of the present disclosure, preferably, in the method for preparing the semiconductor device, the first interlayer insulating layer is a three-layer stacked structure, including an upper dielectric layer, a middle dielectric layer and a lower dielectric layer;

[0044] Wherein, the wet etching rates of the upper-layer medium and the lower-layer medium are both greater than the wet etching rate of the middle-layer medium.

[0045] According to an embodiment of the present disclosure, preferably, in the method for preparing the semiconductor device, forming a plurality of trench gate structures spaced apart along the second direction on the substrate comprises the following steps:

[0046] forming a plurality of grooves spaced apart along a second direction on the substrate;

[0047] forming a gate insulating layer on the sidewall and bottom of the trench;

[0048] Filling a gate material in the trench to form a gate; wherein the thickness of the gate is less than the depth of the trench;

[0049] A second interlayer insulating layer is formed in the trench and above the gate; wherein the trench, the gate insulating layer, the gate and the second interlayer insulating layer constitute a trench gate structure.

[0050] According to an embodiment of the present disclosure, preferably, in the method for manufacturing the semiconductor device, forming a bit line stack filled in the contact hole above the first interlayer insulation comprises the following steps:

[0051] forming a first conductive layer filled in the contact hole on the first interlayer insulating layer;

[0052] forming a metal barrier layer over the first conductive layer;

[0053] A second conductive layer is formed above the metal barrier layer; wherein the first conductive layer, the metal barrier layer and the second conductive layer constitute a bit line stack.

[0054] According to an embodiment of the present disclosure, preferably, the method for preparing the semiconductor device further includes:

[0055] A spacer layer is formed which covers the bit line structure and is disposed at the bottom and sidewalls of the contact hole; wherein in the second direction, the spacer layer isolates the bit line structure from the sidewalls of the contact hole.

[0056] Compared with the prior art, one or more embodiments of the above scheme may have the following advantages or beneficial effects:

[0057] The present disclosure provides a semiconductor device and a method for preparing the same. In the semiconductor device, the aperture of a second contact hole extending to the active pattern, the isolation pattern and the inside of the trench gate structure in the direction of the trench gate structure is larger than the aperture of a first contact hole penetrating the first interlayer insulating layer, so that there is sufficient space between the bit line structure and the side walls of the contact holes on both sides thereof to form spacers, and the bit line has a larger line width, thereby reducing the process difficulty and the generation of device defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0059] Figure 1 is a schematic front plan view of a semiconductor device shown in an exemplary embodiment of the present disclosure;

[0060] Figure 2 is a schematic cross-sectional structure diagram of a semiconductor device shown in an exemplary embodiment of the present disclosure;

[0061] Figure 3 is another cross-sectional structural schematic diagram of a semiconductor device shown in an exemplary embodiment of the present disclosure;

[0062] Figure 4 is a schematic cross-sectional structure diagram of another semiconductor device shown in an exemplary embodiment of the present disclosure;

[0063] Figure 5 is another cross-sectional structural schematic diagram of another semiconductor device shown in an exemplary embodiment of the present disclosure;

[0064] Figure 6 is a schematic cross-sectional structure diagram of another semiconductor device shown in an exemplary embodiment of the present disclosure;

[0065] Figure 7 is another cross-sectional structural schematic diagram of yet another semiconductor device shown in an exemplary embodiment of the present disclosure;

[0066] Figure 8 It is a schematic flow chart of a method for preparing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0067] Figure 9-20 It is a front top view schematic diagram and a cross-sectional structure schematic diagram formed by relevant steps of a method for preparing a semiconductor device shown in an exemplary embodiment of the present disclosure;

[0068] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale;

[0069] 101-substrate; 1011-active pattern; 102-isolation pattern; 103-trench gate structure; 104-first interlayer insulating layer; 105-contact hole; 1051-first contact hole; 1052-second contact hole; 106-first conductive layer; 107-metal barrier layer; 108-second conductive layer; 201-substrate; 2011-active pattern; 202-isolation pattern; 203-trench gate structure; 204-first interlayer insulating layer; 2041-upper dielectric layer; 2042-lower dielectric layer; 205 1-first contact hole; 2052-second contact hole; 206-first conductive layer; 207-metal barrier layer; 208-second conductive layer; 301-substrate; 3011-active pattern; 302-isolation pattern; 303-trench gate structure; 304-first interlayer insulating layer; 3041-upper dielectric layer; 3042-middle dielectric layer; 3043-lower dielectric layer; 3051-first contact hole; 3052-second contact hole; 306-first conductive layer; 307-metal barrier layer; 308-second conductive layer. DETAILED DESCRIPTION

[0070] The following will describe the implementation methods of the present disclosure in detail in conjunction with the accompanying drawings and embodiments, so that the implementation process of how the present disclosure applies technical means to solve technical problems and achieve corresponding technical effects can be fully understood and implemented accordingly. The embodiments of the present disclosure and the various features in the embodiments can be combined with each other without conflict, and the technical solutions formed are all within the protection scope of the present disclosure. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0071] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0072] It will be appreciated that spatially relative terms, such as "above", "above", "below", "under", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be appreciated that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below other elements" would be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0073] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0074] Embodiments of the present disclosure are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the present disclosure.

[0075] In order to thoroughly understand the present disclosure, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0076] Embodiment 1

[0077] like Figure 1 , Figure 2 and Figure 3 As shown, an embodiment of the present disclosure provides a semiconductor device, including: a semiconductor substrate 101, an active pattern 1011, an isolation pattern 102, a trench gate structure 103, a first interlayer insulating layer 104, a contact hole 105, a bit line structure (not marked in the figure) and a spacer (not shown in the figure).

[0078] The semiconductor substrate 101 may include, for example, at least one of a single crystal silicon substrate and a silicon epitaxial layer.

[0079] A plurality of active patterns 1011 are arranged at intervals on the substrate 101, each active pattern 1011 is parallel to each other and arranged along the first direction, the active pattern 1011 is formed by ion implantation to form a doping region (not shown in the figure), and the upper surface of the active pattern 1011 is flush with the upper surface of the substrate 101. The active patterns 1011 of two adjacent rows are arranged in an alternating manner, and the active patterns 1011 of two adjacent columns are arranged in an alternating manner.

[0080] Each active pattern 1011 is isolated from each other by an isolation pattern 102 . The isolation pattern 102 is used to define the shape of the active pattern 1011 .

[0081] A plurality of trench gate structures 103 are disposed on the substrate 101 at intervals. Each of the trench gate structures 103 is parallel to each other and is disposed along a second direction (eg Figure 1 Each trench gate structure 103 intersects with at least one active pattern 1011, illustratively, as shown in the horizontal direction. Figure 1 As shown, each trench gate structure 103 intersects with two corresponding rows of active patterns 1011. The trench gate structure 103 includes a trench, a gate insulating layer 1031 disposed on the sidewall and bottom of the trench, and a gate 1032 and a second interlayer insulating layer 1033 respectively filled in the lower and upper parts of the trench. The thickness of the gate is less than the depth of the trench, but the top of the gate 1032 is higher than the bottom of the doped region in the active pattern 1011 (not shown in the figure). The second interlayer insulating layer 1033 is formed of, for example, a silicon nitride layer and / or a silicon oxynitride layer.

[0082] The first interlayer insulating layer 104 is located above the substrate 101 and covers the active pattern 1011 and the trench gate structure 103 . The material of the first interlayer insulating layer 104 includes at least one of a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer.

[0083] The contact hole 105 penetrates the first interlayer insulating layer 104 and extends to the inside of the active pattern 1011, the isolation pattern 102 and the trench gate structure 103. The contact hole 105 is arranged at the middle position of the active pattern 1011, and the contact hole 105 includes a first contact hole 1051 penetrating the first interlayer insulating layer 104, and a second contact hole 1052 extending to the inside of the active pattern 1011, the isolation pattern 102 and the trench gate structure 103; the aperture D2 of the second contact hole 1052 along the second direction is greater than the aperture D1 of the first contact hole 1051 along the second direction. The second contact hole 1052 is located between two adjacent trench gate structures 103.

[0084] A plurality of spaced-apart bit line structures are located above the first interlayer insulating layer 104 and along a third direction (eg Figure 1 The bit line structure is vertically intersected with the trench gate structure 103, that is, the third direction is perpendicular to the second direction. Each bit line structure is connected to at least one active pattern 1011 through a corresponding contact hole 105, for example, Figure 1 As shown, each bit line structure is connected to the active pattern 1011 of a corresponding column through a corresponding contact hole 105 .

[0085] The line width of the bit line structure along the second direction is smaller than the aperture D1 of the first contact hole 1051 along the second direction, and the aperture D1 of the first contact hole 1051 along the second direction is smaller than the aperture D2 of the second contact hole 1052 along the second direction. In the second direction and at the corresponding contact hole 105 position, the distance between the bit line structure and the side wall of the second contact hole 1052 is greater than the distance between the bit line structure and the side wall of the first contact hole 1051. This structure can ensure that there is enough space between the bit line structure and the side walls of the contact holes 105 (second contact holes 1052) on both sides of the bit line structure to form spacers, while the bit line has a larger line width, reduces the process difficulty, and reduces the occurrence of device defects.

[0086] In addition, due to process reasons, the line width at the bottom of the bit line structure is larger than the line width of other parts. Correspondingly, in the second direction and at the corresponding contact hole 105 position, the depth of the second contact hole 1052 on both sides of the bit line structure is greater than the depth of the part at the position of the bit line structure. This structure fully ensures that there is enough space between the bottom of the bit line and the side wall of the contact hole 105 (second contact hole 1052) to form a spacer.

[0087] The bit line structure includes a first conductive layer 106, a metal barrier layer 107 and a second conductive layer 108. The material of the first conductive layer 106 and the second conductive layer 108 may be at least one of metal silicide, polysilicon, metal nitride and metal.

[0088] The first conductive layer 106 is located above the first interlayer insulating layer 104 and in the contact hole 105 , the metal barrier layer 107 is located above the first conductive layer, and the second conductive layer 108 is located above the metal barrier layer 107 .

[0089] The spacer layer (not shown) is located at the bottom and sidewalls of the contact hole 105 and covers the bit line structure. Figure 1 In the lateral direction (shown in FIG. 1 ), the spacer isolates the bit line structure from the sidewall of the contact hole 105. The spacer includes at least one of silicon nitride and silicon oxide.

[0090] In the prior art, the apertures of the first contact hole 1051 and the second contact hole 1052 are the same. Due to the high integration density, the aperture of the first contact hole 1051 is limited. In order to ensure that the aperture of the first contact hole 1051 is Figure 1 In the lateral direction (as shown in the figure), there is enough space between the bit line structure and the side wall of the contact hole 105 to form a spacer, so the line width of the bit line structure is limited. In the present embodiment, since the aperture D1 of the first contact hole 1051 along the second direction is smaller than the aperture D2 of the second contact hole 1052 along the second direction, in the second direction and at the corresponding contact hole 105 position, the distance between the bit line structure and the side wall of the second contact hole 1052 is greater than the distance between the bit line structure and the side wall of the first contact hole 1051. While ensuring that there is enough space between the bit line structure and the side walls of the contact holes 105 (second contact holes 1052) on both sides of the bit line, the bit line has a larger line width, thereby reducing the process difficulty and reducing the occurrence of device defects.

[0091] The present embodiment provides a semiconductor device, which includes a contact hole 105 that penetrates a first interlayer insulating layer 104 and extends to an active pattern 1011, an isolation pattern 102, and an interior of a trench gate structure 103; wherein the contact hole 105 is disposed at a middle position of the active pattern 1011, and the contact hole 105 includes a first contact hole 1051 that penetrates the first interlayer insulating layer 104, and a second contact hole 1051 that extends to the active pattern 1011, the isolation pattern 102, and the interior of the trench gate structure 103. The invention relates to a method for manufacturing a bit line structure of the present invention, wherein the first contact hole 1051 has a plurality of bit line structures disposed at intervals along the third direction and located above the first interlayer insulating layer 104; wherein the bit line structure intersects the trench gate structure 103 vertically, each bit line structure is connected to at least one active pattern 1011 through a corresponding contact hole 105, and the line width of the bit line structure along the second direction is smaller than the hole diameter D1 of the first contact hole 1051 along the second direction. While ensuring that there is enough space between the sidewalls of the bit line structure and the contact holes 105 (second contact holes 1052) on both sides thereof to form spacers, the bit line has a larger line width, thereby reducing the difficulty of the process and the generation of device defects.

[0092] Embodiment 2

[0093] like Figure 4 and Figure 5 As shown, an embodiment of the present disclosure provides another semiconductor device, including: a semiconductor substrate 201, an active pattern 2011, an isolation pattern 202, a trench gate structure 203, a first interlayer insulating layer 204, a contact hole (not marked in the figure), a bit line structure (not marked in the figure) and a spacer (not shown in the figure).

[0094] The semiconductor substrate 201 may include, for example, at least one of a single crystal silicon substrate and a silicon epitaxial layer.

[0095] A plurality of active patterns 2011 are arranged at intervals on the substrate 201, each active pattern 2011 is parallel to each other and arranged along the first direction, the active pattern 2011 is formed by ion implantation to form a doping region (not shown in the figure), and the upper surface of the active pattern 2011 is flush with the upper surface of the substrate 201. The active patterns 2011 of two adjacent rows are arranged in an alternating manner, and the active patterns 2011 of two adjacent columns are arranged in an alternating manner.

[0096] Each active pattern 2011 is isolated from each other by an isolation pattern 202 . The isolation pattern 202 is used to define the shape of the active pattern 2011 .

[0097] A plurality of trench gate structures 203 are arranged on the substrate 201 at intervals, each trench gate structure 203 is parallel to each other and arranged along the second direction, each trench gate structure 203 intersects with at least one active pattern 2011, and illustratively, each trench gate structure 203 intersects with two corresponding rows of active patterns 2011. The trench gate structure 203 includes a trench, a gate insulating layer 2031 arranged on the sidewall and bottom of the trench, and a gate 2032 and a second interlayer insulating layer 2033 filled in the lower and upper parts of the trench, respectively. The thickness of the gate is less than the depth of the trench, but the top of the gate 2032 is higher than the bottom of the doped region in the active pattern 2011 (not shown in the figure). The second interlayer insulating layer 2033 is formed of, for example, a silicon nitride layer and / or a silicon oxynitride layer.

[0098] The first interlayer insulating layer 204 is located above the substrate 201 and covers the active pattern 2011 and the trench gate structure 203. The material of the first interlayer insulating layer 204 includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. In this embodiment, the first interlayer insulating layer 204 is a two-layer stacked structure, including an upper dielectric layer 2041 and a lower dielectric layer 2042.

[0099] The contact hole penetrates the first interlayer insulating layer 204 and extends to the inside of the active pattern 2011, the isolation pattern 202 and the trench gate structure 203. The contact hole is arranged at the middle of the active pattern 2011, and the contact hole includes a first contact hole 2051 penetrating the first interlayer insulating layer 204, and a second contact hole 2052 extending to the inside of the active pattern 2011, the isolation pattern 202 and the trench gate structure 203.

[0100] The first contact hole 2051 includes an upper contact hole (not marked in the figure) penetrating the upper dielectric layer 2041 and a lower contact hole (not marked in the figure) penetrating the lower dielectric layer 2042. The aperture D4 of the lower contact hole along the second direction is larger than the aperture D3 of the upper contact hole along the second direction. Although the aperture D4 of the lower contact hole along the second direction is larger than the aperture D3 of the upper contact hole along the second direction, considering the first interlayer insulating layer 204 as a whole, the aperture of the first contact hole 2051 along the second direction is the aperture D3 of the upper contact hole along the second direction.

[0101] The diameter D5 of the second contact hole 2052 along the second direction is larger than the diameter D3 of the first contact hole 2051 along the second direction. The second contact hole 2052 is located between two adjacent trench gate structures 203 .

[0102] A plurality of spaced bit line structures (not labeled in the figure) are located above the first interlayer insulating layer 204 and arranged along the third direction; wherein the bit line structure intersects the trench gate structure 203 vertically, that is, the third direction is perpendicular to the second direction. Each bit line structure is connected to at least one active pattern 2011 through a corresponding contact hole. Exemplarily, each bit line structure is connected to the active pattern 2011 of the corresponding column through a corresponding contact hole.

[0103] The line width of the bit line structure along the second direction is smaller than the aperture D3 of the first contact hole 2051 along the second direction, and the aperture D3 of the first contact hole 2051 along the second direction is smaller than the aperture D5 of the second contact hole 2052 along the second direction. In the second direction and at the corresponding contact hole position, the distance between the bit line structure and the side wall of the second contact hole 2052 is greater than the distance between the bit line structure and the side wall of the first contact hole 2051. This structure can ensure that there is enough space between the bit line structure and the side walls of the contact holes (second contact holes 2052) on both sides of the bit line structure to form spacers, while the bit line has a larger line width, reduces the process difficulty, and reduces the occurrence of device defects.

[0104] That is to say, although the first interlayer insulating layer 204 is a two-layer stacked structure, as long as the aperture of the contact hole in one layer meets the integration requirement, the aperture of the contact hole in other layers can be relatively larger (can be consistent with the aperture of the second contact hole 2052), further ensuring that there is sufficient space between the bit line structure and the side walls of the contact holes on both sides to form spacers.

[0105] In addition, due to process reasons, the line width at the bottom of the bit line structure is larger than the line width of other parts. Correspondingly, in the second direction and at the corresponding contact hole position, the depth of the second contact hole 2052 on both sides of the bit line structure is greater than the depth of the part at the position of the bit line structure. This structure fully ensures that there is enough space between the bottom of the bit line and the side wall of the contact hole (second contact hole 2052) to form a spacer.

[0106] The bit line structure includes a first conductive layer 206, a metal barrier layer 207 and a second conductive layer 208. The material of the first conductive layer 206 and the second conductive layer 208 may be at least one of metal silicide, polysilicon, metal nitride and metal.

[0107] The first conductive layer 206 is located above the first interlayer insulating layer 204 and in the contact hole, the metal barrier layer 207 is located above the first conductive layer, and the second conductive layer 208 is located above the metal barrier layer 207 .

[0108] The spacer layer (not shown) is located at the bottom and sidewall of the contact hole and covers the bit line structure. In the second direction, the spacer layer isolates the bit line structure from the sidewall of the contact hole. The spacer layer includes at least one of silicon nitride and silicon oxide.

[0109] In the prior art, the apertures of the first contact hole 2051 and the second contact hole 2052 are the same. Due to the high integration density, the aperture of the first contact hole 2051 is limited. In order to ensure that there is enough space between the bit line structure and the side wall of the contact hole in the second direction to form a spacer, the line width of the bit line structure is limited. In the present embodiment, since the aperture D3 of the first contact hole 2051 along the second direction is smaller than the aperture D5 of the second contact hole 2052 along the second direction, in the second direction and at the corresponding contact hole position, the distance between the bit line structure and the side wall of the second contact hole 2052 is greater than the distance between the bit line structure and the side wall of the first contact hole 2051. While ensuring that there is enough space between the bit line structure and the side walls of the contact holes (second contact holes 2052) on both sides of the bit line structure to form a spacer, the bit line has a larger line width, thereby reducing the process difficulty and reducing the generation of device defects.

[0110] The present embodiment provides a semiconductor device, which includes a contact hole penetrating a first interlayer insulating layer 204 and extending to an active pattern 2011, an isolation pattern 202 and an interior of a trench gate structure 203; wherein the contact hole is arranged at a middle position of the active pattern 2011, and the contact hole includes a first contact hole 2051 penetrating the first interlayer insulating layer 204, and a second contact hole 2052 extending to an interior of the active pattern 2011, the isolation pattern 202 and the trench gate structure 203; an aperture D5 of the second contact hole 2052 along the second direction is larger than an aperture D3 of the first contact hole 2051 along the second direction; and a plurality of bit line structures arranged at intervals along a third direction above the first interlayer insulating layer 204; wherein the bit line structure intersects the trench gate structure 203 perpendicularly, each bit line structure is connected to at least one active pattern 2011 through a corresponding contact hole, and a line width of the bit line structure along the second direction is smaller than an aperture D3 of the first contact hole 2051 along the second direction. While ensuring that there is enough space between the bit line structure and the side walls of the contact holes (second contact holes 2052) on both sides thereof to form spacers, the bit line has a larger line width, which reduces the process difficulty and reduces the generation of device defects.

[0111] Embodiment 3

[0112] like Figure 6 and Figure 7 As shown, the embodiment of the present disclosure provides another semiconductor device, including: a semiconductor substrate 301, an active pattern 3011, an isolation pattern 302, a trench gate structure 303, a first interlayer insulating layer 304, a contact hole, a bit line structure (not marked in the figure) and a spacer (not shown in the figure).

[0113] The semiconductor substrate 301 may include, for example, at least one of a single crystal silicon substrate and a silicon epitaxial layer.

[0114] A plurality of active patterns 3011 are arranged at intervals on the substrate 301, each active pattern 3011 is parallel to each other and arranged along the first direction, the active pattern 3011 is formed by ion implantation to form a doping region (not shown in the figure), and the upper surface of the active pattern 3011 is flush with the upper surface of the substrate 301. The active patterns 3011 of two adjacent rows are arranged in an alternating manner, and the active patterns 3011 of two adjacent columns are arranged in an alternating manner.

[0115] Each active pattern 3011 is isolated from each other by an isolation pattern 302 . The isolation pattern 302 is used to define the shape of the active pattern 3011 .

[0116] A plurality of trench gate structures 303 are arranged on the substrate 301 at intervals, each trench gate structure 303 is parallel to each other and arranged along the second direction, each trench gate structure 303 intersects with at least one active pattern 3011, and illustratively, each trench gate structure 303 intersects with two corresponding rows of active patterns 3011. The trench gate structure 303 includes a trench, a gate insulating layer 3031 arranged on the sidewall and bottom of the trench, and a gate 3032 and a second interlayer insulating layer 3033 filled in the lower and upper parts of the trench respectively. The thickness of the gate is less than the depth of the trench, but the top of the gate 3032 is higher than the bottom of the doped region in the active pattern 3011 (not shown in the figure). The second interlayer insulating layer 3033 is formed of, for example, a silicon nitride layer and / or a silicon oxynitride layer.

[0117] The first interlayer insulating layer 304 is located above the substrate 301 and covers the active pattern 3011 and the trench gate structure 303. The material of the first interlayer insulating layer 304 includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. In this embodiment, the first interlayer insulating layer 304 is a three-layer stacked structure, including an upper dielectric layer 3041, a middle dielectric layer 3042, and a lower dielectric layer 3043.

[0118] The contact hole penetrates the first interlayer insulating layer 304 and extends to the inside of the active pattern 3011, the isolation pattern 302 and the trench gate structure 303. The contact hole is arranged at the middle of the active pattern 3011, and the contact hole includes a first contact hole 3051 penetrating the first interlayer insulating layer 304, and a second contact hole 3052 extending to the inside of the active pattern 3011, the isolation pattern 302 and the trench gate structure 303.

[0119] The first contact hole 3051 includes an upper contact hole penetrating the upper dielectric layer 3041, a middle contact hole penetrating the middle dielectric layer 3042, and a lower contact hole penetrating the lower dielectric layer 3043. The apertures D7 of the upper contact hole and the lower contact hole along the second direction are larger than the aperture D6 of the middle contact hole along the second direction. Although the apertures D7 of the upper contact hole and the lower contact hole along the second direction are larger than the aperture D6 of the middle contact hole along the second direction, considering the first interlayer insulating layer 304 as a whole, the aperture of the first contact hole 3051 along the second direction is the aperture D6 of the middle contact hole along the second direction.

[0120] The diameter D8 of the second contact hole 3052 along the second direction is larger than the diameter D6 of the first contact hole 3051. The second contact hole 3052 is located between two adjacent trench gate structures 303.

[0121] A plurality of spaced bit line structures are located above the first interlayer insulating layer 304 and arranged along the third direction; wherein the bit line structure intersects the trench gate structure 303 vertically, that is, the third direction is perpendicular to the second direction. Each bit line structure is connected to at least one active pattern 3011 through a corresponding contact hole. Exemplarily, each bit line structure is connected to the active pattern 3011 of the corresponding column through a corresponding contact hole.

[0122] The line width of the bit line structure along the second direction is smaller than the aperture D6 of the first contact hole 3051 along the second direction, and the aperture D6 of the first contact hole 3051 along the second direction is smaller than the aperture D8 of the second contact hole 3052 along the second direction. In the second direction and at the corresponding contact hole position, the distance between the bit line structure and the side wall of the second contact hole 3052 is greater than the distance between the bit line structure and the side wall of the first contact hole 3051. This structure can ensure that there is enough space between the bit line structure and the side walls of the contact holes (second contact holes 3052) on both sides of the bit line structure to form spacers, while the bit line has a larger line width, reduces the process difficulty, and reduces the occurrence of device defects.

[0123] That is to say, although the first interlayer insulating layer 304 is a three-layer stacked structure, as long as the aperture of the contact hole in one layer meets the integration requirement, the aperture of the contact hole in other layers can be relatively larger (can be consistent with the aperture of the second contact hole 3052), further ensuring that there is sufficient space between the bit line structure and the side walls of the contact holes on both sides to form spacers.

[0124] In addition, due to process reasons, the line width at the bottom of the bit line structure is larger than the line width of other parts. Correspondingly, in the second direction and at the corresponding contact hole position, the depth of the second contact hole 3052 on both sides of the bit line structure is greater than the depth of the part at the position of the bit line structure. This structure fully ensures that there is enough space between the bottom of the bit line and the side wall of the contact hole (second contact hole 3052) to form a spacer.

[0125] The bit line structure includes a first conductive layer 306, a metal barrier layer 307 and a second conductive layer 308. The material of the first conductive layer 306 and the second conductive layer 308 may be at least one of metal silicide, polysilicon, metal nitride and metal.

[0126] The first conductive layer 306 is located above the first interlayer insulating layer 304 and in the contact hole, the metal barrier layer 307 is located above the first conductive layer, and the second conductive layer 308 is located above the metal barrier layer 307 .

[0127] The spacer layer (not shown) is located at the bottom and sidewall of the contact hole and covers the bit line structure. In the second direction, the spacer layer isolates the bit line structure from the sidewall of the contact hole. The spacer layer includes at least one of silicon nitride and silicon oxide.

[0128] In the prior art, the apertures of the first contact hole 3051 and the second contact hole 3052 are the same. Due to the high integration density, the aperture of the first contact hole 3051 is limited. In order to ensure that there is enough space between the bit line structure and the side wall of the contact hole in the second direction to form a spacer, the line width of the bit line structure is limited. In the present embodiment, since the aperture D6 of the first contact hole 3051 along the second direction is smaller than the aperture D8 of the second contact hole 3052 along the second direction, in the second direction and at the corresponding contact hole position, the distance between the bit line structure and the side wall of the second contact hole 3052 is greater than the distance between the bit line structure and the side wall of the first contact hole 3051. While ensuring that there is enough space between the bit line structure and the side walls of the contact holes (second contact holes 3052) on both sides of the bit line structure to form a spacer, the bit line has a larger line width, thereby reducing the process difficulty and reducing the generation of device defects.

[0129] The present embodiment provides a semiconductor device, which includes a contact hole that penetrates a first interlayer insulating layer 304 and extends to an active pattern 3011, an isolation pattern 302, and a trench gate structure 303; wherein the contact hole is arranged at a middle position of the active pattern 3011, and the contact hole includes a first contact hole 3051 that penetrates the first interlayer insulating layer 304, and a second contact hole 3052 that extends to the active pattern 3011, the isolation pattern 302, and the trench gate structure 303; the aperture D8 of the second contact hole 3052 along the second direction is larger than the aperture D6 of the first contact hole 3051 along the second direction; and a plurality of bit line structures that are arranged at intervals along a third direction above the first interlayer insulating layer 304; wherein the bit line structure intersects the trench gate structure 303 perpendicularly, each bit line structure is connected to at least one active pattern 3011 through a corresponding contact hole, and the line width of the bit line structure along the second direction is smaller than the aperture D6 of the first contact hole 3051 along the second direction. While ensuring that there is enough space between the bit line structure and the side walls of the contact holes (second contact holes 3052) on both sides thereof to form spacers, the bit line has a larger line width, which reduces the process difficulty and reduces the generation of device defects.

[0130] Embodiment 4

[0131] Based on the first embodiment, this embodiment provides a method for preparing a semiconductor device. Figure 8 It is a schematic flow chart of a method for preparing a semiconductor device shown in an embodiment of the present disclosure. Figure 9-Figure 20 The following is a schematic diagram of a front view and a schematic diagram of a cross-sectional structure formed by the relevant steps of a method for preparing a semiconductor device shown in an embodiment of the present disclosure. Figure 8 and Figure 9-Figure 20The detailed steps of an exemplary method for preparing a semiconductor device proposed in an embodiment of the present disclosure are described.

[0132] like Figure 8 As shown, the method for preparing the semiconductor device of this embodiment includes the following steps:

[0133] Step S101: providing a semiconductor substrate 101 .

[0134] The substrate 101 may include, for example, at least one of a single crystal silicon substrate 101 and a silicon epitaxial layer.

[0135] Step S102 : forming a plurality of active patterns 1011 arranged at intervals along a first direction on the substrate 101 ; wherein each active pattern 1011 is isolated by an isolation pattern 102 .

[0136] A plurality of active patterns 1011 are arranged at intervals on the substrate 101, each active pattern 1011 is parallel to each other and arranged along the first direction, the active pattern 1011 is formed by ion implantation to form a doping region (not shown in the figure), and the upper surface of the active pattern 1011 is flush with the upper surface of the substrate 101. The active patterns 1011 of two adjacent rows are arranged in an alternating manner, and the active patterns 1011 of two adjacent columns are arranged in an alternating manner.

[0137] Each active pattern 1011 is isolated from each other by an isolation pattern 102 . The isolation pattern 102 is used to define the shape of the active pattern 1011 .

[0138] Step S103: Fig. 9 , Fig.10 and Fig.11 As shown, a plurality of trench gate structures 103 arranged at intervals along the second direction are formed on the substrate 101 ; wherein each trench gate structure 103 intersects with at least one active pattern 1011 .

[0139] A plurality of trench gate structures 103 are disposed on the substrate 101 at intervals. Each of the trench gate structures 103 is parallel to each other and is disposed along a second direction (eg Fig. 9 Each trench gate structure 103 intersects with at least one active pattern 1011, illustratively, as shown in the horizontal direction. Fig. 9 As shown, each trench gate structure 103 intersects with two corresponding rows of active patterns 1011. The trench gate structure 103 includes a trench (not marked in the figure), a gate insulating layer 1031 disposed on the sidewall and bottom of the trench, and a gate 1032 and a second interlayer insulating layer 1033 respectively filled in the lower and upper parts of the trench. The top of the gate 1032 is higher than the bottom of the doped region in the active pattern 1011 (not shown in the figure). The second interlayer insulating layer 1033 is formed of, for example, a silicon nitride layer and / or a silicon oxynitride layer.

[0140] Specifically, step S103 includes the following steps:

[0141] S103a: forming a plurality of grooves spaced apart along a second direction on the substrate 101;

[0142] S103b: forming a gate insulating layer 1031 on the sidewall and bottom of the trench;

[0143] S103c: filling the trench with a gate material to form a gate 1032; wherein the thickness of the gate 1032 is smaller than the depth of the trench;

[0144] S103d: forming a second interlayer insulating layer 1033 in the trench and above the gate; wherein the trench, the gate insulating layer 1031 , the gate and the second interlayer insulating layer 1033 constitute a trench gate structure 103 .

[0145] Step S104 : forming a first interlayer insulating layer 104 on the substrate 101 .

[0146] The first interlayer insulating layer 104 is located above the substrate 101 and covers the active pattern 1011 and the trench gate structure 103 . The material of the first interlayer insulating layer 104 includes at least one of a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer.

[0147] Step S105: Fig.12 , Fig.13 and Fig.14 As shown, a contact hole 105 is formed on the first interlayer insulating layer 104 at a position corresponding to the middle position of the active pattern 1011 by a dry etching process, which penetrates the first interlayer insulating layer 104 and extends to the active pattern 1011, the isolation pattern 102 and the trench gate structure 103; wherein the contact hole 105 includes a first contact hole 1051 that penetrates the first interlayer insulating layer 104, and a second contact hole 1052 that extends to the active pattern 1011, the isolation pattern 102 and the trench gate structure 103.

[0148] The contact hole 105 penetrates the first interlayer insulating layer 104 and extends to the inside of the active pattern 1011, the isolation pattern 102 and the trench gate structure 103. The contact hole 105 is arranged at the middle position of the active pattern 1011, and the contact hole 105 includes a first contact hole 1051 penetrating the first interlayer insulating layer 104, and a second contact hole 1052 extending to the inside of the active pattern 1011, the isolation pattern 102 and the trench gate structure 103. Due to the anisotropy of dry etching, the aperture (along all directions) of the second contact hole 1052 formed in this step is consistent with the aperture (along all directions) of the first contact hole 1051. The second contact hole 1052 is located between two adjacent trench gate structures 103.

[0149] Step S106: Fig.15 , Fig.16 and Fig.17 As shown, a bit line stack filled in the contact hole 105 is formed over the first interlayer insulation.

[0150] The bit line stack includes a first conductive layer 106, a metal barrier layer 107 and a second conductive layer 108. The first conductive layer 106 and the second conductive layer 108 may be made of at least one of metal silicide, polysilicon, metal nitride and metal.

[0151] The first conductive layer 106 is located above the first interlayer insulating layer 104 and in the contact hole 105 , the metal barrier layer 107 is located above the first conductive layer, and the second conductive layer 108 is located above the metal barrier layer 107 .

[0152] Specifically, step S106 includes the following steps:

[0153] S106a: forming a first conductive layer 106 filling the contact hole 105 on the first interlayer insulating layer 104;

[0154] S106b: forming a metal barrier layer 107 on the first conductive layer 106;

[0155] S106c: forming a second conductive layer 108 on the metal barrier layer 107; wherein the first conductive layer 106, the metal barrier layer 107 and the second conductive layer 108 constitute a bit line stack.

[0156] Step S107: Fig.18 , Fig.19 and Fig. 20 As shown, the bit line stack is patterned by a wet etching process to form a third direction (eg, Fig.18 The bit line structures are arranged at intervals along the second direction (in the vertical direction shown in the figure), and the second contact hole 1052 is etched again at the same time, so that the aperture D2 of the second contact hole 1052 along the second direction after the second etching is larger than the aperture D1 of the first contact hole 1051 along the second direction; wherein the bit line structure intersects the trench gate structure 103 vertically, each bit line structure is connected to at least one active pattern 1011 through the corresponding contact hole 105, and the line width of the bit line structure along the second direction is smaller than the aperture D1 of the first contact hole 1051 along the second direction.

[0157] Due to the isotropy of wet etching, during the etching of the bit line stack, the second contact hole 1052 along the second direction will be etched again to form a side corrosion structure, that is, the aperture D2 of the second contact hole 1052 along the second direction after the second etching is larger than the aperture D1 of the first contact hole 1051 along the second direction. In the second direction and at the corresponding contact hole 105 position, the distance between the bit line structure and the side wall of the second contact hole 1052 after the second etching is larger than the distance between the bit line structure and the side wall of the first contact hole 1051. This structure can ensure that there is enough space between the bit line structure and the side walls of the contact holes 105 (second contact holes 1052) on both sides to form spacers, and the bit line has a larger line width, which reduces the process difficulty and reduces the generation of device defects.

[0158] In addition, in the wet etching process, the line width at the bottom of the bit line structure is larger than the line width of other parts. Correspondingly, in the second direction and at the corresponding contact hole 105 position, the depth of the second contact hole 1052 on both sides of the bit line structure after re-etching is greater than the depth of the part at the position of the bit line structure. This structure fully ensures that there is enough space between the bottom of the bit line and the side wall of the contact hole 105 (second contact hole 1052) to form a spacer.

[0159] Step S108: forming a spacer layer (not shown) covering the bit line structure and disposed at the bottom and sidewalls of the contact hole 105; wherein the spacer layer isolates the bit line structure from the sidewalls of the contact hole 105 in the second direction.

[0160] The spacer layer is located at the bottom and sidewalls of the contact hole 105 and covers the bit line structure. Fig.18 In the lateral direction (shown in FIG. 1 ), the spacer isolates the bit line structure from the sidewall of the contact hole 105. The spacer includes at least one of silicon nitride and silicon oxide.

[0161] In the prior art, the apertures of the first contact hole 1051 and the second contact hole 1052 are the same. Due to the high integration density, the aperture of the first contact hole 1051 is limited. In order to ensure that the aperture of the first contact hole 1051 is Fig.18In the lateral direction (as shown in the figure), there is enough space between the bit line structure and the side wall of the contact hole 105 to form a spacer, and the line width of the bit line structure is limited. In the present embodiment, through the wet etching process, the aperture D1 of the first contact hole 1051 finally formed along the second direction is smaller than the aperture D2 of the second contact hole 1052 finally formed along the second direction. Then, in the second direction and at the corresponding contact hole 105 position, the distance between the bit line structure and the side wall of the second contact hole 1052 is greater than the distance between the bit line structure and the side wall of the first contact hole 1051. While ensuring that there is enough space between the bit line structure and the side walls of the contact holes 105 (second contact holes 1052) on both sides of the bit line, the bit line has a larger line width, which reduces the process difficulty and reduces the generation of device defects.

[0162] The present disclosure provides a method for preparing a semiconductor device, the method comprising forming a contact hole 105 penetrating the first interlayer insulating layer 104 and extending to the inside of the active pattern 1011, the isolation pattern 102 and the trench gate structure 103 on the first interlayer insulating layer 104 at a position corresponding to the middle position of the active pattern 1011 by a dry etching process; wherein the contact hole 105 comprises a first contact hole 1051 penetrating the first interlayer insulating layer 104 and extending to the inside of the active pattern 1011, the isolation pattern 102 and the trench gate structure 103; and the second contact hole 1052 inside the trench gate structure 103; forming a bit line stack filled in the contact hole 105 above the first interlayer insulation; patterning the bit line stack by a wet etching process to form a plurality of bit line structures arranged at intervals along the third direction above the first interlayer insulation layer 104, and etching the second contact hole 1052 again at the same time, so that the aperture D2 of the second contact hole 1052 along the second direction after the second etching is larger than the aperture D1 of the first contact hole 1051 along the second direction. While ensuring that there is enough space between the bit line structure and the side walls of the contact holes 105 (second contact holes 1052) on both sides thereof to form spacers, the bit line has a larger line width, which reduces the process difficulty and reduces the generation of device defects.

[0163] Embodiment 5

[0164] Based on the second embodiment, this embodiment provides another method for preparing a semiconductor device.

[0165] In this embodiment, a method for preparing another semiconductor device is similar to the method for preparing the semiconductor device in Embodiment 4, with the only difference being that the first interlayer insulating layer 204 is a two-layer stacked structure, including an upper dielectric 2041 and a lower dielectric 2042, wherein the wet etching rate of the lower dielectric 2042 is greater than the wet etching rate of the upper dielectric 2041, so in the wet etching step of the bit line stack, when the contact hole is etched again, the lower dielectric 2042 will be etched again, ultimately making the aperture D4 of the lower contact hole along the second direction larger than the aperture D3 of the upper contact hole along the second direction.

[0166] Although the aperture D4 of the lower contact hole along the second direction is larger than the aperture D3 of the upper contact hole along the second direction, considering the first interlayer insulating layer 204 as a whole, the aperture of the first contact hole 2051 along the second direction is the aperture D3 of the upper contact hole along the second direction.

[0167] The aperture D5 of the second contact hole 2052 along the second direction is greater than the aperture D3 of the first contact hole 2051 along the second direction.

[0168] That is to say, although the first interlayer insulating layer 204 is a two-layer stacked structure, as long as the aperture of the contact hole in one layer meets the integration requirement, the contact holes in other layers can be etched again in the wet etching step, and the aperture can be relatively larger (consistent with the aperture of the second contact hole 2052), further ensuring that there is sufficient space between the bit line structure and the side walls of the contact holes on both sides of it to form spacers.

[0169] Embodiment 6

[0170] Based on the third embodiment, this embodiment provides another method for preparing a semiconductor device.

[0171] In the present embodiment, another method for preparing a semiconductor device is similar to the method for preparing the semiconductor device in the fourth embodiment, with the only difference being that the first interlayer insulating layer 304 is a three-layer stacked structure, including an upper dielectric 3041, a middle dielectric 3042 and a lower dielectric 3043, and the wet etching rates of the upper dielectric 3041 and the lower dielectric 3043 are both greater than the wet etching rate of the middle dielectric 3042, so in the wet etching step of the bit line stack, when the contact hole is etched again, the upper dielectric 3041 and the lower dielectric 3043 will be etched again, and finally the aperture D7 of the upper contact hole and the lower contact hole along the second direction is greater than the aperture D6 of the upper contact hole along the second direction.

[0172] Although the aperture D7 of the upper contact hole and the lower contact hole along the second direction is larger than the aperture D6 of the middle contact hole along the second direction, considering the first interlayer insulating layer 304 as a whole, the aperture of the first contact hole 3051 along the second direction is the aperture D6 of the middle contact hole along the second direction.

[0173] The aperture D8 of the second contact hole 3052 along the second direction is greater than the aperture D6 of the first contact hole 3051 along the second direction.

[0174] That is to say, although the first interlayer insulating layer 304 is a three-layer stacked structure, as long as the aperture of the contact hole in one layer meets the integration requirement, the contact holes in other layers can be etched again in the wet etching step, and the aperture can be relatively larger (consistent with the aperture of the second contact hole 3052), further ensuring that there is sufficient space between the bit line structure and the side walls of the contact holes on both sides of it to form spacers.

[0175] Although the embodiments disclosed in the present invention are as above, the contents thereof are only embodiments adopted for facilitating the understanding of the present invention and are not intended to limit the present invention. Any technician in the technical field to which the present invention belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention, but the protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: Semiconductor substrate; A plurality of active patterns disposed at intervals along a first direction on the substrate; The active pattern comprises a doped region; wherein each of the active patterns is isolated by an isolation pattern; A plurality of trench gate structures disposed at intervals along a second direction on the substrate; wherein each of the trench gate structures intersects with at least one of the active patterns; a first interlayer insulating layer located above the substrate and covering the active pattern and the trench gate structure; A contact hole penetrating the first interlayer insulating layer and extending to the active pattern, the isolation pattern and the inside of the trench gate structure; wherein the contact hole is arranged at a middle position of the active pattern, and the contact hole comprises a first contact hole penetrating the first interlayer insulating layer, and a second contact hole extending to the active pattern, the isolation pattern and the inside of the trench gate structure; the aperture of the second contact hole along the second direction is larger than the aperture of the first contact hole along the second direction; A plurality of bit line structures disposed at intervals along a third direction above the first interlayer insulating layer; wherein the bit line structures intersect the trench gate structures perpendicularly, each of the bit line structures is connected to at least one of the active patterns through the corresponding contact holes, and the line width of the bit line structure along the second direction is smaller than the aperture of the first contact hole along the second direction; The first interlayer insulating layer is a three-layer stacked structure, including an upper dielectric layer, a middle dielectric layer and a lower dielectric layer; Wherein, the first contact hole comprises an upper contact hole penetrating the upper dielectric layer, a middle contact hole penetrating the middle dielectric layer, and a lower contact hole penetrating the lower dielectric layer; The apertures of the upper contact hole and the lower contact hole along the second direction are both larger than the aperture of the middle contact hole along the second direction; The aperture of the middle contact hole along the second direction is the aperture of the first contact hole along the second direction.

2. The semiconductor device according to claim 1, wherein: In the second direction and at the corresponding contact hole position, the distance between the bit line structure and the side wall of the second contact hole is greater than the distance between the bit line structure and the side wall of the first contact hole.

3. The semiconductor device according to claim 1, wherein: In the second direction and at the corresponding contact hole position, the depth of the second contact hole at both sides of the bit line structure is greater than the depth of the second contact hole at the bit line structure position.

4. The semiconductor device according to claim 1, wherein: The second contact hole is located between two adjacent trench gate structures.

5. The semiconductor device according to claim 1, wherein: Also includes: A spacer layer is located at the bottom and sidewalls of the contact hole and covers the bit line structure; wherein in the second direction, the spacer layer isolates the bit line structure from the sidewalls of the contact hole.

6. The semiconductor device according to claim 1, wherein: The bit line structure comprises: a first conductive layer located above the first interlayer insulating layer and within the contact hole; a metal barrier layer located above the first conductive layer; A second conductive layer is located above the metal barrier layer.

7. The semiconductor device according to claim 1, wherein: The trench gate structure comprises a trench, a gate insulating layer arranged on the sidewall and bottom of the trench, and a gate and a second interlayer insulating layer respectively filled in the lower part and the upper part of the trench.

8. A method for preparing a semiconductor device, characterized in that: include: providing a semiconductor substrate; Forming a plurality of active patterns spaced apart along a first direction on the substrate; wherein each of the active patterns is isolated by an isolation pattern; Forming a plurality of trench gate structures spaced apart along a second direction on the substrate; wherein each of the trench gate structures intersects with at least one of the active patterns; forming a first interlayer insulating layer over the substrate; A contact hole is formed on the first interlayer insulating layer at a position corresponding to the middle position of the active pattern by a dry etching process, and the contact hole penetrates the first interlayer insulating layer and extends to the active pattern, the isolation pattern and the inside of the trench gate structure; wherein the contact hole includes a first contact hole penetrating the first interlayer insulating layer, and a second contact hole extending to the active pattern, the isolation pattern and the inside of the trench gate structure; forming a bit line stack filled in the contact hole above the first interlayer insulation; The bit line stack is patterned by a wet etching process to form a plurality of bit line structures arranged at intervals along the third direction above the first interlayer insulating layer, and the second contact hole is etched again at the same time, so that the aperture of the second contact hole after the second etching along the second direction is larger than the aperture of the first contact hole along the second direction; Wherein, the bit line structure intersects the trench gate structure vertically, each of the bit line structures is connected to at least one of the active patterns through the corresponding contact hole, and the line width of the bit line structure along the second direction is smaller than the aperture of the first contact hole along the second direction; The first interlayer insulating layer is a three-layer stacked structure, including an upper dielectric layer, a middle dielectric layer and a lower dielectric layer; Wherein, the wet etching rates of the upper layer medium and the lower layer medium are both greater than the wet etching rate of the middle layer medium; Wherein, the first contact hole comprises an upper contact hole penetrating the upper dielectric layer, a middle contact hole penetrating the middle dielectric layer, and a lower contact hole penetrating the lower dielectric layer; The apertures of the upper contact hole and the lower contact hole along the second direction are both larger than the aperture of the middle contact hole along the second direction; The aperture of the middle contact hole along the second direction is the aperture of the first contact hole along the second direction.

9. The method according to claim 8, characterized in that In the second direction and at the corresponding contact hole position, the distance between the bit line structure and the side wall of the second contact hole after re-etching is greater than the distance between the bit line structure and the side wall of the first contact hole.

10. The method according to claim 8, characterized in that In the second direction and at the corresponding contact hole position, the depth of the second contact hole at both sides of the bit line structure after re-etching is greater than the depth of the second contact hole at the bit line structure position.

11. The method according to claim 8, characterized in that The second contact hole is located between two adjacent trench gate structures.

12. The method according to claim 8, characterized in that Forming a plurality of trench gate structures spaced apart along a second direction on the substrate, comprising the following steps: forming a plurality of grooves spaced apart along a second direction on the substrate; forming a gate insulating layer on the sidewall and bottom of the trench; Filling a gate material in the trench to form a gate; wherein the thickness of the gate is less than the depth of the trench; A second interlayer insulating layer is formed in the trench and above the gate; wherein the trench, the gate insulating layer, the gate and the second interlayer insulating layer constitute a trench gate structure.

13. The method according to claim 8, characterized in that Forming a bit line stack filled in the contact hole above the first interlayer insulation, comprising the following steps: forming a first conductive layer filled in the contact hole on the first interlayer insulating layer; forming a metal barrier layer over the first conductive layer; A second conductive layer is formed above the metal barrier layer; wherein the first conductive layer, the metal barrier layer and the second conductive layer constitute a bit line stack.

14. The method according to claim 8, characterized in that Also includes: A spacer layer is formed which covers the bit line structure and is disposed at the bottom and sidewalls of the contact hole; wherein in the second direction, the spacer layer isolates the bit line structure from the sidewalls of the contact hole.

15. A semiconductor device, characterized in that: include: Semiconductor substrate; A plurality of active patterns arranged at intervals along a first direction on the substrate; wherein each of the active patterns is isolated by an isolation pattern; A plurality of trench gate structures disposed at intervals along a second direction on the substrate; wherein each of the trench gate structures intersects with at least one of the active patterns; a first interlayer insulating layer located above the substrate and covering the active pattern and the trench gate structure, wherein the first interlayer insulating layer is a three-layer stacked structure, including an upper dielectric layer, a middle dielectric layer and a lower dielectric layer; A contact hole penetrating the first interlayer insulating layer and extending to the active pattern, the isolation pattern and the inside of the trench gate structure; wherein the contact hole comprises a first contact hole penetrating the first interlayer insulating layer; the first contact hole comprises an upper contact hole penetrating the upper dielectric layer, a middle contact hole penetrating the middle dielectric layer and a lower contact hole penetrating the lower dielectric layer; the apertures of the upper contact hole and the lower contact hole along the second direction are both larger than the aperture of the middle contact hole along the second direction; A plurality of bit line structures are arranged at intervals along a third direction above the first interlayer insulating layer; wherein the bit line structure intersects the trench gate structure vertically, each of the bit line structures is connected to at least one of the active patterns through the corresponding contact hole, and the line width of the bit line structure along the second direction is smaller than the aperture of the first contact hole along the second direction.

16. The semiconductor device according to claim 15, characterized in that The contact hole also includes: a second contact hole extending to the active pattern, the isolation pattern and the inside of the trench gate structure; in the second direction and at the corresponding contact hole position, the distance between the bit line structure and the side wall of the second contact hole is greater than the distance between the bit line structure and the side wall of the first contact hole.

17. The semiconductor device according to claim 15, characterized in that In the second direction and at the corresponding contact hole position, the depth of the second contact hole at both sides of the bit line structure is greater than the depth of the second contact hole at the bit line structure position.

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