Display device

Abstract

A display device according to an embodiment includes a first substrate including a plurality of connection lines disposed on one end of the first substrate and a plurality of pads disposed on a side of the first substrate and electrically connected to each of the plurality of connection lines. Each of the plurality of connection lines includes a first region and a second region extending from the first region, a width of the first region being greater than a width of the second region, and the width of the second region being substantially the same as a width of each of the plurality of pads, thereby enabling improved reliability.

Description

Technical Field

[0001] This disclosure relates to a display panel, a display device including the display panel, and a method for manufacturing the display device. More specifically, it relates to a display device having a flexible circuit board attached to the side of the display module of the display device. Background Technology

[0002] Various display devices are being developed for use in multimedia devices such as televisions, mobile phones, tablets, navigators, and game consoles. These display devices provide users with various images and videos by displaying them.

[0003] Specifically, the display surface of a display device includes a display area for displaying images and a non-display area for not displaying images. Recently, research has been actively conducted on reducing the non-display area, i.e., the bezel area, of display devices. However, since the drive circuit board and the like, which generate signals for driving the display device, need to be formed in the non-display area, and because the drive circuit board has a certain size, there are limitations in reducing the size of the non-display area. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display panel and display device with a reduced bezel area.

[0005] Another object of this disclosure is to provide a method for manufacturing a display device with improved reliability.

[0006] A display panel according to an embodiment of the present disclosure includes: a substrate layer including a display area and a non-display area adjacent to the display area; a plurality of connecting lines disposed in the non-display area of ​​the substrate layer and disposed at one end adjacent to a side of the substrate layer; and a plurality of pads disposed on the side and electrically connected to each of the plurality of connecting lines, each of the plurality of connecting lines including a first region adjacent to the display area and a second region extending from the first region, the second region being disposed adjacent to the plurality of pads, the width of the first region being greater than the width of the second region, and the width of the second region being substantially the same as the width of each of the plurality of pads.

[0007] In one embodiment, the two ends of the second region of each of the plurality of connecting lines may coincide with the two ends of each of the plurality of pads.

[0008] In one embodiment, each of the plurality of connecting lines may contact each of the plurality of pads.

[0009] In one embodiment, the plurality of connecting lines may be arranged spaced apart from each other at a certain interval, and the plurality of pads may be formed spaced apart from each other at a certain interval.

[0010] In one embodiment, the second regions of each of the plurality of connecting lines may be spaced apart by a distance of 5 μm or more and 15 μm or less, the plurality of pads may be spaced apart by a distance of 5 μm or more and 15 μm or less, and the width of each of the plurality of pads may be 5 μm or more and 15 μm or less.

[0011] A display device according to an embodiment of the present disclosure includes: a first substrate; and a second substrate disposed on the first substrate and including an input sensing unit. The first substrate includes: a base layer including a display area and a non-display area; a plurality of connecting lines disposed on the non-display area of ​​the base layer and disposed at one end adjacent to a side of the base layer; and a plurality of pads disposed on the side and electrically connected to each of the plurality of connecting lines. Each of the plurality of connecting lines includes a first region disposed adjacent to the display area and a second region extending from the first region. The second region is disposed adjacent to the plurality of pads. The width of the first region is greater than the width of the second region, and the width of the second region is substantially the same as the width of each of the plurality of pads.

[0012] In one embodiment, the two ends of the second region of each of the plurality of connecting lines may coincide with the two ends of each of the plurality of pads.

[0013] In one embodiment, each of the plurality of connecting lines may contact each of the plurality of pads.

[0014] In one embodiment, the plurality of connecting lines may be configured to be spaced apart from each other at a certain interval, wherein the second region of each of the plurality of connecting lines is spaced apart from each other by an interval of more than 5 μm and less than 15 μm.

[0015] In one embodiment, the plurality of pads may be arranged with a certain interval between them, wherein the interval between the plurality of pads is greater than 5 μm and less than 15 μm.

[0016] In one embodiment, each of the plurality of pads may have a width of 5 μm or more and 15 μm or less.

[0017] In one embodiment, the display device may further include a driving circuit board electrically connected to the plurality of pads.

[0018] In one embodiment, the driving circuit substrate may be a flexible circuit substrate.

[0019] In one embodiment, the first substrate may further include a light-emitting element disposed on the display area.

[0020] A method for manufacturing a display device according to an embodiment of the present disclosure further includes: preparing a first substrate by forming a plurality of first interconnect lines on one end of a substrate layer; disposing a second substrate on the first substrate; forming a metal plate electrically connected to each of the plurality of first interconnect lines on one side of the first substrate and the second substrate; irradiating the plurality of first interconnect lines and the metal plate with a laser to form a plurality of second interconnect lines and each of a plurality of pads; and soldering a driving circuit board to each of the plurality of pads, each of the plurality of second interconnect lines including: a first region; and a second region extending from the first region and formed adjacent to the plurality of pads, the width of the first region being greater than the width of the second region, and the width of the second region being substantially the same as the width of each of the plurality of pads.

[0021] In one embodiment, the side may include a connection area having the plurality of pads formed thereon, and the metal plate may be formed to overlap the entire surface of the connection area.

[0022] In one embodiment, the step of irradiating each of the plurality of first connecting lines and the metal plate with a laser to form each of the plurality of second connecting lines and the plurality of pads may be performed in the same process as the steps of irradiating the plurality of first connecting lines with a laser to remove a first removal area and form the plurality of second connecting lines and irradiating the metal plate with a laser to remove a second removal area and form the plurality of pads.

[0023] In one embodiment, the two ends of the second region of each of the plurality of second connecting lines may be in consistent contact with the two ends of each of the plurality of pads.

[0024] In one embodiment, each of the plurality of second connection lines may be formed at a certain interval, and the plurality of pads may be formed at a certain interval.

[0025] In one embodiment, the second regions of the plurality of second connecting lines may be spaced apart by a distance of 5 μm or more and 15 μm or less, the plurality of pads may be spaced apart by a distance of 5 μm or more and 15 μm or less, and the width of each of the plurality of pads may be 5 μm or more and 15 μm or less.

[0026] Invention Effects

[0027] In one embodiment of the display panel, the bezel area can be reduced.

[0028] In a display device according to one embodiment, the bezel area can be reduced.

[0029] A display device manufacturing method according to one embodiment can provide a display device with improved reliability. Attached Figure Description

[0030] Figure 1 This is a perspective view of a display device according to one embodiment.

[0031] Figure 2 This is an exploded perspective view of a display device according to one embodiment.

[0032] Figure 3 This is a cross-sectional view of the first substrate according to one embodiment.

[0033] Figure 4a This is a top view of a first substrate according to an embodiment.

[0034] Figure 4b This is a side view of a first substrate according to an embodiment.

[0035] Figure 5 This is an equivalent circuit diagram of a pixel according to one embodiment.

[0036] Figure 6a This is a top view showing an enlarged view of one side of a display module according to one embodiment.

[0037] Figure 6b It is shown in magnification Figure 4a A top view of the BB area.

[0038] Figure 7 This is a sequence diagram of a method for manufacturing a display device according to an embodiment.

[0039] Figure 8a , Figure 8b , Figure 8c as well as Figure 8d This is a perspective view showing a portion of a display module in the order of a display device manufacturing method according to an embodiment.

[0040] Figure 9a as well as Figure 9b The diagram is enlarged according to the manufacturing method of a display device according to one embodiment. Figure 4a A top view of the BB area.

[0041] Explanation of reference numerals in the attached figures

[0042] DP: First substrate; IS: Second substrate

[0043] CL: Connecting wire; CL1: First connecting wire

[0044] CL2: Second connection line; PD: Pad Detailed Implementation

[0045] This disclosure can be implemented with various modifications and can take various forms, and specific embodiments are illustrated in the accompanying drawings and described in detail herein. However, it should be understood that this is not intended to limit this disclosure to a particular form, but rather to include all modifications, equivalents, and substitutions within the scope of the ideas and techniques of this disclosure.

[0046] "And / or" includes all combinations of more than one that can be defined by the relevant composition.

[0047] The terms "first," "second," etc., can be used to describe various constituent elements; however, the constituent elements should not be limited by these terms. These terms are used only to distinguish one constituent element from others. For example, without departing from the scope of this disclosure, a first constituent element can be referred to as a second constituent element, and similarly, a second constituent element can be referred to as a first constituent element. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0048] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formal meaning, unless expressly defined herein.

[0049] In this application, terms such as "substantially identical" should be understood to mean identical, including the same meaning as possible process errors that may occur within the numerical range usually described in the specification.

[0050] Terms such as “including” or “having” should be understood to specify the presence of features, figures, steps, actions, components, accessories, or combinations thereof as described in the specification, without precluding the existence or additional possibility of one or more other features or figures, steps, actions, components, parts, or combinations thereof.

[0051] In this application, when a layer, film, region, plate, or other part is described as being "above" or "on top of" another part, it includes not only the case where it is "directly" "above" the other part, but also the case where there is another part in between. Conversely, when a layer, film, region, plate, or other part is described as being "below" or "under" another part, it includes not only the case where it is "directly" "below" the other part, but also the case where there is another part in between. Furthermore, in this application, the description of being "disposed on" includes not only being disposed above, but may also include being disposed below.

[0052] On the other hand, in this application, "direct connection" can mean that no additional layers, films, regions, plates, etc. are added between the layers, films, regions, plates, etc. and other parts. For example, "direct connection" can mean that a configuration is made without the use of additional components such as adhesive components between two layers or two components.

[0053] Hereinafter, a display panel, a display device, and a method of manufacturing the display device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0054] Figure 1 This is a perspective view of a display device DD according to an embodiment. Figure 2 This is an exploded perspective view of a display device DD according to an embodiment. Figure 3 This is a cross-sectional view of the first substrate DP according to an embodiment. Figure 4a This is a top view of a first substrate DP according to an embodiment. Figure 5 This is an equivalent circuit diagram of a pixel PX according to one embodiment. Figure 4b This is a side view of a first substrate DP according to an embodiment.

[0055] Reference Figure 1 The display device DD may include a display surface DD-IS. A display area DA and a non-display area NDA may be defined on the display surface DD-IS. The display area DA may be an area displaying an image IM. Figure 1 In the example, an icon is displayed as an image IM. The non-display area NDA can be an area where the image IM is not displayed. Pixels can be configured in the display area DA, while no pixels can be configured in the non-display area NDA. A pixel can refer to the effective pixels that provide the image IM.

[0056] The display area DA is parallel to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display area DA, i.e., the thickness direction of the display device DD, is indicated by the third direction DR3. The front (or top) and back (or bottom) of each component are divided by the third direction DR3. However, the directions indicated by the first direction DR1 to the third direction DR3 are relative concepts and can be converted to other directions. Hereinafter, the first direction to the third direction refers to the directions indicated by the first direction DR1 to the third direction DR3 respectively, referring to the same reference numerals.

[0057] exist Figure 1 The present invention exemplarily illustrates a display device DD suitable for use in mobile terminals. Although not shown, a mobile terminal can be constructed by configuring the display device DD together with a bracket / housing, etc., via an electronic module, camera module, power module, etc., mounted on a motherboard. The display device DD according to the present disclosure is applicable to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as tablets, car navigation systems, game consoles, and smartwatches.

[0058] The border area of ​​the display device DD can be defined by a non-display area NDA. The non-display area NDA can be an area adjacent to the display area DA. The non-display area NDA can surround the display area DA. However, it is not limited to this; the shape of the display area DA and the shape of the non-display area NDA can be designed relative to each other. In another embodiment of this disclosure, the non-display area NDA can also be omitted.

[0059] One embodiment of this disclosure illustrates a display device DD having a planar display surface DD-IS, but it is not limited thereto. The display device DD may also include a curved display surface or a three-dimensional display surface. A three-dimensional display surface may also include multiple display areas indicating different directions from each other.

[0060] Reference Figure 2 The display device DD may include a window WM, a display module DM, a driving circuit DDC, a printed circuit board PB, and a housing component BC. The housing component BC can accommodate the display module DM and is combined with the window WM.

[0061] A window WM can be configured above a display module DM and transmits the image provided by the display module DM to the outside. The window WM includes a transmittance area TA and a non-transmittance area NTA. The transmittance area TA can overlap with the display area DA and has a shape corresponding to the display area DA. The image IM displayed in the display area DA of the display device DD can be visually confirmed from the outside through the transmittance area TA of the window WM.

[0062] The non-transparent region NTA can overlap with the non-display region NDA and have a shape corresponding to the non-display region NDA. Compared to the transparent region TA, the non-transparent region NTA can be a region with relatively low light transmittance. The non-transparent region NTA can overlap with the border region defined by the non-display region NDA of the display device DD. However, the technical concept of this disclosure is not limited to this, and the non-transparent region NTA can also be omitted. The window WM can be made of glass, sapphire, or plastic, etc. In addition, although the window WM is shown as a single layer, the window WM can include multiple layers. The window WM can include a base layer and at least one printed layer that overlaps with the non-transparent region NTA and is disposed on the back side of the base layer. The printed layer can have a predetermined color. As an example, the printed layer can be provided as black, or it can be provided as a color other than black.

[0063] The display module DM is disposed between the window WM and the housing member BC. The display module DM includes a first substrate DP and a second substrate IS. The first substrate DP may be a display panel. Hereinafter, the description of the display panel can be applied in the same way to the description of the first substrate DP.

[0064] The first substrate DP can generate an image and transmit the generated image to the window WM. According to embodiments of this disclosure, the first substrate DP can be a light-emitting display panel, and its type is not particularly limited. For example, the first substrate DP can be any of the following: liquid crystal display panel, electrophoretic display panel, microelectromechanical system display panel, electrowetting display panel, organic light emitting display panel, micro LED display panel, quantum dot display panel, and quantum rod display panel, without particular limitation.

[0065] Although not shown separately, the first substrate DP may also include a chassis component or a molding component, and depending on the type of the first substrate DP, may also include a backlight unit. Hereinafter, the first substrate DP will be described using an organic light-emitting display panel. However, the technical concept of this disclosure is not limited thereto, and various display panels may be applied to this disclosure according to embodiments.

[0066] The second substrate IS can be directly disposed on the first substrate DP. The second substrate IS may include an input sensing unit. The input sensing unit may include sensing electrodes, signal lines connected to the sensing electrodes, and at least one insulating layer overlapping the display area DA and the non-display area NDA. The sensing electrodes and the insulating layer may be cross-layered. The second substrate IS may also include a packaging substrate disposed on the input sensing unit. The packaging substrate can protect the input sensing unit from external impacts, moisture, and oxygen. In addition, the packaging substrate can provide a substrate surface for the window WM disposed on the second substrate IS. Although not shown, the second substrate IS may include any one of a phase retarder, a polarizer, and a color filter, depending on the type of the first substrate DP. Although not shown, a sealing member for bonding the first substrate DP and the second substrate IS may be disposed between the first substrate DP and the second substrate IS. The sealing member may be configured to overlap with the non-display area NDA of the display device DD.

[0067] The display device DD may include a driving circuit DDC that provides electrical signals to a first substrate DP and a second substrate IS, and a printed circuit board PB. The driving circuit DDC may be in a tape carrier package (TCP) type.

[0068] According to the description of this disclosure, when describing a display device DD suitable for a smartphone, a driving circuit DDC is shown, but it is not limited thereto. That is, the display device DD may include a plurality of driving circuits DDC, and at least any one of the plurality of driving circuits DDC may include an input pad that provides driving signals to a first substrate DP and a second substrate IS.

[0069] Furthermore, although the driving circuit DDC is shown configured on one side CM-DM of the display module DM according to the description of this disclosure, the embodiments are not limited thereto. Multiple driving circuits DDC can be provided and can be configured on at least one side of the display module DM.

[0070] The driving circuit DDC may include a driving circuit substrate DCB and a driving chip DC. The driving chip DC may be disposed on the driving circuit substrate DCB. According to one embodiment, the driving circuit substrate DCB may be provided as a flexible printed circuit board. Exemplarily, the driving circuit substrate DCB may also be bent from the side CM-DM of the display module DM toward the underside of the display module DM.

[0071] The driver chip DC can transmit control signals received from the printed circuit board PB. Based on the input control signals, the driver chip DC can generate the drive signals required to drive the first substrate DP. The drive signals output from the driver chip DC can be transmitted to the first substrate DP through the driver circuit board DCB.

[0072] The driving circuit DDC can be electrically connected to the side CM-DM of the display module DM. In one embodiment, the driving circuit DDC can be directly connected to the side CM-DM of the display module DM using ultrasonic direct metal bonding (MDB). Specifically, the driving circuit DDC can be connected to multiple pads PD (on the side CM-DM of the display module DM). Figure 4a They can be directly connected. However, this is not limited to this embodiment.

[0073] In one embodiment, the printed circuit board PB can be electrically connected to the driving circuit DDC. The printed circuit board PB can be electrically connected to a plurality of pads PD disposed on the side CM-DM of the display module DM via the driving circuit DDC.

[0074] like Figure 3 As shown, the first substrate DP may include a substrate layer BL, a circuit element layer DP-CL disposed on the substrate layer BL, a display element layer DP-OLED, and a thin-film encapsulation layer TFE. Although not shown separately, the first substrate DP may also include functional layers such as an anti-reflective layer and a refractive index adjustment layer.

[0075] The first substrate DP includes a display area DP-DA and a non-display area DP-NDA on a plane. The display area DP-DA and the non-display area DP-NDA of the first substrate DP can be respectively connected to… Figure 1 The display area DA and the non-display area NDA of the display device DD shown correspond to each other.

[0076] In this embodiment, the non-display area DP-NDA can be defined along the border of the display area DP-DA. However, it is not limited to this; the shape of the display area DP-DA and the non-display area DP-NDA can be designed relative to each other. In another embodiment of this disclosure, the non-display area DP-NDA can also be omitted.

[0077] The substrate layer BL can provide a substrate surface to the circuit element layer DP-CL. The display area DP-DA and the non-display area DP-NDA of the first substrate DP can be defined identically on the plane of the substrate layer BL. That is, the display area DP-DA of the substrate layer BL can coincide with the display area DP-DA of the first substrate DP on the plane. Similarly, the non-display area DP-NDA of the substrate layer BL can coincide with the non-display area DP-NDA of the first substrate DP on the plane.

[0078] A driving circuit or driving wiring can be configured on the non-display area DP-NDA of the substrate layer BL. For example, in one embodiment of this disclosure, multiple connection lines CL (see reference) can be configured on the non-display area DP-NDA of the substrate layer BL. Figure 4a ). Will be Figure 4a as well as Figure 4b The details are described for multiple connection lines (CL).

[0079] The substrate layer BL may include a synthetic resin film. A synthetic resin layer is formed on a working substrate used in manufacturing the first substrate DP. Then, a conductive layer and an insulating layer, etc., are formed on the synthetic resin layer. If the working substrate is removed, the synthetic resin layer corresponds to the substrate layer BL. The synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. Furthermore, the substrate layer BL may include a glass substrate, a metal substrate, or an organic composite material substrate / inorganic composite material substrate, etc.

[0080] The circuit element layer DP-CL includes at least one insulating layer and circuit elements. Hereinafter, the insulating layer included in the circuit element layer DP-CL is referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit elements include signal lines, pixel driving circuits, etc. The circuit element layer DP-CL can be formed by insulating layer, semiconductor layer, and conductive layer formation processes based on coating, evaporation, etc., and patterning processes of insulating layer, semiconductor layer, and conductive layer based on photolithography. In one embodiment of this disclosure, multiple connection lines CL may be included in the circuit element layer DP-CL.

[0081] The display element layer of a DP-OLED may include light-emitting elements. The DP-OLED display element layer may also include organic films such as pixel definition films. The light-emitting elements may be organic light-emitting diodes (OLEDs) or self-emissive elements. Self-emissive elements may include organic light-emitting elements or quantum dot light-emitting elements. However, it is not limited to these.

[0082] A thin-film encapsulation layer (TFE) seals the display element layer of a DP-OLED. The TFE includes at least one insulating layer. According to one embodiment of this disclosure, the TFE may include at least one inorganic film (hereinafter, encapsulating inorganic film). According to another embodiment of this disclosure, the TFE may include at least one organic film (hereinafter, encapsulating organic film) and at least one encapsulating inorganic film.

[0083] The inorganic encapsulation film protects the DP-OLED display element layer from moisture / oxygen, while the organic encapsulation film protects the DP-OLED display element layer from foreign matter such as dust particles. The inorganic encapsulation film can include silicon nitride layers, silicon oxide nitride layers, silicon oxide layers, titanium oxide layers, or aluminum oxide layers, etc., and is not particularly limited thereto. The organic encapsulation film can include acrylic organic films, and is not particularly limited thereto.

[0084] On the one hand, refer to Figure 4a Multiple signal lines SGL, multiple pixels PX, and multiple connection lines CL can be formed on the substrate layer BL of the first substrate DP. Figure 4a The illustrated BB region may include multiple interconnect lines CL formed on the substrate layer BL and multiple pads PD corresponding to each of the multiple interconnect lines CL and configured outside the substrate layer BL. The multiple interconnect lines CL may be spaced apart from each other. For example, the spacing between each of the multiple interconnect lines CL may be more than about 5 μm and less than 15 μm. However, this is not a limitation. The multiple pads PD may be spaced apart from each other at a certain interval. For example, the spacing may be more than about 5 μm and less than 15 μm. However, this is not a limitation.

[0085] Figure 4bThis is a side view of the first substrate DP as viewed in the second direction DR2. Hereinafter, in this specification, the side surface of the first substrate DP can be understood as the side surface on the same plane as the side surface CM of the substrate layer BL. Therefore, Figure 4b The side of the first substrate DP shown can be the side of the substrate layer BL as viewed in the second direction DR2, CM.

[0086] The side surface CM of the substrate layer BL may include a connection area CA and a non-connection area NCA. Multiple pads PD may be configured on the side surface CM of the substrate layer BL. The connection area CA may be an area configured with multiple connection lines CL and multiple pads PD. The non-connection area NCA may be an area without multiple connection lines CL and multiple pads PD.

[0087] Specifically, multiple connection lines (CLs) can be configured separately from each other in the connection area (CA). Multiple pads (PDs) can be configured separately from each other in the connection area (CA).

[0088] According to the description of this disclosure, although a plurality of pads PD are shown disposed on one side CM of the substrate layer BL, the embodiments are not limited thereto. The plurality of pads PD may be disposed on at least one of the other sides of the substrate layer BL.

[0089] Reference Figure 4a as well as Figure 4b A plurality of interconnect lines CL are disposed on one end of the substrate layer BL, and a plurality of pads PD are disposed on the side CM of the substrate layer BL adjacent to the end of the substrate layer BL where the interconnect lines CL are disposed. The plurality of pads PD are electrically connected to each of the plurality of interconnect lines CL.

[0090] Re-reference Figure 4a The first substrate DP may include an active region AA and a peripheral region NAA. Multiple pixels PX may be configured in the active region AA. The active region AA can be the area for displaying images. The peripheral region NAA can be the area where driving circuitry or driving wiring is configured.

[0091] Multiple connection lines CL can be configured to overlap with the peripheral area NAA of the first substrate DP. Multiple pads PD are configured on the side CM of the substrate layer BL. That is, multiple pads PD can be configured on the side of the first substrate DP. With the second substrate IS configured on the first substrate DP, multiple pads PD can be configured on the side CM-DM of the display module DM including the first substrate DP and the second substrate IS. Hereinafter, this specification describes the configuration of multiple pads PD on the side CM-DM of the display module DM.

[0092] In one embodiment, the drive circuit DDC can be electrically connected to multiple pads PD. As described above, the drive circuit DDC can be connected using ultrasonic waves via Meta Direct Bonding (MDB), thereby directly connecting to the multiple pads PD. Therefore, the drive circuit DDC can be disposed on the side CM-DM of the display module DM. With the drive circuit DDC disposed on the side CM-DM of the display module DM, compared to display devices with the drive circuit disposed above or below the display module, the display device DD of this disclosure can reduce the dead space (DS).

[0093] The multiple signal lines SGL include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Gate lines GL are connected to corresponding pixels PX, and data lines DL are connected to corresponding pixels PX. Power lines PL are connected to the pixels PX. Additionally, a gate drive circuit DCV connected to gate lines GL can be configured in the peripheral area NAA. The control signal lines CSL can provide control signals to the gate drive circuit DCV.

[0094] A portion of the gate line GL, data line DL, power line PL, and control signal line CSL are configured in the same layer, while a portion are configured in another layer. When a signal line configured in one layer is defined as the first signal line, a signal line configured in another layer can be defined as the second signal line. A signal line configured in yet another layer can be defined as the third signal line.

[0095] Figure 5 The diagram shown here is an enlarged and exemplary representation of the signal circuitry of one of the plurality of pixels PX shown in Figure 4. Pixel PX may include a light-emitting element EE and pixel circuitry CC.

[0096] The pixel circuit CC can include multiple transistors T1-T7 and a capacitor CP. The multiple transistors T1-T7 can be formed by LTPS (Low Temperature Polycrystalline Silicon) or LTPO (Low Temperature Polycrystalline Oxide) processes.

[0097] The pixel circuit CC controls the amount of current flowing through the light-emitting element EE in response to a data signal. The light-emitting element EE can emit light at a predetermined brightness in response to the amount of current supplied from the pixel circuit CC. For this purpose, the level of the first power supply ELVDD can be set higher than the level of the second power supply ELVSS. The light-emitting element EE can include an organic light-emitting element or a quantum dot light-emitting element.

[0098] Each of the plurality of transistors T1-T7 may include an input electrode (or, source electrode), an output electrode (or, drain electrode), and a control electrode (or, gate electrode). For ease of illustration, in this specification, either the input electrode or the output electrode may be referred to as the first electrode, and the other as the second electrode.

[0099] The first electrode of the first transistor T1 is connected to the first power supply ELVDD via the fifth transistor T5, and the second electrode of the first transistor T1 is connected to the anode electrode of the light-emitting element EE via the sixth transistor T6. The first transistor T1 may be referred to as the driving transistor in this specification.

[0100] The first transistor T1 controls the amount of current flowing through the light-emitting element EE in response to the voltage applied to the control electrode of the first transistor T1.

[0101] The second transistor T2 is connected between the data line DL and the first electrode of the first transistor T1. Furthermore, the control electrode of the second transistor T2 is connected to the i-th scan line GLi. The second transistor T2 is turned on when the i-th scan signal is provided to the i-th scan line GLi, thereby electrically connecting the data line DL and the first electrode of the first transistor T1.

[0102] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the i-th scan line GLi. The third transistor T3 is turned on when the i-th scan signal is provided to the i-th scan line GLi, so that the second electrode of the first transistor T1 and the control electrode of the first transistor T1 are electrically connected. Therefore, when the third transistor T3 is turned on, the first transistor T1 is turned on as a diode.

[0103] The fourth transistor T4 is connected between node ND and the initialization power generation unit (not shown). Furthermore, the control electrode of the fourth transistor T4 is connected to the (i-1)th scan line GLi-1. The fourth transistor T4 is turned on when the (i-1)th scan signal is provided to the (i-1)th scan line GLi-1 to provide the initialization voltage Vint to node ND.

[0104] The fifth transistor T5 is connected between the power supply line PL and the first electrode of the first transistor T1. The control electrode of the fifth transistor T5 is connected to the i-th light-emitting control line ECLi.

[0105] The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode electrode of the light-emitting element EE. Furthermore, the control electrode of the sixth transistor T6 is connected to the i-th light-emitting control line ECLi.

[0106] The seventh transistor T7 is connected between the initialization power generation unit (not shown) and the anode electrode of the light-emitting element EE. Furthermore, the control electrode of the seventh transistor T7 is connected to the (i+1)th scan line GLi+1. As described above, the seventh transistor T7 is turned on when the (i+1)th scan signal is provided to the (i+1)th scan line GLi+1 to provide the initialization voltage Vint to the anode electrode of the light-emitting element EE.

[0107] The seventh transistor T7 improves the black level performance of pixel PX. Specifically, when the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the light-emitting element EE discharges. Then, when black brightness is achieved, the light-emitting element EE does not emit light due to the leakage current from the first transistor T1, thereby improving the black level performance.

[0108] On the one hand, Figure 5 The diagram shows that the control electrode of the seventh transistor T7 is connected to the (i+1)th scan line GLi+1, but this disclosure is not limited thereto. In another embodiment of this disclosure, the control electrode of the seventh transistor T7 may be connected to the i-th scan line GLi or the (i-1)th scan line GLi-1.

[0109] Capacitor CP is positioned between power line PL and node ND. Capacitor CP stores the voltage corresponding to the data signal. Based on the voltage stored in capacitor CP, the amount of current flowing through first transistor T1 can be determined when fifth transistor T5 and sixth transistor T6 are turned on.

[0110] In this disclosure, the equivalent circuit of pixel PX is not limited to Figure 5 The equivalent circuit is shown. In another embodiment of this disclosure, the pixel PX can be implemented in various forms for causing the light-emitting element EE to emit light. Figure 5 The pixel circuit CC is shown based on PMOS, but is not limited thereto. In another embodiment of this disclosure, the pixel circuit CC may be constructed using NMOS. In yet another embodiment of this disclosure, the pixel circuit CC may be constructed using a combination of NMOS and PMOS.

[0111] Figure 6a This is a top view showing an enlarged portion of the side CM-DM of a display module DM according to one embodiment. Figure 6b It is shown in magnification Figure 4a A top view of the BB area.

[0112] Reference Figure 6a and Figure 6b The display module DM may include multiple connection lines CL and multiple pads PD. Multiple pads PD may be configured on the side CM-DM of the display module DM.

[0113] like Figure 6b As shown, each of the multiple connection lines CL includes a first region PT1 and a second region PT2. The second region PT2 extends from the first region PT1. The first region PT1 and the second region PT2 may have a single integral shape. The second region PT2 may be configured adjacent to multiple pads PD.

[0114] In one embodiment of this disclosure, the second region PT2 is electrically connected to a plurality of pads PD. Specifically, the second region PT2 may contact the plurality of pads PD.

[0115] In one embodiment, the width WD1 of the first region PT1 is greater than the width WD2 of the second region PT2. The width WD2 of the second region PT2 is substantially the same as the width WD3 of each of the plurality of pads PD. The width WD2 of the second region PT2 can be more than about 5 μm and less than 15 μm. The width WD3 of each of the plurality of pads PD can be more than about 5 μm and less than 15 μm. In this specification, width may refer to the length extending along the second direction DR2.

[0116] On one hand, each of the plurality of interconnect lines CL can be configured to be spaced apart from each other. Each of the plurality of pads PD can be configured to be spaced apart from each other. The spacing LN1 between the second regions PT2 of each of the plurality of interconnect lines CL can be more than about 5 μm and less than 15 μm. The spacing LN2 between the plurality of pads PD can be more than about 5 μm and less than 15 μm. In this specification, the spacing between them may refer to the length of the distance between them along the second direction DR2.

[0117] On the side CM-DM of the display module DM, multiple pads PD can be configured to overlap with multiple connection lines CL. Specifically, the two ends of the second region PT2 of each of the multiple connection lines CL can be configured to coincide with the two ends of each of the multiple pads PD. Furthermore, the multiple pads PD can be electrically connected to the multiple connection lines CL. The multiple pads PD can contact the multiple connection lines CL.

[0118] By ensuring that the two ends of the second region PT2 of each of the multiple connector lines CL and the two ends of each of the multiple pads PD are aligned, short circuits between the multiple connector lines CL and the multiple pads PD can be prevented.

[0119] Furthermore, by ensuring that the two ends of the second region PT2 of each of the plurality of connection lines CL are aligned with the two ends of each of the plurality of pads PD, the pitch of the plurality of pads PD can be controlled to be approximately 10 μm or more and 30 μm or less. This improves the reliability of the display device according to an embodiment of the present disclosure.

[0120] Figure 7 This is a sequence diagram S10 of a method for manufacturing a display device DD according to an embodiment. Figures 8a to 8d This is a perspective view showing a portion of the steps in a method for manufacturing a display device DD according to an embodiment. Figure 9a as well as Figure 9b This is a cross-sectional view showing a portion of the steps in a method for manufacturing a display device (DD) according to an embodiment. Figures 8a to 8d The image briefly illustrates the various steps of a manufacturing method for a display device DD in a portion of a side panel CM-DM of a display module DM. Figure 9a as well as Figure 9b The text briefly illustrates the process in the context of... Figure 4a This is a step in the manufacturing process of the display device DD in the BB area.

[0121] refer to Figure 7 A method for manufacturing a display device DD according to an embodiment includes: a step of preparing a first substrate DP (S100); a step of disposing of a second substrate IS on the first substrate DP (S200); a step of forming a metal plate MP on one side of the first substrate DP and the second substrate IS (S300); a step of forming a plurality of second connection lines CL2 and a plurality of pads PD (S400); and a step of soldering a driving circuit board DCB to each of the plurality of pads PD (S500).

[0122] Specifically, the step of preparing the first substrate DP (S100) may include forming a plurality of first interconnect lines CL1 on one end of the substrate layer BL. In one embodiment, each of the plurality of first interconnect lines CL1 may be formed spaced apart from each other.

[0123] The plurality of first connecting lines CL1 can be made of metallic materials including copper (Cu), silver (Ag), gold (Au), or aluminum (Al). The plurality of first connecting lines CL1 can be a single layer or can be composed of multiple layers stacked together. Furthermore, the plurality of first connecting lines CL1 can be composed of metal layers including the aforementioned metallic materials and insulating layers stacked in a cross-layer configuration. However, this is not a limitation.

[0124] like Figure 8aAs shown, the step (S200) of configuring the second substrate IS on the first substrate DP can be a step of configuring the second substrate IS on a plurality of first connection lines CL1. The second substrate IS can be attached to the first substrate DP by means of an adhesive component or the like. For example, the adhesive component can be provided as a sealing component. However, it is not limited thereto. The second substrate IS may include an input sensing unit. Hereinafter, the description of the second substrate IS is equally applicable to the foregoing description of the second substrate IS, and detailed descriptions will be omitted.

[0125] The display module DM includes a first substrate DP and a second substrate IS. In this specification, it can be understood that one side of the first substrate DP and the second substrate IS refers to the side CM-DM of the display module DM.

[0126] Furthermore, the connection region CA of the substrate layer BL can also be applied to the first substrate DP in the same way. The region in the first substrate DP in which a plurality of first connection lines CL1 are disposed can be called the connection region CA.

[0127] like Figure 8b As shown, the step (S300) of forming a metal plate MP on one side of the first substrate DP and the second substrate IS can be a step of forming a metal plate MP on the side CM-DM of the display module DM. Specifically, the metal plate MP can be formed to overlap the entire surface of the connection area CA in the side CM-DM of the display module DM.

[0128] For example, the metal plate MP can be formed to be directly connected to the side CM-DM of the display module DM via sputtering. Alternatively, the metal plate MP can be formed to be directly connected to the side CM-DM of the display module DM using silver paste. However, it is not limited to these methods.

[0129] Reference Figure 8c Multiple second connection lines CL2 are formed. Figure 9b The steps (S400) of irradiating multiple first interconnects CL1 and metal plate MP with laser LZ can include the step of irradiating multiple first interconnects CL1 and metal plate MP with laser LZ. In one embodiment of this disclosure, the step of irradiating the first interconnects CL1 and metal plate MP with laser LZ can be the same process. Specifically, multiple second interconnects CL2 can be formed while removing a portion of the first interconnects CL1 and metal plate MP. Figure 9b ) and multiple pads PD.

[0130] For ease of explanation, Figure 8c The example shows two pads (PDs), and multiple pads (PDs) can be further configured between the two shown pads (PDs). Multiple second connection lines (CL2) Figure 9bThe pads (PDs) are positioned between the first substrate (DP) and the second substrate (IS), and are therefore not visible externally. The area with multiple pads (PDs) can be defined as the connection area (CA). The connection area (CA) can be the region where the multiple pads (PDs) are electrically connected to the drive circuit (DDC).

[0131] Simultaneously refer to Figure 8c and Figure 9b By forming multiple second connection lines CL2 and multiple pads PD using the same process, the two ends of the second portion PT2 of each of the second connection lines CL2 can be aligned with the two ends of each of the multiple pads PD. This prevents short circuits between the second connection lines CL2 and the multiple pads PD.

[0132] like Figure 8d As shown, the step (S500) of soldering the drive circuit board DCB to each of the multiple pads PD can be a step of electrically connecting the drive circuit board DCB to the multiple pads PD. Specifically, the side CM-DM of the display module DM may include a connection area CA and a non-connection area NCA. The connection area CA may be the area where the drive circuit DDC is electrically connected to the multiple pads PD. Thus, the drive circuit board DCB of the drive circuit DDC can be electrically connected to the multiple pads PD.

[0133] For example, the drive circuit DDC can contact multiple pads PD via ultrasonic welding, i.e., metal-to-metal direct bonding (MDB). Additionally, the printed circuit board PB can be electrically connected to the drive circuit DDC. Therefore, signals transmitted from the printed circuit board PB can be transmitted to the multiple pads PD via the drive circuit DDC.

[0134] In one embodiment, since the two ends of the second region PT2 are consistent with the two ends of each of the plurality of pads PD, short circuits can be prevented between the plurality of pads PD and the second connection line CL2, and the signals transmitted by the plurality of pads PD can be transmitted to the display module DM through the second connection line CL2.

[0135] exist Figure 9a The image shows two first removal regions RA1 and a second removal region RA2. (See reference...) Figure 9b Laser LZ can be applied to multiple first connecting lines CL1 and metal plates MP to remove two first removal areas RA1 and a second removal area RA2.

[0136] Specifically, such as Figure 9aAs shown, a first removal region RA1 can be removed by irradiating each of a plurality of first connecting lines CL1 with laser LZ. A plurality of second connecting lines CL2 can be formed simultaneously by removing the first removal region RA1 from each of the plurality of first connecting lines CL1. The plurality of second connecting lines CL2 may include a first region PT1 and a second region PT2. The first region PT1 may be a region that is not irradiated with laser LZ. The second region PT2 may be a region that is irradiated with laser LZ and in which the first removal region RA1 is removed. Therefore, the width WD1 of the first region PT1 is greater than the width WD2 of the second region PT2 in which the first removal region RA1 is removed.

[0137] Alternatively, the second removal area RA2 can be removed by irradiating the metal plate MP with a laser LZ. After removing the second removal area RA2 from the metal plate MP, multiple spaced-apart pads PD can be formed.

[0138] In one embodiment of this disclosure, the steps of irradiating a plurality of first connection lines CL1 with laser LZ to remove the first removal area RA1 and irradiating a metal plate MP with laser LZ to remove the second removal area RA2 can be performed in the same process. That is, the plurality of second connection lines CL2 and the plurality of pads PD can be formed in the same process.

[0139] In a display device manufacturing method according to one embodiment, in order to form a plurality of second connection lines CL2 and a plurality of pads PD by irradiating a plurality of first connection lines CL1 and a metal plate MP with a laser LZ on the same process, the intensity of the laser LZ can be adjusted. Specifically, the number of laser LZ irradiations, the irradiation time, and the irradiation overlap rate can be adjusted so that the plurality of first connection lines CL1 and the metal plate MP are simultaneously patterned to form a plurality of second connection lines CL2 and a plurality of pads PD respectively.

[0140] Additionally, refer to Figure 9b By removing the first removal region RA1 and the second removal region RA2 using the same process, it is possible to adjust the two ends of the second region PT2 to coincide with the two ends of each of the plurality of pads PD. Therefore, the width WD2 of the second region PT2 is substantially the same as the width WD3 of each of the plurality of pads PD. For example, the width WD2 of the second region PT2 can be approximately 5 μm or more and 15 μm or less. The width WD3 of each of the plurality of pads PD can be approximately 5 μm or more and 15 μm or less. However, the substantial similarity between the width WD2 of the second region PT2 and the width WD3 of each of the plurality of pads PD means that they have substantially the same width, taking into account the range of process errors.

[0141] In a method for manufacturing a display device DD according to an embodiment of the present disclosure, by forming a plurality of second connection lines CL2 and a plurality of pads PD using the same process, it is possible to form that the two ends of the second region PT2 and the two ends of each of the plurality of pads PD are consistent. This prevents short circuits between the plurality of connection lines CL2 and the plurality of pads PD, and improves the reliability of the display device DD.

[0142] The above description refers to preferred embodiments of the present disclosure. However, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and alterations can be made to the present disclosure without departing from the spirit and technical scope of the present disclosure as set forth in the appended claims.

[0143] Therefore, the technical scope of this disclosure should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device, wherein, include: First substrate; as well as A second substrate, disposed on the first substrate, includes an input sensing unit. The first substrate includes: The base layer includes both the display area and the non-display area; Multiple connecting lines are configured in the non-display area of ​​the substrate layer and at one end adjacent to one side of the substrate layer; and Multiple pads are configured on one side and electrically connected to each of the multiple connection lines. Each of the plurality of connecting lines includes a first region and a second region extending from the first region. The second region is configured adjacent to the plurality of pads. The width of the first region is greater than the width of the second region. The widths of the first region and the second region are both constant. The width of the second region is substantially the same as the width of each of the plurality of pads. The first region includes a central portion that is adjacent to the second region and has the same width as the second region, and an edge portion that is adjacent to the central portion and spaced apart from the second region.

2. The display device according to claim 1, wherein, The two ends of the second region of each of the plurality of connecting lines coincide with the two ends of each of the plurality of pads.

3. The display device according to claim 1, wherein, Each of the plurality of connecting lines contacts each of the plurality of pads.

4. The display device according to claim 1, wherein, The plurality of connecting lines are arranged apart from each other at certain intervals. The second regions of each of the plurality of connecting lines are spaced apart from each other by a distance of more than 5 μm and less than 15 μm.

5. The display device according to claim 1, wherein, The plurality of pads are arranged apart from each other at certain intervals. The spacing between the plurality of pads is greater than 5 μm and less than 15 μm.

6. The display device according to claim 1, wherein, Each of the plurality of pads has a width of more than 5 μm and less than 15 μm.

7. The display device according to claim 1, wherein, The display device further includes: The driving circuit board is electrically connected to the plurality of solder pads.

8. The display device according to claim 7, wherein, The driving circuit substrate is a flexible circuit substrate.

9. The display device according to claim 1, wherein, The first substrate further includes a light-emitting element disposed on the display area.

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