Display device and method of repairing a display device

Abstract

The present disclosure relates to a display device and a method of repairing a display device, the display device including a substrate including a display area and a non-display area, a display element over the display area, a thin film transistor provided between the substrate and the display element and connected to the display element, a first wiring connected to the thin film transistor and extending in a first direction, and a second wiring provided over the first wiring and extending in a second direction intersecting the first direction. The display device includes a connection conductive layer overlapping with an intersection portion in which the first wiring and the second wiring intersect each other, an insulating layer between the connection conductive layer and the second wiring, and at least one connection contact hole defined in the insulating layer, the at least one connection contact hole connecting the connection conductive layer to the second wiring.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0119094, filed on September 26, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to display devices for achieving high resolution and improved reliability, and methods for repairing display devices. Background Technology

[0004] With the continuous development of the information society, the demand for various types of display devices has been increasing. The field of display devices has rapidly focused on flat panel display (FPD) devices, which are thin, lightweight, and capable of achieving large display areas. FPD devices have replaced the relatively bulky cathode ray tube (CRT) devices. Examples of FPD devices include liquid crystal display (LCD) devices, plasma display panels (PDP), organic light-emitting diode (OLED) displays, and electrophoretic display (EPD) devices.

[0005] Such a display device may include a substrate containing a display area and a non-display area, and may include various wirings capable of transmitting electrical signals to the display area.

[0006] It will be understood that this background section is intended in part to provide useful background for understanding the technology. However, this background section may also include ideas, concepts, or knowledge that were known or understood by a person skilled in the art prior to the corresponding valid application date of the subject matter disclosed herein, but are not part of the subject matter disclosed herein. Summary of the Invention

[0007] One or more embodiments include a highly reliable display device.

[0008] Additional aspects will be set forth in part in the description which follows, and will be apparent from the description or may be learned by practice of the embodiments provided in this disclosure.

[0009] According to one or more embodiments, a display device may include: a substrate including a display area and a non-display area; a display element above the display area; a thin-film transistor disposed between the substrate and the display element and connected to the display element; a first wiring connected to the thin-film transistor and extending in a first direction; a second wiring disposed above the first wiring and extending in a second direction intersecting the first direction; a connecting conductive layer overlapping with an intersection portion where the first wiring and the second wiring may intersect each other; an insulating layer disposed between the connecting conductive layer and the second wiring; and at least one connecting contact hole defined in the insulating layer, the at least one connecting contact hole connecting the connecting conductive layer and the second wiring.

[0010] The conductive layer can be located between the substrate and the first wiring.

[0011] A buffer layer may be provided between the conductive layer and the first wiring.

[0012] The display device may further include: a bias electrode disposed between the substrate and the semiconductor layer and overlapping the semiconductor layer, wherein the thin-film transistor includes the semiconductor layer, and the connecting conductive layer and the bias electrode may be disposed on the same layer.

[0013] The conductive layer can be spaced apart from the bias electrode.

[0014] The conductive layer can be disposed above the second wiring.

[0015] The display element may include a pixel electrode and a counter electrode, and the conductive layer and the pixel electrode are disposed on the same layer.

[0016] The conductive layer can be spaced apart from the pixel electrode.

[0017] The display device may further include a planarization layer between the display element and the thin-film transistor, wherein the conductive connection layer may be on the planarization layer.

[0018] The thin-film transistor may include a gate electrode, a source electrode, and a drain electrode, wherein the first wiring may be connected to the gate electrode.

[0019] The second wiring can be connected to the source electrode or the drain electrode.

[0020] The conductive layer can extend in the second direction.

[0021] The conductive connecting layer may include island-like structures.

[0022] The length of the connecting conductive layer in the second direction can be greater than the length of the intersection portion in the second direction.

[0023] The at least one connection contact hole may include a first contact hole and a second contact hole, wherein the intersection portion may be between the first contact hole and the second contact hole.

[0024] The second wiring may include a data line.

[0025] The display device may further include an inorganic protective layer covering the second wiring.

[0026] According to one or more embodiments, a method for repairing a display device, wherein the display device may include: a substrate; a first wiring extending over the substrate in a first direction; a second wiring disposed over and intersecting the first wiring; a connecting conductive layer overlapping with an intersection portion where the first wiring and the second wiring may intersect each other; an insulating layer between the connecting conductive layer and the second wiring; and at least one connecting contact hole in the insulating layer, wherein the connecting conductive layer is connected to the second wiring via the at least one connecting contact hole, wherein the method may include cutting the second wiring by irradiating a region between the intersection portion and the at least one connecting contact hole with a laser.

[0027] The method may further include: testing whether the first wiring and the second wiring may be short-circuited before cutting the second wiring.

[0028] The display device may further include: a display element including a pixel electrode and a counter electrode, wherein the method may further include: after cutting the second wiring, connecting the second wiring by forming the connection conductive layer and the pixel electrode on the same layer. Attached Figure Description

[0029] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 This is a schematic plan view of a display device according to an embodiment;

[0031] Figure 2 This is an equivalent circuit diagram showing the pixels of a display device according to an embodiment;

[0032] Figure 3 This is a schematic diagram showing the positions of thin-film transistors and capacitors included in a pixel circuit according to an embodiment;

[0033] Figure 4 This illustrates a structure that may include an organic light-emitting diode along [the path of the structure]. Figure 3 A schematic cross-sectional view of line A-A';

[0034] Figure 5 It is along Figure 3 A schematic cross-sectional view of line B-B';

[0035] Figure 6A This is a flowchart illustrating a method for repairing a display device according to an embodiment;

[0036] Figure 6B This is a schematic cross-sectional view illustrating the operation of testing whether the first and second wirings may be short-circuited according to an embodiment;

[0037] Figure 6C This is a schematic enlarged view illustrating the operation of cutting the second wiring according to an embodiment;

[0038] Figure 7 This is a schematic representation showing the positions of thin-film transistors and capacitors included in a pixel circuit according to another embodiment;

[0039] Figure 8 This is a schematic representation showing the positions of thin-film transistors and capacitors included in a pixel circuit according to another embodiment;

[0040] Figure 9 It is along Figure 8 A schematic cross-sectional view of line C-C';

[0041] Figure 10A This is a flowchart illustrating a method for repairing a display device according to another embodiment;

[0042] Figure 10B This is a schematic cross-sectional view illustrating the operation of cutting the second wiring according to another embodiment;

[0043] Figure 10C This is a schematic cross-sectional view illustrating the operation of forming a conductive interconnect layer according to another embodiment; and

[0044] Figure 11 This is a schematic diagram showing the positions of thin-film transistors and capacitors included in a pixel circuit according to another embodiment. Detailed Implementation

[0045] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. Repeated descriptions of the same elements may be omitted. Embodiments may take different forms and should not be construed as limited to the descriptions set forth herein. Therefore, embodiments are described below with reference only to the accompanying drawings to explain various aspects of this specification.

[0046] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms "and" and "or" may be used in a combined or separate sense and may be understood as equivalent to "and / or". Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all a, b, and c, or variations thereof.

[0047] While terms such as “first” and “second” can be used to describe various components, these components are not necessarily limited to the terms mentioned above. The terms are used only to distinguish one component from another. Similarly, for ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship of one element or feature to another element (or more elements) or feature (or more features) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatially relative terms are also intended to encompass different orientations of the apparatus in use or operation.

[0048] Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” used herein are intended to include the plural forms as well.

[0049] It will be understood that the terms “comprising,” “including,” “containing,” and / or “having” as used herein indicate the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0050] It will also be understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, the layer, region, or component may be directly or indirectly on that other layer, region, or component. For example, intermediate layers, intermediate regions, or intermediate components may exist.

[0051] For ease of explanation, the dimensions of components in the accompanying drawings may be exaggerated or reduced. For example, since the dimensions and thicknesses of components in the accompanying drawings are arbitrarily shown for ease of explanation, this disclosure is not limited thereto.

[0052] When embodiments can be implemented differently, a particular process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0053] It will also be understood that when layers, regions, or components are referred to as being “connected” to each other, they can be “directly connected” to each other or “indirectly connected” to each other through intermediate layers, regions, or components. For example, when layers, regions, or components are referred to as being “electrically connected” to each other, they can be “directly electrically connected” to each other or “indirectly electrically connected” to each other through intermediate layers, regions, or components.

[0054] The term “overlap” may include: layer, stack, facing or oriented, extending above (or below), covering or partially covering (or being covered or partially covered), or any other suitable term that will be understood and appreciated by one of ordinary skill in the art.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined in this specification, terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and not as having an idealized or overly formal meaning.

[0056] A display device can be a device for displaying images, and examples of display devices can include: liquid crystal display devices, electrophoretic display devices, organic light-emitting display devices, inorganic light-emitting display devices, field emission display devices, surface conduction electron emission display devices, quantum dot display devices, plasma display devices, and cathode ray tube display devices. Although organic light-emitting display devices are described below as examples, the embodiments can be applied to various display devices such as those described above.

[0057] Figure 1 This is a schematic plan view of a display device according to an embodiment.

[0058] Reference Figure 1 A display device may include a display area DA and a non-display area NDA surrounding the display area DA. Pixels PX, including display elements, may be positioned above the display area DA to provide an image.

[0059] A pixel (PX) can emit colored light, such as red, green, blue, or white light, and, as an example, may include an organic light-emitting diode (OLED). A pixel (PX) may also include devices such as thin-film transistors (TFTs) and capacitors.

[0060] As described above, the pixel PX described in this article refers to a sub-pixel that can emit light such as red, green, blue or white light.

[0061] The non-display area NDA can be an area where no image is provided. A controller, such as a scan driver and a data driver (or a portion of a printed circuit board to which a controller is attached), can be positioned above the non-display area NDA. The controller can provide electrical signals that can be applied to the pixels PX of the display area DA.

[0062] Figure 2 This is an equivalent circuit diagram showing the pixel PX of a display device according to an embodiment.

[0063] Reference Figure 2 A pixel PX may include an organic light-emitting diode (OLED) and a pixel circuit PC including TFTs for driving the OLED. The pixel circuit PC may include a driving TFT T1, a switching TFT T2, a sensing TFT T3, and a storage capacitor Cst.

[0064] In one or more embodiments, the pixel circuit PC may include three TFTs and a storage capacitor Cst, the three TFTs being, for example, a driving TFT T1, a switching TFT T2, and a sensing TFT T3. However, in another embodiment, the number of TFTs and the storage capacitor included in the pixel circuit PC, or the structure of the pixel circuit PC, may be modified.

[0065] The scan line SL can be connected to the gate electrode G2 of the switch TFT T2, the data line DL can be connected to the source electrode S2, and the first electrode CE1 of the storage capacitor Cst can be connected to the drain electrode D2.

[0066] Therefore, the switch TFT T2 can respond to the scan signal Sn from the scan line SL of each pixel PX and supply the data voltage of the data line DL to the first node N.

[0067] The gate electrode G1 of the driving TFT T1 can be connected to the first node N, the source electrode S1 can be connected to the first power line PL1 for transmitting the driving power supply voltage ELVDD, and the drain electrode D1 can be connected to the anode of the organic light-emitting diode OLED.

[0068] Therefore, the driving TFT T1 can adjust the amount of current flowing through the organic light-emitting diode (OLED) based on its own source-gate voltage. For example, the driving TFT T1 can adjust the amount of current based on the voltage that can be applied between the driving power supply voltage ELVDD and the first node N.

[0069] The sensing control line SSL can be connected to the gate electrode G3 of the sensing TFT T3, the source electrode S3 can be connected to the second node S, and the drain electrode D3 can be connected to the reference voltage line RL. In some embodiments, the sensing TFT T3 can be controlled by the scan line SL instead of the sensing control line SSL.

[0070] The sensing TFT T3 can sense the potential of the anode of the organic light-emitting diode (OLED). The sensing TFT T3 can supply a pre-charge voltage from the reference voltage line RL to the second node S in response to the sensing signal SSn from the sensing control line SSL, or the sensing TFT T3 can supply the voltage of the anode of the OLED to the reference voltage line RL during the sensing period.

[0071] The storage capacitor Cst may have a first electrode CE1 connected to a first node N and a second electrode CE2 connected to a second node S. The storage capacitor Cst may be charged with a voltage difference between the voltages supplied to the first node N and the second node S, and this voltage difference may be supplied as a driving voltage for the TFT T1. For example, the storage capacitor Cst may be charged with a voltage difference between a data voltage and a pre-charge voltage, which may be supplied to the first node N and the second node S, respectively.

[0072] The bias electrode BSM can be formed corresponding to the driving TFT T1 and can be connected to the source electrode S3 of the sensing TFT T3. Since the bias electrode BSM can receive a voltage that is potential-locked with the source electrode S3 of the sensing TFT T3, the driving TFT T1 can be stably driven. In some embodiments, the bias electrode BSM may not be connected to the source electrode S3 of the sensing TFT T3, but may be connected to a separate bias wiring.

[0073] The opposite electrode (e.g., the cathode) of an organic light-emitting diode (OLED) can receive a common power supply voltage ELVSS. The OLED can receive driving current from the driving TFT T1 and can emit light.

[0074] Figure 2 A pixel PX is shown, comprising signal lines such as a scan line SL, a sense control line SSL, a data line DL, a reference voltage line RL, a first power line PL1, and a second power line PL2. However, in another embodiment, at least one of the signal lines, such as the scan line SL, the sense control line SSL, the data line DL, the reference voltage line RL, the first power line PL1, and the second power line PL2, may be shared between adjacent pixels.

[0075] Figure 3This is a schematic diagram showing the positions of the TFT and capacitor Cst included in the pixel circuit PC according to an embodiment. Figure 4 This illustrates a structure that may include an organic light-emitting diode (OLED). Figure 3 A schematic cross-sectional view of the line A-A'. Figure 5 It is along Figure 3 A schematic cross-sectional view of line B-B'.

[0076] Reference Figure 3 According to the embodiment, the pixel circuit PC of the display device can be connected to a scan line SL, a sensing control line SSL, a first lower power line UPL1, a second lower power line UPL2, and a lower reference voltage line URL extending in the first direction DR1.

[0077] Additionally, the pixel circuit PC can be connected to the data line DL, reference voltage line RL, first power line PL1, second power line PL2, and connecting conductive layer BML, which extend on the second direction DR2 that intersects the first direction DR1.

[0078] In this embodiment, the scan line SL, the sensing control line SSL, the first lower power line UPL1, and the second lower power line UPL2 can be disposed on the same layer as each other. The data line DL, the reference voltage line RL, the first power line PL1, and the second power line PL2 can also be disposed on the same layer as each other, and can be configured such that the scan line SL, etc., and the interlayer insulating layer 115 (see reference) Figure 4 In one embodiment, the first power line PL1 and the second power line PL2 may be disposed on a different layer than the data line DL. However, for ease of description, the case in which the first power line PL1 and the second power line PL2 may be disposed on the same layer as the data line DL will be described in detail below.

[0079] In one embodiment, the lower reference voltage line URL can be disposed on the same layer as the scan line SL. In another embodiment, the lower reference voltage line URL can be disposed on the same layer as the semiconductor layer. The case where the lower reference voltage line URL can be disposed on the same layer as the scan line SL will be described in detail below.

[0080] In the specification, the scan line SL, the sensing control line SSL, the first lower power line UPL1, the second lower power line UPL2, or the lower reference voltage line URL extending on the first direction DR1 can be referred to as the first wiring. The data line DL, the reference voltage line RL, the first power line PL1, or the second power line PL2 can be referred to as the second wiring.

[0081] The pixel circuit PC may include a driving TFT T1, a switching TFT T2, a sensing TFT T3, and a storage capacitor Cst.

[0082] The semiconductor layer A1 of driving TFT T1, the semiconductor layer A2 of switching TFT T2, and the semiconductor layer A3 of sensing TFT T3 can be disposed on the same layers as each other and can contain the same materials. For example, semiconductor layers A1, A2, and A3 can contain amorphous silicon or polycrystalline silicon. Additionally, semiconductor layers A1, A2, and A3 can contain an oxide semiconductor material comprising an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In some embodiments, semiconductor layers A1, A2, and A3 can contain Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc., where Zn oxide, In-Zn oxide, and Ga-In-Zn oxide can be Zn oxide-based materials. In some embodiments, semiconductor layers A1, A2, and A3 may comprise IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) semiconductors contained in ZnO, having metals such as indium (In), gallium (Ga), and tin (Sn). Semiconductor layers A1, A2, and A3 may have a single-layer structure or a multi-layer structure.

[0083] Semiconductor layers A1, A2, and A3 may each include a channel region and source and drain regions located on opposite sides of the channel region. The source and drain regions may be regions with regulated carrier concentrations. For example, if semiconductor layers A1, A2, and A3 comprise silicon, the source and drain regions may be doped with impurities. As another example, if semiconductor layers A1, A2, and A3 comprise oxide semiconductors, the source and drain regions may be regions with increased carrier concentrations through plasma treatment.

[0084] Gate electrodes G1, G2, and G3 may overlap with the channel regions of semiconductor layers A1, A2, and A3, and gate insulating layer 113 (refer to...) Figure 4 The source electrodes S1, S2 and S3 and the drain electrodes D1, D2 and D3 can be disposed on the interlayer insulating layer 115 and can be connected to the source region and the drain region via contact holes.

[0085] The gate electrode G1 of the driving TFT T1 may be island-shaped (e.g., spaced apart from another feature). The gate electrode G1 can serve not only as the gate electrode of the driving TFT T1 but also as the first electrode CE1 of the storage capacitor Cst. In one embodiment, the gate electrode G1 may be integrally formed with the first electrode CE1 of the storage capacitor Cst. A portion of the gate electrode G1 may overlap with the semiconductor layer A1 of the driving TFT T1, and a portion of the gate electrode G1 may overlap with the second electrode CE2 of the storage capacitor Cst to form a first capacitor. In another embodiment, the first electrode CE1 of the storage capacitor Cst may extend from the gate electrode G1 that overlaps with the semiconductor layer A1 of the driving TFT T1.

[0086] The bias electrode BSM can be disposed below the driving TFT T1 to correspond to the gate electrode G1 (e.g., the first electrode CE1 of the storage capacitor Cst). Therefore, the first electrode CE1 and the bias electrode BSM can form a second capacitor. In addition, one end of the gate electrode G1 can be connected to the drain electrode D2 of the switching TFT T2 via the first node contact hole NCNT1.

[0087] In an embodiment, the gate electrode G2 and scan line SL of the switching TFT T2 can be connected to each other via the first intermediate conductive layer IM1. For example, as Figure 3 As shown, the first intermediate conductive layer IM1 can be disposed on the same layer as the data line DL, and can be connected to the gate electrode G2 and the scan line SL of the switch TFT T2 via contact holes, respectively. In another embodiment, the gate electrode G2 of the switch TFT T2 can be a part of the scan line SL. For example, the gate electrode G2 can be a region protruding from the scan line SL in the second direction DR2, and the scan line SL extends in the first direction DR1. Therefore, the scan signal Sn that can be transmitted by the scan line SL can be transmitted to the gate electrode G2, and the switch TFT T2 can operate in response to the scan signal Sn.

[0088] In one embodiment, the gate electrode G3 of the sensing TFT T3 and the sensing control line SSL can be connected to each other via a second intermediate conductive layer IM2. For example, the second intermediate conductive layer IM2 can be disposed on the same layer as the data line DL, and can be connected to the gate electrode G3 of the sensing TFT T3 and the sensing control line SSL via contact holes, respectively. In another embodiment, the gate electrode G3 of the sensing TFT T3 can be part of the sensing control line SSL. For example, the sensing control line SSL can overlap with the semiconductor layer A3 of the sensing TFT T3, and the overlapping area can be used as the gate electrode G3. Therefore, the sensing signal SSn that can be transmitted by the sensing control line SSL can be transmitted to the gate electrode G3, and the sensing TFT T3 can operate in response to the sensing signal SSn.

[0089] The drain electrode D1 of the driving TFT T1 can be provided integrally with the second electrode CE2 of the storage capacitor Cst and the source electrode S3 of the sensing TFT T3, and can also be connected to the bias electrode BSM via the second node contact hole NCNT2. The source electrode S1 of the driving TFT T1 can be connected to the first power line PL1 via a contact hole.

[0090] The source electrode S2 of the switching TFT T2 can be part of the data line DL, and therefore the data signal Dm of the data line DL can be transmitted to the source region of the switching TFT T2. One end of the drain electrode D2 of the switching TFT T2 can be connected to the first electrode CE1 of the storage capacitor Cst via the first node contact hole NCNT1.

[0091] The source electrode S3 of the sensing TFT T3 can be connected to the drain electrode D1 of the driving TFT T1, and the drain electrode D3 can correspond to the drain region of the semiconductor layer A3 of the sensing TFT T3. The drain electrode D3 can be connected to the lower reference voltage line URL via a contact hole. The lower reference voltage line URL can be connected to the reference voltage line RL via a contact hole.

[0092] The first electrode CE1 of the storage capacitor Cst can be integrally formed with the gate electrode G1, and the second electrode CE2 can overlap with the first electrode CE1, with an interlayer insulating layer 115 (refer to...). Figure 5 The second electrode CE2 of the storage capacitor Cst is located between the second electrode CE2 and the first electrode CE1. The second electrode CE2 can be connected to the pixel electrode 310 of the organic light-emitting diode OLED (refer to...) via the first via VH1. Figure 4 ).

[0093] Below the first electrode CE1 of the storage capacitor Cst, the bias electrode BSM can be disposed in the first buffer layer 111 (see reference). Figure 5 ) and second buffer layer 112 (refer to Figure 5 Therefore, the first electrode CE1 of the bias electrode BSM and the storage capacitor Cst can form a second capacitor. Since one end of the bias electrode BSM can be connected to the source electrode S3 of the sensing TFT T3 via the second node contact hole NCNT2, the voltage that can be applied to the source electrode S3 can be applied to the bias electrode BSM in an interlocked manner. In another embodiment, a separate bias voltage can be provided to the bias electrode BSM, or no voltage can be applied to the bias electrode BSM.

[0094] The first power line PL1 and the second power line PL2 may extend on the same layer in the second direction DR2. The first power line PL1 and the second power line PL2 may be voltage lines for transmitting different voltages from each other, and the first power line PL1 may transmit the drive power supply voltage ELVDD, while the second power line PL2 may transmit the common power supply voltage ELVSS.

[0095] The first power line PL1 can be connected via a contact hole to a first lower power line UPL1 extending in the first direction DR1. Through the first lower power line UPL1 extending in the first direction DR1 and the first power line PL1 extending in the second direction DR2, the drive power supply voltage ELVDD can be provided in a mesh structure.

[0096] The second power line PL2 can be connected via a contact hole to the second lower power line UPL2 extending in the first direction DR1. Through the second lower power line UPL2 extending in the first direction DR1 and the second power line PL2 extending in the second direction DR2, the common power supply voltage ELVSS can be provided in a mesh structure.

[0097] The first power line PL1 can be connected to the source electrode S1 of the driving TFT T1 via a contact hole. The second power line PL2 can be connected to the opposite electrode 330 of the organic light-emitting diode OLED (refer to) via the second via hole VH2. Figure 4 ).

[0098] In this embodiment, the connecting conductive layer BML may be disposed below the first wiring. For example, the connecting conductive layer BML may be disposed below the scan line SL, the sensing control line SSL, or the lower reference voltage line URL. Specifically, the connecting conductive layer BML may be disposed between the substrate 100 and the first wiring.

[0099] In one embodiment, the conductive layer BML can be disposed on the same layer as the bias electrode BSM. For example, the conductive layer BML can be disposed between the first buffer layer 111 and the second buffer layer 112. In another embodiment, the conductive layer BML can be disposed between the substrate 100 and the first buffer layer 111. The conductive layer BML can be spaced apart from the bias electrode BSM. Specifically, the conductive layer BML can be spaced apart from the bias electrode BSM in the first direction DR1 or the second direction DR2.

[0100] In an embodiment, the conductive layer BML may include a first conductive layer BML1, a second conductive layer BML2, and a third conductive layer BML3. The first conductive layer BML1, the second conductive layer BML2, and the third conductive layer BML3 may be spaced apart from each other. For example, the first conductive layer BML1, the second conductive layer BML2, and the third conductive layer BML3 may be spaced apart from each other in a first direction DR1.

[0101] The first conductive layer BML1 may overlap with the data line DL. In an embodiment, the first conductive layer BML1 may extend in the second direction DR2 while overlapping with the data line DL. For example, the first conductive layer BML1 may extend while continuously overlapping with the data line DL.

[0102] In this embodiment, the first conductive layer BML1 may overlap with a first crossing portion CP1 in which the data line DL and the scan line SL may intersect each other. The first conductive layer BML1 may overlap with a second crossing portion CP2 in which the data line DL and the sensing control line SSL may intersect each other. Additionally, the first conductive layer BML1 may overlap with a third crossing portion CP3 in which the data line DL and the lower reference voltage line URL may intersect each other.

[0103] The first conductive layer BML1 can be connected to the data line DL via at least one connecting contact hole. In an embodiment, the first conductive layer BML1 can be connected to the data line DL via a first contact hole CNT1 and a second contact hole CNT2. In this regard, a first cross portion CP1 can be disposed between the first contact hole CNT1 and the second contact hole CNT2. Therefore, the data signal of the data line DL can be transmitted indirectly (e.g., via an alternative connection route or path) through the first conductive layer BML1. As another example, the first conductive layer BML1 can be connected to the data line DL via a third contact hole CNT3, a fourth contact hole CNT4, or a fifth contact hole CNT5. In this regard, a second cross portion CP2 can be disposed between the third contact hole CNT3 and the fourth contact hole CNT4. A third cross portion CP3 can be disposed between the fourth contact hole CNT4 and the fifth contact hole CNT5.

[0104] In another embodiment, some of the first contact holes CNT1 to the fifth contact holes CNT5 may be omitted. For example, the fourth contact hole CNT4 in the third contact hole CNT3, fourth contact hole CNT4, and fifth contact hole CNT5 may be omitted. In another embodiment, a contact hole may also be included between the third contact hole CNT3 and the fourth contact hole CNT4.

[0105] The second conductive layer BML2 can overlap with the reference voltage line RL. In an embodiment, the second conductive layer BML2 can extend in the second direction DR2 while overlapping with the reference voltage line RL. For example, the second conductive layer BML2 can extend while continuously overlapping with the reference voltage line RL.

[0106] In one embodiment, the second conductive layer BML2 may overlap with a fourth intersection portion CP4 where the reference voltage line RL and the scan line SL may intersect each other. Additionally, the second conductive layer BML2 may overlap with a fifth intersection portion CP5 where the reference voltage line RL and the sensing control line SSL may intersect each other.

[0107] The second conductive layer BML2 can be connected to the reference voltage line RL via at least one connecting contact hole. For example, the second conductive layer BML2 can be connected to the reference voltage line RL via a sixth contact hole CNT6 or a seventh contact hole CNT7. In this regard, a fourth cross portion CP4 can be disposed between the sixth contact hole CNT6 and the seventh contact hole CNT7. As another example, the second conductive layer BML2 can be connected to the reference voltage line RL via an eighth contact hole CNT8 or a ninth contact hole CNT9. In this regard, a fifth cross portion CP5 can be disposed between the eighth contact hole CNT8 and the ninth contact hole CNT9. Therefore, the pre-charge voltage of the reference voltage line RL can be transmitted indirectly via the second conductive layer BML2.

[0108] The third connecting conductive layer BML3 may overlap with the second intermediate conductive layer IM2. In an embodiment, the third connecting conductive layer BML3 may extend in the second direction DR2 while overlapping with the second intermediate conductive layer IM2. For example, the third connecting conductive layer BML3 may extend while continuously overlapping with the second intermediate conductive layer IM2. The third connecting conductive layer BML3 may overlap with the sixth crossing portion CP6 in which the second intermediate conductive layer IM2 and the sensing control line SSL may intersect each other.

[0109] The third connecting conductive layer BML3 can be connected to the second intermediate conductive layer IM2 via at least one connecting contact hole. For example, the third connecting conductive layer BML3 can be connected to the second intermediate conductive layer IM2 via the tenth contact hole CNT10 or the eleventh contact hole CNT11. In this regard, the sixth cross portion CP6 can be disposed between the tenth contact hole CNT10 and the eleventh contact hole CNT11. Therefore, the pre-charge voltage of the reference voltage line RL can be transmitted indirectly via the third connecting conductive layer BML3.

[0110] In the event that the first and second wirings may short-circuit, a connecting conductive layer BML overlapping the second wiring can be provided as described above to cut the second wiring. In the event that the first and second wirings may short-circuit, the intersection portion where the first and second wirings may intersect each other can be cut. In this respect, if the second wiring may not have a mesh-like structure like the first power line PL1 or the second power line PL2, signals may not be transmitted to the pixel circuit PC. In the embodiment, a connecting conductive layer BML overlapping the second wiring can be provided, and therefore, even when the intersection portion is cut, signals can be transmitted to the pixel circuit PC. Specifically, the second wiring and the connecting conductive layer BML can be connected to each other via at least one contact hole, and therefore, signal detours can be made.

[0111] In this embodiment, the conductive layer BML can be formed simultaneously with the bias electrode BSM, and therefore, no additional mask is required. Furthermore, the conductive layer BML can reduce the resistance of the second wiring.

[0112] In a display device according to one or more embodiments, a reference is provided. Figure 3 The pixel circuits PC with the same shape described can be arranged parallel to each other in the first direction DR1 and the second direction DR2. In another embodiment, the pixel circuit PC included in the display device can have a shape symmetrical to the shape of the pixel circuits adjacent to the pixel circuit PC.

[0113] In the following text, reference will be made to Figure 4 and Figure 5 The stacking order of the structure of the display device according to the embodiment is described.

[0114] Reference Figure 4 The substrate 100, an organic light-emitting diode (OLED) that can serve as a display element disposed above the substrate 100, a switching TFT T2, an interlayer insulating layer 115 covering the gate electrode G2 of the switching TFT T2, and data lines DL, reference voltage lines RL, and a second power line PL2 located on the interlayer insulating layer 115 can be disposed in at least one pixel included in the display device according to the embodiment. In this regard, a first connecting conductive layer BML1 can be disposed at a first intersection portion CP1 in which the data lines DL and SL can intersect each other, and the first connecting conductive layer BML1 can be connected to the data line DL via a first contact hole CNT1 or a second contact hole CNT2. In addition, a second connecting conductive layer BML2 can be disposed at a fourth intersection portion (not shown) in which the reference voltage line RL and SL can intersect each other, and the second connecting conductive layer BML2 can be connected to the reference voltage line RL via a sixth contact hole CNT6.

[0115] Substrate 100 may include glass, ceramic, metal, flexible or bendable materials, or combinations thereof. When substrate 100 is flexible or bendable, it may include polymeric resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Substrate 100 may have a single-layer or multi-layer structure of the aforementioned materials, and in a multi-layer structure, substrate 100 may further include an inorganic layer. In some embodiments, substrate 100 may have a structure of inorganic materials (e.g., organic / inorganic / organic) between organic materials.

[0116] The first buffer layer 111 can increase the smoothness of the upper surface of the substrate 100, and the first buffer layer 111 can contain silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), or combinations thereof.

[0117] A barrier layer (not shown) may also be included between the substrate 100 and the first buffer layer 111. The barrier layer can prevent or reduce the penetration of impurities from the substrate 100 into the semiconductor layers A1 and A2 (see reference). Figure 4 and Figure 5 The barrier layer may contain inorganic materials such as oxides or nitrides, organic materials, or organic-inorganic composites, and may have a single-layer or multi-layer structure of inorganic and organic materials.

[0118] A first conductive layer BML1 or a second conductive layer BML2 can be disposed on the first buffer layer 111. The first conductive layer BML1 can be connected to the data line DL via the first contact hole CNT1 or the second contact hole CNT2. Therefore, the data signal of the data line DL can be transmitted indirectly via the first conductive layer BML1. The second conductive layer BML2 can be connected to the reference voltage line RL via the sixth contact hole CNT6. Therefore, the pre-charge voltage of the reference voltage line RL can be transmitted indirectly via the second conductive layer BML2.

[0119] The second buffer layer 112 may cover the first conductive layer BML1 or the second conductive layer BML2, and may be formed above the surface (e.g., the entire surface) of the substrate 100. The second buffer layer 112 may comprise silicon oxide (SiO2) or silicon nitride (SiN). x), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), or combinations thereof.

[0120] Semiconductor layer A2 can be disposed on second buffer layer 112. Gate electrodes G1 and G2 can be disposed above semiconductor layer A2, and gate insulating layer 113 is disposed between gate electrodes G1 and G2 and semiconductor layer A2. Gate electrodes G1 and G2 can contain molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can have a single-layer structure or a multi-layer structure. As an example, gate electrodes G1 and G2 can include a single Mo layer.

[0121] Interlayer insulating layer 115 may cover gate electrodes G1 and G2. Interlayer insulating layer 115 may contain silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), or combinations thereof.

[0122] The scan line SL and the second lower power line UPL2 can be disposed on the gate insulating layer 113. In this respect, the scan line SL can be disposed above the second connection conductive layer BML2 to overlap with the second connection conductive layer BML2. In order to connect to the data line DL disposed above the scan line SL, the width W2 of the first connection conductive layer BML1 can be greater than the width W1 of the scan line SL.

[0123] The second electrode CE2, source electrode S2, drain electrode D2, data line DL, reference voltage line RL, and second power supply line PL2 of the storage capacitor Cst can be disposed on the interlayer insulating layer 115.

[0124] The second electrode CE2, source electrode S2, drain electrode D2, data line DL, reference voltage line RL, and second power line PL2 of the storage capacitor Cst may comprise conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer or single-layer structure comprising the aforementioned materials. As an example, the second electrode CE2, source electrode S2, drain electrode D2, data line DL, reference voltage line RL, and second power line PL2 may have a multilayer structure of aluminum (e.g., Ti / Al / Ti) between titanium layers.

[0125] The source electrodes S1 and S2 and the drain electrode D2 can be connected to the source or drain regions of the semiconductor layers A1 and A2 via contact holes.

[0126] An inorganic protective layer PVX can be provided to cover the second electrode CE2, source electrode S2, drain electrode D2, data line DL, and reference voltage line RL of the storage capacitor Cst. The inorganic protective layer PVX, which can serve as an inorganic insulating layer, can comprise a single film or multiple layers of silicon nitride and silicon oxide. The inorganic protective layer PVX can at least partially cover the data line DL and the wiring formed together with the data line DL, and thus prevent the wiring from being damaged during the patterning process of the pixel electrode 310.

[0127] A planarization layer 117 can be disposed above the drain electrodes D1 and D2, the source electrode S2, the data line DL, the reference voltage line RL, and the second power line PL2, and an organic light-emitting diode (OLED) can be positioned on the planarization layer 117.

[0128] Planarization layer 117 may comprise a single-layer or multi-layer membrane containing organic materials. Planarization layer 117 may comprise benzocyclobutene (BCB), polyimide, hexamethyl disilicide (HMDSO), commonly available polymers such as polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. Planarization layer 117 may comprise inorganic materials. Planarization layer 117 may comprise silicon oxide (SiO2), silicon nitride (SiN2), etc. x The planarization layer 117 may contain inorganic materials, such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), or combinations thereof. In cases where the planarization layer 117 comprises inorganic materials, chemical planarization polishing may be performed in some situations. The planarization layer 117 may comprise both organic and inorganic materials.

[0129] In the display area DA of the substrate 100, an organic light-emitting diode (OLED) can be disposed on the planarization layer 117. The OLED may include a pixel electrode 310, an intermediate layer 320 including an organic emitting layer, and a counter electrode 330.

[0130] The planarization layer 117 may include a first via VH1 exposing a portion of the drain electrode D1 and a second via VH2 exposing a portion of the second power line PL2. The pixel electrode 310 may be connected to the drain electrode D1 of the driving TFT T1 via the first via VH1.

[0131] The opposite electrode 330 can be connected to the second power line PL2 via the second via VH2. Since the intermediate layer 320 of the organic light-emitting diode OLED can have a multilayer structure, at least one layer of the intermediate layer 320 can be disposed in the second via VH2 during the process of forming the intermediate layer 320.

[0132] Before the opposing electrode 330 can be formed, the intermediate layer 320 that may remain in the second via hole VH2 can be removed by irradiating it with a laser. Furthermore, after the opposing electrode 330 can be formed, the contact characteristics of the opposing electrode 330 and the second power line PL2 can be improved by irradiating the second via hole VH2 with a laser. Therefore, the second via hole VH2 can be provided taking into account the irradiation area of ​​the laser. In some embodiments, the area of ​​the second via hole VH2 can be larger than the area of ​​the first via hole VH1.

[0133] The pixel electrode 310 may be a (semi)transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 310 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or compounds thereof, and a transparent or semi-transparent electrode layer located on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO).

[0134] A pixel defining layer 119 can be disposed on the planarization layer 117, and the pixel defining layer 119 can have a first opening portion OP1 that exposes the central portion of the pixel electrode 310 in the display area DA, thereby defining the emission area of ​​the organic light-emitting diode OLED. In addition, the pixel defining layer 119 can increase the distance between the edge of the pixel electrode 310 and the opposing electrode 330 disposed above the pixel electrode 310, and thus prevent the occurrence of electric arcs or the like above the edge of the pixel electrode 310.

[0135] The pixel defining layer 119 may include a second opening portion OP2 corresponding to the second via hole VH2 in the planarization layer 117. A portion of the second power line PL2 may be exposed through the second opening portion OP2 and the second via hole VH2, and therefore, a laser may later be directed to the area of ​​the second via hole VH2.

[0136] The pixel-defining layer 119 can be formed using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, BCB and phenolic resin by a method such as spin coating.

[0137] The intermediate layer 320 of an organic light-emitting diode (OLED) may include an organic emitting layer. The organic emitting layer may include organic materials, including fluorescent or phosphorescent materials capable of emitting red, green, blue, or white light. The organic emitting layer may include low molecular weight organic materials or polymeric organic materials, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be selectively further disposed below the organic emitting layer and selectively further disposed on the organic emitting layer. The intermediate layer 320 may be configured to correspond to each of the pixel electrodes 310. In another embodiment, the intermediate layer 320 may include an integral layer located above the pixel electrodes 310.

[0138] The counter electrode 330 can be a light-transmitting electrode or a reflective electrode. In some embodiments, the counter electrode 330 can be a transparent or translucent electrode and can include a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg and / or compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 can be further disposed on the metal thin film. The counter electrode 330 can be disposed above the display area DA and the non-display area NDA, and can be disposed on the intermediate layer 320 and the pixel defining layer 119. The counter electrode 330 can be integrally formed in an organic light-emitting diode (OLED) to correspond to the pixel electrode 310.

[0139] The relative electrode 330 can be connected to the second power line PL2 via the second opening portion OP2 and the second passage hole VH2.

[0140] Organic light-emitting diodes (OLEDs) can be damaged by external moisture or oxygen, and therefore, a thin-film encapsulation layer (not shown) can be disposed on the OLED to cover and protect this organic light-emitting device. The thin-film encapsulation layer (not shown) can cover the display area DA while extending beyond the display area DA. This thin-film encapsulation layer can include an inorganic encapsulation layer containing at least one inorganic material and an organic encapsulation layer containing at least one organic material. In some embodiments, the thin-film encapsulation layer can have a stacked structure of organic encapsulation layers (e.g., a first inorganic encapsulation layer / organic encapsulation layer / second inorganic encapsulation layer) between the inorganic encapsulation layers.

[0141] Additionally, the pixel defining layer 119 may include spacers for preventing mask imprinting, and various functional layers such as a polarizing layer for reducing external light reflection and a touch screen layer including a black matrix, color filters, and / or touch electrodes may be provided on the thin film encapsulation layer.

[0142] In this embodiment, a first conductive layer BML1 overlapping the data line DL can be provided, and therefore, data signals can be transmitted even when the first cross portion CP1 is cut. Specifically, the data line DL and the first conductive layer BML1 can be connected to each other via a first contact hole CNT1 or a second contact hole CNT2, and therefore, the data signal can be routed. Additionally, in this embodiment, the first conductive layer BML1 can reduce the resistance of the data line DL.

[0143] Reference Figure 5 The display device according to an embodiment may include a substrate 100 and a driving TFT T1 and a sensing TFT T3 disposed above the substrate 100. Additionally, the display device may include a first lower power line UPL1, a lower reference voltage line URL, and a sensing control line SSL disposed above the substrate 100, and may include a data line DL intersecting the sensing control line SSL, the lower reference voltage line URL, the reference voltage line RL, or the first power line PL1. In an embodiment, the display device may include a first conductive layer BML1 overlapping with the intersection portion, the intersection portion intersecting the sensing control line SSL or the lower reference voltage line URL, and the first conductive layer BML1 may be connected to the data line DL via a third contact hole CNT3, a fourth contact hole CNT4, or a fifth contact hole CNT5.

[0144] In an embodiment, the display device may further include a storage capacitor Cst connected to the driving TFT T1 and a bias electrode BSM disposed below the driving TFT T1.

[0145] The bias electrode BSM can overlap with the storage capacitor Cst. Therefore, the first electrode CE1 and the second electrode CE2 of the storage capacitor Cst can form a first capacitor, and the first electrode CE1 and the bias electrode BSM can form a second capacitor.

[0146] A bias electrode BSM can be disposed on the first buffer layer 111 to correspond to the driving TFT T1 and the storage capacitor Cst. Although not shown, the bias electrode BSM can be connected to the source electrode S3 of the sensing TFT T3, and therefore, the voltage of the source electrode S3 can be applied to the bias electrode BSM. In addition, the bias electrode BSM can prevent external light from reaching the semiconductor layer A1. Therefore, the characteristics of the driving TFT T1 can be stabilized.

[0147] In an embodiment, the first conductive layer BML1 or the third conductive layer BML3 may be spaced apart from the bias electrode BSM. The first conductive layer BML1 or the third conductive layer BML3 may comprise the same material as the bias electrode BSM. For connection to the data line DL, which may be positioned above the sensing control line SSL, the width W4 of the first conductive layer BML1 may be greater than the width W3 of the sensing control line SSL.

[0148] In one embodiment, the first electrode CE1 of the storage capacitor Cst may be provided integrally with the gate electrode G1. In another embodiment, the first electrode CE1 of the storage capacitor Cst may extend from the gate electrode G1 driving the TFT T1.

[0149] The first power supply line PL1 can be connected to the source electrode S1 of the driving TFT T1. In an embodiment, the first power supply line PL1 can be provided integrally with the source electrode S1 of the driving TFT T1.

[0150] Data line DL can be disposed on interlayer insulation layer 115. In an embodiment, data line DL can overlap with sensing control line SSL or lower reference voltage line URL. Specifically, data line DL can cross sensing control line SSL to have a second crossing portion CP2, and can cross lower reference voltage line URL to have a third crossing portion CP3.

[0151] In this embodiment, the data line DL can be connected to the first conductive layer BML1 via a third contact hole CNT3, a fourth contact hole CNT4, or a fifth contact hole CNT5. A second cross portion CP2 can be disposed between the third contact hole CNT3 and the fourth contact hole CNT4. A third cross portion CP3 can be disposed between the fourth contact hole CNT4 and the fifth contact hole CNT5.

[0152] In another embodiment, the fourth contact hole CNT4 may be omitted. In another embodiment, a contact hole connecting the data line DL and the first conductive layer BML1 to each other may also be included between the third contact hole CNT3 and the fourth contact hole CNT4.

[0153] In this embodiment, the reference voltage line RL can be connected to the third conductive layer BML3. Specifically, the reference voltage line RL can be connected to the third conductive layer BML3 via the tenth contact hole CNT10.

[0154] The first contact hole CNT1 to the tenth contact hole CNT10 can be set as follows: Figure 4 or Figure 5 The vias in the second buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 115.

[0155] The following describes a method for repairing a potential short circuit in the first and second wiring of the aforementioned display device.

[0156] Figure 6A This is a flowchart illustrating a method for repairing a display device according to an embodiment. Figure 6B This is a schematic cross-sectional view illustrating the operation of testing whether the first and second wirings may be short-circuited according to an embodiment. Figure 6C This is a schematic enlarged view illustrating the operation of cutting the second wiring according to an embodiment.

[0157] exist Figure 6B and Figure 6C In, with Figure 4 In the accompanying drawings, the same reference numerals denote the same elements, and therefore their repeated descriptions are omitted.

[0158] Reference Figure 6A The method for repairing the display device may include an operation S110 of testing whether the first wiring and the second wiring may be short-circuited, and an operation S120 of cutting the second wiring by irradiating the area between the intersection and at least one contact hole with a laser.

[0159] The first wiring can be based on a reference. Figure 3 The described circuit includes a scan line SL, a sensing control line SSL, a first lower power supply line UPL1, a second lower power supply line UPL2, or a lower reference voltage line URL extending along the first direction DR1. The second wiring may be a data line DL, a reference voltage line RL, a first power supply line PL1, or a second power supply line PL2.

[0160] The intersection can be a reference. Figure 3 Any one of the first cross portion CP1 to the sixth cross portion CP6 described.

[0161] At least one contact hole can be a reference Figure 3 Any one of the first contact holes CNT1 to the tenth contact hole CNT10 described.

[0162] In cases where a short circuit may occur between the first and second wirings at an intersection where they can intersect, the short circuit can be prevented by cutting the second wiring. Specifically, the second wiring can be cut by irradiating the area between the intersection and at least one contact hole with a laser.

[0163] Reference Figure 6B The data line DL and the scan line SL can cross each other to have a first crossing portion CP1. This allows for testing to determine if the data line DL and the scan line SL might be short-circuited.

[0164] Reference Figure 6CIn the event that the data line DL and the scan line SL may be short-circuited, the laser can be directed at the area between the first cross portion CP1 and the first contact hole CNT1 and / or the area between the first cross portion CP1 and the second contact hole CNT2. Therefore, the data line DL can be cut.

[0165] In this embodiment, since the data line DL is connected to the first conductive layer BML1 via the first contact hole CNT1 or the second contact hole CNT2, the data signal can be indirectly transmitted to the pixel via the first conductive layer BML1. Therefore, improved reliability of the display device can be achieved.

[0166] Figure 7 This is a schematic diagram showing the positions of a TFT and a capacitor Cst included in a pixel circuit PC according to another embodiment. Figure 7 In, with Figure 3 In the accompanying drawings, the same reference numerals denote the same elements, and therefore their repeated descriptions are omitted.

[0167] Reference Figure 7 According to the embodiment, the pixel circuit PC of the display device can be connected to a scan line SL, a sensing control line SSL, a first lower power line UPL1, a second lower power line UPL2, and a lower reference voltage line URL extending in the first direction DR1.

[0168] In this embodiment, the conductive bonding layer BML can be island-shaped. Specifically, the first conductive bonding layer BML1 may include a first portion BML1-1 or a second portion BML1-2. The second conductive bonding layer BML2 may include a third portion BML2-1 or a fourth portion BML2-2. The third conductive bonding layer BML3 may include a fifth portion BML3-1. The first portion BML1-1 to the fifth portion BML3-1 can be island-shaped. Therefore, the first portion BML1-1 to the fifth portion BML3-1 can be spaced apart from each other.

[0169] The first portion BML1-1 may overlap with a first crossing portion CP1 in which the data line DL and the scan line SL may intersect each other. The first portion BML1-1 may be connected to the data line DL via a first contact hole CNT1 or a second contact hole CNT2. In this respect, the length of the first portion BML1-1 in the second direction DR2 may be greater than the width of the scan line SL in the second direction DR2.

[0170] The second portion BML1-2 may overlap with a second crossing portion CP2 in which the data line DL and the sensing control line SSL may cross each other. Additionally, the second portion BML1-2 may overlap with a third crossing portion CP3 in which the data line DL and the lower reference voltage line URL may cross each other. The second portion BML1-2 may be connected to the data line DL via a third contact hole CNT3, a fourth contact hole CNT4, or a fifth contact hole CNT5. In this respect, the length of the second portion BML1-2 in the second direction DR2 may be greater than the width of the sensing control line SSL or the lower reference voltage line URL in the second direction DR2. In another embodiment, some of the third contact holes CNT3, the fourth contact hole CNT4, and the fifth contact hole CNT5 may be omitted. In another embodiment, the second portion BML1-2 may include a first region overlapping with the second crossing portion CP2 and a second region overlapping with the third crossing portion CP3 and spaced apart from the first region. In this respect, a contact hole for connecting to the data line DL may also be included between the third contact hole CNT3 and the fourth contact hole CNT4.

[0171] The third part BML2-1 may overlap with the fourth crossing part CP4, in which the reference voltage line RL and the scan line SL may intersect each other. The third part BML2-1 may be connected to the reference voltage line RL via the sixth contact hole CNT6 or the seventh contact hole CNT7. In this respect, the length of the third part BML2-1 in the second direction DR2 may be greater than the width of the scan line SL in the second direction DR2.

[0172] The fourth part BML2-2 may overlap with the fifth crossing part CP5, in which the reference voltage line RL and the sensing control line SSL may cross each other. The fourth part BML2-2 may be connected to the reference voltage line RL via the eighth contact hole CNT8 or the ninth contact hole CNT9. In this respect, the length of the fourth part BML2-2 in the second direction DR2 may be greater than the width of the sensing control line SSL in the second direction DR2.

[0173] The fifth portion BML3-1 may overlap with the sixth crossing portion CP6, in which the second intermediate conductive layer IM2 and the sensing control line SSL may intersect each other. The fifth portion BML3-1 may be connected to the second intermediate conductive layer IM2 via the tenth contact hole CNT10 or the eleventh contact hole CNT11. In this respect, the length of the fifth portion BML3-1 in the second direction DR2 may be greater than the width of the sensing control line SSL in the second direction DR2.

[0174] Figure 8 This is a schematic diagram showing the positions of a TFT and a capacitor Cst included in a pixel circuit PC according to another embodiment. Figure 8In, with Figure 3 In the accompanying drawings, the same reference numerals denote the same elements, and therefore their repeated descriptions are omitted.

[0175] Reference Figure 8 According to an embodiment, the pixel circuit PC of the display device can be connected to a scan line SL, a sensing control line SSL, a first lower power line UPL1, a second lower power line UPL2, and a lower reference voltage line URL extending in a first direction DR1. The pixel electrode 310 can be connected to the second electrode CE2 of the storage capacitor Cst via a first via VH1. Additionally, the pixel defining layer 119 may include a first opening portion OP1 that exposes the central portion of the pixel electrode 310 in the display area DA.

[0176] In this embodiment, an upper conductive layer CM may be disposed above the second wiring. For example, the upper conductive layer CM may be disposed above the data line DL, the reference voltage line RL, the first power line PL1, and the second power line PL2.

[0177] In this embodiment, the upper conductive layer CM can be disposed on the same layer as the pixel electrode 310 and can be spaced apart from the pixel electrode 310. Specifically, the upper conductive layer CM can be spaced apart from the pixel electrode 310 in the first direction DR1 or the second direction DR2. In this embodiment, the upper conductive layer CM can include the same material as the pixel electrode 310.

[0178] In an embodiment, the upper conductive layer CM may include a first upper conductive layer CM1, a second upper conductive layer CM2, and a third upper conductive layer CM3. The first upper conductive layer CM1, the second upper conductive layer CM2, and the third upper conductive layer CM3 may be spaced apart from each other. For example, the first upper conductive layer CM1, the second upper conductive layer CM2, and the third upper conductive layer CM3 may be spaced apart from each other in a first direction DR1.

[0179] The first upper conductive layer CM1 may overlap with the data line DL. In an embodiment, the first upper conductive layer CM1 may extend in the second direction DR2 while overlapping with the data line DL. For example, the first upper conductive layer CM1 may extend while continuously overlapping with the data line DL.

[0180] In this embodiment, the first upper conductive layer CM1 may overlap with a first crossing portion CP1 in which data line DL and scan line SL may intersect each other. The first upper conductive layer CM1 may overlap with a second crossing portion CP2 in which data line DL and sensing control line SSL may intersect each other. Additionally, the first upper conductive layer CM1 may overlap with a third crossing portion CP3 in which data line DL and lower reference voltage line URL may intersect each other.

[0181] The first upper conductive layer CM1 can be connected to the data line DL via at least one connection contact hole. In an embodiment, the first upper conductive layer CM1 can be connected to the data line DL via a first contact hole CNT1' and a second contact hole CNT2'. In this regard, a first cross portion CP1 can be disposed between the first contact hole CNT1' and the second contact hole CNT2'. Therefore, the data signal Dm of the data line DL can be transmitted indirectly via the first upper conductive layer CM1. As another example, the first upper conductive layer CM1 can be connected to the data line DL via a third contact hole CNT3', a fourth contact hole CNT4', or a fifth contact hole CNT5'. In this regard, a second cross portion CP2 can be disposed between the third contact hole CNT3' and the fourth contact hole CNT4'. A third cross portion CP3 can be disposed between the fourth contact hole CNT4' and the fifth contact hole CNT5'.

[0182] In another embodiment, some of the first contact holes CNT1' to the fifth contact holes CNT5' may be omitted. For example, the fourth contact hole CNT4' of the third contact hole CNT3', fourth contact hole CNT4', and fifth contact hole CNT5' may be omitted. In another embodiment, a contact hole may also be included between the third contact hole CNT3' and the fourth contact hole CNT4'.

[0183] The second upper conductive layer CM2 may overlap with the reference voltage line RL. In an embodiment, the second upper conductive layer CM2 may extend in the second direction DR2 while overlapping with the reference voltage line RL. For example, the second upper conductive layer CM2 may extend while continuously overlapping with the reference voltage line RL.

[0184] In one embodiment, the second upper conductive layer CM2 may overlap with a fourth intersection portion CP4, in which the reference voltage line RL and the scan line SL may intersect each other. Additionally, the second upper conductive layer CM2 may overlap with a fifth intersection portion CP5, in which the reference voltage line RL and the sensing control line SSL may intersect each other.

[0185] The second upper conductive layer CM2 can be connected to the reference voltage line RL via at least one connecting contact hole. For example, the second upper conductive layer CM2 can be connected to the reference voltage line RL via a sixth contact hole CNT6' or a seventh contact hole CNT7'. In this regard, a fourth cross portion CP4 can be disposed between the sixth contact hole CNT6' and the seventh contact hole CNT7'. As another example, the second upper conductive layer CM2 can be connected to the reference voltage line RL via an eighth contact hole CNT8' or a ninth contact hole CNT9'. In this regard, a fifth cross portion CP5 can be disposed between the eighth contact hole CNT8' and the ninth contact hole CNT9'. Therefore, the pre-charge voltage of the reference voltage line RL can be transmitted indirectly via the second upper conductive layer CM2.

[0186] The third upper conductive layer CM3 may overlap with the second intermediate conductive layer IM2. In an embodiment, the third upper conductive layer CM3 may extend in the second direction DR2 while overlapping with the second intermediate conductive layer IM2. For example, the third upper conductive layer CM3 may extend while continuously overlapping with the second intermediate conductive layer IM2. The third upper conductive layer CM3 may overlap with the sixth intersection portion CP6 in which the second intermediate conductive layer IM2 and the sensing control line SSL may intersect each other.

[0187] The third upper conductive layer CM3 can be connected to the second intermediate conductive layer IM2 via at least one connecting contact hole. For example, the third upper conductive layer CM3 can be connected to the second intermediate conductive layer IM2 via the tenth contact hole CNT10' or the eleventh contact hole CNT11'. In this regard, the sixth cross portion CP6 can be disposed between the tenth contact hole CNT10' and the eleventh contact hole CNT11'. Therefore, the pre-charge voltage of the reference voltage line RL can be transmitted indirectly via the third upper conductive layer CM3.

[0188] In the event that the first and second wirings may short-circuit, an upper conductive layer CM overlapping the second wiring can be provided as described above to cut the second wiring. In the event that the first and second wirings may short-circuit, the intersection portions where the first and second wirings may intersect each other can be cut. In this respect, if the second wiring may not have a mesh-like structure like the first power line PL1 or the second power line PL2, the signal may not be transmitted to the pixel circuit PC. In an embodiment, an upper conductive layer CM overlapping the second wiring can be provided, and therefore, even when the intersection portions are cut, the signal can still be transmitted to the pixel circuit PC. Specifically, the second wiring and the upper conductive layer CM can be connected to each other via at least one contact hole, and therefore, the signal can be routed. In an embodiment, the upper conductive layer CM can be formed simultaneously with the pixel electrode 310, and therefore, no additional mask is required. Additionally, in an embodiment, the upper conductive layer CM can reduce the resistance of the second wiring.

[0189] Figure 9 It is along Figure 8 A schematic cross-sectional view taken from line C-C'. Figure 9 In, with Figure 4 or Figure 5 In the accompanying drawings, the same reference numerals denote the same elements, and therefore their repeated descriptions are omitted.

[0190] Reference Figure 9 It may include a first lower power line UPL1, a lower reference voltage line URL, and a sensing control line SSL disposed above the substrate 100, and may include a data line DL that intersects with the lower reference voltage line URL or the sensing control line SSL, and a reference voltage line RL that intersects with the sensing control line SSL.

[0191] In one embodiment, the first upper conductive layer CM1 may overlap with a second crossing portion CP2 in which the sensing control line SSL and the data line DL may cross each other. Additionally, the first upper conductive layer CM1 may overlap with a third crossing portion CP3 in which the lower reference voltage line URL and the data line DL may cross each other. In another embodiment, the second upper conductive layer CM2 may overlap with a fifth crossing portion CP5 in which the sensing control line SSL and the reference voltage line RL may cross each other.

[0192] The first upper conductive layer CM1 and the second upper conductive layer CM2 can be disposed on the first planarization layer 117. Specifically, the first upper conductive layer CM1 and the second upper conductive layer CM2 can be disposed on the same layer as the pixel electrode.

[0193] The first upper conductive layer CM1 can be connected to the data line DL via at least one connection contact hole. In an embodiment, the first upper conductive layer CM1 can be connected to the data line DL via a third contact hole CNT3', a fourth contact hole CNT4', or a fifth contact hole CNT5'. In this regard, a second cross portion CP2 can be disposed between the third contact hole CNT3' and the fourth contact hole CNT4'. A third cross portion CP3 can be disposed between the fourth contact hole CNT4' and the fifth contact hole CNT5'. Therefore, the data signal of the data line DL can be transmitted indirectly via the first upper conductive layer CM1.

[0194] In another embodiment, some of the third contact holes CNT3' to the fifth contact holes CNT5' may be omitted. For example, the fourth contact hole CNT4' of the third contact hole CNT3', fourth contact hole CNT4', and fifth contact hole CNT5' may be omitted.

[0195] The second upper conductive layer CM2 can be connected to the reference voltage line RL via at least one connecting contact hole. As another example, the second upper conductive layer CM2 can be connected to the reference voltage line RL via an eighth contact hole CNT8' or a ninth contact hole CNT9'. In this regard, a fifth cross portion CP5 can be disposed between the eighth contact hole CNT8' and the ninth contact hole CNT9'. Therefore, the pre-charge voltage of the reference voltage line RL can be transmitted indirectly via the second upper conductive layer CM2.

[0196] The first contact hole CNT1' to the tenth contact hole CNT10' can be set as a through hole located in the inorganic protective layer PVX and the planarization layer 117.

[0197] Figure 10A This is a flowchart illustrating a method for repairing a display device according to another embodiment. Figure 10B This is a schematic cross-sectional view illustrating the operation of cutting the second wiring according to another embodiment. Figure 10C This is a schematic cross-sectional view illustrating the operation of forming a conductive layer according to another embodiment.

[0198] exist Figure 10B and Figure 10C In, with Figure 9 In the accompanying drawings, the same reference numerals denote the same elements, and therefore their repeated descriptions are omitted.

[0199] Reference Figure 10AThe method for repairing the display device may include an operation S210 of testing whether the first wiring and the second wiring may be short-circuited, an operation S220 of cutting the second wiring by irradiating the area between the intersection and at least one contact hole with a laser, and an operation S230 of connecting the second wiring by forming a connection conductive layer on the same layer as the pixel electrode.

[0200] The first wiring can be based on a reference. Figure 8 The described circuit includes a scan line SL, a sensing control line SSL, a first lower power supply line UPL1, a second lower power supply line UPL2, or a lower reference voltage line URL extending along the first direction DR1. The second wiring may be a data line DL, a reference voltage line RL, a first power supply line PL1, or a second power supply line PL2.

[0201] The intersection can be a reference. Figure 8 Any one of the first cross portion CP1 to the sixth cross portion CP6 described.

[0202] At least one contact hole can be a reference Figure 8 Any one of the first contact hole CNT1' to the tenth contact hole CNT10' described.

[0203] In cases where a short circuit may occur between the first and second wirings at an intersection where they can intersect, the short circuit can be prevented by cutting the second wiring. Specifically, the second wiring can be cut by irradiating the area between the intersection and at least one contact hole with a laser.

[0204] Reference Figure 10B The data cable DL and the sensing control cable SSL can cross each other to form a second crossing portion CP2. It is possible to test whether the data cable DL and the sensing control cable SSL might be short-circuited. In this regard, if a short circuit is possible, a laser can be directed at the area between the second crossing portion CP2 and the third contact hole CNT3' and / or the area between the second crossing portion CP2 and the fourth contact hole CNT4'. Therefore, the data cable DL can be cut.

[0205] Reference Figure 10C After the second wiring can be cut, it can be connected by forming a conductive layer on the same layer as the pixel electrode. For example, after the data line DL can be cut, a first upper conductive layer CM1 can be formed on the planarization layer 117. The first upper conductive layer CM1 can be connected to the data line DL via a third contact hole CNT3' or a fourth contact hole CNT4'. Therefore, the data signal of the data line DL can be indirectly transmitted to the pixel via the first upper conductive layer CM1. Thus, improved reliability of the display device can be obtained.

[0206] Figure 11 This is a schematic diagram showing the positions of a TFT and a capacitor Cst included in a pixel circuit PC according to another embodiment. Figure 11 In, with Figure 8 In the accompanying drawings, the same reference numerals denote the same elements, and therefore their repeated descriptions are omitted.

[0207] Reference Figure 11 According to the embodiment, the pixel circuit PC of the display device can be connected to a scan line SL, a sensing control line SSL, a first lower power line UPL1, a second lower power line UPL2, and a lower reference voltage line URL extending in the first direction DR1.

[0208] In this embodiment, the upper conductive layer CM may have an island-like shape. Specifically, the first upper conductive layer CM1 may include a first upper portion CM1-1 or a second upper portion CM1-2. The second upper conductive layer CM2 may include a third upper portion CM2-1 or a fourth upper portion CM2-2. The third upper conductive layer CM3 may include a fifth upper portion CM3-1. The first upper portions CM1-1 to the fifth upper portions CM3-1 may have an island-like shape. Therefore, the first upper portions CM1-1 to the fifth upper portions CM3-1 may be spaced apart from each other.

[0209] The first upper portion CM1-1 may overlap with the first crossing portion CP1, in which the data line DL and the scan line SL may cross each other. The first upper portion CM1-1 may be connected to the data line DL via a first contact hole CNT1' or a second contact hole CNT2'. In this respect, the length of the first upper portion CM1-1 in the second direction DR2 may be greater than the width of the scan line SL in the second direction DR2.

[0210] The second upper portion CM1-2 may overlap with a second crossing portion CP2 in which the data line DL and the sensing control line SSL may cross each other. Additionally, the second upper portion CM1-2 may overlap with a third crossing portion CP3 in which the data line DL and the lower reference voltage line URL may cross each other. The second upper portion CM1-2 may be connected to the data line DL via a third contact hole CNT3', a fourth contact hole CNT4', or a fifth contact hole CNT5'. In this respect, the length of the second upper portion CM1-2 in the second direction DR2 may be greater than the width of the sensing control line SSL or the lower reference voltage line URL in the second direction DR2. In another embodiment, some of the third contact holes CNT3', fourth contact holes CNT4', and fifth contact holes CNT5' may be omitted. In another embodiment, the second upper portion CM1-2 may include a first region overlapping with the second crossing portion CP2 and a second region overlapping with the third crossing portion CP3 and spaced apart from the first region. In this respect, a contact hole for connecting to the data line DL may also be included between the third contact hole CNT3' and the fourth contact hole CNT4'.

[0211] The third upper portion CM2-1 may overlap with the fourth crossing portion CP4, in which the reference voltage line RL and the scan line SL may intersect each other. The third upper portion CM2-1 may be connected to the reference voltage line RL via the sixth contact hole CNT6' or the seventh contact hole CNT7'. In this respect, the length of the third upper portion CM2-1 in the second direction DR2 may be greater than the width of the scan line SL in the second direction DR2.

[0212] The fourth upper portion CM2-2 may overlap with the fifth crossing portion CP5, in which the reference voltage line RL and the sensing control line SSL may cross each other. The fourth upper portion CM2-2 may be connected to the reference voltage line RL via the eighth contact hole CNT8' or the ninth contact hole CNT9'. In this respect, the length of the fourth upper portion CM2-2 in the second direction DR2 may be greater than the width of the sensing control line SSL in the second direction DR2.

[0213] The fifth upper portion CM3-1 may overlap with the sixth crossing portion CP6, in which the second intermediate conductive layer IM2 and the sensing control line SSL may cross each other. The fifth upper portion CM3-1 may be connected to the second intermediate conductive layer IM2 via the tenth contact hole CNT10' or the eleventh contact hole CNT11'. In this respect, the length of the fifth upper portion CM3-1 in the second direction DR2 may be greater than the width of the sensing control line SSL in the second direction DR2.

[0214] According to one or more embodiments, a display device may include a conductive layer that overlaps with an intersection portion in which signal wiring may cross each other, the conductive layer detours the signals and thus improves the reliability of the display device.

[0215] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by this disclosure and its equivalents.

Claims

1. A display device, wherein, The display device includes: The substrate includes both the display area and the non-display area; A display element is located above the display area and includes a pixel electrode and a counter electrode. A thin-film transistor, including a semiconductor layer, is disposed between the substrate and the display element and connected to the display element; A first wiring is connected to the thin-film transistor and extends in a first direction; The second wiring is disposed above the first wiring and extends in a second direction that intersects the first direction; A conductive layer is provided below the first wiring and overlaps with the intersection portion where the first wiring and the second wiring intersect each other; A first insulating layer is disposed between the connecting conductive layer and the first wiring; A second insulating layer is disposed between the first wiring and the second wiring; A third insulating layer is disposed between the second insulating layer and the opposing electrode; The first connecting contact hole and the second connecting contact hole are defined in the first insulating layer and the In the second insulating layer, the first connection contact hole and the second connection contact hole connect the connection conductive layer and the second wiring; A power line, disposed on the same layer as the second wiring, spaced apart from the second wiring, extending along the second direction, and connected to the opposing electrode through an opening defined in the third insulating layer; and A bias electrode is disposed between the substrate and the semiconductor layer and overlaps with the semiconductor layer. The intersecting portion is located between the first connecting contact hole and the second connecting contact hole. The connecting conductive layer and the bias electrode are disposed on the same layer, and in the plan view, the connecting conductive layer is spaced apart from the bias electrode and the power line.

2. The display device according to claim 1, wherein, The conductive layer is located between the substrate and the first wiring.

3. The display device according to claim 2, wherein, The display device further includes: A buffer layer is disposed between the conductive layer and the first wiring.

4. The display device according to claim 1, wherein, The conductive layer has a single integral portion between the first and second connection contact holes.

5. The display device according to claim 1, wherein, The thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. The first wiring is connected to the gate electrode.

6. The display device according to claim 5, wherein, The second wiring is connected to the source electrode or the drain electrode.

7. The display device according to claim 1, wherein, The conductive layer extends in the second direction.

8. The display device according to claim 1, wherein, The conductive connecting layer comprises islands.

9. The display device according to claim 1, wherein, The length of the connecting conductive layer in the second direction is greater than the length of the intersection portion in the second direction.

10. The display device according to claim 1, wherein, The second wiring includes a data line.

11. The display device according to claim 1, wherein, The display device further includes: an inorganic protective layer covering the second wiring.

12. A display device, wherein, The display device includes: The substrate includes both the display area and the non-display area; Display element, above the display area; A thin-film transistor is disposed between the substrate and the display element and connected to the display element; A first wiring is connected to the thin-film transistor and extends in a first direction; The second wiring is disposed above the first wiring and extends in a second direction that intersects the first direction; A conductive layer is connected, overlapping the intersection portion where the first wiring and the second wiring intersect each other; An insulating layer is disposed between the conductive connecting layer and the second wiring; and At least one connection contact hole is defined in the insulating layer, the at least one connection contact hole connecting the connection conductive layer and the second wiring. The conductive layer is disposed above the second wiring. The display element includes pixel electrodes and opposing electrodes, and The conductive layer and the pixel electrode are disposed on the same layer.

13. The display device according to claim 12, wherein, The conductive layer is spaced apart from the pixel electrode.

14. The display device according to claim 12, wherein, The display device further includes a planarization layer between the display element and the thin-film transistor. The conductive layer is located on the planarization layer.

15. A method for repairing a display device, wherein, The display device includes: Base; A display element is located above the display area and includes a pixel electrode and a counter electrode. A thin-film transistor, including a semiconductor layer, is disposed between the substrate and the display element and connected to the display element; A first wiring is connected to the thin-film transistor and extends over the substrate in a first direction; The second wiring is positioned above and intersects the first wiring; A conductive layer is provided below the first wiring and overlaps with the intersection portion where the first wiring and the second wiring intersect each other; An insulating layer is located between the conductive connecting layer and the second wiring. An additional insulating layer is provided between the insulating layer and the opposing electrode; At least one connection contact hole, in which the connection conductive layer is connected to the second wiring via the at least one connection contact hole in the insulating layer; A power line, disposed on the same layer as the second wiring, spaced apart from the second wiring, extending along the second direction, and connected to the opposing electrode through an opening defined in the additional insulating layer; and A bias electrode is disposed between the substrate and the semiconductor layer and overlaps with the semiconductor layer. The conductive connecting layer and the bias electrode are disposed on the same layer, and in the plan view, the conductive connecting layer is spaced apart from the bias electrode and the power line. The method includes cutting the second wiring by irradiating the area between the cross portion and the at least one connection contact hole after forming the cross portion and the at least one connection contact hole with a laser.

16. The method according to claim 15, wherein, The method further includes: Before cutting the second wiring, test whether the first wiring and the second wiring are short-circuited.

17. A method for repairing a display device, wherein, The display device includes: Base; A first wiring extends over the substrate in a first direction; The second wiring is positioned above and intersects the first wiring; A conductive layer is provided above the second wiring and overlaps with the intersection portion where the first wiring and the second wiring intersect each other; An insulating layer is located between the conductive connecting layer and the second wiring. At least one connection contact hole, in which the connection conductive layer is connected to the second wiring via the at least one connection contact hole in the insulating layer; and Display elements, including pixel electrodes and relative electrodes, The method includes: cutting the second wiring by irradiating the area between the intersection and the at least one connection contact hole with a laser before forming the at least one connection contact hole. The method further includes: After the second wiring is cut, the second wiring is connected by forming the connection conductive layer and the pixel electrode on the same layer.

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