Display Devices

Abstract

The present invention discloses a display device. The display device includes a first pixel, a second pixel, a first data line connected to the first pixel, and a second data line connected to the second pixel. Each of the first pixel and the second pixel includes: a transistor including a conductive layer, a semiconductor layer on the conductive layer, a gate electrode on the semiconductor layer, and a source / drain electrode connected to the semiconductor layer; a capacitor including a first capacitor electrode in the same layer as the gate electrode and a second capacitor electrode on the first capacitor electrode; and a light emitting device on the transistor and the capacitor. The first data line is in the same layer as the source / drain electrode, and the second data line is in the same layer as the conductive layer and one of the second capacitor electrodes.

Description

Technical Field

[0001] Embodiments relate to a display device, and more particularly, to a display device driven at a high speed. Background Art

[0002] With the development of technology related to display devices, display devices have become larger in size, higher in resolution and faster in speed. Therefore, in such display devices, gate signals can be applied to a larger number of gate lines within a predetermined time period. Therefore, the time for allowing data signals to be input to pixels can be reduced. Summary of the invention

[0003] As described above, in a display device that reduces the time allowed for a data signal to be input to a pixel, the number of data lines may be increased to compensate for the reduction in the time for the data signal to be input to the pixel. The number of conductive layers included in the display device may be increased to provide more data lines in a limited space. When the number of conductive layers increases, the number of mask processes for forming the conductive layers may increase, and thus the manufacturing time and manufacturing cost of the display device may increase.

[0004] The embodiment provides a display device that is driven at a high speed and manufactured using a reduced number of mask processes.

[0005] According to an embodiment of the present invention, a display device includes: a first pixel; a second pixel adjacent to the first pixel in a predetermined direction; a first data line extending in a predetermined direction and connected to the first pixel; and a second data line extending in a predetermined direction and connected to the second pixel. In such an embodiment, each of the first pixel and the second pixel includes: a transistor including a conductive layer, a semiconductor layer arranged on the conductive layer, a gate electrode arranged on the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer; a capacitor including a first capacitor electrode arranged in the same layer as the gate electrode and a second capacitor electrode arranged on the first capacitor electrode; and a light emitting device arranged on the transistor and the capacitor. In such an embodiment, the first data line is arranged in the same layer as the source electrode and the drain electrode, and the second data line is arranged in the same layer as the conductive layer and one of the second capacitor electrodes.

[0006] In an embodiment, the first data line may be integrally formed with a source electrode or a drain electrode of a transistor of the first pixel.

[0007] In an embodiment, the first data line and the second data line may overlap each other when viewed in a plan view.

[0008] In an embodiment, the display device may further include: a buffer layer arranged between the conductive layer and the semiconductor layer; a first insulating layer arranged between the semiconductor layer and the gate electrode; a second insulating layer arranged between the first capacitor electrode and the second capacitor electrode; and a third insulating layer arranged between the second capacitor electrode and the source electrode and the drain electrode.

[0009] In an embodiment, the second data line may be arranged in the same layer as the second capacitor electrode, and the second data line may be connected to the source electrode or the drain electrode of the transistor of the second pixel through a contact hole defined through the third insulating layer.

[0010] In an embodiment, the second data line may be arranged in the same layer as the conductive layer and connected to the source electrode or drain electrode of the transistor of the second pixel through a contact hole defined through the buffer layer, the first insulating layer, the second insulating layer and the third insulating layer.

[0011] In an embodiment, the display device may further include a third data line extending in a predetermined direction and connected to the second pixel. The second data line may be arranged in the same layer as the second capacitor electrode, and the third data line may be arranged in the same layer as the conductive layer.

[0012] In an embodiment, the first data line, the second data line, and the third data line may overlap each other when viewed in a plan view.

[0013] In an embodiment, the second data line can be connected to the source electrode or drain electrode of the transistor of the second pixel through a contact hole defined through the third insulating layer, and the third data line can be connected to the source electrode or drain electrode of the transistor of the second pixel through a contact hole defined through the buffer layer, the first insulating layer, the second insulating layer and the third insulating layer.

[0014] In an embodiment, the second data line may include a material having a resistance less than that of the gate electrode.

[0015] In an embodiment, the display device may further include a plurality of pixel rows arranged along a predetermined direction. In such an embodiment, the first pixel may be included in an odd pixel row of the plurality of pixel rows, and the second pixel may be included in an even pixel row of the plurality of pixel rows.

[0016] In an embodiment, the semiconductor layer may include at least one material selected from amorphous silicon, polysilicon, and metal oxide.

[0017] According to an embodiment of the present invention, a display device includes: a first pixel; a second pixel adjacent to the first pixel in a predetermined direction; a first data line extending in a predetermined direction and connected to the first pixel; and a second data line extending in a predetermined direction and connected to the second pixel. In such an embodiment, each of the first pixel and the second pixel includes: a transistor including a conductive layer, a semiconductor layer arranged on the conductive layer, a gate electrode arranged on the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer; and a light emitting device arranged on the transistor. In such an embodiment, the first data line is arranged in the same layer as the source electrode and the drain electrode, and the second data line is arranged in the same layer as the conductive layer.

[0018] In an embodiment, the display device may further include: a buffer layer disposed between the conductive layer and the semiconductor layer; a first insulating layer disposed between the semiconductor layer and the gate electrode; and a second insulating layer disposed between the gate electrode and the source and drain electrodes.

[0019] In an embodiment, the second data line may be connected to a source electrode or a drain electrode of a transistor of the second pixel through a contact hole defined through the buffer layer, the first insulating layer, and the second insulating layer.

[0020] In an embodiment, each of the first pixel and the second pixel may further include a capacitor including a first capacitor electrode arranged in the same layer as the conductive layer and a second capacitor electrode arranged on the first capacitor electrode.

[0021] In an embodiment, the second capacitor electrode may be arranged in the same layer as the gate electrode.

[0022] In an embodiment, the second capacitor electrode may be arranged in the same layer as the semiconductor layer.

[0023] According to an embodiment of the present invention, a display device includes: a first pixel; a second pixel adjacent to the first pixel in a predetermined direction; a first data line extending in a predetermined direction and connected to the first pixel; and a second data line extending in a predetermined direction and connected to the second pixel. In such an embodiment, each of the first pixel and the second pixel includes: a transistor including a semiconductor layer, a gate electrode arranged on the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer; a capacitor including a first capacitor electrode arranged in the same layer as the gate electrode and a second capacitor electrode arranged on the first capacitor electrode; and a light emitting device arranged on the transistor and the capacitor. In such an embodiment, the first data line is arranged in the same layer as the source electrode and the drain electrode, and the second data line is arranged in the same layer as the second capacitor electrode.

[0024] In an embodiment, the display device may further include: a first insulating layer arranged between the semiconductor layer and the gate electrode; a second insulating layer arranged between the first capacitor electrode and the second capacitor electrode; and a third insulating layer arranged between the second capacitor electrode and the source and drain electrodes.

[0025] In an embodiment, the second data line may be connected to a source electrode or a drain electrode of a transistor of the second pixel through a contact hole defined through the third insulating layer.

[0026] In an embodiment of the present invention, a display device may include a first data line and a second data line respectively connected to a first pixel and a second pixel included in different pixel rows from each other, the first data line may be arranged in the same layer as a source / drain electrode of a transistor, and the second data line may be arranged in the same layer as a second capacitor electrode of a capacitor. Therefore, the display device may be driven at high speed, and the number of mask processes in a manufacturing process of the display device may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a diagram illustrating a display device according to an embodiment of the present invention.

[0029] Figure 2 It is a graphic Figure 1 FIG. 4 is a diagram of a demultiplexer DM and pixels PX1 and PX2 connected thereto.

[0030] Figure 3 It is a graphic Figure 2 A circuit diagram of one example of a first pixel PX1 and a second pixel PX2 is shown in FIG.

[0031] Figure 4 is a plan view illustrating a display device according to an embodiment of the present invention.

[0032] Figure 5 The diagram is along Figure 4 FIG. 5 is a cross-sectional view of an embodiment of a first pixel PX1 taken along line II′ of FIG.

[0033] Figure 6 The diagram is along Figure 4 FIG. 5 is a cross-sectional view of an embodiment of a second pixel PX2 taken along line II-II′.

[0034] Figure 7 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of an example of a second pixel PX2 taken along line II-II′.

[0035] Figure 8is a plan view illustrating a display device according to an alternative embodiment of the present invention.

[0036] Fig. 9 The diagram is along Figure 8 FIG. 5 is a cross-sectional view of an embodiment of a second pixel PX2 taken along line III-III′.

[0037] Fig.10 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of an alternative embodiment of the first pixel PX1 taken along line II′.

[0038] Fig.11 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of an alternative embodiment of the second pixel PX2 taken along line II-II′.

[0039] Fig.12 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of another alternative embodiment of the second pixel PX2 taken along line II-II′.

[0040] Fig.13 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of another alternative embodiment of the first pixel PX1 taken along line II′.

[0041] Fig.14 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of another alternative embodiment of the second pixel PX2 taken along line II-II′. DETAILED DESCRIPTION

[0042] The present invention will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be detailed and comprehensive, and will fully convey the scope of the present invention to those skilled in the art. Throughout the text, the same reference numerals refer to the same elements.

[0043] It should be understood that when an element is referred to as being "on" another element, the element may be directly "on" the other element or intervening elements may exist between them. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0044] It will be understood that, although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this article, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as the second element, second component, second region, second layer or second part.

[0045] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be limiting. The singular forms "one" and "the" used herein are intended to include plural forms including "at least one", unless the context clearly indicates otherwise. "Or" means "and / or". The term "and / or" used herein includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "include" and / or "comprising" when used in this specification indicate the presence of stated features, regions, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or combinations thereof.

[0046] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as illustrated in the accompanying drawings. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the accompanying drawings. For example, if the device in one of the figures in the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the exemplary term "lower" can include both "lower" and "upper" orientations. Similarly, if the device in one of the figures in the accompanying drawings is turned over, the element described as being "below" or "below" the other elements will then be oriented as being "above" the other element. Therefore, the exemplary terms "below" and "below" can include both "upper" and "lower" orientations.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0048] Herein, exemplary embodiments are described with reference to cross-sectional illustrations, which are schematic illustrations of rationalized embodiments. Thus, variations between the illustrated shapes may be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the illustrated regions herein, but will include deviations in shapes caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features. Moreover, the illustrated sharp corners may be rounded. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the illustrated regions and are not intended to limit the scope of the claims.

[0049] Hereinafter, embodiments of a display device will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 is a diagram illustrating a display device according to an embodiment of the present invention.

[0051] refer to Figure 1 , a display device according to an embodiment of the present invention may include a display unit DU, a gate driver GD, a data driver DD, a demultiplexer DM, a demultiplexer controller DMC, and a timing controller TC. The display unit DU may include a plurality of pixels PX. The pixels PX may be arranged in a basic matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. Therefore, the display unit DU may include a plurality of pixel rows PR arranged along the first direction DR1. The pixel rows PR may include a plurality of odd pixel rows PRO and a plurality of even pixel rows PRE alternately arranged in the first direction DR1.

[0052] The gate driver GD may supply a gate signal to the gate line GL in response to a gate driver control signal GCS provided from the timing controller TC. In one embodiment, for example, the gate driver GD may sequentially supply the gate signal to the gate line GL. When the gate signal is sequentially supplied to the gate line GL, the pixels PX may be sequentially selected in units of pixel rows PR.

[0053] The data driver DD may supply the data signal to the output line OL in response to the data driver control signal DCS provided from the timing controller TC. The data driver DD may supply the data signal to the demultiplexer DM through the output line OL.

[0054] The demultiplexer DM may receive a data signal from the data driver DD and supply the data signal to the data lines DL1 and DL2. In one embodiment, for example, the demultiplexer DM may receive a data signal through an output line OL and output the data signal to the data lines DL1 and DL2 in a time-division manner, and the number of the data lines DL1 and DL2 is greater than the number of the output lines OL. Therefore, each of the pixels PX may receive a data signal through the data lines DL1 and DL2. In one embodiment, for example, the number of the data lines DL1 and DL2 may be twice the number of the output lines OL of the data driver DD.

[0055] In an embodiment, a capacitor may be defined or formed in each of the data lines DL1 and DL2 to store a signal applied to the data lines DL1 and DL2. In such an embodiment, the capacitor defined or formed in the data lines DL1 and DL2 may be attributed to parasitic capacitance. In addition, the capacitor may be physically formed in the data lines DL1 and DL2.

[0056] The demultiplexer controller DMC may control the operation of the demultiplexer DM through the drive signal CD. In one embodiment, for example, the drive signal CD may be used to control the operation of transistors respectively included in the demultiplexer DM. The demultiplexer controller DMC may receive the demultiplexer control signal MCS supplied from the timing controller TC and generate the drive signal CD corresponding to the demultiplexer control signal MCS. In an embodiment, as shown in FIG. Figure 1 As shown in , the demultiplexer controller DMC may be separated from the timing controller TC, but is not limited thereto. Alternatively, the demultiplexer controller DMC may be integrated with the timing controller TC.

[0057] In an embodiment, the timing controller TC may control the gate driver GD, the data driver DD, and the demultiplexer controller DMC. In such an embodiment, the timing controller TC may supply the gate driver control signal GCS, the data driver control signal DCS, and the demultiplexer control signal MCS to the gate driver GD, the data driver DD, and the demultiplexer controller DMC, respectively.

[0058] The first power supply VDD and the second power supply VSS may provide a power voltage to the display unit DU. The first power supply VDD may be a high potential voltage source, and the second power supply VSS may be a low potential voltage source. In one embodiment, for example, the first power supply VDD may provide a positive voltage to the display unit DU, and the second power supply VSS may provide a negative voltage or a ground voltage to the display unit DU.

[0059] The pixel rows PR may be connected to the gate lines GL, respectively. The pixels PX may be connected to a first power source VDD and a second power source VSS, and may be supplied with power voltages from the first power source VDD and the second power source VSS. Each of the pixels PX may control the amount of current flowing from the first power source VDD to the second power source VSS via the light emitting device in response to a data signal, and the light emitting device included in each of the pixels PX may generate light having a brightness corresponding to the amount of current.

[0060] Figure 2 It is a graphic Figure 1 For ease of illustration and description, Figure 2 Shows Figure 1 1 and 2. In the embodiment of the present invention, one of the demultiplexers DM of the demultiplexers DM is shown, and two pixels PX1 and PX2 of the pixels PX connected to the demultiplexer DM are shown.

[0061] refer to Figure 1 and Figure 2 The demultiplexer DM may be connected between the output line OL and the data lines DL1 and DL2. The data lines DL1 and DL2 may include a first data line DL1 and a second data line DL2.

[0062] In an embodiment, the demultiplexer DM may time-divisionally transmit a data signal received from the data driver DD through the output line OL to the first data line DL1 and the second data line DL2. In such an embodiment, the first data line DL1 and the second data line DL2 may be connected to the pixels PX1 and PX2 included in one pixel column. In an embodiment, for example, the first data line DL1 may be connected to the first pixel PX1, and the second data line DL2 may be connected to the second pixel PX2 located in the first direction DR1 from the first pixel PX1 or adjacent to the first pixel PX1 in the first direction DR1.

[0063] The first data line DL1 may be connected to a portion of the pixel row PR, and the second data line DL2 may be connected to the remaining portion of the pixel row PR. In one embodiment, for example, the first data line DL1 may be connected to pixels in an odd pixel row PRO in the pixel row PR, and the second data line DL2 may be connected to pixels in an even pixel row PRE in the pixel row PR. In such an embodiment, the first pixel PX1 may be included in an odd pixel row PRO in the pixel row PR, and the second pixel PX2 may be included in an even pixel row PRE in the pixel row PR.

[0064] The demultiplexer DM may include a first transistor M1 and a second transistor M2 .

[0065] The first transistor M1 may be connected between the output line OL and the first data line DL1, and the on-off operation may be controlled by the first drive signal CD1. The second transistor M2 may be connected between the output line OL and the second data line DL2, and the on-off operation may be controlled by the second drive signal CD2. In one embodiment, for example, when the first drive signal CD1 is supplied, the first transistor M1 may be turned on. Therefore, the data signal of the output line OL may be supplied to the first data line DL1. In such an embodiment, when the second drive signal CD2 is supplied, the second transistor M2 may be turned on. Therefore, the data signal of the output line OL may be supplied to the second data line DL2.

[0066] The first transistor M1 and the second transistor M2 may be turned on independently of each other or in different periods from each other. Therefore, the supply period of the first driving signal CD1 and the supply period of the second driving signal CD2 may not overlap with each other.

[0067] Figure 3 It is a graphic Figure 2 2 is a circuit diagram of an embodiment of a first pixel PX1 and a second pixel PX2 shown in FIG.

[0068] refer to Figure 3 In an embodiment, each of the first pixel PX1 and the second pixel PX2 may include a light emitting device LE and a pixel circuit.

[0069] The anode of the light emitting device LE may be connected to the pixel circuit, and the cathode may be connected to the second power supply VSS. The light emitting device LE may generate light having a predetermined brightness corresponding to the amount of current supplied from the pixel circuit. The voltage of the first power supply VDD supplied to the anode of the light emitting device LE may be greater than the voltage of the second power supply VSS, so that current flows through the light emitting device LE.

[0070] The pixel circuit may control the amount of current flowing from the first power source VDD to the second power source VSS via the light emitting device LE in response to the data signal. Figure 3 As shown in , the pixel circuit may include a first transistor TR1, a second transistor TR2, and a capacitor CAP.

[0071] A first electrode of the first transistor TR1 (or driving transistor) may be connected to a first power source VDD, and a second electrode of the first transistor TR1 may be connected to an anode of the light emitting device LE. A gate electrode of the first transistor TR1 may be connected to a first node N1. The first transistor TR1 may control the amount of current supplied from the first power source VDD to the second power source VSS via the light emitting device LE in response to a voltage stored in the capacitor CAP.

[0072] The second transistor TR2 (or switching transistor) may be connected between the data lines DL1 and DL2 and the first node N1. The second transistor TR2 of the first pixel PX1 may be connected between the first data line DL1 and the first node N1, and the second transistor TR2 of the second pixel PX2 may be connected between the second data line DL2 and the first node N1. The gate electrode of the second transistor TR2 may be connected to the gate line GL. The second transistor TR2 may be turned on when a gate signal is supplied to the gate line GL, thereby providing a data signal to the first node N1. The capacitor CAP may be connected between the first power supply VDD and the first node N1.

[0073] The capacitor CAP may store a voltage corresponding to a data signal.

[0074] The first electrode of each of the transistors TR1 and TR2 may be one of the source electrode and the drain electrode, and the second electrode of each of the transistors TR1 and TR2 may be the other of the source electrode and the drain electrode. In one embodiment, for example, the first electrode of each of the transistors TR1 and TR2 may be the source electrode, and the second electrode of each of the transistors TR1 and TR2 may be the drain electrode.

[0075] Figure 4 is a plan view illustrating a display device according to an embodiment of the present invention. Figure 4 Pictured Figure 2 An embodiment of a first pixel PX1 and a second pixel PX2 is shown in FIG.

[0076] refer to Figure 4 In an embodiment, the first data line DL1 may extend in the first direction DR1 and be connected to the first pixel PX1, and the second data line DL2 may extend in the first direction DR1 and be connected to the second pixel PX2. In such an embodiment, the first pixel PX1 may be connected to the first data line DL1, and the second pixel PX2 may be connected to the second data line DL2.

[0077] In an embodiment, when viewed from a plan view (e.g., a plan view in a thickness direction of the display unit DU), the first data line DL1 and the second data line DL2 may overlap each other. In an embodiment, for example, at least a portion of the first data line DL1 may overlap at least a portion of the second data line DL2. In such an embodiment, in the case where the first data line DL1 and the second data line DL2 overlap each other, the area in which the data lines DL1 and DL2 are formed in a plan view may be reduced. Therefore, the area of ​​the first pixel PX1 and the second pixel PX2 may be increased.

[0078] Figure 5 The diagram is along Figure 4FIG. 5 is a cross-sectional view of an embodiment of a first pixel PX1 taken along line II′ of FIG. Figure 6 The diagram is along Figure 4 FIG. 5 is a cross-sectional view of an embodiment of a second pixel PX2 taken along line II-II′.

[0079] refer to Figure 4 , Figure 5 and Figure 6 , each of the first pixel PX1 and the second pixel PX2 may include a first transistor TR1, a second transistor TR2, a capacitor CAP, and a light emitting device LE arranged on a substrate SUB. The first transistor TR1 may include a first conductive layer 111, a first semiconductor layer 121, a first gate electrode 131, a first source electrode 141, and a first drain electrode 142. The second transistor TR2 may include a second conductive layer 112, a second semiconductor layer 122, a second gate electrode 132, a second source electrode 143, and a second drain electrode 144. The capacitor CAP may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The light emitting device LE may include a pixel electrode 160, a light emitting layer 170, and an opposing electrode 180.

[0080] The substrate SUB may be a transparent insulating substrate. In one embodiment, for example, the substrate SUB may include or be formed of a transparent insulating material such as glass, quartz, plastic, etc.

[0081] In an embodiment, the first conductive layer 111 and the second conductive layer 112 may be arranged on the substrate SUB. The first conductive layer 111 and the second conductive layer 112 may block external light, impurities, etc. from entering the first semiconductor layer 121 and the second semiconductor layer 122 through the substrate SUB. In such an embodiment, when a voltage is applied to the first conductive layer 111 and the second conductive layer 112, the first conductive layer 111 and the second conductive layer 112 may be used as a lower gate electrode of the first transistor TR1 and a lower gate electrode of the second transistor TR2, respectively. In an embodiment, for example, the first conductive layer 111 may be electrically connected to the first source electrode 141 or the first drain electrode 142, and the second conductive layer 112 may be electrically connected to the second gate electrode 132. In such an embodiment, the threshold voltages of the first transistor TR1 and the second transistor TR2 may be adjusted so that the hysteresis characteristics of the first transistor TR1 and the second transistor TR2 may be improved.

[0082] Each of the first conductive layer 111 and the second conductive layer 112 may include or be formed of a conductive material having a relatively low resistance. In one embodiment, for example, each of the first conductive layer 111 and the second conductive layer 112 may include or be formed of a metal such as aluminum (Al) or copper (Cu).

[0083] In an embodiment, the buffer layer BUF may be arranged on the first conductive layer 111 and the second conductive layer 112. The buffer layer BUF may be arranged on the substrate SUB while covering the first conductive layer 111 and the second conductive layer 112. The buffer layer BUF may prevent impurities from entering through the substrate SUB. In such an embodiment, the buffer layer BUF may provide a flat surface on the substrate SUB. The buffer layer BUF may include an inorganic insulating material. In an embodiment, for example, the buffer layer BUF may include at least one selected from silicon nitride, silicon oxide, etc.

[0084] The first semiconductor layer 121 and the second semiconductor layer 122 may be arranged on the buffer layer BUF. The first semiconductor layer 121 and the second semiconductor layer 122 may overlap with the first conductive layer 111 and the second conductive layer 112, respectively. In an embodiment, each of the first semiconductor layer 121 and the second semiconductor layer 122 may include amorphous silicon, polycrystalline silicon, etc. In an alternative embodiment, each of the first semiconductor layer 121 and the second semiconductor layer 122 may include an oxide semiconductor, a metal oxide, etc. Each of the first semiconductor layer 121 and the second semiconductor layer 122 may include a source region, a drain region, and a channel region arranged therebetween. The source region and the drain region may be doped with P-type impurities or N-type impurities, respectively.

[0085] The first insulating layer 101 may be disposed on the first semiconductor layer 121 and the second semiconductor layer 122. The first insulating layer 101 may be disposed on the buffer layer BUF while covering the first semiconductor layer 121 and the second semiconductor layer 122. The first insulating layer 101 may include an inorganic insulating material. In one embodiment, for example, the first insulating layer 101 may include silicon nitride, silicon oxide, or the like.

[0086] The first gate electrode 131, the second gate electrode 132, and the first capacitor electrode CE1 may be arranged on the first insulating layer 101. The first gate electrode 131 may overlap with the channel region of the first semiconductor layer 121, and the second gate electrode 132 may overlap with the channel region of the second semiconductor layer 122. The first capacitor electrode CE1 may be spaced apart from the first gate electrode 131 and the second gate electrode 132. Each of the first gate electrode 131, the second gate electrode 132, and the first capacitor electrode CE1 may include a conductive material having a relatively large resistance or be formed of a conductive material having a relatively large resistance. In one embodiment, for example, each of the first gate electrode 131, the second gate electrode 132, and the first capacitor electrode CE1 may include a metal such as molybdenum (Mo) or be formed of a metal such as molybdenum (Mo).

[0087] The second insulating layer 102 may be disposed on the first gate electrode 131, the second gate electrode 132, and the first capacitor electrode CE1. The second insulating layer 102 may be disposed on the first insulating layer 101 while covering the first gate electrode 131, the second gate electrode 132, and the first capacitor electrode CE1. The second insulating layer 102 may include an inorganic insulating material. In one embodiment, for example, the second insulating layer 102 may include silicon nitride, silicon oxide, or the like.

[0088] The second capacitor electrode CE2 may be disposed on the second insulating layer 102. The second capacitor electrode CE2 may overlap the first capacitor electrode CE1. The second capacitor electrode CE2 may define or form a capacitor CAP together with the first capacitor electrode CE1.

[0089] The second capacitor electrode CE2 may include or be formed of a conductive material having a relatively low resistance. In one embodiment, for example, the second capacitor electrode CE2 may include or be formed of a metal such as aluminum (Al) or copper (Cu).

[0090] The third insulating layer 103 may be disposed on the second capacitor electrode CE2. The third insulating layer 103 may be disposed on the second insulating layer 102 while covering the second capacitor electrode CE2. The third insulating layer 103 may include an inorganic insulating material. In one embodiment, for example, the third insulating layer 103 may include silicon nitride, silicon oxide, or the like.

[0091] The first source electrode 141, the first drain electrode 142, the second source electrode 143, and the second drain electrode 144 may be disposed on the third insulating layer 103. The first source electrode 141 and the first drain electrode 142 may be collectively referred to as first source / drain electrodes 141 / 142, and the second source electrode 143 and the second drain electrode 144 may be collectively referred to as second source / drain electrodes 143 / 144.

[0092] The first source electrode 141 may be connected to the source region of the first semiconductor layer 121 through a contact hole defined or formed in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103, and the first drain electrode 142 may be connected to the drain region of the first semiconductor layer 121 through a contact hole defined or formed in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The second source electrode 143 may be connected to the source region of the second semiconductor layer 122 through contact holes OP1 and OP2 defined or formed in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103, and the second drain electrode 144 may be connected to the drain region of the second semiconductor layer 122 through contact holes defined or formed in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The first source electrode 141 and the first drain electrode 142 may define or form the first transistor TR1 together with the first conductive layer 111, the first semiconductor layer 121, and the first gate electrode 131. The second source electrode 143 and the second drain electrode 144 may define or form a second transistor TR2 together with the second conductive layer 112 , the second semiconductor layer 122 and the second gate electrode 132 .

[0093] Each of the first source electrode 141, the first drain electrode 142, the second source electrode 143, and the second drain electrode 144 may include or be formed of a conductive material having a relatively low resistance. In one embodiment, for example, each of the first source electrode 141, the first drain electrode 142, the second source electrode 143, and the second drain electrode 144 may include or be formed of a metal such as aluminum (Al), titanium (Ti), or copper (Cu).

[0094] The protection layer PVL may be disposed on the first source electrode 141, the first drain electrode 142, the second source electrode 143, and the second drain electrode 144. The protection layer PVL may be disposed on the third insulating layer 103 while covering the first source electrode 141, the first drain electrode 142, the second source electrode 143, and the second drain electrode 144. The protection layer PVL may include an organic insulating material. In one embodiment, for example, the protection layer PVL may include polyimide ("PI") or the like.

[0095] The pixel electrode 160 may be disposed on the protective layer PVL. The pixel electrode 160 may be connected to the first source / drain electrode 141 / 142 through a contact hole defined or formed in the protective layer PVL. Figure 5 and Figure 6As shown in , the pixel electrode 160 can be connected to the first drain electrode 142, but the present invention is not limited to this. In an alternative embodiment, the pixel electrode 160 can also be connected to the first source electrode 141. The pixel electrode 160 may include a conductive material such as a metal, an alloy or a transparent conductive oxide. In one embodiment, for example, the pixel electrode 160 may include silver (Ag), indium tin oxide ("ITO"), etc.

[0096] The pixel defining layer PDL may be arranged on the pixel electrode 160. The pixel defining layer PDL may be arranged on the protective layer PVL while covering the pixel electrode 160. The pixel opening is defined through the pixel defining layer PDL to expose at least a portion of the pixel electrode 160. In an embodiment, the pixel opening may expose a central portion of the pixel electrode 160, and the pixel defining layer PDL may cover a peripheral portion of the pixel electrode 160. The pixel defining layer PDL may include an organic insulating material. In one embodiment, for example, the pixel defining layer PDL may include PI or the like.

[0097] The light emitting layer 170 may be disposed on the pixel electrode 160. The light emitting layer 170 may be disposed on the pixel electrode 160 exposed by the pixel opening. The light emitting layer 170 may include at least one material selected from an organic light emitting material and a quantum dot.

[0098] In an embodiment, the organic light-emitting material may include a low molecular weight organic compound or a high molecular weight organic compound. In an embodiment, for example, the low molecular weight organic compound may include copper phthalocyanine, diphenylbenzidine (N, N'-diphenylbenzidine), trihydroxyquinoline aluminum (tris-(8-hydroxyquinoline) aluminum), etc. The high molecular weight organic compound may include polyethylenedioxythiophene (poly (3,4-ethylenedioxythiophene)), polyaniline, polyparaphenylene vinylene, polyfluorene, etc.

[0099] In an embodiment, the quantum dot may include a II-VI compound, a III-V compound, a IV-VI compound, a IV element, a IV compound, and a combination thereof. In an embodiment, the quantum dot may have a core-shell structure including a core and a shell surrounding the core. The shell may prevent chemical denaturation of the core, thereby serving as a protective layer for maintaining semiconductor properties and a charging layer for imparting electrophoretic properties to the quantum dot.

[0100] The counter electrode 180 may be disposed on the light emitting layer 170. In an embodiment, the counter electrode 180 may also be disposed on the pixel defining layer PDL. The counter electrode 180 may include a conductive material such as a metal, an alloy, or a transparent conductive oxide. In an embodiment, for example, the counter electrode 180 may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc. The pixel electrode 160, the light emitting layer 170, and the counter electrode 180 may collectively define or form a light emitting device LE.

[0101] In an embodiment, the first data line DL1 may be arranged in the same layer as the first source / drain electrode 141 / 142 of the first transistor TR1 and the second source / drain electrode 143 / 144 of the second transistor TR2. Herein, when two elements are arranged in the same layer as each other, the two elements are arranged directly on the same layer as each other. In such an embodiment, the first data line DL1 may be arranged on the third insulating layer 103. In such an embodiment, the first data line DL1 may include the same material as the first source / drain electrode 141 / 142 of the first transistor TR1 and the second source / drain electrode 143 / 144 of the second transistor TR2.

[0102] The first data line DL1 may be integrated with the second source / drain electrode 143 / 144 of the second transistor TR2 of the first pixel PX1. Figure 4 and Figure 5 As shown in FIG. 1 , the first data line DL1 may be integrated with the second source electrode 143 of the second transistor TR2 of the first pixel PX1 , but the present invention is not limited thereto. In an alternative embodiment, the first data line DL1 may be integrated with the second drain electrode 144 of the second transistor TR2 of the first pixel PX1 .

[0103] The first data line DL1 may include a protrusion protruding in the second direction DR2 and connected to the first pixel PX1. The protrusion may be connected to the source region of the second semiconductor layer 122 of the second transistor TR2 of the first pixel PX1 through the contact hole OP1. Therefore, the protrusion may serve as the second source electrode 143 of the second transistor TR2 of the first pixel PX1.

[0104] In an embodiment, the second data line DL2 may be arranged in the same layer as the second capacitor electrode CE2 of the capacitor CAP. In such an embodiment, the second data line DL2 may be arranged on the second insulating layer 102. In such an embodiment, the second data line DL2 may include the same material as the second capacitor electrode CE2 of the capacitor CAP.

[0105] The second data line DL2 may be connected to the second source / drain electrode 143 / 144 of the second transistor TR2 of the second pixel PX2 through a contact hole OP3 defined in the third insulating layer 103. Figure 4 and Figure 6 As shown in the figure, the second data line DL2 can be connected to the second source electrode 143 of the second transistor TR2 of the second pixel PX2 through the contact hole OP3, but the present invention is not limited thereto. In an alternative embodiment, the second data line DL2 can also be connected to the second drain electrode 144 of the second transistor TR2 of the second pixel PX2 through the contact hole OP3.

[0106] The second data line DL2 may include a protrusion protruding in the second direction DR2 and connected to the second pixel PX2. The protrusion may be connected to the second source electrode 143 of the second transistor TR2 of the second pixel PX2 through the contact hole OP3.

[0107] In an embodiment, the second data line DL2 may include a material having a lower resistance than the first gate electrode 131, the second gate electrode 132, and the first capacitor electrode CE1. In an embodiment, for example, the second data line DL2 may include or be formed of aluminum (Al), copper (Cu), etc. In such an embodiment, the second capacitor electrode CE2 and the second data line DL2 may include a material having a relatively low resistance.

[0108] In the case where the second data line DL2 includes or is formed of a material having a relatively large resistance (such as molybdenum (Mo)) included in the first gate electrode 131, the second gate electrode 132, and the first capacitor electrode CE1, the transmission of a data signal through the second data line DL2 may be delayed. However, in an embodiment of the present invention, the second data line DL2 may include a material having a relatively low resistance such as aluminum (Al) or copper (Cu), so that the transmission of the data signal may be effectively prevented from being delayed due to the resistance of the second data line DL2.

[0109] In such an embodiment, the second data line DL2 for high-speed driving of the display device is arranged in the same layer as the second capacitor electrode CE2, so that the second data line DL2 can be formed in the process of forming the second capacitor electrode CE2 without forming an additional conductive layer and an insulating layer. Therefore, the number of mask processes during the manufacture of the display device can be reduced.

[0110] Figure 7 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of an alternative embodiment of the second pixel PX2 taken along line II-II′.

[0111] Except for the position of the second data line DL2, Figure 7 The embodiment of the display device shown in FIG. Figure 5 and Figure 6 The described embodiments of the display device are essentially the same. Figure 7 The same or similar elements shown in FIG. 1 have been used as those described above. Figure 5 and Figure 6 The embodiments shown in the drawings are marked with the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0112] refer to Figure 4 and Figure 7 In an embodiment, the second data line DL2 may be arranged in the same layer as the first conductive layer 111 of the first transistor TR1 and the second conductive layer 112 of the second transistor TR2. In such an embodiment, the second data line DL2 may be arranged on the substrate SUB. In such an embodiment, the second data line DL2 may include the same material as the first conductive layer 111 of the first transistor TR1 and the second conductive layer 112 of the second transistor TR2.

[0113] The second data line DL2 may be connected to the second source / drain electrode 143 / 144 of the second transistor TR2 of the second pixel PX2 through a contact hole OP3 defined in the buffer layer BUF, the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. Figure 4 and Figure 7 As shown in the figure, the second data line DL2 can be connected to the second source electrode 143 of the second transistor TR2 of the second pixel PX2 through the contact hole OP3, but the present invention is not limited thereto. In an alternative embodiment, the second data line DL2 can also be connected to the second drain electrode 144 of the second transistor TR2 of the second pixel PX2 through the contact hole OP3.

[0114] In the process of forming the contact hole OP3 by etching the buffer layer BUF, the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103, there is a risk that the source region and the drain region of the first semiconductor layer 121 and the source region and the drain region of the second semiconductor layer 122 exposed by the contact hole may be etched together. However, when the contact hole is formed using an etching gas such as SF6 or CF4 in which the etching rate relative to the inorganic insulating layer is greater than the etching rate relative to the semiconductor layer, the source region and the drain region of the first semiconductor layer 121 and the source region and the drain region of the second semiconductor layer 122 can be effectively prevented from being damaged in the process of forming the contact hole OP3.

[0115] In an embodiment, the second data line DL2 may include a material having a lower resistance than the first gate electrode 131, the second gate electrode 132, and the first capacitor electrode CE1. In an embodiment, for example, the second data line DL2 may be formed of aluminum (Al), copper (Cu), etc. In such an embodiment, the first conductive layer 111, the second conductive layer 112, and the second data line DL2 may include a material having a relatively low resistance.

[0116] In such an embodiment, the second data line DL2 for high-speed driving of the display device is arranged in the same layer as the first conductive layer 111 and the second conductive layer 112, so that the second data line DL2 can be formed without forming an additional conductive layer and an insulating layer during the process of forming the first conductive layer 111 and the second conductive layer 112. Therefore, the number of mask processes during the manufacture of the display device can be reduced.

[0117] Figure 8 is a plan view illustrating a display device according to an alternative embodiment of the present invention. Fig. 9 The diagram is along Figure 8 FIG. 5 is a cross-sectional view of an embodiment of a second pixel PX2 taken along line III-III′.

[0118] In addition to adding the third data line DL3, Figure 8 and Fig. 9 The embodiment of the display device shown in FIG. Figure 4 , Figure 5 and Figure 6 The described embodiments of the display device are essentially the same. Figure 8 and Fig. 9 The same or similar elements shown in FIG. 1 have been used as those described above. Figure 4 , Figure 5 and Figure 6 The embodiments shown in the drawings are marked with the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0119] refer to Figure 8 In an embodiment, the first data line DL1 may extend in the first direction DR1 and be connected to the first pixel PX1, the second data line DL2 may extend in the first direction DR1 and be connected to the second pixel PX2, and the third data line DL3 may extend in the first direction DR1 and be connected to the second pixel PX2. In such an embodiment, the first pixel PX1 may be connected to the first data line DL1, and the second pixel PX2 may be connected to the second and third data lines DL2 and DL3.

[0120] In an embodiment, when viewed from a plan view, the first data line DL1, the second data line DL2, and the third data line DL3 may overlap with each other. In an embodiment, for example, at least a portion of the first data line DL1 may overlap with at least a portion of the second data line DL2 and at least a portion of the third data line DL3, and at least a portion of the second data line DL2 may overlap with at least a portion of the third data line DL3. In such an embodiment where the first data line DL1, the second data line DL2, and the third data line DL3 overlap with each other, the area in which the data lines DL1, DL2, and DL3 are formed in a plan view may be reduced. Therefore, the area of ​​the first pixel PX1 and the second pixel PX2 may be increased.

[0121] refer to Fig. 9 , the third data line DL3 may be arranged in the same layer as the first conductive layer 111 of the first transistor TR1 and the second conductive layer 112 of the second transistor TR2. In such an embodiment, the third data line DL3 may be arranged on the substrate SUB. In such an embodiment, the third data line DL3 may include the same material as the first conductive layer 111 of the first transistor TR1 and the second conductive layer 112 of the second transistor TR2.

[0122] The third data line DL3 may be connected to the second source / drain electrode 143 / 144 of the second transistor TR2 of the second pixel PX2 through a contact hole OP4 defined in the buffer layer BUF, the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. Figure 8 and Fig. 9 As shown in the figure, the third data line DL3 can be connected to the second source electrode 143 of the second transistor TR2 of the second pixel PX2 through the contact hole OP4, but the present invention is not limited thereto. In an alternative embodiment, the third data line DL3 can also be connected to the second drain electrode 144 of the second transistor TR2 of the second pixel PX2 through the contact hole OP4.

[0123] In an embodiment, the third data line DL3 may include a material having a lower resistance than the first gate electrode 131, the second gate electrode 132, and the first capacitor electrode CE1. In an embodiment, for example, the third data line DL3 may include or be formed of aluminum (Al), copper (Cu), etc. In such an embodiment, the first conductive layer 111, the second conductive layer 112, and the third data line DL3 may include a material having a relatively low resistance.

[0124] In an embodiment, the second data line DL2 and the third data line DL3 are electrically connected to each other, so that the resistance of the data line for transmitting the data signal applied to the second pixel PX2 can be reduced. Therefore, the second data line DL2 and the third data line DL3 can effectively prevent the transmission of the data signal applied to the second pixel PX2 from being delayed.

[0125] Fig.10 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of an alternative embodiment of the first pixel PX1 taken along line II′. Fig.11 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of an alternative embodiment of the second pixel PX2 taken along line II-II′.

[0126] Except for the position of the first capacitor electrode CE1, the position of the second capacitor electrode CE2, and the omission of the third insulating layer 103, Fig.10 and Fig.11 The embodiment of the display device shown in FIG. Figure 7 The described embodiments of the display device are essentially the same. Fig.10 and Fig.11 The same or similar elements shown in FIG. 1 have been used as those described above. Figure 5 and Figure 7 The embodiments shown in the drawings are marked with the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0127] refer to Figure 4 , Fig.10 and Fig.11 In an embodiment, the first conductive layer 111 , the second conductive layer 112 , and the first capacitor electrode CE1 may be disposed on the substrate SUB. The first capacitor electrode CE1 may include the same material as the first conductive layer 111 and the second conductive layer 112 .

[0128] The buffer layer BUF may be disposed on the first conductive layer 111, the second conductive layer 112, and the first capacitor electrode CE1. The buffer layer BUF may be disposed on the substrate SUB while covering the first conductive layer 111, the second conductive layer 112, and the first capacitor electrode CE1.

[0129] The first gate electrode 131, the second gate electrode 132, and the second capacitor electrode CE2 may be disposed on the first insulating layer 101. The second capacitor electrode CE2 may include the same material as the first gate electrode 131 and the second gate electrode 132. The second insulating layer 102 may be disposed on the first gate electrode 131, the second gate electrode 132, and the second capacitor electrode CE2. The second insulating layer 102 may be disposed on the first insulating layer 101 while covering the first gate electrode 131, the second gate electrode 132, and the second capacitor electrode CE2.

[0130] The first source electrode 141 , the first drain electrode 142 , the second source electrode 143 , and the second drain electrode 144 may be disposed on the second insulating layer 102 .

[0131] In such an embodiment, the first capacitor electrode CE1 is arranged in the same layer as the first conductive layer 111 and the second conductive layer 112, and the second capacitor electrode CE2 is arranged in the same layer as the first gate electrode 131 and the second gate electrode 132, so that the capacitor electrode of the capacitor CAP can be formed without forming an additional conductive layer and an insulating layer during the process of forming the first conductive layer 111 and the second conductive layer 112 or the first gate electrode 131 and the second gate electrode 132. Therefore, the number of mask processes during the manufacture of the display device can be reduced.

[0132] Fig.12 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of another alternative embodiment of the second pixel PX2 taken along line II-II′.

[0133] Except for the position of the second capacitor electrode CE2, Fig.12 The embodiment of the display device shown in FIG. Fig.10 and Fig.11 The described embodiments of the display device are essentially the same. Fig.12 The same or similar elements shown in FIG. 1 have been used as those described above. Fig.10 and Fig.11 The embodiments shown in the drawings are marked with the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0134] refer to Fig.12 In an embodiment, the first semiconductor layer 121, the second semiconductor layer 122, and the second capacitor electrode CE2 may be arranged on the buffer layer BUF. The second capacitor electrode CE2 may include the same material as the first semiconductor layer 121 and the second semiconductor layer 122. The second capacitor electrode CE2 may be doped with P-type or N-type impurities, such as the source region and the drain region of each of the first semiconductor layer 121 and the second semiconductor layer 122. Therefore, the second capacitor electrode CE2 may have conductivity.

[0135] The first insulating layer 101 may be disposed on the first semiconductor layer 121, the second semiconductor layer 122, and the second capacitor electrode CE2. The first insulating layer 101 may be disposed on the buffer layer BUF while covering the first semiconductor layer 121, the second semiconductor layer 122, and the second capacitor electrode CE2.

[0136] The first gate electrode 131 and the second gate electrode 132 may be disposed on the first insulating layer 101 .

[0137] In such an embodiment, the second capacitor electrode CE2 is arranged in the same layer as the first semiconductor layer 121 and the second semiconductor layer 122, and the capacitor electrode of the capacitor CAP can be formed without forming an additional conductive layer and an insulating layer during the process of forming the first semiconductor layer 121 and the second semiconductor layer 122. Therefore, the number of mask processes during the manufacture of the display device can be reduced.

[0138] Fig.13 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of another alternative embodiment of the first pixel PX1 taken along line II′. Fig.14 The diagram is along Figure 4 FIG. 1 is a cross-sectional view of another alternative embodiment of the second pixel PX2 taken along line II-II′.

[0139] In addition to the omission of the first conductive layer 111 and the second conductive layer 112, Fig.13 and Fig.14 The embodiment of the display device shown in FIG. Figure 5 and Figure 6 The described embodiments of the display device are essentially the same. Fig.13 and Fig.14 The same or similar elements shown in FIG. 1 have been used as those described above. Figure 5 and Figure 6 The embodiments shown in the drawings are marked with the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0140] refer to Figure 4 , Fig.13 and Fig.14 In an embodiment, each of the first pixel PX1 and the second pixel PX2 may include a first transistor TR1, a second transistor TR2, a capacitor CAP, and a light emitting device LE arranged on a substrate SUB. The first transistor TR1 may include a first semiconductor layer 121, a first gate electrode 131, a first source electrode 141, and a first drain electrode 142. The second transistor TR2 may include a second semiconductor layer 122, a second gate electrode 132, a second source electrode 143, and a second drain electrode 144.

[0141] In such an embodiment, the first conductive layer 111 and the second conductive layer 112 are omitted, and the formation of a conductive layer for forming a lower gate electrode of each of the first transistor TR1 and the second transistor TR2 can be omitted. Therefore, the number of mask processes during the manufacture of the display device can be reduced. In such an embodiment, when the first conductive layer 111 and the second conductive layer 112 are omitted, the buffer layer BUF configured to insulate the first semiconductor layer 121 and the second semiconductor layer 122 from the first conductive layer 111 and the second conductive layer 112 can be omitted.

[0142] Embodiments of the display device described herein may be applied to display devices included in computers, laptop computers, mobile phones, smart phones, smart tablets, portable media players ("PMP"), personal digital assistants ("PDA"), MP3 players, etc.

[0143] The present invention should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0144] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, comprising: First pixel; a second pixel adjacent to the first pixel in a predetermined direction; a first data line extending in the predetermined direction and connected to the first pixel; as well as A second data line extending in the predetermined direction and connected to the second pixel, wherein Each of the first pixel and the second pixel includes: A transistor comprising a conductive layer, a semiconductor layer arranged on the conductive layer, a gate electrode arranged on the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer; a capacitor including a first capacitor electrode arranged in the same layer as the gate electrode and a second capacitor electrode arranged on the first capacitor electrode; and a light emitting device arranged on the transistor and the capacitor, and wherein The first data line is arranged in the same layer as the source electrode and the drain electrode, and The second data line is arranged in the same layer as the conductive layer and one of the second capacitor electrodes, and The first data line and the second data line are arranged in different layers.

2. The display device according to claim 1, wherein: The first data line is formed integrally with the source electrode or the drain electrode of the transistor of the first pixel.

3. The display device according to claim 1, wherein: The first data line and the second data line overlap each other when viewed in a plan view.

4. The display device according to claim 1, further comprising: a buffer layer disposed between the conductive layer and the semiconductor layer; a first insulating layer disposed between the semiconductor layer and the gate electrode; a second insulating layer disposed between the first capacitor electrode and the second capacitor electrode; as well as A third insulating layer is disposed between the second capacitor electrode and the source and drain electrodes.

5. The display device according to claim 4, wherein: The second data line and the second capacitor electrode are arranged in the same layer, and The second data line is connected to the source electrode or the drain electrode of the transistor of the second pixel through a contact hole defined through the third insulating layer.

6. The display device according to claim 4, wherein: The second data line is arranged in the same layer as the conductive layer, and The second data line is connected to the source electrode or the drain electrode of the transistor of the second pixel through a contact hole defined through the buffer layer, the first insulating layer, the second insulating layer, and the third insulating layer.

7. The display device according to claim 4, further comprising: a third data line extending in the predetermined direction and connected to the second pixel, in, The second data line and the second capacitor electrode are arranged in the same layer, and The third data line and the conductive layer are arranged in the same layer.

8. The display device according to claim 7, wherein: The first data line, the second data line, and the third data line overlap each other when viewed in a plan view.

9. The display device according to claim 7, wherein: The second data line is connected to the source electrode or the drain electrode of the transistor of the second pixel through a contact hole defined through the third insulating layer, and The third data line is connected to the source electrode or the drain electrode of the transistor of the second pixel through a contact hole defined through the buffer layer, the first insulating layer, the second insulating layer, and the third insulating layer.

10. The display device according to claim 1, wherein: The second data line includes a material having a resistance smaller than a resistance of the gate electrode.

11. The display device according to claim 1, further comprising: a plurality of pixel rows arranged along the predetermined direction, in, The first pixel is included in an odd-numbered pixel row among the plurality of pixel rows, and The second pixels are included in even-numbered pixel rows among the plurality of pixel rows.

12. The display device according to claim 1, wherein: The semiconductor layer includes at least one material selected from amorphous silicon, polycrystalline silicon, and metal oxide.

13. A display device, comprising: First pixel; a second pixel adjacent to the first pixel in a predetermined direction; a first data line extending in the predetermined direction and connected to the first pixel; as well as a second data line extending in the predetermined direction and connected to the second pixel, in, Each of the first pixel and the second pixel includes: a transistor including a conductive layer, a semiconductor layer disposed on the conductive layer, a gate electrode disposed on the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer; and a light emitting device disposed on the transistor, in, The first data line is arranged in the same layer as the source electrode and the drain electrode, and The second data line and the conductive layer are arranged in the same layer.

14. The display device according to claim 13, wherein: Each of the first pixel and the second pixel further includes a capacitor including a first capacitor electrode arranged in the same layer as the conductive layer and a second capacitor electrode arranged on the first capacitor electrode.

15. A display device comprising: First pixel; a second pixel adjacent to the first pixel in a predetermined direction; a first data line extending in the predetermined direction and connected to the first pixel; as well as a second data line extending in the predetermined direction and connected to the second pixel, in, Each of the first pixel and the second pixel includes: A transistor including a semiconductor layer, a gate electrode arranged on the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer; a capacitor including a first capacitor electrode arranged in the same layer as the gate electrode and a second capacitor electrode arranged on the first capacitor electrode; and a light emitting device disposed on the transistor and the capacitor, and in, The first data line is arranged in the same layer as the source electrode and the drain electrode, and The second data line and the second capacitor electrode are arranged in the same layer, and The first data line and the second data line are arranged in different layers.

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