Input circuit with wide range input voltage compatibility

Abstract

An input circuit having wide range input voltage compatibility is disclosed. The input circuit (400) includes an input stage having input nodes (VIN+, VIN-) and a direct current (DC) amplifier (402) coupled to the input nodes. The input circuit (400) also includes an alternating current (AC) amplifier (200) coupled to output nodes (Vinp, Vinn) of the DC amplifier 402. The input circuit further includes capacitors (C1p, C1n) coupled between the input nodes (VIN+, VIN-) and the output nodes (Vinp, Vinn) of the DC amplifier. The input circuit (400) also includes a voltage divider coupled to the DC amplifier (402) and the AC amplifier. The voltage divider includes first resistors (R2p, R2n) associated with the DC amplifier (402) and second resistors (R1p, R1n) associated with the AC amplifier (200), wherein the first resistors (R2p, R2n) are greater than the second resistors (R1p, R1n).

Description

Background Technology

[0001] In electronic systems, different components (circuits) have different voltage or current requirements. To address this difference, input stages can be used to regulate the signal so that it can be input to the next stage or component. For example, buffer circuits are used between mismatched components. A buffer is a unity-gain or higher amplifier configured to provide sufficient drive capability to pass a signal or data bit all the way to the next stage or component. Voltage buffers increase the available current for low-impedance inputs while maintaining the voltage level. Current buffers maintain a constant current while driving high-impedance inputs at higher voltage levels.

[0002] The performance targets for clock buffer input stages are increasingly demanding in terms of low propagation delay (tdp), supported frequency range, input clock signal standards (such as LVPECL, LVDS, HSDS, CML, etc.), and phase noise performance. Migrating to faster technologies (e.g., lower technology nodes) helps improve propagation delay, phase noise, and operating frequency. On the other hand, supply voltage scaling often imposes limitations on supported input clock standards. As an example, in the case of the LVPECL standard, voltage levels are defined relative to the input supply voltage (e.g., a high voltage level of VDD-0.8V and a low voltage level of VDD-1.8V). If the minimum VDD of the LVPECL standard is 2.5V, and the VDD of the clock buffer input stage components using 130nm or lower technology is 1.2V or lower, then the LVPECL voltage level may corrupt components in the clock buffer input stage. Efforts to improve buffering are underway. Summary of the Invention

[0003] According to at least some examples of this disclosure, the input circuitry includes an input stage having a first input node and a direct current (DC) amplifier coupled to the first input node. The input circuitry also includes an alternating current (AC) amplifier having a second input node coupled to the first output node of the DC amplifier. The input circuitry also includes a capacitor coupled between the first input node and the first output node. The input circuitry also includes a voltage divider between the first output node and the second input node. The voltage divider includes a first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, wherein the first resistor is larger than the second resistor.

[0004] According to at least some examples of this disclosure, the input circuitry includes a clock buffer circuit. The clock buffer circuitry includes a complementary metal-oxide-semiconductor (CMOS) input stage having a first input node and a DC amplifier coupled to the first input node. The CMOS input stage also includes an AC amplifier having a second input node coupled to the first output node of the DC amplifier. The CMOS input stage also includes a capacitor coupled between the first input node and the first output node, wherein the CMOS input stage is configured to receive a clock voltage at the first input node. The clock voltage is higher than the input voltage supply of the DC amplifier and the AC amplifier.

[0005] According to at least some examples of this disclosure, a method for signal input includes receiving a differential input signal having a DC signal component and an AC signal component. The method further includes performing a first amplification associated with the DC signal component of the differential input signal. The method also includes performing a second amplification associated with the AC signal component of the differential input signal, wherein the second amplification is greater than the first amplification. Attached Figure Description

[0006] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0007] Figure 1 This is a block diagram illustrating a system based on some examples;

[0008] Figure 2 This is a schematic diagram showing an AC amplifier circuit according to some examples;

[0009] Figure 3 This is a schematic diagram illustrating a DC preamplifier circuit according to some examples;

[0010] Figure 4 This is a schematic diagram illustrating a buffer circuit according to some examples;

[0011] Figure 5 This is a schematic diagram illustrating an input common-mode (ICM) amplifier circuit according to some examples;

[0012] Figure 6 This is a schematic diagram illustrating an ICM amplifier circuit for differential signals, based on some examples;

[0013] Figure 7 This is a schematic diagram showing a gain amplifier circuit according to some examples; and

[0014] Figure 8 This is a flowchart illustrating buffering methods based on some examples. Detailed Implementation

[0015] This document discloses an input circuit topology known as a buffer circuit topology, whose input stage includes a DC amplifier, an AC amplifier, and a voltage divider. The voltage divider includes a first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, wherein the first resistor is larger than the second resistor. Using the voltage divider, the input common-mode voltage can be greater than the input supply voltage of the buffer circuit components (circuit) (e.g., an inverter component) without damaging these buffer circuit components. In some examples, the DC amplifier receives the input common-mode voltage, while the AC amplifier receives a reduced input common-mode voltage via the DC amplifier. Another description applicable to the buffer circuit topology described herein is that the DC amplifier is "weak" such that it does not overwrite the AC component of the input signal.

[0016] In some examples, the DC amplifier includes a preamplifier circuit with a frequency-compensated voltage divider configured to scale the input common-mode voltage. Several design goals are considered using the buffer circuit topology described herein. One goal is compatibility with different input common-mode voltages. Another goal is that the input common-mode voltage can be higher than the input supply voltage of the buffer circuit. Another goal is compatibility with different differential inputs with swing voltages. Another goal is to use a frequency-compensated voltage divider to enable the DC amplifier to have a wide input frequency range (e.g., up to 10 GHz). Another goal is to support frequencies from DC (single pulse) to the GHz range. Another goal is to connect the DC amplifier and AC amplifier in a manner that does not degrade the performance of the AC amplifier, and vice versa. Another goal is to avoid external decoupling capacitors. Another goal is to avoid reducing the input signal duty cycle of differential input signals. Another goal is compatibility with single-ended inputs. Another goal is to use complementary metal-oxide-semiconductor (CMOS) components, which are smaller, cheaper, and easier to migrate to other technology nodes compared to bipolar transistor components. Other goals include fast response (low propagation delay), low jitter (phase noise), low power, and small circuit placement area. To better understand, the various buffer circuit options and related scenarios are described using the following diagram.

[0017] Figure 1 This is a block diagram illustrating a system 100 according to some examples. Figure 1 In this context, system 100 represents a consumer product, an integrated circuit or chip, a printed circuit board (PCB) having integrated circuits and / or discrete components, and / or another electrical device. As shown, system 100 includes a phase-locked loop (PLL) 102 configured to receive a frequency input signal 111 and a feedback signal 112. The output of PLL 102 is a signal 114, the frequency of which is based on the difference between the VIN signal 111 and the feedback signal 112. Figure 1In one example, signal 114 is provided to clock buffer circuit 104, which in turn provides signal 116 (a buffered version of signal 114) to clock driver 108. In some examples, clock buffer circuit 104 is a standalone integrated circuit (IC) or chip. In other examples, clock buffer circuit 104 is a standalone integrated circuit (IC) or chip combined with other components (e.g., PLL 102, clock driver 108, and / or one or more other components 110). Clock driver 108 is configured to provide multiple clock signals 118 to other components 110. Without limitation, other components 110 may correspond to receiver components, demodulation components, processors, or other components.

[0018] As shown in the figure, the clock buffer circuit 104 includes an input stage 106 with various features. More specifically, in some examples, the input stage 106 includes features such as CMOS components and a DC amplifier. The input stage 106 also includes features such as an AC amplifier and a voltage divider, where the voltage divider reduces the input-side voltage of the AC amplifier. Several design goals are considered using the clock buffer circuit 104. One goal is compatibility with different input common-mode voltages. Another goal is that the input common-mode voltage can be higher than the input supply voltage of the clock buffer circuit 104. Another goal is compatibility with different differential inputs with swing voltages. Another goal is to use a frequency-compensated voltage divider to enable the DC amplifier to have a wide input frequency range (e.g., up to 10 GHz). Another goal is to support frequencies from DC (single pulse) to the GHz range. Another goal is to connect the DC amplifier and the AC amplifier in a manner that does not degrade the performance of the AC amplifier, and vice versa. Another goal is to avoid external decoupling capacitors. Another goal is to avoid reducing the input signal duty cycle of the differential input signals. Another goal is compatibility with single-ended inputs. Another goal is to use CMOS components. Other objectives include fast response (low propagation delay), low jitter (phase noise), low power, and small circuitry settling area.

[0019] Figure 2This is a schematic diagram illustrating an AC amplifier circuit 200 according to some examples. As shown, the AC amplifier circuit 200 includes a first differential input (VIN+) node and a second or complementary differential input (VIN-) node. The VIN+ node is coupled to the first plate of a capacitor (C1p), where the second plate of C1p is coupled to the first terminal of a resistor (R1p). Simultaneously, the VIN- node is coupled to the first plate of a complementary capacitor (C1n), where the second plate of C1n is coupled to the first terminal of a complementary resistor (R1n). As shown, the second terminals of R1p and R1n are coupled to each other at node 202. Furthermore, node 202 is coupled between two transistors M0 and M1, where the first current terminal of M0 is coupled to an input supply voltage (VDD) node. The control terminal and second current terminal of M0 are coupled to node 202. As shown, the control terminal and first current terminal of M1 are coupled to node 202. Additionally, the second current terminal of M1 is coupled to a ground node.

[0020] exist Figure 2 In the example, the second plate of C1p and the first end of R1p are coupled to an internal node (vinp). In operation, the signal at vinn is provided to the first differential output (OUT+) node via a first inverter (I1) and a second inverter (I2). Furthermore, the second plate of C1n and the first end of R1n are coupled to another internal node (vinn). In operation, the signal at the vinn node is provided to the second or complementary differential output (OUT-) node via a third inverter (I3) and a fourth inverter (I4).

[0021] In some examples, the inverters (e.g., I1-I4) of the AC amplifier circuit 200 are biased for maximum gain, with the DC point set by M0 and M1 (e.g., diode-connected transistors). The AC amplifier 200 can support any input common-mode voltage standard because C1p and C1n remove the DC voltage of the input signal. During operation, at each rising and falling edge, the voltage difference (Δv) associated with nodes vimp and vinn will change polarity (e.g., Δv > 0V on the rising edge; Δv < 0V on the falling edge), triggering inverters I1-I4 so that the amplified input signal propagates rapidly to the OUT+ and OUT- nodes. Frequencies below the bandwidth of the filters (associated with R1p, R1, C1p, C1n) can cause inappropriate operation of the AC amplifier circuit 200. If the filter's time constant is much smaller than the input signal period, the voltages at nodes vimp and vinn will become equal, and the AC amplifier circuit 200 will begin to malfunction. Even without input signal switching, any small disturbance or noise at vinp and vinn can cause switching of inverters I1-I4. According to various aspects of this disclosure, a DC amplifier is used to prevent the voltages at vinp and vinn from becoming equal. Figure 3 This is a schematic diagram illustrating a DC preamplifier circuit 300 according to some examples. The DC preamplifier circuit 300 (e.g., with some modifications) can be added to the AC amplifier circuit 200 to prevent the voltages at vinp and vinn from becoming equal.

[0022] Figure 4 A schematic diagram of a buffer circuit 400 according to some examples is shown. As shown, the buffer circuit 400 includes... Figure 2 The components of the AC amplifier circuit 200 introduced in the text. More specifically, Figure 4 Showing the previous target Figure 2 The AC amplifier circuit 200 describes the VIN+ node, VIN- node, C1p, C1n, vinp, vinn, M0, M1, R1p, R1n, I1-I4, OUT+ node, and OUT- node. Additionally, the buffer circuit 400 includes a DC amplifier circuit 402 coupled to the VIN+ and VIN- nodes, as well as the vinp and vinn nodes.

[0023] exist Figure 4In the example, DC amplifier circuit 402 includes a DC preamplifier stage 404 with input nodes coupled to VIN+ and VIN- nodes. The output node of DC preamplifier stage 404 is coupled to gain stages 406 and 410. The output of gain stage 406 is coupled to the input node of inverter 408. Additionally, the output node of inverter 408 is coupled to the first terminal of resistor (R2p), where the second terminal of R2p is coupled to vinn. Meanwhile, the output of gain stage 410 is coupled to the input node of inverter 412. The output node of inverter 412 is coupled to the first terminal of resistor (R2n), where the second terminal of R2n is coupled to vinn.

[0024] In operation, inverters 408 and 412 are used as drivers for resistors R2p and R2n. The use of R2p and R2n results in a voltage divider based on R1p, R1n, R2p, and R2n, making the DC amplifier circuit 402 weaker than the AC amplifier. More specifically, R1p, R1n, R2p, and R2n are used to divide the output signal from inverters 408 and 412. If inverters 408 and 412 were directly connected to vinp and vin, the DC amplifier circuit 402 would suppress the AC components of the signal from the VIN+ and VIN- nodes through capacitors C1p and C1n. Therefore, without R2p and R2n, the AC signal components from the VIN+ and VIN- nodes would be suppressed by inverters 408 and 412. In this case, inverters 408 and 412 would act as a voltage source with low output impedance (a near-ideal voltage source), and the AC amplifier would be ineffective. The addition of R2p and R2n weakens the effect of DC amplifier circuit 402 because vinp and vin are not strongly driven by ideal voltage sources. Figure 4 In the example buffer circuit 400, the total signal at vinp and vinn is the superposition of the AC component after passing through C1p and C1n and the DC component after passing through the DC amplifier circuit 402. Using the DC amplifier circuit 402, even at extremely low frequencies, the voltages at vinp and vinn will never be equal (e.g., Δv ≠ 0V), which is designed to prevent false triggering. Simultaneously, the AC component will trigger inverters I1-I4, and the amplified signal will propagate very quickly to the OUT+ and OUT- nodes.

[0025] In some examples, the ratio of resistors R2 (R2p, R2n) to resistors R1 (R1p, R1n) is predetermined to improve performance. As an example, if resistor R1 is larger than resistor R2 (e.g., R1 = 5 * R2), for low input voltage swings (e.g., below 100mV), Δv will change polarity slowly because the DC voltage component is greater than the AC voltage component at vinp / vinn. In this example, the switching speed will depend primarily on the speed of the DC amplifier circuit 402, which degrades performance. On the other hand, if resistor R1 is smaller than resistor R2 (e.g., 5 * R1 = R2), Δv will change polarity more quickly because the DC voltage component is smaller than the AC voltage component at vinp / vinn. Therefore, in some examples, each resistor R2 is chosen to be larger than each resistor R1. On the other hand, resistor R2 cannot be too large compared to resistor R1, as this would cause Δv to approach 0V, increasing the circuit's sensitivity to interference. In some examples, R2 = 5 * R1 is used in the buffer circuit 400 as a trade-off between speed and interference sensitivity. In other examples, the ratio of R2 to R1 varies (e.g., R2 = 1.5 * R1, R2 = 2 * R1, R2 = 3 * R1, etc.).

[0026] Figure 5 This is a schematic diagram illustrating an input common-mode (ICM) amplifier circuit 500 according to some examples. In some examples, the ICM amplifier circuit 500 is... Figure 4 This is a portion of the DC preamplifier circuit 404 shown. As shown, the ICM amplifier circuit 500 is formed by transistors M1p-M4p and resistors R3p-R6p. Figure 5 In the example, the other transistors Mcs1 and MCs2 are current source transistors used for amplification.

[0027] When the input signal is a differential signal, two ICM amplifier circuits can be used in the DC preamplifier circuit 404. Figure 6 This is a schematic diagram illustrating an ICM amplifier circuit 600 for differential signals according to some examples, wherein an ICM amplifier circuit 500 is used in the ICM amplifier circuit 600. Figure 5 and Figure 6 In the example, resistors R3p-R6p improve the input common-mode range of the ICM amplifier. Figure 3Unlike the DC amplifier circuit 300, each ICM amplifier circuit 500 has only 6 transistors and 4 resistors. The strategy for the ICM amplifier circuit 500 is to have a fast circuit (e.g., with low propagation delay where performance is not critical). Reducing the number of transistors used in the ICM amplifier circuit 500 compared to the DC amplifier circuit 300 results in the ICM amplifier circuit 500 being faster (with less parasitic capacitance) and simpler, where the same function is achieved by adding R3p, R3n, R4p, and R4n (for compatibility with high input common-mode voltage). These resistors prevent the current path from VDD to ground from being interrupted. By properly designing the dimensions of the R3p, R3n, R4p, and R4n resistors, the unit will effectively provide amplification of the input signal. Compared to the DC amplifier circuit 300, Figure 5 and Figure 6 R3p, R4p, R5p, R6p and / or R3n, R4n, R5n, R6n will have a higher ratio than Figure 3 The resistors used in the DC amplifier circuit 300 have higher values. Furthermore, Figure 5 and Figure 6 The transistors M1p-M4p and / or M1n-M4n used in ICM circuits 500 and 600 can be smaller than the transistors in DC amplifier circuit 300. Figure 5 and Figure 6 The gain of the ICM amplifier circuits 500 and 600 depends on the values ​​of R3p, R4p, R5p, R6p and / or R3n, R4n, R5n, R6n, and the size of the transistors (M1p-M4p and / or M1n-M4n), where larger transistors and resistors result in higher gain. In some examples, the ICM amplifier circuit 500 has approximately the same area as the DC amplifier circuit 300 but provides faster performance.

[0028] Using ICM amplifier circuits 500 or 600, DC preamplifier circuit 404 is compatible with input voltages higher than VDD. In some examples, a frequency-compensated voltage divider can be used to scale the input voltage. ICM amplifier circuit 600 shows an example of a frequency-compensated voltage divider. More specifically, two resistors (R7p, R8p) and one capacitor (Ccp1) form a frequency-compensated voltage divider at the VIN+ node. Meanwhile, two other resistors (R7n, R8n) and another capacitor (Ccp2) form a frequency-compensated voltage divider at the VIN- node. Figure 6 As shown, R7p and Ccp1 are coupled in parallel between the VIN+ node and node 602. Additionally, R8p is coupled between node 602 and the ground node. Furthermore, R7n and Ccp2 are coupled in parallel between the VIN- node and node 604. Additionally, R8n is coupled between node 604 and the ground node.

[0029] In some examples, the values ​​of R7p, R7n, R8p, and R8n should be high to avoid additional loading from the input signal source (preventing additional current from being drawn from the signal source). In one example, R7p = R7n = R8p = R8n = 100kΩ. The parasitic capacitances of the input transistors M1p-M4p and / or M1n-M4n, combined with the large values ​​of R7p, R7n, R8p, and R8n, create a low-pass filter, which can limit the high-frequency range. To extend the operating range, Ccp1 and Ccp2 are included, where the values ​​of Ccp1 and Ccp2 can be related to the values ​​of the parasitic capacitances. Using a frequency-compensated voltage divider, the impedance formed by the parasitic capacitances M1p-M4p and / or M1n-M4n together with R8p and R8n is equal to the impedance of R7p and R7n in parallel with Ccp1 and Ccp2. In this scenario, the input signal is divided by 2 (R7 = R8) without any filtering effect (e.g., in the case of a low-pass filter, the amplitude will not decrease by 20 dB / dec). In one example, if the maximum VDD of the buffer circuit 400 is 1.65V, the input signal (e.g., common-mode voltage) can be as high as 3.3V. This means that the input stage of the buffer circuit 400 can support VDD values ​​higher than 3.3V, such as those of LVPECL standards (in the case of LVPECL, the maximum input voltage is VDD - 0.8V). Although the input signal is divided by 2, the gain of the DC preamplifier circuit 404 is approximately 8 times, which is sufficient to drive the gain stages 406 and 410. The task of the gain stages 406 and 410 is to amplify the signal from rail to rail (VDD to GND).

[0030] Figure 7 This is a schematic diagram illustrating a gain amplifier circuit 700 suitable for gain stages 406 and 410 according to some examples. As shown, the gain amplifier circuit 700 includes an arrangement of transistors (M8-M11, Mcs3, and Mcs4). More specifically, M8 and M10 have control terminals coupled to the VIN+ node, while M9 and M11 have control terminals coupled to the VIN- node. The first current terminal of M8, the second current terminal of M10, and the control terminals of Mcs3 and Mcs4 are coupled together (e.g., at node 702). Furthermore, the first current terminals of M10 and M11 are coupled to the second current terminal of Mcs4. Additionally, the first current terminal of Mcs4 is coupled to the VDD node. Additionally, the second current terminals of M8 and M9 are coupled to the first current terminal of Mcs3. Additionally, the second current terminal of Mcs3 is coupled to the ground node. Between the second current terminal of M11 and the first current terminal of M9 is a differential output (OUTP) node. In operation, the gain amplifier circuit 700 is configured to amplify the input signals corresponding to VIN+ and VIN- from rail to rail (VDD to GND).

[0031] In some examples, buffer circuits (e.g., Figure 1 The clock buffer circuit 104 or buffer circuit 400) includes an input stage (e.g., Figure 1 Input level 106), which has input nodes (e.g., Figure 4 The input stage also includes an AC amplifier (e.g., VIN+ or VIN-) coupled to the output node (vinp or vinn) of the DC amplifier and a DC amplifier (e.g., DC amplifier circuit 402). Figure 2 The AC amplifier circuit 200 is described. The input stage also includes a capacitor (C1p or C1n) coupled between the input node (e.g., VIN+ or VIN-) and the output node (vinp or vinn) of the DC amplifier. The input stage also includes a voltage divider coupled to both the DC amplifier and the AC amplifier. The voltage divider includes a first resistor (R2p or R2n) associated with the DC amplifier and a second resistor (R1p or R1n) associated with the AC amplifier, wherein the first resistor is larger than the second resistor.

[0032] In some examples, the DC amplifier (e.g., DC amplifier 402) includes an ICM amplifier (e.g., VIN+ or VIN-) coupled to the input node (e.g., VIN+ or VIN-). Figure 5 ICM amplifier circuit 500 or Figure 6 The ICM amplifier circuit 600). The DC amplifier also includes a gain amplifier coupled to the output node of the ICM amplifier (e.g., Figure 7 The gain amplifier circuit 700). The DC amplifier also includes an inverter (e.g., inverter 408 or 412) coupled to the output node of the gain amplifier. In some examples, the ICM amplifier includes a frequency-compensated voltage divider (see, for example, see...). Figure 6 (R1p, R2p, Ccp1, R1n, R2n, Cccp2 in the diagram). In some examples, the frequency-compensated voltage divider includes a third resistor (e.g., Figure 6 R1p or R1n in the middle), the fourth resistor (e.g. Figure 6 R2p or R2n in the capacitor ( Figure 6 In the case of Ccp1 or Ccp2), the first terminal of the fourth resistor (e.g., R2p or R2n) and the first plate of the second capacitor (e.g., Ccp1 or Ccp2) are coupled to the input node (e.g., VIN+ or VIN-). Additionally, the fourth resistor (e.g., Figure 6 The second terminal of R2p or R2n and the second capacitor ( Figure 6 The second plate of Ccp1 or Ccp2 in the resistor is coupled to an internal node (e.g., vinp or vinn). The third resistor (e.g., Figure 6The first end of R1p or R1n in the resistor is coupled to an internal node (e.g., vinp or vinn), and a third resistor (e.g., ...) is also coupled to an internal node (e.g., vinp or vinn). Figure 6 The second end of R1p or R1n is coupled to the ground node.

[0033] In some examples, the input level (e.g., Figure 1 The input stage 106 is configured to receive a clock voltage at an input node (e.g., VIN+ or VIN-), where the clock voltage is higher than the input voltage supply (e.g., VDD) used for the DC and AC amplifiers. In some examples, the first resistor (e.g., R2p or R2n) is at least five times larger than the second resistor (R1p or R1n). Furthermore, the DC and AC amplifiers include CMOS components. When the input stage is a differential input stage, it includes complementary input nodes (e.g., VIN-) and complementary output nodes (e.g., vinn) of the DC amplifier. The differential input stage also includes complementary capacitors (e.g., C1n) between the complementary input nodes (VIN-) and complementary output nodes (vinn) of the DC amplifier. The differential input stage also includes complementary voltage divider resistors coupled to the AC and DC amplifiers. These complementary voltage divider resistors include a first complementary resistor (e.g., R2n) associated with the DC amplifier and a second complementary resistor (e.g., R1n) associated with the AC amplifier, where the first complementary resistor is larger than the second complementary resistor.

[0034] Figure 8 This is a flowchart illustrating a buffering method 800 according to some examples. In different examples, the buffering method 800 consists of a buffer circuit (e.g., Figure 4 The buffer circuit 400) or clock buffer circuit (e.g., Figure 1 The clock buffer circuit 104 in the PLL or other input stage circuitry is used to perform this. In one example, the buffer method 800 is used in conjunction with the PLL's output signal, allowing the PLL output to be used to generate multiple signals.

[0035] As shown in the figure, buffering method 800 includes receiving a differential input signal having DC and AC signal components at block 802. At block 804, a first amplification associated with the DC signal component of the differential input signal is performed. At block 806, a second amplification associated with the AC signal component of the differential input signal is performed, wherein the second amplification is greater than the first amplification. In some examples, the operation of blocks 804 and 806 involves a voltage divider or frequency-compensated voltage divider as described herein (e.g., see...). Figure 4 The buffer circuit 400 contains R1p, R1n, R2p, and R2n; or Figure 6The ICM circuit 600 contains R7p, R8p, R7n, and R8n. The result of buffering method 800 is that even at very low frequencies, the voltages at vinp and vin will not be equal. Additionally, the buffer circuit implementing buffering method 800 (e.g., Figure 1 Clock buffer circuit 104 or Figure 4 The buffer circuit 400 can receive an input voltage (e.g., common-mode voltage) that is greater than the input power supply voltage of the buffer circuit.

[0036] In this specification, the terms "coupled" or "connected" refer to an indirect or direct wired or wireless connection. Therefore, if a first device is coupled to a second device, the connection can be either a direct connection or an indirect connection via other devices and connections. The statement "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any other factors.

[0037] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. An input circuit comprising: Input stage, the input stage having: Input node; The DC amplifier coupled to the input node is a DC amplifier; An AC amplifier is coupled to the output node of the DC amplifier. A capacitor coupled between the input node and the output node of the DC amplifier; as well as A voltage divider coupled to the DC amplifier and the AC amplifier, wherein the voltage divider includes a first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, wherein the first resistor is larger than the second resistor to make the DC amplifier weaker than the AC amplifier.

2. The input circuit according to claim 1, wherein the DC amplifier comprises: An input common-mode amplifier coupled to the input node; A gain amplifier coupled to the output node of the input common-mode amplifier; as well as An inverter coupled to the output node of the gain amplifier.

3. The input circuit according to claim 2, wherein the input common-mode amplifier includes a frequency-compensated voltage divider.

4. The input circuit of claim 3, wherein the capacitor includes a first capacitor, and wherein the frequency compensation voltage divider includes: Third resistor; Fourth resistor; as well as Second capacitor, The first terminal of the fourth resistor and the first plate of the second capacitor are coupled to the input node. The second end of the fourth resistor and the second plate of the second capacitor are coupled to an internal node, and The first end of the third resistor is coupled to the internal node, and the second end of the third resistor is coupled to the ground node.

5. The input circuit of claim 1, wherein the input stage is configured to receive a clock voltage at the input node, wherein the clock voltage is higher than the input voltage supply of the DC amplifier and the AC amplifier.

6. The input circuit of claim 1, wherein the first resistor is at least five times larger than the second resistor.

7. The input circuit of claim 1, wherein the DC amplifier and the AC amplifier comprise complementary metal-oxide-semiconductor components, i.e., CMOS components.

8. The input circuit according to claim 1, wherein the input stage is a differential input stage, wherein the differential input stage comprises: Complementary input nodes; The complementary output node of the DC amplifier; A complementary capacitor between the complementary input node and the complementary output node of the DC amplifier; as well as A complementary voltage divider resistor coupled to the AC amplifier and the DC amplifier, wherein the complementary voltage divider resistor includes a first complementary resistor associated with the DC amplifier and a second complementary resistor associated with the AC amplifier, wherein the first complementary resistor is larger than the second complementary resistor.

9. A clock buffer circuit, comprising: A complementary metal-oxide-semiconductor (CMOS) input stage, also known as a CMOS input stage, has the following characteristics: Input node; The DC amplifier coupled to the input node is a DC amplifier; An AC amplifier is coupled to the output node of the DC amplifier. A capacitor coupled between the input node and the output node of the DC amplifier, wherein the CMOS input stage is configured to receive a clock voltage at the input node, wherein the clock voltage is higher than the input voltage supply of the DC amplifier and the AC amplifier; as well as A voltage divider coupled to the AC amplifier and the DC amplifier, wherein the voltage divider includes a first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, wherein the first resistor is larger than the second resistor to make the DC amplifier weaker than the AC amplifier.

10. The clock buffer circuit of claim 9, wherein the DC amplifier comprises: The input common-mode amplifier is coupled to the first input node; A gain amplifier coupled to the output node of the input common-mode amplifier; as well as An inverter coupled to the output node of the gain amplifier.

11. The clock buffer circuit of claim 10, wherein the input common-mode amplifier includes a frequency-compensated voltage divider.

12. The clock buffer circuit of claim 11, wherein the capacitor includes a first capacitor, and wherein the frequency compensation voltage divider includes: Third resistor; Fourth resistor; as well as Second capacitor, The first terminal of the fourth resistor and the first plate of the second capacitor are coupled to the input node. The second end of the fourth resistor and the second plate of the second capacitor are coupled to an internal node, and The first end of the third resistor is coupled to the internal node, and the second end of the third resistor is coupled to the ground node.

13. The clock buffer circuit of claim 9, wherein the DC amplifier and the AC amplifier comprise complementary metal-oxide-semiconductor components, i.e., CMOS components.

14. The clock buffer circuit of claim 9, wherein the input stage is a differential input stage, wherein the differential input stage comprises: Complementary input nodes; The complementary output node of the DC amplifier; A complementary capacitor between the complementary input node and the complementary output node of the DC amplifier; as well as A complementary voltage divider resistor coupled to the DC amplifier and the AC amplifier, wherein the complementary voltage divider resistor includes a first complementary resistor associated with the DC amplifier and a second complementary resistor associated with the AC amplifier, wherein the first complementary resistor is larger than the second complementary resistor.

15. A signal input method, comprising: It receives differential input signals containing both DC and AC signal components. Perform a first amplification associated with the DC signal component of the differential input signal; Perform a second amplification associated with the AC signal component of the differential input signal, wherein the second amplification is greater than the first amplification; as well as The DC signal component is voltage-divided for the second amplification, wherein the voltage division is based on a first resistor associated with the first amplification and a second resistor associated with the second amplification, and wherein the first resistor is larger than the second resistor.

16. The method of claim 15, applicable to an input stage comprising a complementary metal-oxide-semiconductor device, i.e., a CMOS device.

17. The method of claim 15, wherein the first amplification involves performing a frequency-compensated voltage divider on the differential input signal.

18. The method of claim 15, wherein the DC signal component is greater than the input power supply voltage used for the first amplification and the second amplification.

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