Method for manufacturing three-dimensional NOR memory array

Abstract

A process for manufacturing a three-dimensional memory structure includes: (a) providing one or more active layers above a planar surface of a semiconductor substrate, each active layer including (i) a first semiconductor layer and a second semiconductor layer having a first conductivity; (ii) a dielectric layer separating the first semiconductor layer and the second semiconductor layer; and (ii) one or more sacrificial layers, at least one of the sacrificial layers being adjacent to the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches, each trench separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches with silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each adjacent to adjacent active stacks and exposing portions of one or more sidewalls of the active stacks; and (e) removing the sacrificial layer from the exposed portions of the sidewalls by isotropically etching through the exposed portions of the sidewalls of the active stacks to create corresponding cavities in the active layers.

Description

Technical Field

[0001] The present invention relates to memory strings of the non-volatile NOR type. In particular, the present invention relates to a process for manufacturing a three-dimensional array of memory strings of the non-volatile NOR type. Background Art

[0002] High density structures representing arrays of general non-volatile memory cells have been described in co-pending applications I and II. The memory arrays of co-pending applications I and II are organized as stacks of connected storage transistors fabricated on top of a semiconductor substrate ("active stack"). Specifically, co-pending applications I and II disclose multiple strips of semiconductor layers in each active stack ("active strips"), each strip providing storage transistors organized as NOR-type memory strings or "NOR memory strings". The semiconductor substrate on which the memory array is constructed includes various types of support circuits, such as power supply circuits, address decoders, sense amplifiers, input and output circuits, comparators, and control and other logic circuits.

[0003] Figure 1a A memory structure 100 containing NOR memory strings that can be manufactured using the method of the present invention is schematically illustrated. In this context, a NOR memory string is composed of separate and independently addressable storage transistors that share a common source region and a common drain region. As described in co-pending applications I and II, each memory string can be formed along one side of an active stripe that includes multiple layers of semiconductor and conductor materials. The memory structure 100 is organized into m active stacks, each containing n active stripes, where m and n can be any integer. For example, m can be 1, 2, 4, 8, 16, 32, 64, ..., 8192 or more. Similarly, n can be 1, 2, 4, 8, ..., 64 or more.

[0004] like Figure 1aAs shown, the memory structure 100 is represented by active stacks 130-(p-1), 130-p, 130-(p+1). In each active stack, n active strips - marked as 101-1, 102-1, ..., 101-n - are separated and electrically isolated from each other by isolation layers 106. Isolation layer 106 can be, for example, silicon nitride. Each active stack is covered on the outside by a layer of charge storage material 121, which can be provided by, for example, three layers of oxide-nitride-oxide ("ONO"), as known to those skilled in the art. A plurality of conductive columns (not shown) separated from the active strips by charge storage material 121 are provided in the spaces between the active stacks. These conductive columns provide gate electrodes, which are used to select and operate storage transistors formed along the active strips on either side of the adjacent active stacks during read, write and erase operations. In the detailed description that follows, to simplify the detailed description and for ease of reference, the direction substantially perpendicular to the surface of the semiconductor substrate ("vertical") is labeled z, the direction along the length of each active strip is labeled y, and the direction along the width of each active strip is labeled x. The x and y directions are also referred to as "horizontal." One or more interconnect layers ("global interconnect layers") may be formed above or below the memory structure 100 to provide conductors to interconnect the terminals of the storage transistors in the NOR memory strings of the memory structure 100 to circuits in the semiconductor substrate.

[0005] Typically, one or more portions 108 in each active stack are dedicated to forming a "staircase" or "reverse staircase" structure that allows one or more of the semiconductor or conductor material layers in each active strip (e.g., semiconductor layers that provide common drain regions or "bit lines" in the active strips) to be electrically accessed from the global interconnect layer through conductors in vias (and buried contacts). Figure 1a In , portions 108 ("stepped portions") are provided on the front and back sides of each active stack. Storage transistors are formed in one or more portions of the active strips in each active stack outside of the one or more stepped portions ("one or more array portions"). Figure 1a In the embodiment, the array portion 109 is provided between the step portions 108 .

[0006] Figure 1b The semiconductor and conductor layers of the active strip 101 are schematically illustrated. Figure 1b As shown, the active strip 101 includes (i) n + Semiconductor layers 103 and 104 (e.g., n-type polysilicon) that can provide a common source region (or "source line") and a common drain region (or "bit line") for a NOR memory string; and (ii) an intrinsic or lightly doped p-type (p -) semiconductor layer 102, which can provide a channel region for a storage transistor of a NOR memory string. Between the dashed lines and separated from each active strip by a layer of charge storage material 121 is a hypothetical conductor (not shown) that serves as a gate electrode for a storage transistor of a NOR string. Figure 1b The dashed lines in FIG. 1 indicate the locations of conductors 122-(k-1), 122-k, and 122-(k+1) (which represent such conductors). Figure 1b As shown, in n + A conductor layer 105 (e.g., tungsten with adhesion and barrier films) is provided adjacent to the semiconductor layers 103 and 104. The conductor layer 105 reduces the resistance in the common source region and the common drain region of the NOR memory string. An isolation layer 106 (e.g., silicon nitride) electrically isolates each active strip in the active stack from each other.

[0007] The present invention provides a desirably efficient process for fabricating memory structure 100 . Summary of the invention

[0008] According to one embodiment of the present invention, a process for manufacturing a three-dimensional memory structure includes: (a) providing one or more active layers on a planar surface of a semiconductor substrate, each active layer including (i) a first semiconductor layer and a second semiconductor layer having a first conductivity; (ii) a dielectric layer separating the first semiconductor layer and the second semiconductor layer; and (ii) one or more sacrificial layers, at least one of the sacrificial layers being adjacent to the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches, each trench separating and exposing sidewalls of adjacent active stacks; and (c) filling the active layers with silicon oxide. A first set of trenches; (d) patterning and etching silicon oxide to create silicon oxide columns that each abuts adjacent active stacks and expose portions of one or more sidewalls of the active stacks; (e) removing a sacrificial layer from the exposed portions of the sidewalls by isotropically etching through the exposed portions of the sidewalls of the active stacks to create corresponding cavities in the active layers; (f) filling the cavities in the active stacks with a metal or conductor material; (g) recessing a dielectric layer from the exposed sidewalls of the active stacks; and (h) filling the recesses in the dielectric layer with a third semiconductor layer having a second conductivity opposite to the first conductivity. In addition, an isolation layer is provided to separate adjacent active layers.

[0009] According to one embodiment, the process further includes recessing the metal or conductor layer from the exposed sidewalls of the active step, wherein filling the recess in the dielectric layer also fills the recess in the metal or conductor layer.

[0010] According to one embodiment, the process further includes: (a) removing the silicon oxide columns before recessing the dielectric layer, and (b) recreating the silicon oxide columns after filling the recesses in the dielectric layer with the second semiconductor layer.

[0011] In one embodiment, the process further includes providing a charge material over the exposed sidewalls of the active stack and forming a word line by filling the space surrounded by the adjacent silicon oxide columns and the adjacent active stack with a conductor material. The third semiconductor layer includes polysilicon doped with boron in situ. In this embodiment, (i) the first semiconductor layer and the second semiconductor layer of each active layer respectively form a common drain region and a common drain region of a plurality of storage transistors organized as a NOR memory string; (ii) the third semiconductor layer forms a channel region of a storage transistor in the NOR memory string; and (iii) the word line forms a gate electrode of a storage transistor in the NOR memory string.

[0012] According to one embodiment of the present invention, a stepped structure for accessing one or more semiconductor layers in a three-dimensional memory structure includes: (i) providing a first active layer; (ii) providing a first isolation layer on top of the first active layer; (iii) providing a second active layer on top of the first isolation layer, wherein the first active layer and the second active layer each include (a) a first semiconductor layer having a first conductivity; (b) a dielectric layer of an insulating material under the first semiconductor layer; and (c) a second semiconductor layer under the dielectric layer; (iv) providing a second isolation layer on top of the second active layer; (iv) providing a photoresist layer on top of the second isolation layer and patterning the photoresist to create an opening in the photoresist layer, thereby exposing a first region of the second isolation layer; and (v) anisotropically removing the exposed first region of the second isolation layer and the second active layer at a position where the first region of the second isolation layer is exposed. (viii) filling the cavity created by the anisotropic removal steps of (v) and (vii) with an insulating material; (ix) repeating steps (i) to (viii) a predetermined number of times; and (x) anisotropically removing the insulating material at a predetermined position to create a through hole opening of the first semiconductor layer reaching the two or more active layers.

[0013] The present invention will be better understood by considering the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1a A memory structure 100 containing NOR memory strings of the type that can be fabricated using the method of the present invention is schematically illustrated.

[0015] Figure 1b Schematically illustrates Figure 1a The semiconductor and conductor layers of the active strip 101 in the memory structure 100 are shown in FIG.

[0016] Figure 2(i) , 2(ii) , 2(iii), 2(iv), 2(v), and 2(vi) illustrate a stepped portion 108 of the memory structure 100 according to one embodiment of the present invention.

[0017] 3(i) is an xz plane cross-sectional view of the array portion 109 of the memory structure 100 showing the patterned photoresist layer 205 defining a 45-nm width for each active stack and a 65-nm width for each trench between adjacent active stacks.

[0018] FIG. 3( ii ) shows the resulting memory structure 100 with active stacks 207 a - 207 e after filling the trenches with silicon oxide, removing the photoresist 206 , and planarizing the resulting surface by CMP.

[0019] Figure 3(iii) and 3(iv) 2 and 3. A top view and an xz plane cross-sectional view, respectively, show the resulting memory structure 100 after etching trenches 209 to form word lines.

[0020] FIG. 3( v ) shows the resulting memory structure 100 after removing the SAC4 layers 105 s - b and 105 s - t from the active stack, thereby creating a cavity 211 in their place.

[0021] Figure 3(vi) and 3(vii) 2 and 3. A top view and an xz plane cross-sectional view, respectively, show the resulting memory structure 100 after filling the trench 209 and the cavity 211 with a metal / conductor material.

[0022] Figure 3(viii) and 3(ix) 1 and 2, respectively, show the resulting memory structure 100 after both the metal / conductor layer 105 and the spline oxide 102o are recessed.

[0023] FIG. 3( x ) shows an xz plane cross-sectional view through the wordline trench, showing the trench polysilicon 102 filling the metal / conductor layer 105 and the recessed plugging oxide 102 o .

[0024] 3(xi) is an xz plane cross-sectional view of the memory structure 100 after the charge storage material 213 and word lines 214 are deposited and planarized.

[0025] FIG. 3(xii) is a top view illustrating the array portion 108 of the memory structure 100 after forming a global interconnect layer.

[0026] Figure 4 A top view of the memory structure 100 is shown after the word line spacer columns have been patterned and etched.

[0027] In this detailed description, like elements in the drawings are provided with like reference numerals to facilitate referring to the features in the drawings. DETAILED DESCRIPTION

[0028] The present invention provides an efficient process for manufacturing a memory structure containing an array of NOR memory strings. In the detailed description below, the parameters of each step (e.g., temperature, pressure, precursors, components and dimensions) are provided for exemplary purposes only. Upon consideration of this detailed description, one of ordinary skill in the art will be able to modify or change these parameters without departing from the scope of the present invention.

[0029] According to one embodiment of the present invention, a process is provided by which a memory structure containing NOR memory strings can be formed over a planar surface of a semiconductor substrate. Initially, various types of support circuits can be formed in or at the surface of the semiconductor substrate (e.g., power supply circuits, address decoders, sense amplifiers, input and output circuits, comparators, and control and other logic circuits are fabricated).

[0030] An isolation layer (e.g., silicon oxide) may be formed on the planar surface. Buried contacts may be formed in the isolation layer for connection to underlying circuitry. One or more global interconnect layers may then be formed over the isolation layer. (In the detailed description below, these layers are collectively referred to as substrate 150.)

[0031] Thereafter, a base oxide film 107 (e.g., a 50-nm silicon oxide film) is provided. Then, semiconductor layers and conductor layers of active strips (collectively referred to as "active layers") are provided. Multiple active layers may be provided layer by layer, each active layer being isolated from the next active layer by an isolation film 106 (e.g., a 30-nm nitride layer). In one embodiment, in a sequence of deposition, each active layer may include (a) a sacrificial layer 105s-b ("SAC4 layer 105s-b"; for example, a 40-nm layer of silicon germanium); and (b) a sacrificial layer 105s-b. +doped polysilicon layer 104 ("drain polysilicon 104"; for example, a 30-nm in-situ arsenic-doped polysilicon film); (c) silicon oxide layer 102o ("gap oxide 102o"; an 80-nm silicon oxide film); (d) n + Polysilicon layer 103 ("source polysilicon 103"; for example, a 30-nm in situ arsenic-doped polysilicon film); (e) sacrificial layers 105s-t ("SAC4 layers 105s-t"; for example, a 40-nm layer of silicon germanium). SAC4 layers 105s-b and 105s-t are sacrificial layers that will each be subsequently replaced by a metal conductor layer, as described below.

[0032] During the deposition of the active layer, a step structure for electrically accessing the drain polysilicon 104 of each active strip to be formed is formed in the step portion 108. The array portion 109 is protected from the step forming step by a mask over the array portion 109. According to the present invention, the step structure can be formed using one photolithography step for every two active layers. Figures 2(i) to 2(vi) The diagram illustrates the formation of a stepped structure in the stepped portion 108 of the memory structure 100 in accordance with one embodiment of the present invention.

[0033] FIG2(i) shows the memory structure 100 after depositing the active layers 101-1 and 101-2. Thereafter, a photoresist layer 201 is deposited and patterned over the memory structure 100. A first etching step removes (a) the isolation layer 106 and (b) the active layer 101-2 (i.e., the SAC4 layer 105s-tb, source polysilicon 103, plug oxide 102o, drain polysilicon 104, and SAC4 layer 105s-b of the active layer 101-2) film by film from areas not protected by the photoresist 201. This first etching step stops at the isolation 106 immediately above the active layer 101-1. The resulting structure is shown in FIG2(ii).

[0034] Then, the photoresist layer 201 is recessed to further expose additional areas of the active layer 101-2. The resulting structure is shown in FIG2(iii). Thereafter, a second etching step removes (a) the SAC4 layer 105s-t of the two active layers 101-1 and 101-2, and (b) the source polysilicon 103 of the active layers 101-1 and 101-2 from the exposed portion of the isolation film 106 immediately above the active layers 101-1 and 101-2. The second etching step stops at the plugging oxide layer 102o of both the two active layers 101-1 and 101-2. The resulting structure as a stepped structure with two steps is shown in FIG2(iv). The photoresist layer 201 is then removed.

[0035] Silicon oxide 202 is then provided to fill the cavity created by the first etching step and the second etching step. A subsequent planarization step (e.g., chemical mechanical polishing (CMP)) flattens the resulting surface. The resulting structure is shown in FIG. 2( v). Vias can then be created in the silicon oxide 202 and the underlying plugging oxide 102o of each of the active layers 101-1 and 101-2 to allow access to the drain polysilicon 104 of each of the active layers 101-1 and 101-2. As discussed below, these vias are created in the subsequent oxide etching after all active layers are deposited.

[0036] Every two deposited active layers are repeatedly combined Figures 2(i) to 2(v) Steps of discussion. Note that, combined with Figures 2(i) to 2(v) The step formation steps discussed require one photolithography step for every two deposited active layers, which is more advantageous than previously used step formation steps which required one photolithography step for each deposited active layer.

[0037] After all active layers of the memory structure 100 are deposited and the cavities from the most recent first and second etching steps on the last two active layers are filled, oxide etching can be performed at an appropriate time to create vias that reach the drain polysilicon layer 104 of each active layer. The resulting structure is shown in Figure 2(vi). In Figure 2(vi) and each of the figures discussed below, four active layers 101-1, 101-2, 101-3, and 101-4 are shown for exemplary purposes only. In Figure 2(vi), vias 203-1, 203-2, 203-3, and 203-4 are illustrative vias that can be created to access the semiconductor and conductor material layers of the active layers that exist. Those of ordinary skill in the art will understand that the present invention is applicable to any structure having any desired number of active layers and vias. When using a conductor material (e.g., tungsten or p + When filled with polysilicon (polysilicon), these vias provide electrical connections between drain polysilicon 104 and circuits in semiconductor substrate 150 through conductors in one or more global interconnect layers to be formed above memory structure 100.

[0038] After all active layers are deposited, a hard mask layer 205 is provided over the active layers in the array portion 109. A photoresist layer 206 is provided and patterned to define active stacks and trenches between active stacks. FIG3(i) is an xz plane cross-sectional view of the array portion 109 of the memory structure 100, showing the patterned photoresist layer 206 defining a 45-nm width for each active stack and a 65-nm width for each trench between adjacent active stacks. Etching through the hard mask layer 205 and active layers not protected by the photoresist layer 206 creates active stacks and trenches between active stacks. Silicon oxide 208 is then deposited to fill the trenches. FIG3(ii) shows the resulting memory structure 100 having active stacks 207a to 207e after the trenches are filled with silicon oxide, the photoresist 206 is removed, and planarized by CMP. Unless otherwise specified, Figure 3(i)-3(xii) All xz plane cross-sectional views in FIG. 1 are made in array portion 109 of memory structure 100 .

[0039] The disilicon oxide 208 is then patterned and etched to define trenches ("word line trenches") that are subsequently filled with conductors. The remaining silicon oxide 208 ("silicon oxide columns") provides electrical insulation between adjacent word line conductors. Figure 3(iii) and 3(iv) 2 and 3 are top views and xz plane cross-sectional views, respectively, showing the resulting memory structure 100 after etching the word line trenches 209. Figure 3(iii) and 3(iv) In FIG3(iv), the word line trench and the remaining oxide column are both 65 nm wide. The cross section of FIG3(iv) is taken along the dashed line AA' shown in FIG3(iii).

[0040] Next, the sacrificial SAC4 layers 105s-t and 105s-b adjacent to the source polysilicon 103 and the drain polysilicon 104, respectively, in each active layer are removed by a selective isotropic etching technique. Isotropic etching continues laterally from the word line trench 209 until all sacrificial material in the SAC4 layers 105s-t and 105s-b is removed. During this process, the silicon oxide columns provide mechanical support to the active stack (e.g., active stacks 207a-207e of Figure 3(iv)). Figure 3(v) shows the resulting memory structure 100 after all SAC4 layers 105s-b and 105s-t are removed from the active stack, thereby creating a cavity 211 in their place.

[0041] The cavity 211 and the wordline trench 209 are then filled with a metal / conductor material. The metal / conductor material may be provided, for example, by successive depositions of a barrier material (eg, tungsten nitride or titanium nitride) and tungsten. Figure 3(vi) and 3(vii) 3(vii) and 3(f) are top views and xz plane cross-sectional views, respectively, showing the memory structure 100 obtained after filling the wordline trenches 209 and cavities 211 with metal / conductor material. In FIG3(vii), the cavities 211 in the active stripes are replaced by metal / conductor layers 305. The xz plane cross-sectional view of FIG3(vii) is taken along the dashed line BB' shown in FIG3(vi).

[0042] Thereafter, an anisotropic etch removes the metal / conductor material 305 from the wordline trenches. In one embodiment, the silicon oxide columns 208 continue to provide mechanical support after the SAC4 layer is replaced by the metal / conductor layer 305. Alternatively, the silicon oxide columns may be removed by the anisotropic oxide at this time.

[0043] A selective isotropic etch may then be performed to recess the metal / conductor layer 105 and the gap oxide 102o. In one embodiment, the selective isotropic etch recesses each metal / conductor layer 305 by 5-6 nm from the sidewalls of the active stack. The isotropic oxide etch recesses the gap oxide 102o from the sidewalls of the active stack by, for example, 5-6 nm. If the silicon oxide columns 208 are not removed, the isotropic oxide etch also recesses the exposed sidewalls of the silicon oxide columns 208 by the same amount on each side in the y-direction. Figure 3(viii) and 3(ix) The top view and xz plane cross-sectional view, respectively, show the resulting memory structure 100 after both the metal / conductor layer 305 and the gap oxide 102o are recessed. Figure 3(viii) relates to an embodiment in which the silicon oxide columns 208 are retained.

[0044] Lightly doped p - Polysilicon ("channel polysilicon 102") may then be deposited to fill the recesses in both the metal / conductor layer 305 and the gap oxide 102o as well as the wordline trenches. An anisotropic etch of the channel polysilicon 102 may follow to remove the channel polysilicon 102 from the wordline trenches 209. The channel polysilicon 102 may be deposited to have a thickness of, for example, 5.0×10 18 cm -3The channel polysilicon 102 is provided by in-situ boron-doped polysilicon with a dopant concentration of 100 Å. FIG. 3( x) is an xz plane cross-sectional view through the wordline trench 209, showing the recessed channel polysilicon 102 in the fill metal / conductor layer 305 and the plugging oxide 102o. One disadvantage of not removing the silicon oxide columns 208 prior to the isotropic oxide etch is that the portion of the plugging oxide 102o behind the silicon oxide columns 208 is protected and not recessed. Therefore, the channel polysilicon 102 deposited on the active strip is not continuous in the y direction, and each memory cell on the active strip has a very small separate, discrete area of ​​channel polysilicon, which may not be effective in providing sufficient charge carriers during storage transistor operation (e.g., erase operation).

[0045] If the silicon oxide columns 208 are removed after the SAC4 layers 105s-t and 105s-t are replaced by the metal / conductor layer 305 as discussed above, then word line spacer columns can now be provided by filling the trenches between adjacent active stacks (created by the removal of the silicon oxide columns 208) with silicon oxide, patterning and etching the silicon oxide. The resulting word line spacer columns are similar, and they are referred to as forward silicon oxide columns 208 if they have been retained. Figure 4 A top view of the memory structure 100 is shown after the wordline spacer columns have been patterned and formed. To simplify the following detailed description, in the remainder of the processing, these wordline spacer columns may be processed identically to the silicon oxide columns 208. Therefore, these wordline spacer columns are also labeled 208, and no other distinction is made between the two sets of columns in the remainder of this detailed description.

[0046] Charge storage material 213 may then be deposited, conformally aligned with the sidewalls of wordline trench 209. Charge storage material 213 may be implemented by sequentially depositing: 2-nm thick tunnel oxide, 6-nm thick silicon-rich nitride, 6-nm thick silicon oxide, and 2-nm thick aluminum oxide (Al2O3). Thereafter, wordline trench 209 lined with charge storage material may then be formed by conductor material 214 (e.g., p-type). + Polysilicon) is filled to provide word lines. Excess charge storage material 213 and conductor material 214 can then be removed from the top surface of memory structure 100 by CMP planarization. FIG3(xi) is an xz plane cross-sectional view of memory structure 100 after charge storage material 213 and word lines 214 have been deposited and planarized.

[0047] A buffer oxide 215 may be deposited over the memory structure 100, patterned and etched to provide contact vias to the word lines 214 beneath the buffer oxide 215. These contact vias may be filled with tungsten ("tungsten plugs"). Tungsten plugs may also be provided simultaneously in the vias formed in the stepped portion 108 to contact the drain polysilicon or the bit lines 104. Global interconnect lines may be provided over the memory structure 100 to subsequently interconnect the word lines 214 and the bit lines 104 to circuits in the semiconductor substrate 150. FIG3(xii) shows a top view of a portion of the array portion 108 of the memory structure 100. As shown in FIG3(xii), the connections from the global interconnect lines 216 to the word lines 214 are staggered (i.e., each of the global interconnect lines 216 connects to every other word line 214; the other global interconnect lines connect to the remaining word lines along the first global interconnect line).

[0048] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting of the above detailed description. Many changes and modifications are possible within the scope of the present invention. The present invention is set forth in the appended claims.

Claims

1. A method for manufacturing a three-dimensional NOR memory array, comprising: Providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) a first semiconductor layer and a second semiconductor layer having a first conductivity type; (ii) a dielectric layer separating the first semiconductor layer and the second semiconductor layer; and (ii) one or more sacrificial layers, at least one of the sacrificial layers being adjacent to the first semiconductor layer; etching the active layer to create a plurality of active stacks and a first set of trenches, each trench separating and exposing sidewalls of adjacent active stacks; filling the first set of trenches with a silicon oxide material; patterning and etching the silicon oxide material to create silicon oxide columns each abutting adjacent active stacks and exposing portions of one or more sidewalls of the active stacks; removing the sacrificial layer from the active layer by isotropically etching through the exposed portions of the sidewalls, wherein an etchant of the isotropic etch passes through the exposed portions of the sidewalls of the active stack to the sacrificial layer, thereby creating a cavity in the active layer; as well as The cavity is filled with a conductive material.

2. The method according to claim 1, further comprising, in each active layer: etching the dielectric layer from exposed sidewalls of the active stack to form a recess in the dielectric layer; as well as The recess in the dielectric layer is filled with a third semiconductor layer having a second conductivity type opposite to the first conductivity type.

3. The method according to claim 2, further comprising: removing the silicon oxide columns prior to etching the dielectric layer, and After the recesses in the dielectric layer are filled by the third semiconductor layer, the silicon oxide columns are recreated.

4. The method according to claim 2, wherein: The third semiconductor layer includes polysilicon in-situ doped with boron. 5 . The method of claim 2 , further comprising providing a charge storage material over the exposed sidewalls of the active stack. 6 . The method of claim 5 , further comprising forming a word line by filling a space surrounded by adjacent silicon oxide columns and adjacent the active stack with a conductive material.

7. The method according to claim 6, wherein: (i) the first semiconductor layer, the second semiconductor layer and the third semiconductor layer of each active layer respectively form a common source region, a common drain region and a channel region of a plurality of storage transistors organized into one or more NOR memory strings; and (ii) the word lines form gate electrodes of storage transistors in the NOR memory string.

8. The method according to claim 1, wherein: Adjacent active layers are separated by isolation layers.

9. The method of claim 2 further comprising etching the conductor material in each active layer from exposed sidewalls of the active stack to form recesses in the conductor material such that filling the recesses in the dielectric layer also fills the recesses in the conductor material.

10. A method for manufacturing a three-dimensional NOR memory array, comprising: (i) providing a first active layer, comprising (a) a first semiconductor layer having a first conductivity type; (b) a dielectric layer of insulating material beneath the first semiconductor layer; and (c) a second semiconductor layer beneath the dielectric layer; (ii) providing a first isolation layer on top of the first active layer; (iii) providing a second active layer on top of the first isolation layer, the second active layer having the same composition as the first active layer; (iv) providing a second isolation layer on top of the second active layer; (v) providing a photoresist layer over the second isolation layer and patterning the photoresist layer to create an opening in the photoresist layer, thereby exposing a first region of the second isolation layer; (vi) anisotropically removing the exposed first region of the second isolation layer and a portion of the second active layer below the first region of the second isolation layer to expose the first region of the first isolation layer; (vii) recessing the photoresist layer to enlarge the opening in the photoresist layer so as to expose a second region of the second isolation layer; (viii) anisotropically removing the exposed first region of the first isolation layer and the exposed second region of the second isolation layer, and a portion of the first semiconductor layer below the exposed first region of the first isolation layer and the exposed second region of the second isolation layer; as well as (ix) filling the cavity created by the anisotropic removal steps of (vi) and (viii) with the insulating material.

11. The method according to claim 10, further comprising: (x) repeating steps (i) to (ix) a predetermined number of times; as well as (xi) Anisotropically removing the insulating material at predetermined locations to create via openings in the second semiconductor layer that reach two or more active layers.

12. The method of claim 11, further comprising filling the via opening with a conductive material.

13. The method according to claim 12, wherein: The second semiconductor layer and the first semiconductor layer respectively form a common drain region and a common source region of storage transistors in the NOR memory string.

14. The method according to claim 12, wherein: The conductor material in the via opening forms an electrical conduit for providing a voltage to a common drain region.

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