Integrated assembly, memory device, and method of forming an integrated assembly

Abstract

The present application relates to an integrated assembly, a memory device, and a method of forming an integrated assembly. A conductive level includes a first region and includes a second region laterally adjacent to the first region. The first region has a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second region has a second vertical thickness at least as large as the first vertical thickness and has only a single metal-containing material along the second vertical thickness. A dielectric barrier material is laterally adjacent to the first region. A charge blocking material is laterally adjacent to the dielectric barrier material. A charge storage material is laterally adjacent to the charge blocking material. A dielectric material is laterally adjacent to the charge storage material. A channel material is laterally adjacent to the dielectric material.

Description

Technical Field

[0001] Integrated assemblies (eg, memory devices). Methods of forming integrated assemblies. Background Art

[0002] Memory provides data storage for electronic systems. Flash memory is a type of memory and is used extensively in modern computers and devices. For example, modern personal computers may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0003] NAND may be the basic architecture of flash memory and may be configured to include vertically stacked memory cells.

[0004] Before describing NAND in detail, it may be helpful to more generally describe the relationship of the memory array within the integrated arrangement. FIG. 1 shows a block diagram of a prior art device 1000 including: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; and access lines 1004 (e.g., word lines for conducting signals WL0 to WLm); and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). The access lines 1004 and the first data lines 1006 may be used to transfer information into and out of the memory cells 1003. The row decoder 1007 and the column decoder 1008 decode the address signals A0 to AX on the address lines 1009 to determine which of the memory cells 1003 are to be accessed. The sense amplifier circuit 1015 is used to determine the value of the information read from the memory cell 1003. The I / O circuit 1017 transmits the value of the information between the memory array 1002 and the input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O line 1005 may represent the value of information to be read from or written to memory cell 1003. Other devices may communicate with device 1000 via I / O line 1005, address line 1009, or control line 1020. Memory control unit 1018 is used to control memory operations to be performed on memory cell 1003 and utilizes signals on control line 1020. Device 1000 may receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuit 1040 and input / output (I / O) circuit 1017. Selection circuit 1040 may respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013 that may represent the value of information to be read from or programmed into memory cell 1003. Column decoder 1008 may selectively activate CSEL1 through CSELn signals based on A0 through AX address signals on address line 1009. Selection circuit 1040 may select signals on first and second data lines 1006 and 1013 to provide communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0005] The memory array 1002 of FIG. 1 may be a NAND memory array, and FIG. 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that may be used for the memory array 1002 of FIG. 1 . The device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked on top of each other, wherein each charge storage device corresponds to, for example, one of thirty-two layers (e.g., Tier 0 to Tier 31). The charge storage devices of the corresponding strings may share a common channel region, such as a common channel region formed in a corresponding semiconductor material (e.g., polysilicon) column, around which the charge storage device string is formed. In a second direction (XX'), each of, for example, sixteen first groups of the multiple strings may include, for example, eight strings that share multiple (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines", also referred to as word lines WL). Each of the access lines may couple the charge storage devices within the layer. When each charge storage device includes a cell capable of storing two bits of information, the charge storage devices coupled by the same access line (and therefore corresponding to the same layer) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), each second group of, for example, eight second groups in a plurality of strings may include sixteen strings coupled by a corresponding one of eight data lines. The size of the memory block may include 1,024 pages, and a total of approximately 16MB (e.g., 16 word lines x 32 layers * 2 bits = 1,024 pages / block, block size = 1,024 pages x 16KB / page = 16MB). The number of strings, layers, access lines, data lines, first groups, second groups, and / or pages may be larger or smaller than those shown in FIG. 2 .

[0006] 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in the XX′ direction, the memory block including fifteen strings of charge storage devices in one of the sixteen first groups of strings described with respect to FIG. The multi-string memory block 300 can be grouped into a plurality of subsets 310, 320, 330 (e.g., tile columns), such as tile columns. I , Piece Column j and tile columns K, where each subset (e.g., tile column) includes a "partial block" (sub-block) of the memory block 300. A global drain-side select gate (SGD) line 340 may be coupled to the SGD of multiple strings. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding sub-SGD drivers in multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a respective subset (e.g., tile column). Each of the sub-SGD drivers 332, 334, 336 may simultaneously couple or cut off the SGD of the strings of the corresponding partial block (e.g., tile column) independently of the SGD of the strings of the other partial blocks. A global source-side select gate (SGS) line 360 ​​may be coupled to the SGS of multiple strings. For example, the global SGS line 360 ​​may be coupled to a plurality of sub-SGS lines 362, 364, 366 via a corresponding sub-SGS driver in a plurality of sub-SGS drivers 322, 324, 326, wherein each sub-SGS line corresponds to a corresponding subset (e.g., tile column). Each of the sub-SGS drivers 322, 324, 326 may simultaneously couple or cut off the SGS of the string of the corresponding partial block (e.g., tile column) independently of the SGS of the string of the other partial blocks. The global access line (e.g., global CG line) 350 may couple the charge storage device of the corresponding layer of each of the plurality of strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding sub-string driver in a plurality of sub-string drivers 312, 314, and 316. Each of the sub-string drivers may simultaneously couple or cut off the charge storage device corresponding to the corresponding partial block and / or layer independently of the corresponding charge storage device of the other partial blocks and / or other layers. The charge storage devices corresponding to the respective subsets (e.g., partial blocks) and the respective layers may include charge storage devices of a "partial layer" (e.g., a single "tile"). The strings corresponding to the respective subsets (e.g., partial blocks) may be coupled to respective ones of the sub-sources 372, 374, and 376 (e.g., "tile sources"), each of which is coupled to a respective power source.

[0007] Alternatively, the NAND memory device 200 is described with reference to the schematic illustration of FIG. 4 .

[0008] The memory array 200 includes word lines 202 1 By 202 N , and bit line 228 1 To 228 M .

[0009] The memory array 200 also includes NAND strings 206. 1 To 206 M Each NAND string includes a charge storage transistor 208 1To 208 N The charge storage transistor may use a floating gate material (eg, polysilicon) to store charge, or may use a charge trapping material (eg, silicon nitride, metal nanodots, etc.) to store charge.

[0010] The charge storage transistor 208 is located at the intersection of the word line 202 and the string 206. The charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in source-drain series between a source select device (e.g., source side select gate SGS) 210 and a drain select device (e.g., drain side select gate SGD) 212. Each source select device 210 is located at the intersection of the string 206 and the source select line 214, and each drain select device 212 is located at the intersection of the string 206 and the drain select line 215. The select devices 210 and 212 can be any suitable access devices and are generally illustrated by the blocks in Figure 4.

[0011] The source of each source selection device 210 is connected to the common source line 216. The drain of each source selection device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the source selection device 210 1 The drain of the corresponding NAND string 206 is connected to 1 The charge storage transistor 208 1 The source selection device 210 is connected to the source selection line 214.

[0012] The drain of each drain select device 212 is connected to a bit line (ie, digit line) 228 at a drain contact. 1 The drain is connected to the bit line 228 1 The source of each drain select device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the drain select device 212 1 The source is connected to the corresponding NAND string 206 1 The charge storage transistor 208 N of the drain.

[0013] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 has its control gate 236 coupled to the word line 202. The columns of charge storage transistors 208 are those transistors within the NAND string 206 that are coupled to a given bit line 228. The rows of charge storage transistors 208 are those transistors that are commonly coupled to a given word line 202.

[0014] It is desirable to develop improved memory devices (eg, NAND architectures), and to develop methods for making improved memory devices. Summary of the invention

[0015] One aspect of the present disclosure relates to an integrated assembly comprising: a vertical stack of alternating insulating layers and conductive layers; and the conductive layers have a first region and a second region laterally adjacent to the first region; the first region comprises a conductive core material and comprises a conductive lining material along the upper and lower surfaces of the conductive core material; the composition of the conductive lining material is different from that of the conductive core material; the first regions each have a first vertical thickness extending over the conductive lining material and the conductive core material; the second regions each comprise a conductive track, the total vertical thickness of the conductive track being at least approximately the same as the first vertical thickness; each of the conductive tracks has a uniform composition along its total vertical thickness.

[0016] Another aspect of the present disclosure relates to a memory device comprising: a vertical stack of alternating insulating levels and conductive levels; the conductive levels include a first region and a second region laterally adjacent to the first region; the first region has a first vertical thickness and at least two different metal-containing materials along the first vertical thickness; the second region has a second vertical thickness and only a single metal-containing material along the second vertical thickness; a charge blocking material laterally adjacent to the first region; a charge storage material laterally adjacent to the charge blocking material; a dielectric material laterally adjacent to the charge storage material; and a channel material laterally adjacent to the dielectric material.

[0017] Another aspect of the present disclosure relates to a method of forming an integrated assembly, comprising: forming a vertical stack of alternating first and second levels; the first level includes a first material and the second level includes a second material; forming an opening extending through the stack; forming a channel material in the opening; forming a gap extending through the stack, wherein the gap is laterally offset relative to the channel material; after forming the gap, removing the second material to leave a void; forming a first conductive structure in the void; the first conductive structure has a proximal region adjacent to the channel material and has a distal region adjacent to the gap; removing the distal region to form a cavity adjacent to the proximal region; and forming a second conductive structure in the cavity directly against the proximal region of the first conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 shows a block diagram of a prior art memory device having a memory array including memory cells.

[0019] 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device.

[0020] FIG. 3 shows a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in the XX′ direction.

[0021] FIG. 4 is a schematic diagram of a prior art NAND memory array.

[0022] Figure 5 is a schematic cross-sectional side view of a region of an example integrated assembly illustrating example process stages of an example method for fabricating an example memory device.

[0023] Figure 6 yes Figure 5 The example integrated assembly is located in the Figure 5 Schematic cross-sectional side view of an example process stage following a process stage of .

[0024] Figure 7 yes Figure 5 The example integrated assembly is located in the Figure 6 Schematic cross-sectional side view of an example process stage following a process stage of .

[0025] Fig. 7A yes Figure 7 Magnified view of area 7A.

[0026] Figure 8-15 yes Figure 5 The example integrated assembly is located in the Figure 7 Schematic cross-sectional side view of an example sequential processing stages following a process stage. Fig.15 Regions of an example memory device are shown at process stages.

[0027] Fig.15A yes Fig.15 Magnified view of region 15A.

[0028] Fig. 15B It is along Fig.15 A diagrammatic top view of line 15B-15B. Fig.15 The view along Fig. 15B Line 15-15.

[0029] Fig.16 is an alternative Fig.15 Example of a memory device Schematic cross-sectional side view of a region of a memory device.

[0030] Fig.17 and 18 yes Figure 5 An instance of an integrated assembly is located in Fig.10Schematic cross-sectional side view of an example sequential processing stages following a process stage. Fig.17 The process stage can be replaced Fig.11 process stage. Fig.18 Another example memory device is shown in FIG. 10 during the process stages of FIG.

[0031] Figure 19-21 yes Figure 5 An instance of an integrated assembly is located in Fig.10 Schematic cross-sectional side view of an example sequential processing stages following a process stage. Fig.19 The process stage can be replaced Fig.11 process stage. Fig. 20 and 21 Regions of an example memory device are shown in processing stages.

[0032] Figure 22-24 yes Figure 5 An instance of an integrated assembly is located in Fig.10 Schematic cross-sectional side view of an example sequential processing stages following a process stage. Fig. 22 The process stage can be replaced Fig.11 process stage. Fig.23 and 24 Regions of an example memory device are shown in processing stages. DETAILED DESCRIPTION

[0033] Some embodiments include a memory device (e.g., a NAND memory array) having a conductive level with two different conductive structures laterally adjacent to each other. A first of the conductive structures is adjacent to the channel material and includes a conductive liner along an outer surface of the conductive core. A second of the conductive structures is distal to the channel material and includes a single conductive material extending through its entire vertical thickness. The control gates of the memory cells may include the first of the conductive structures, and the word lines (routing structures) between the memory cells may include the second of the conductive structures. Reference Figure 5-24 Example embodiments are described.

[0034] refer to Figure 5 , a construction (i.e., assembly, architecture, etc.) 10 includes a stack 12 of alternating first levels 14 and second levels 16. The first levels 14 include a first material 18, and the second levels 16 include a second material 20. The second material 20 may be a sacrificial material (e.g., silicon nitride), and the first material 18 may be an insulating material (e.g., silicon dioxide).

[0035] Levels 14 and 16 may have any suitable thickness; and may have the same thickness as one another, or different thicknesses from one another. In some embodiments, levels 14 and 16 may have a vertical thickness in a range from about 10 nanometers (nm) to about 400 nm.

[0036] The sacrificial material 20 of the second level 16 may be replaced with the conductive material of the memory cell gates (as discussed below). Thus, the level 16 may ultimately correspond to a memory cell level of a NAND configuration. A NAND configuration will include a string of memory cells (i.e., a NAND string), where the number of memory cells in the string is determined by the number of levels 16 that are vertically stacked. A NAND string may include any suitable number of memory cell levels. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, and so on. The vertical stack 12 is shown extending outward beyond the illustrated area of ​​the stack to indicate that there may be more levels of vertical stacking than 12. Figure 5 Those specifically shown in the drawings.

[0037] Stack 12 is shown supported on base 22. Base 22 may include semiconductor material; and, for example, may include, consist essentially of, or consist entirely of single crystal silicon. Base 22 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including a semiconducting material, including but not limited to bulk semiconducting material, such as a semiconducting wafer (either alone or in an assembly including other materials), and a layer of semiconducting material (either alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above. In some applications, base 22 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffuse materials, insulator materials, and the like.

[0038] A gap is provided between the stack 12 and the substrate 22 to indicate that other components and materials may be provided between the stack 12 and the substrate 22. Such other components and materials may include additional stack levels, source line levels, source side select gates (SGS), and the like.

[0039] refer to Figure 6, forming openings 24 through stack 12. The openings are ultimately used to fabricate pillars of channel material associated with vertically stacked memory cells of a memory array, and in some embodiments, may be referred to as pillar openings. Openings 24 may have any suitable configuration when viewed from above; in some example embodiments, they may be circular, elliptical, polygonal, and the like. Openings 24 may represent a large number of substantially identical openings formed to extend through stack 12; wherein the term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement.

[0040] refer to Figure 7 , forming a material within opening 24. One of the materials is channel material 26. Channel material 26 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist entirely of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, and the like; wherein the term III / V semiconductor material refers to a semiconductor material including an element selected from Groups III and V of the periodic table (wherein Groups III and V are old nomenclature, now referred to as Groups 13 and 15). In some example embodiments, channel material 26 may include, consist essentially of, or consist entirely of appropriately doped silicon.

[0041] The channel material 26 is configured as a pillar 28 extending through the stack 12. The pillar is configured as a ring (in Fig. 15B ). The ring surrounds the insulating material 30 (e.g., silicon dioxide). The configuration of the channel material pillar 28 as a ring can be considered to correspond to a "hollow" channel configuration, where the dielectric material 30 is provided within the cavity of the channel material pillar. In other embodiments, the channel material pillar 28 can be configured as a solid pillar, rather than as a hollow pillar as shown.

[0042] Channel material pillar 28 is spaced apart from levels 14 and 16 of stack 12 by an intervening region 32. Region 32 may include tunneling material, charge storage material, and charge blocking material. Fig. 7A Show Figure 7 1 and 12. FIG. 1 is an enlarged view of a region of assembly 10 of FIG. 1 and illustrates tunneling material 34, charge storage material 36, and charge blocking material 38 within insertion region 32. FIG.

[0043] Tunneling material 34 (also referred to as gate dielectric material, or simply dielectric material) may include any suitable composition; and in some embodiments, may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, and the like.

[0044] Charge storage material 36 may include any suitable composition; and in some embodiments, may include a charge trapping material; such as one or more of silicon nitride, silicon oxynitride, conductive nanodots, and the like.

[0045] Charge blocking material 38 may include any suitable composition; and in some embodiments, may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, and the like.

[0046] refer to Figure 8 , forming a gap 40 extending through the stack 12. The gap 40 is laterally offset relative to the channel material 26.

[0047] refer to Fig. 9 , remove the second material 20( Figure 8 ), leaving gaps 42 along the second level 16. Selectively with respect to the first material 18 and with respect to the charge blocking material 38 ( Fig. 7A ) selectively removes second material 20. In some embodiments, second material 20 comprises silicon nitride, while materials 18 and 38 comprise silicon dioxide. In such embodiments, material 20 may be selectively removed using, for example, phosphoric acid. For purposes of interpreting the present disclosure and the appended claims, a second material is considered to be selectively removed relative to a first material if the second material is removed faster than the first material, which may include, but is not limited to, etching of the second material with 100% selectivity relative to the first material.

[0048] refer to Fig.10 , in the gap 42( Fig. 9 ) dielectric material 44 and conductive materials 46 and 48 are formed therein.

[0049] In some embodiments, dielectric material 44 may be a dielectric-barrier material; and may include one or more high-k components (e.g., aluminum oxide, hafnium dioxide, zirconium oxide, etc.). The term "high-k component" means a component having a dielectric constant greater than the dielectric constant associated with silicon dioxide (i.e., greater than about 3.9). Dielectric material 44 may have a thickness T in a range of, for example, from about 2 nm to about 40 nm. 1 In some embodiments, dielectric material 44 may be considered to be in gap 42 ( Fig. 9 ) is formed as a first lining to narrow the gap.

[0050] Conductive material 46 may include a metal-containing component (eg, a metal nitride, a metal carbide, a metal silicide, etc.); and in some embodiments, may include titanium nitride. Conductive material 46 may have a thickness T in a range from about 2 nm to about 60 nm. 2 In some embodiments, conductive material 46 may be considered to be formed within void 42 as a second liner.

[0051] Conductive material 48 may include a metal; and in some embodiments, may consist essentially of, or completely consist of, one or more of tungsten, tantalum, titanium, cobalt, molybdenum, nickel, ruthenium, and the like.

[0052] In some embodiments, conductive material 48 may be considered a conductive core material, and conductive material 46 may be considered a conductive lining material along an outer peripheral surface 49 of the core material. Lining material 46 includes a different composition than core material 48, and may or may not include the same metal as the core material. In some embodiments, liner material 46 may be considered to include a first metal (e.g., titanium), and core material 48 may be considered to include a second metal (e.g., tungsten).

[0053] In some embodiments, it is contemplated that conductive materials 46 and 48 are configured together to form a gap 42 ( Fig. 9 ) is formed within the conductive structure 50. The conductive structure 50 has a proximal region 52 adjacent to the channel material 26 (ie, close to the channel material 26, or in the vicinity of the channel material 26), and has a distal region 54 adjacent to the gap 40.

[0054] The conductive structure 50 has a vertical thickness T that may be, for example, in the range from about 10 nm to about 400 nm. 3 .

[0055] refer to Fig.11 , removing the distal region 54 of the conductive structure 50 ( Fig.10 ) to form a cavity 56 adjacent to the proximal region 52 of the conductive structure 50.

[0056] The distal region of the conductive structure 50 may be removed using any suitable etch or combination of etches; and in some embodiments, may be removed using nitric acid (HNO 3 ) are removed by one or more etches. In the illustrated embodiment, the etching recesses all of the materials 44, 46, and 48 approximately equally to form a flat (straight) vertical surface 58 extending along all of the materials 44, 46, and 48. In other embodiments, one or more of the materials 44, 46, and 48 may be recessed by unequal amounts relative to one or more of the other materials, as described below with reference to Figure 19-24 Describe in more detail.

[0057] refer to Fig.12, semiconductor material 60 is formed within gap 40 and fills cavity 56. Semiconductor material 60 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist entirely of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, and the like. For example, semiconductor material 60 may include, consist essentially of, or consist entirely of one or more of silicon and germanium. In some embodiments, the semiconductor material may be doped with one or both of carbon and boron at a concentration of at least about 10 15 Atom / cm 3 In some embodiments, the dopant in the semiconductor material 60 may be at least about 10 18 Atom / cm 3 , 10 20 Atom / cm 3 , 10 22 Atom / cm 3 Equal concentration.

[0058] In the illustrated embodiment, semiconductor material 60 only partially fills gap 40. In other embodiments, semiconductor material may completely fill the gap.

[0059] refer to Fig.13 , the semiconductor material 60 is removed from the gap 40 , leaving only the semiconductor material 60 in the gap 56 .

[0060] refer to Fig.14 , semiconductor material 60 is exposed to one or more suitable precursors to convert at least some of the semiconductor material into metal-containing material 62 (i.e., to replace at least some of semiconductor material 60 with metal-containing material 62). In some embodiments, metal-containing material 62 may include, consist essentially of, or consist entirely of one or more of cobalt, molybdenum, nickel, ruthenium, tantalum, titanium, tungsten, and the like.

[0061] In some embodiments, metal-containing material 62 may be formed using one or more metal-halide precursors. For example, in some embodiments, material 62 may include, consist essentially of, or consist entirely of tungsten, and may be formed using a tungsten halide (e.g., tungsten fluoride WF). 6 ) is formed from a precursor. The precursor may be used under any suitable reaction conditions; and in some embodiments, may be used at a temperature of at least about 300° C. and a pressure of approximately atmospheric pressure.

[0062] Material 62 may be a pure metal or may include one or more non-metallic components in addition to the metal. In some embodiments, material 62 may include one or more of boron, carbon, nitrogen, oxygen, germanium, and silicon. Thus, one or more metals in material 62 may be present as metal borides, metal carbides, metal nitrides, metal germanides, metal silicides, and / or metal oxides. Metal nitrides may be formed by incorporating nitriding (nitriding) substances (e.g., NH 3 ) and a metal halide precursor. The metal oxide can be formed by incorporating an oxidizing species (e.g., O 2 and / or 3 ) and a metal halide precursor. The metal carbide can be formed by incorporating a carbon-containing substance (e.g., a carbon halide) and a metal halide precursor during the formation of material 62. The metal boron compound can be formed by incorporating a boron-containing substance (e.g., B) during the formation of material 62. 2 H 6 ) and a metal halide precursor. The metal silicide can be formed by incorporating a silicon-containing substance (e.g., silane) and a metal halide precursor during the formation of the material 62. Alternatively or in addition, one or more of the non-metallic components in the semiconductor material 60 ( Fig.12 ) can initially serve as a dopant. Additionally or alternatively, one or more of the non-metallic components can be a semiconductor material 60 ( Fig.12 ) residues; for example, one or both of silicon and germanium may be residues of semiconductor material 60.

[0063] The metal-containing material 62 is directly against the proximal region 52 of the first conductive structure 50. In some embodiments, Fig.14 The configuration can be viewed as comprising a vertical stack 64 of alternating first levels 14 and second levels 16; wherein the first levels 14 are insulating levels and the second levels 16 are conductive levels. The conductive levels 16 can be viewed as comprising a first region 64 corresponding to the conductive structure 50, and comprising a second region 66 laterally adjacent to the first region 64; wherein the second region 66 corresponds to the metal-containing material 62. The first region 64 and the second region 66 are joined along an interface 65. In Fig.14 In the illustrated embodiment, such interfaces 65 are substantially straight vertical interfaces that extend along the conductive liner material 46 and the conductive core material 48 and along the metal-containing material 62. The term "substantially straight" means straight within reasonable tolerances of manufacturing and measurement.

[0064] The metal-containing material 62 of the second region 66 also directly abuts against the surface of the dielectric-barrier material 44 (ie, the high-k dielectric material); and can be considered to be bonded to the dielectric-barrier material 44 along an interface 67. The interface 67 can be referred to as a second interface to distinguish it from the first interface 65. Fig.14 In the illustrated embodiment, the second interface 67 is a generally straight vertical extension of the first interface 65 .

[0065] In some embodiments, first region 64 of conductive level 16 may be considered to include conductive core material 48 and conductive liner material 46 along upper surface 69 and lower surface 71 of the conductive core material. First region 64 has a first vertical thickness T 3 (Ref. Fig.10 The vertical thickness T described 3 ), wherein such first vertical thickness extends over the conductive liner material 46 and the conductive core material 48. In the illustrated embodiment, the first region 64 extends along the vertical thickness T 3 having two different conductive materials (eg, materials 46 and 48). In other embodiments, first region 64 may be formed along a vertical thickness T 3 Having more than two different conductive materials.

[0066] The second region 66 of the conductive level 16 has a total vertical thickness T t extending along the entire vertical length of the second region 66 . 4 In some embodiments, the vertical thickness T of the second region 66 is 4 The second vertical thickness may be referred to as the second vertical thickness so as to be equal to the first vertical thickness T of the first region 64. 3 The second region 66 has a total vertical thickness T 4 In the illustrated embodiment, the second vertical thickness T 4 Greater than (ie, longer than) the first vertical thickness T 3 . The first vertical thickness T 3 and the second vertical thickness T 4 The length difference between the first vertical thickness T and the second vertical thickness T may be any suitable amount, and in some embodiments, may be in the range of from about 4 nm to about 100 nm. 3 and the second vertical thickness T 4 can be substantially the same as each other (as described below with reference to Fig.18 and accordingly, in some embodiments, the second vertical thickness T 4 It can be said to have at least the first vertical thickness T 3 Roughly the same size.

[0067] Figure 11-14 The processing from the gap 40 ( Fig.13) so that when the semiconductor material is converted to metal-containing material 62, only the semiconductor material is left in cavity 56. In other embodiments, at least some of the semiconductor material may remain in gap 40 to be converted to metal-containing material 62, and then excess metal-containing material 62 may be removed from gap 40, leaving Fig.14 Configuration.

[0068] refer to Fig.15 , the gap 40 is filled with an insulating material 68 (eg, silicon dioxide). In other embodiments, a void may remain in the gap 40 .

[0069] Fig.15 The assembly 10 may be considered a memory device comprising vertically stacked memory cells 70. Each of the memory cells comprises a segment of the first region 64 of the conductive level 16 and a segment of the channel material 26. The segment of the conductive region 64 may be considered a control gate region of the memory cell.

[0070] Fig.15A Show Fig.15 1 is an enlarged view of a region of memory device 10 and illustrates that each of memory cells 70 may include segments of tunneling material 34, charge storage material 36, charge blocking material 38, and dielectric-barrier material 44; as well as segments of channel material 26 and segments of conductive materials 46 and 48 of conductive structure 50.

[0071] Memory cell 70 may be viewed as representing a large number of substantially identical memory cells (where the term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement) that may be fabricated on a memory array; such as a NAND memory array similar to those described above with reference to FIGS. 1-4.

[0072] Second region 66 of conductive level 16 may be considered a track (routing structure, word line region, etc.) that couples memory cell 70 with another circuitry (eg, row decoder circuitry similar to that described above with reference to FIG. 1 ).

[0073] Fig. 15B Show Fig.15 15B-15B, and illustrates that the channel material pillar 28 shown may be one of a plurality of substantially identical channel material pillars disposed between the gaps 40. In some embodiments, the region 72 between the gaps 40 may correspond to a block (or sub-block) of a NAND memory device. The channel material pillars 28 may be arranged in a hexagon within the region 72, and any suitable number of channel material pillars may be packed within this region.

[0074] The uniform metal-containing composition of tracks 66 may enable more efficient routing of electrical signals throughout memory device 10 than may be achieved with conventional memory devices that do not have tracks 66 with uniform metal-containing composition.

[0075] The metal-containing composition of track 66 may be any suitable composition. In some embodiments, core material 48 may be composed of a metal (eg, tungsten), and track 66 may include, consist essentially of, or consist entirely of the same metal.

[0076] Track 66 may include any suitable metal-containing component. In some embodiments, track 66 may include, consist essentially of, or consist entirely of one or more of cobalt, molybdenum, nickel, ruthenium, tantalum, titanium, tungsten, etc. In some embodiments, track 66 may further include one or more of boron, carbon, nitrogen, oxygen, germanium, and silicon.

[0077] The memory cells 70 may be used as part of a NAND memory device. In operation, the charge storage material 36 may be configured to store information in the memory cells 70. The value of the information stored in an individual memory cell 70 (where the term "value" refers to one or more bits) may be based on the amount of charge (e.g., the number of electrons) stored in the charge storage region. The amount of charge within an individual charge storage region may be controlled (e.g., increased or decreased) based at least in part on a voltage value applied to an associated control gate and / or based on a voltage value applied to an associated channel material.

[0078] The tunneling material 34 may be configured to allow for desired tunneling (e.g., transfer) of charge (e.g., electrons) between the charge storage material 36 and the channel material 26. The tunneling material may be configured (i.e., engineered) to achieve selected criteria, such as, but not limited to, equivalent oxide thickness (EOT). The EOT quantifies the electrical properties (e.g., capacitance) of the tunneling material in terms of a representative physical thickness. For example, the EOT may be defined as the thickness of a theoretical silicon dioxide layer required to have the same capacitance density as a given dielectric (e.g., tunneling material 34) without regard to leakage current and reliability.

[0079] Charge blocking material 38 may provide a mechanism to prevent charge from flowing from the charge storage material to the control gate.

[0080] The dielectric barrier material 44 may be used to prevent reverse tunneling of electrons from the control gate toward the charge storage material.

[0081] Fig.14 The processing stage shows that the entire semiconductor material 60 ( Fig.13) is converted to metal-containing material 62 (i.e., replaced with metal-containing material 62). In other embodiments, the conversion to metal-containing material may be incomplete, such that some incompletely converted semiconductor material remains within second region 66 of conductive level 16. For example, Fig.16 An embodiment is shown in which regions 66 each include a first portion 74 laterally adjacent to a second portion 76. The compositions of first portion 74 and second portion 76 may differ from one another. Specifically, first portion 74 may be completely converted to metal-containing material 62 (and in some embodiments, may consist essentially of, or consist entirely of, one or more of cobalt, molybdenum, nickel, ruthenium, tantalum, titanium, tungsten, etc.); and second portion 76 may not be completely converted to metal-containing material and may include a metal and one or more of silicon, germanium, carbon, nitrogen, oxygen, and boron. In some embodiments, first portion 74 and second portion 76 may include the same metal as one another (e.g., tungsten), with portion 74 consisting of such metal and portion 76 including such metal and one or more of silicon, germanium, carbon, nitrogen, oxygen, and boron.

[0082] The boundary between the portions 74 and 76 may be a sudden change boundary or a slope.

[0083] exist Fig.16 In the illustrated embodiment, second portion 76 directly abuts conductive materials 46 and 48 of first region 64 of conductive level 16. In some embodiments, conductive material 48 is a metal-containing material composed of the same metal present in first portion 74. For example, in some embodiments, first portion 74 of region 66 and core material 48 of region 64 may each consist essentially of tungsten, or consist entirely of tungsten, while second portion 76 of region 66 includes tungsten, and one or both of silicon and germanium (i.e., includes tungsten silicide and / or tungsten germanide).

[0084] References Fig.11 The described embodiment shows that all materials 44, 46, and 48 are recessed approximately equally to form cavity 56. In other embodiments, one or more of materials 44, 46, and 48 may be recessed more than another of materials 44, 46, and 48. It may be advantageous to adjust the relative amounts of recessing of materials 44, 46, and 48. Such adjustment may be achieved, at least in part, by adjusting one or more of the nitric acid concentration, temperature, and duration of the etch used to form cavity 56.

[0085] Fig.17 An embodiment is shown in which conductive materials 46 and 48 are recessed and dielectric material 44 is not recessed during formation of cavity 56 .

[0086] Fig.18 Shown in Fig.17 After the processing stage and after the conductive material 62 is formed on Fig.17 The processing stage after that in the chamber 56. Fig.18 The configuration is similar to the reference above Fig.15 The configuration described above, but the vertical thickness T of the second region 66 of the conductive level 16 4 The vertical thickness T of the first region 64 of the conductive level 16 3 About the same.

[0087] Fig.18 The embodiment of FIG. 6 shows that the entire second zone 66 includes the metal-containing material 62. In other embodiments, the second zone 66 may include two or more portions having different compositions, similar to the above reference. Fig.16 Portions 74 and 76 are described.

[0088] Fig.19 Shown in Fig.10 4 and illustrates an embodiment in which materials 44 , 46 , and 48 are all recessed to different levels relative to one another during formation of cavity 56 .

[0089] Fig. 20 Shown in Fig.19 After the processing stage and after the conductive material 62 is formed on Fig.19 The processing stage after that in the chamber 56. Fig. 20 The configuration is similar to the reference above Fig.15 The configuration described above is similar to that described above, but conductive region 64 does not join conductive region 66 at a straight vertical interface. Instead, conductive core material 48 of first region 64 joins metal-containing material 62 of second region 66 along a first vertically extending interface 80, and conductive liner material 46 of first region 64 joins metal-containing material 62 along a second vertically extending interface 82. Second vertically extending interface 82 is horizontally offset relative to first vertically extending interface 80. In some embodiments, first vertically extending interface 80 may be considered to be along a vertical surface of conductive core material 48, and second vertically extending interface 82 may be considered to be along a vertical surface of conductive liner material 46.

[0090] Fig. 20 The configuration also shows that the dielectric-barrier material 44 is joined to the metal-containing material 62 of the second region 66 at a third vertically-extending interface 84 that is horizontally offset relative to the first vertically-extending interface 80 and the second vertically-extending interface 82 .

[0091] It may be desirable to extend the conductive liner material 46 beyond the conductive core material 48 (e.g., Fig. 20 to improve adhesion to the track material 62 in some applications.

[0092] Fig.21 Shows something like Fig. 20 The configuration of the configuration, but the second zone 66 is shown to include the above reference Fig.16 Two portions 74 and 76 are depicted having different compositions.

[0093] Fig. 22 Shown in Fig.10 , and illustrates another embodiment in which materials 44 , 46 , and 48 are all recessed to different levels relative to one another during the formation of cavity 56 .

[0094] Fig.23 Shown in Fig. 22 After the processing stage and after the conductive material 62 is formed on Fig. 22 The processing stage after that in the chamber 56. Fig.23 The configuration is similar to the reference above Fig.15 The configuration described above is similar to that described above, but conductive region 64 does not join conductive region 66 at a straight vertical interface. Instead, conductive core material 48 of first region 64 joins metal-containing material 62 of second region 66 along a first vertically extending interface 80, and conductive liner material 46 of first region 64 joins metal-containing material 62 along a second vertically extending interface 82. Second vertically extending interface 82 is horizontally offset relative to first vertically extending interface 80. In some embodiments, first vertically extending interface 80 may be considered to be along a vertical surface of conductive core material 48, and second vertically extending interface 82 may be considered to be along a vertical surface of conductive liner material 46.

[0095] Fig.23 The configuration also shows that the dielectric-barrier material 44 is joined to the metal-containing material 62 of the second region 66 at a third vertically-extending interface 84 that is horizontally offset relative to the first vertically-extending interface 80 and the second vertically-extending interface 82 .

[0096] It may be desirable to extend the conductive liner material 46 beyond the conductive core material 48 (e.g., Fig.23 to improve adhesion to the track material 62 in some applications.

[0097] Fig.24 Shows something like Fig.23 The configuration of the configuration, but the second zone 66 is shown to include the above reference Fig.16 Two portions 74 and 76 are depicted having different compositions.

[0098] The method described above forms the conductive material 62 of the conductive track 66 by first depositing a semiconductor material 60 (eg, Figure 11-13 ), and then converting the semiconductor material into material 62 (e.g., Fig.14 This can effectively replace semiconductor material 60 with metal-containing material 62. In other embodiments, metal-containing material 62 can be formed in cavity 56 using other suitable processes, including, for example, direct deposition of metal-containing material 62, etc.

[0099] The assemblies and structures discussed above may be used within integrated circuits (the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lamps, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0100] Unless otherwise specified, the various materials, substances, components, etc. described herein may be formed by any suitable method now known or to be developed including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0101] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be used within this disclosure to provide language variations to simplify the premise basis within the appended claims, rather than to indicate any significant chemical or electrical differences.

[0102] Both the terms "electrically connected" and "electrically coupled" may be used in the present disclosure. The terms are considered synonymous. One term in some cases and the other term in other cases may be used in the present disclosure to provide language variations to simplify the premise basis in the appended claims.

[0103] The specific orientations of the various embodiments in the drawings are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The descriptions and appended claims provided herein are directed to any structure having the described relationships between the various features, regardless of whether the structure is in the specific orientation of the figures or rotated relative to such orientation.

[0104] Unless otherwise indicated, the cross-sectional views of the accompanying drawings only show features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawings.

[0105] When a structure is referred to as being "on," "adjacent to," or "against" another structure, the structure may be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly over," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0106] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may or may not extend generally orthogonally relative to an upper surface of a base.

[0107] Some embodiments include an integrated assembly having a vertical stack of alternating insulating levels and conductive levels. The conductive levels have a first region and have a second region laterally adjacent to the first region. The first region includes a conductive core material and includes a conductive liner material along the upper surface and lower surface of the conductive core material. The composition of the conductive liner material is different from the conductive core material. The first regions each have a first vertical thickness extending over the conductive liner material and the conductive core material. The second regions each include a conductive track having a total vertical thickness at least approximately the same as the first vertical thickness. Each of the conductive tracks has a uniform composition along its total vertical thickness.

[0108] Some embodiments include a memory device having a vertical stack of alternating insulating levels and conductive levels. The conductive levels include a first region and a second region laterally adjacent to the first region. The first region has a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second region has a second vertical thickness and has only a single metal-containing material along the second vertical thickness. A dielectric-barrier material is laterally adjacent to the first region. A charge blocking material is laterally adjacent to the dielectric-barrier material. A charge storage material is laterally adjacent to the charge blocking material. A dielectric material is laterally adjacent to the charge storage material. A channel material is laterally adjacent to the dielectric material.

[0109] Some embodiments include a method of forming an integrated assembly. A vertical stack of alternating first and second levels is formed. The first level includes a first material and the second level includes a second material. An opening is formed extending through the stack. A channel material is formed within the opening. A gap is formed extending through the stack, wherein the gap is laterally offset relative to the channel material. After forming the gap, the second material is removed, leaving a void. A first conductive structure is formed within the void. The first conductive structure has a proximal region adjacent to the channel material and has a distal region adjacent to the gap. The distal region is removed to form a cavity adjacent to the proximal region. A second conductive structure is formed within the cavity directly against the proximal region of the first conductive structure.

[0110] As specified, the subject matter disclosed herein has been described in language that is more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: a vertical stack of alternating insulating and conducting levels; as well as The conductive level has a first region and has a second region laterally adjacent to the first region; The first zone includes a conductive core material and includes a conductive lining material along the upper surface and the lower surface of the conductive core material; the composition of the conductive lining material is different from that of the conductive core material; the first zones each have a first vertical thickness extending on the conductive lining material and the conductive core material; the second zones each include a conductive track, the total vertical thickness of the conductive track is at least approximately the same as the first vertical thickness; each of the conductive tracks has at least two portions that are laterally offset relative to each other, wherein one of the at least two portions has a first uniform composition along its total vertical thickness, and wherein another of the at least two portions has a second uniform composition different from the first uniform composition along its total vertical thickness.

2. The integrated assembly of claim 1, wherein the total vertical thickness of the conductive track is greater than the first vertical thickness.

3. The integrated assembly of claim 1, wherein the total vertical thickness of the conductive track is substantially equal to the first vertical thickness.

4. The integrated assembly of claim 1 further comprising a channel material through the vertical stack and including memory cells each including a segment of the first region and a segment of the channel material.

5. The integrated assembly of claim 4 wherein the memory cell further comprises a charge blocking material, a charge storage material, and a dielectric material between the segment of the first region and the segment of the channel material.

6. The integrated assembly of claim 5 wherein the memory cell further comprises a dielectric-barrier material between the section of the first region and the section of the channel material.

7. The integrated assembly of claim 1, wherein the conductive tracks of the second region directly abut the conductive core material and the conductive liner material of the first region.

8. The integrated assembly of claim 7, wherein the conductive core material comprises a first metal, the conductive liner material comprises a second metal, and the uniform composition of the track consists of the first metal.

9. The integrated assembly of claim 8, wherein the first metal is tungsten.

10. The integrated assembly of claim 8, wherein the first metal is tungsten; and wherein the second metal is titanium.

11. The integrated assembly of claim 10, wherein the conductive liner material comprises titanium nitride.

12. An integrated assembly according to claim 7, wherein each of the conductive tracks includes a first portion of the conductive core material and the conductive lining material directly abutting an associated first zone, and includes a second portion laterally offset relative to the associated first zone by the first portion; and wherein the composition of the first portion is different from that of the second portion.

13. An integrated assembly according to claim 12, wherein the second portion is composed of one or more of cobalt, molybdenum, nickel, ruthenium, tantalum, titanium and tungsten; and wherein the first portion includes one or more of metal carbides, metal silicides, metal germanides, metal oxides and metal nitrides.

14. The integrated assembly of claim 13, wherein the second portion consists of tungsten; and wherein the first portion includes tungsten and silicon.

15. The integrated assembly of claim 1, wherein an interface between the first region of the conductive level and the second region of the conductive level is a substantially straight vertical interface extending along the conductive liner material and the conductive core material.

16. An integrated assembly according to claim 1, wherein the interface between the first region of the conductive layer and the second region of the conductive layer includes a first vertical surface extending along the conductive core material and a second vertical surface extending along the conductive liner material; and wherein the second vertical surface is horizontally offset relative to the first vertical surface.

17. An integrated assembly according to claim 1, comprising a high-k dielectric material above and below the first region of the conductive level and directly abutting the conductive liner material; wherein the interface between the first region of the conductive level and the second region of the conductive level is a substantially straight vertical interface extending along the conductive liner material and the conductive core material; wherein the second region of the conductive level directly abuts the high-k dielectric material along a second interface; and wherein the second interface is a substantially straight vertical extension of the substantially straight vertical interface.

18. An integrated assembly according to claim 1, comprising a high-k dielectric material above and below the first region of the conductive level and directly abutting the conductive liner material; wherein the interface between the first region of the conductive level and the second region of the conductive level includes a first vertically extending interface extending along the conductive core material and a second vertically extending interface extending along the conductive liner material; wherein the second region of the conductive level directly abuts the high-k dielectric material along a third vertically extending interface; and wherein the third vertically extending interface is horizontally offset relative to the first and second vertically extending interfaces.

19. A memory device comprising: a vertical stack of alternating insulating and conducting levels; The conductive level comprises a first region and a second region laterally adjacent to the first region; The first region has a first vertical thickness extending between an upper surface and a lower surface and at least two different metal-containing materials along the first vertical thickness; the second region has a second vertical thickness and only a single metal-containing material along the second vertical thickness; a high-k dielectric material along the upper and lower surfaces of the first region and absent from the upper and lower surfaces of the second region, the high-k dielectric material having vertical edges in direct physical contact with the single metal-containing material of the second region; a charge blocking material laterally adjacent to the first region, the charge blocking material being absent along the upper surface and the lower surface of the first region; a charge storage material laterally adjacent to the charge blocking material; a dielectric material laterally adjacent to the charge storage material; and A channel material is laterally adjacent to the dielectric material.

20. The memory device of claim 19, wherein the high-k material is located between the first region and the charge blocking material.

21. The memory device of claim 19, wherein the second vertical thickness is substantially the same as the first vertical thickness.

22. The memory device of claim 19, wherein the second vertical thickness is greater than the first vertical thickness.

23. The memory device of claim 19, wherein the second regions each include only the single metal-containing material.

24. The memory device of claim 23, wherein the single metal-containing material comprises one or more of cobalt, molybdenum, nickel, ruthenium, tantalum, titanium, and tungsten.

25. The memory device of claim 24, the single metal-containing material further comprising one or more of boron, carbon, nitrogen, oxygen, germanium, and silicon.

26. The memory device of claim 19, wherein the second regions each include at least two portions that are laterally adjacent to each other and have different compositions from each other.

27. A memory device according to claim 26, wherein one of the at least two portions includes only the single metal-containing material, wherein the single metal-containing material is composed of a first metal; and wherein the other of the at least two portions includes the first metal, and one or more of silicon, germanium, carbon, nitrogen, oxygen and boron.

28. The memory device of claim 26, wherein one of the at least two portions comprises only the single metal-containing material, wherein the single metal-containing material consists of tungsten; and wherein another of the at least two portions comprises tungsten, and one or both of silicon and germanium.

29. The memory device of claim 28, wherein the other of the at least two portions is directly against the at least two different metal-containing materials of the first region.

30. The memory device of claim 29, wherein one of the at least two different metal-containing materials of the first region consists of tungsten.

31. The memory device of claim 30, wherein another of the at least two different metal-containing materials of the first region consists of titanium nitride.

32. A method of forming an integrated assembly, comprising: forming a vertical stack of alternating first and second levels; The first level comprises a first material and the second level comprises a second material; forming an opening extending through the stack; forming a channel material within the opening; forming a slot extending through the stack, wherein the slot is laterally offset relative to the channel material; After forming the gap, removing the second material to leave a gap; forming a first conductive structure in the gap; The first conductive structure has a proximal region adjacent to the channel material and has a distal region adjacent to the gap; removing the distal region to form a cavity adjacent to the proximal region; forming a second conductive structure within the cavity directly against the proximal region of the first conductive structure; as well as A high-k dielectric material is formed along the upper and lower surfaces of the proximal region of the first conductive structure, the high-k dielectric material is not present on the upper and lower surfaces of the second conductive structure, and the second conductive structure has a vertical thickness that is equal to the combined thickness of the first conductive structure and the high-k dielectric material along the upper and lower surfaces of the first conductive structure.

33. The method of claim 32, wherein forming the second conductive structure comprises: forming a semiconductor material within the cavity; as well as At least some of the semiconductor material is replaced with a metal-containing material.

34. The method of claim 33, wherein the semiconductor material is doped with one or both of carbon and boron.

35. The method of claim 33, wherein the displacing comprises exposing the semiconductor material to a precursor comprising a metal halide.

36. The method of claim 35, wherein the metal halide is a metal fluoride.

37. The method of claim 33, wherein the metal-containing material comprises one or more of cobalt, molybdenum, nickel, ruthenium, tantalum, titanium, and tungsten.

38. A method according to claim 37, wherein the semiconductor material includes one or both of germanium and silicon; and wherein only some of the semiconductor material is replaced by the metal-containing material, while a portion of the semiconductor material in the proximal region adjacent to the first conductive structure is converted into one or both of metal silicide and metal germanide.

39. The method of claim 32, wherein each of the first conductive structures comprises a conductive liner and a conductive core material; wherein the conductive liner is along an outer peripheral surface of the conductive core material.

40. The method of claim 32, wherein prior to forming the first conductive structure within the void, a dielectric-barrier material is formed within the void to narrow the void; and wherein forming the cavity comprises recessing the dielectric-barrier material.

41. The method of claim 32, further comprising forming a charge blocking material, a charge storage material, and a dielectric material within the opening adjacent to the channel material.

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