Display device

Abstract

A display device includes a data line, a first voltage line extending in parallel with the data line, a scan line extending in a direction perpendicular to the data line, a second voltage line extending in parallel with the scan line, and a line extending in parallel with the data line or the scan line and including a segment protruding in a direction perpendicular to an extension direction of the line. A portion of the line in parallel with the scan line overlaps the second voltage line.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0119611, filed with the Korean Intellectual Property Office on September 27, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device. Background Technology

[0003] With the rapid development of the field of displays used to visually represent various information, a variety of displays with excellent characteristics such as thinness, light weight, and low power consumption have been introduced. In recent years, dead zones in displays have been reduced, and the area occupied by the display area has been increased.

[0004] It should be understood that this background section is partly intended to provide useful context for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were not known or understood by one of skill in the art prior to the corresponding valid filing date of the subject matter disclosed herein. Summary of the Invention

[0005] One or more embodiments include a display device in which dead zones or dead spaces can be reduced and pattern recognition in the display area can be prevented.

[0006] Additional aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing embodiments of the present disclosure.

[0007] According to one or more embodiments, a display device may include: a substrate including a display area and a peripheral area outside the display area, wherein a display element is disposed in the display area; a data line disposed in the display area of ​​the substrate; a first voltage line extending parallel to the data line; a scan line extending in a direction perpendicular to the data line; a second voltage line extending parallel to the scan line; and a line disposed in the display area of ​​the substrate and extending parallel to the data line or the scan line, wherein the second voltage line is disposed on a layer between the scan line and the line, and a portion of the line parallel to the scan line overlaps with the second voltage line.

[0008] A line may include segments that protrude in a direction perpendicular to the direction in which the line extends, and segments of a line may be branches.

[0009] The width of the second voltage line can be greater than the width of the line.

[0010] The second voltage line can be separated from the scan line.

[0011] The first voltage line can be disposed on a layer between the scan lines and includes a protrusion that extends in the direction of the scan line and overlaps with the scan line.

[0012] The first voltage line and the second voltage line can be placed on different layers.

[0013] The display device may further include: a first transistor including a first semiconductor layer and a first gate electrode; a second transistor including a second semiconductor layer and a second gate electrode, one end of the second semiconductor layer being electrically connected to the first gate electrode of the first transistor; a node electrode being electrically connected to the first gate electrode of the first transistor and one end of the second semiconductor layer of the second transistor; and an electrode pattern being electrically connected to a first voltage line and overlapping the node electrode, the electrode pattern and the line being disposed on the same layer.

[0014] The display device may further include: a sensing electrode disposed above the line, wherein the sensing electrode may include a grid line, and the grid line may overlap with the end portions of segments of the line.

[0015] According to one or more embodiments, a display device may include: a substrate including a display area and a peripheral area outside the display area, wherein a display element is disposed in the display area; a first data line disposed in the display area of ​​the substrate; a first voltage line extending parallel to the first data line; a scan line extending in a direction perpendicular to the first data line; a second voltage line extending parallel to the scan line; and a line disposed in the display area of ​​the substrate, extending parallel to the first data line, and including a segment protruding in a direction perpendicular to the first data line and overlapping the second voltage line, wherein the second voltage line is disposed on a layer between the scan lines.

[0016] A line segment can be a branch.

[0017] The width of the second voltage line can be greater than the width of the line.

[0018] The second voltage line can be separated from the scan line.

[0019] The first voltage line can be disposed on a layer between the scan lines and includes a protrusion that extends in the direction of the scan line and overlaps with the scan line.

[0020] The first voltage line and the second voltage line can be placed on different layers.

[0021] The display device may further include: a sensing electrode disposed above the line, wherein the sensing electrode may include a grid line, and the grid line may overlap with the end portions of segments of the line.

[0022] The display device may further include a second data line spaced apart from the first data line, wherein the line may be electrically connected to the first data line or the second data line.

[0023] According to one or more embodiments, a display device may include: a substrate including a display area and a peripheral area outside the display area, wherein a display element is disposed in the display area; a data line disposed in the display area of ​​the substrate; a first voltage line extending parallel to the data line; a scan line extending in a direction perpendicular to the data line; a second voltage line extending parallel to the scan line; and a line disposed in the display area of ​​the substrate, extending parallel to the scan line, overlapping the second voltage line, and including a segment protruding in a direction parallel to the data line, wherein the second voltage line is disposed on a layer between the scan lines.

[0024] A line segment can be a branch.

[0025] The width of the second voltage line can be greater than the width of the line.

[0026] The second voltage line can be separated from the scan line.

[0027] The first voltage line can be disposed on a layer between the scan lines and includes a protrusion that extends in the direction of the scan line and overlaps with the scan line.

[0028] The first voltage line and the second voltage line can be placed on different layers.

[0029] The display device may further include: a sensing electrode disposed above the line, wherein the sensing electrode may include a grid line, and the grid line may overlap with the end portions of segments of the line. Attached Figure Description

[0030] The above and other aspects, features and advantages of embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 This is a schematic plan view illustrating an example of a display panel according to an embodiment;

[0032] Figure 2 It is a schematic diagram. Figure 1 A partial concept map of part A;

[0033] Figure 3 yes Figure 2 A magnified plan view of part A';

[0034] Figure 4 This is an equivalent circuit diagram illustrating the arrangement or placement of pixels in a display panel according to an embodiment;

[0035] Figures 5 to 7This is a schematic plan view illustrating an example of a first line according to an embodiment;

[0036] Figure 8 This is a schematic diagram illustrating the layout of electrodes and lines according to an embodiment;

[0037] Figure 9 It is along Figure 8 A schematic cross-sectional view of the display panel taken by line I-I';

[0038] Figures 10A to 10E This is a schematic diagram illustrating a layer-based approach. Figure 8 The layout diagram of the components;

[0039] Figure 11 It is a schematic plan view illustrating the pixel electrode and the shielding component;

[0040] Figure 12 This is a schematic cross-sectional view of a display device according to an embodiment;

[0041] Figure 13 and Figure 14 These are schematic cross-sectional and plan views illustrating the input sensing layer on a display panel according to an embodiment;

[0042] Figures 15A to 15D It is a planar diagram of the layer-based input sensing layer;

[0043] Figure 15E This is a plan view illustrating the layout of the shielding components and the input sensing layer; and

[0044] Figures 16 to 19 This is a plan view illustrating the layout of the first line, the second line, and the sensing electrode according to an embodiment. Detailed Implementation

[0045] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals always refer to the same elements. It should be understood that embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain aspects of the specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0046] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0047] As used herein, unless the context explicitly indicates otherwise, the singular forms “one” and “the” are intended to include the plural forms as well.

[0048] It will be further understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features or elements, but do not exclude the presence or addition of one or more other features or elements.

[0049] It will be understood that when a layer, area, or element is referred to as being "formed" "on" another layer, area, or element, that layer, area, or element can be formed directly or indirectly on the other layer, area, or element. That is, for example, intermediate layers, areas, or elements may exist.

[0050] For ease of illustration, the dimensions of the elements in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the elements in the accompanying drawings are arbitrarily illustrated for ease of illustration, the following embodiments are not limited thereto.

[0051] In this specification, the expression "A and / or B" indicates only A, only B, or both A and B. Throughout the disclosure, the expression "at least one of A and B" indicates only A, only B, or both A and B.

[0052] In the following embodiments, the expression "the line extends in the first direction or the second direction" as used herein can include not only cases where the line extends in a substantially linear shape, but also cases where the line extends in a substantially zigzag or substantially arcuate shape along the first or second direction.

[0053] In the following embodiments, the expression "when viewed in a plan view" as used herein may indicate the view of an object from above, and the expression "when viewed in a schematic cross-sectional view" as used herein may indicate the view of a cross-sectional portion obtained by vertically cutting the object from the side. In the following embodiments, the term "overlap" may include the overlap of "when viewed in a plan view" and "when viewed in a schematic cross-sectional view".

[0054] Additionally, the terms "overlapping" or "overlapping" mean that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlapping" can include layer, stack, facing or confronting, extending over, covering or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "confronting" mean that the first element may be directly or indirectly opposite the second element. In the case where a third element is located between the first and second elements, the first and second elements can be understood as indirectly opposite each other, although still facing each other. When an element is described as "not overlapping" with another element, this can include elements spaced apart from each other, offset from each other, or separated from each other, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art.

[0055] For ease of description, the spatial relative terms “below,” “under,” “down,” “above,” or “upper,” etc., may be used herein to describe the relationship between one element or component and another, as illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to also cover different orientations of the device during use or operation. For example, in the case where the device illustrated in the drawings is flipped, the device placed “below” or “under” another device may be placed “above” the other device. Therefore, the illustrative term “below” can include both lower and upper positions. The device may also be positioned in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0056] Throughout this specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element or “indirectly connected” to the other element with one or more intermediate elements placed between the element and the other element. It will be further understood that when the terms “comprising” and / or “including” are used in this specification, they or may specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0057] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant art and shall not be interpreted in an ideal or overly formal sense unless expressly defined in this specification.

[0058] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When describing embodiments of the present disclosure with reference to the accompanying drawings, the same reference numerals are assigned to the same or corresponding parts.

[0059] Figure 1 This is a schematic plan view of an example of a display panel 10 according to an embodiment. Figure 2 It is a schematic diagram. Figure 1 The concept diagram of part A, and Figure 3 yes Figure 2 A magnified plan view of part A'.

[0060] refer to Figure 1 The display device according to the embodiment may include a display panel 10 including a substrate 100. The display panel 10 may have a display area DA and a peripheral area PA, the peripheral area PA being arranged, disposed, or located outside the display area DA. The substrate 100 may have a display area DA and a peripheral area PA respectively corresponding to the display area DA and the peripheral area PA of the display panel 10.

[0061] The edges of the display area DA can generally have a shape similar to a rectangle or a square. For example... Figure 1 and Figure 2 As illustrated, the first corner CN1 at the edge of the display area DA can have a substantially circular shape. For example, the display area DA may include a first edge E1 and a second edge E2 facing each other, and a third edge E3 and a fourth edge E4 arranged, positioned between the first edge E1 and the second edge E2 and facing each other. The pad area PADA may be adjacent to the fourth edge E4 among the first edge E1 to the fourth edge E4. For example, the first corner CN1, having a substantially circular shape, can connect the first edge E1 to the fourth edge E4. In addition to the first corner CN1, the second corner CN2 at the edge of the display area DA can also have a substantially circular shape. The second corner CN2 can connect the second edge E2 to the fourth edge E4. The display area DA may also have a substantially circular shape in the portion of its edge other than the corners.

[0062] The peripheral region PA may surround the display region DA. The peripheral region PA may be an area without any pixel PXs arranged, placed, or disposed therein. The peripheral region PA may include a pad region PADA, to which various electronic components or printed circuit boards may be electrically attached. Voltage lines supplying power for driving the display elements may be arranged, placed, or disposed in the peripheral region PA. The pad region PADA may include pads. The pads may be electrically connected to a data driver. In an embodiment, the data driver, which can supply data signals, may be arranged, placed, or disposed on a film in a chip-on-film (COF) manner, which may be electrically connected to the pads of the pad region PADA. In one or more embodiments, the data driver may be directly arranged, placed, or disposed on the substrate 100 in a chip-on-glass (COG) or chip-on-plastic (COP) manner.

[0063] Figure 1 This is a plan view illustrating an example of substrate 100 during the manufacturing process of a display device. In the final display device or electronic device such as a smartphone that includes a display device, a portion of substrate 100 may be bent to minimize the area of ​​the peripheral region PA that is recognized by the user.

[0064] like Figure 2 As illustrated in the diagram, the peripheral region PA may include a curved region BA. The curved region BA may be arranged, positioned, or disposed between the pad region PADA and the display region DA. The substrate 100 may be bent within the curved region BA, such that at least a portion of the pad region PADA may be arranged, positioned, or disposed to overlap with the display region DA. The bending direction may be set such that the pad region PADA does not cover the display region DA, and the pad region PADA may be arranged, positioned, or disposed behind the display region DA. Therefore, the user can recognize that the display region DA occupies a large portion of the display device.

[0065] Figure 3 The illustration shows a portion of the first corner CN1. When observed by a user in a normal usage environment, the display device according to the embodiment, or the electronic device including the display device, can be identified as having a substantially circular shape, for example, a substantially arcuate shape. However, as Figure 3 As illustrated in the diagram, in an environment where the first corner CN1 is observed under magnification and viewed as a line with a width of several micrometers or tens of micrometers, the first corner CN1 appears to have a substantially linear shape that bends multiple times in the first direction D1 and the second direction D2. Figure 3As illustrated in the diagram, even when the first corner CN1 can be magnified and appears to have a substantially linear shape with multiple bends, in a typical usage environment, the first corner CN1 can still be identified as having a substantially circular shape, such as a substantially arcuate shape. Therefore, when the first corner CN1 and the second corner CN2 have substantially circular shapes, this can include not only cases where the first corner CN1 and the second corner CN2 have substantially circular shapes, but also cases where the first corner CN1 and the second corner CN2 have substantially linear shapes with multiple bends.

[0066] Pixels PX and signal lines that can apply electrical signals to pixels PX can be arranged, positioned, or set in the display area DA.

[0067] Each pixel PX may include a display element and pixel circuitry driving the display element. For example, the display element may be an organic light-emitting diode (OLED), and the pixel circuitry may include transistors and capacitors. A pixel PX may include a first pixel capable of emitting light of a first color, a second pixel capable of emitting light of a second color, and a third pixel capable of emitting light of a third color. For example, the first pixel may be a red pixel (R), the second pixel may be a green pixel (G), and the third pixel may be a blue pixel (B). However, this disclosure is not limited thereto.

[0068] Signal lines capable of applying electrical signals to a pixel PX may include scan lines SL and data lines DL, etc. Each data line DL may extend in a first direction D1, and each scan line SL may extend in a second direction D2. For example, scan lines SL may be arranged, positioned, or configured in a row, and may transmit scan signals to the pixel PX. For example, data lines DL may be arranged, positioned, or configured in a column, and may transmit data signals to the pixel PX. Each pixel PX may be electrically connected to at least one corresponding scan line SL and at least one corresponding data line DL. However, this disclosure is not limited thereto. Figure 3 As illustrated in the diagram, the data line DL may include a first data line DL1 and a second data line DL2. The first data line DL1 may be a data line electrically connected to the first line 200 described below. The second data line DL2 may be a data line other than the first data line DL1.

[0069] The first line 200 can transmit electrical signals supplied from the pad area PADA to signal lines electrically connected to the pixel PX, and can be arranged, positioned, or placed in the display area DA. For example, the first line 200 can be electrically connected to the first data line DL1, and can transmit data signals supplied from the pads of the pad area PADA to the first data line DL1. Each of the first lines 200 can be arranged, positioned, or placed on a different layer than the scan line SL and data line DL of the pixel PX.

[0070] The first line 200 arranged, positioned or set to the left of the virtual center line VCL and the first line 200 arranged, positioned or set to the right of the virtual center line VCL can be substantially symmetrical with respect to the virtual center line VCL, which passes through the substantially center of the display panel 10 in the second direction D2.

[0071] Each of the first lines 200 may include a first portion 200a and a third portion 200c extending in a first direction D1, and a second portion 200b extending in a second direction D2. The second portion 200b may connect the first portion 200a to the third portion 200c. The first portion 200a, the second portion 200b, and the third portion 200c may be integrally formed. The first portion 200a may be arranged, positioned, or disposed around the virtual center line VCL, and the third portion 200c may be arranged, positioned, or disposed at the first corner CN1 and the second corner CN2. The first portion 200a may be located away from the pad area PADA from the fourth edge E4 facing the pad area PADA and extends in the first direction D1. The second portion 200b may be bent at the first portion 200a to face the first edge E1 or the second edge E2 and extends in the second direction D2. The third portion 200c may be bent at the second portion 200b to face the fourth edge E4 and extends in the first direction D1. However, this disclosure is not limited thereto.

[0072] Depending on the presence or absence of the first line 200, the display area DA can be divided into regions. For example, the display area DA may include a first region S1 in which the first line 200 can be arranged, positioned, or located, and a second region S2 other than the first region S1. The second region S2 may be a region in which the first line 200 may not be arranged, positioned, or located.

[0073] The first region S1 can be divided into sub-regions along the extension direction of the first line 200. For example, the first region S1 may include a first sub-region SS1 in which the first part 200a of the first line 200 is arranged, positioned, or located; a second sub-region SS2 in which the second part 200b of the first line 200 is arranged, positioned, or located; and a third sub-region SS3 in which the third part 200c of the first line 200 is arranged, positioned, or located. The first sub-regions SS1, SS2, and SS3 that can be arranged, positioned, or located to the right of the virtual center line VCL can be substantially symmetrical to the first sub-regions SS1, SS2, and SS3 that can be arranged, positioned, or located to the left of the virtual center line VCL.

[0074] refer to Figure 3 Each first line 200 has a first portion 200a that may be parallel to the second data line DL2 and may be arranged, positioned, or configured to partially overlap with or be adjacent to the second data line DL2. The first portion 200a of each first line 200 may extend parallel to the second data line DL2 located in a column of the column. The second portion 200b of each first line 200 may be parallel to the scan line SL and may be arranged, positioned, or configured to partially overlap with or be adjacent to the scan line SL. The second portion 200b of each first line 200 may extend parallel to the scan line SL located in a row of the row. The third portion 200c of each of the first lines 200 may be parallel to the first data line DL1 and may be arranged, positioned, or configured to partially overlap with the first data line DL1, or may be arranged, positioned, or configured adjacent to the first data line DL1. The third portion 200c of each of the first lines 200 may extend parallel to the first data line DL1 arranged, positioned, or configured in a column of the column. It should be understood that, as those skilled in the art will appreciate, the arrangement of the first portions 200a, the second portions 200b, and the third portions 200c can be any arrangement relative to the data lines and scan lines.

[0075] The first portion 200a of each first line 200 may be arranged, positioned, or placed in a column that is separated from the column of the third portion 200c of each first line 200 by at least one column interval. The first portions 200a of a pair of adjacent first lines 200 may be separated from each other by at least one column interval. The third portions 200c of a pair of adjacent first lines 200 may be separated from each other by at least one column interval. The second portions 200b of a pair of adjacent first lines 200 may be separated from each other by at least one row interval.

[0076] like Figure 3 As shown in the diagram, the first connecting line 203 and the second connecting line 205 can be arranged, positioned, or placed in the peripheral area PA.

[0077] Each of the first lines 200 may have one end electrically connected to the first data line DL1 and the other end electrically connected to the first connection line 203. The first connection line 203 may have one end electrically connected to the other end of the first line 200 and the other end electrically connected to the pads of the pad region PADA. In an embodiment, the first connection line 203 may be a portion in which a first portion 200a of the first line 200 extends toward the peripheral region PA. In one or more embodiments, the first connection line 203 may be a separate line arranged, positioned, or disposed on a layer different from the layer of the first line 200, and may be electrically connected in the peripheral region PA to the first portion 200a of the first line 200. A third portion 200c of the first line 200 may be electrically connected to the first data line DL1 in the contact portion CNT of the peripheral region PA. It should be understood that one or more embodiments are combinable within the spirit and scope of this disclosure.

[0078] The second connection line 205 may have one end electrically connected to the second data line DL2 and the other end electrically connected to the pads in the pad area PADA. In an embodiment, the second connection line 205 may be a portion in which the second data line DL2 extends toward the peripheral area PA. In one or more embodiments, the second connection line 205 may be a separate line arranged, positioned, or disposed on a layer different from the layer of the second data line DL2, and may be electrically connected to the second data line DL2 in the peripheral area PA.

[0079] Figure 4 This is an equivalent circuit diagram illustrating the arrangement, layout, or placement of pixels PX in the display panel 10 according to an embodiment.

[0080] Figure 4The diagram illustrates a configuration in which signal lines SL1, SL2, SL3, ECL and DL, an initialization voltage line VIL, and a power supply voltage line PL are provided for each pixel PX. In one or more embodiments, at least one of the signal lines SL1, SL2, SL3, ECL and DL, the initialization voltage line VIL, and / or the power supply voltage line PL may be shared by neighboring pixels.

[0081] The signal lines may include: a first scan line SL1 that can transmit a first scan signal GW, a second scan line SL2 that can transmit a second scan signal GI, a third scan line SL3 that can transmit a third scan signal GB, a transmit control line ECL that can transmit a transmit control signal EM, and a data line DL that can transmit a data signal DATA. The third scan line SL3 may be the second scan line SL2 of the next row, and the third scan signal GB may be the second scan signal GI of the next row. However, this disclosure is not limited thereto.

[0082] The power supply voltage line PL can transmit the first power supply voltage ELVDD to the first transistor T1, and the initialization voltage line VIL can transmit the initialization voltage VINT used to initialize the first transistor T1 and the organic light-emitting diode OLED.

[0083] The first scan line SL1, the second scan line SL2, the third scan line SL3, the transmit control line ECL, and the initialization voltage line VIL can extend in the second direction D2 and can be spaced apart from each other in each row. The data line DL and the power supply voltage line PL can extend in the first direction D1 and can be spaced apart from each other in each column.

[0084] The pixel circuit PC of pixel PX may include a first transistor T1 to a seventh transistor T7 and a capacitor Cst. The first transistor T1 to the seventh transistor T7 may each be implemented using a thin-film transistor.

[0085] The first transistor T1 can be electrically connected to the power supply voltage line PL via the fifth transistor T5, and can be electrically connected to the organic light-emitting diode (OLED) via the sixth transistor T6. The first transistor T1 can be used as a driving transistor, and can receive the data signal DATA according to the switching operation of the second transistor T2, and can supply the driving current Ioled to the OLED.

[0086] The second transistor T2 can be electrically connected to the first scan line SL1 and the data line DL, and can be turned on in response to the first scan signal GW received through the first scan line SL1 to perform a switching operation to transmit the data signal DATA received through the data line DL to node N.

[0087] The third transistor T3 can be electrically connected to the organic light-emitting diode (OLED) via the sixth transistor T6. The third transistor T3 can be turned on in response to the first scan signal GW received through the first scan line SL1 to connect the first transistor T1.

[0088] The fourth transistor T4 can be turned on in response to the second scan signal GI received through the second scan line SL2, so as to transmit the initialization voltage VINT received from the initialization voltage line VIL to the gate electrode of the first transistor T1, thereby initializing the gate voltage of the first transistor T1.

[0089] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously in response to the transmit control signal EM received through the transmit control line ECL, so as to form a current path and allow the drive current Ioled to flow in the direction from the power supply voltage line PL to the organic light-emitting diode OLED.

[0090] The seventh transistor T7 can be turned on in response to the third scan signal GB received via the third scan line SL3, so as to transmit the initialization voltage VINT received via the initialization voltage line VIL to the organic light-emitting diode OLED, thereby initializing the organic light-emitting diode OLED. The seventh transistor T7 can be omitted.

[0091] Figure 4 The illustration shows an example in which a fourth transistor T4 can be electrically connected to a second scan line SL2 and a seventh transistor T7 can be electrically connected to a separate third scan line SL3. In one or more embodiments, the seventh transistor T7 can be electrically connected to the second scan line SL2 together with the fourth transistor T4.

[0092] The capacitor Cst can be electrically connected to the power supply voltage line PL and the gate electrode of the first transistor T1 to store and maintain a voltage corresponding to the difference between the voltages across the capacitor Cst. Therefore, the voltage applied to the gate electrode of the first transistor T1 can be maintained.

[0093] An organic light-emitting diode (OLED) may include a pixel electrode and a counter electrode, and the counter electrode may receive a second power supply voltage, ELVSS. An OLED may receive a drive current, Ioled, from a first transistor, T1 and emit light to display one or more images.

[0094] Figures 5 to 7 This is a schematic plan view illustrating an example of the first line 200 according to an embodiment. Figure 5 yes Figure 1 A magnified plan view of part B. Figure 6 yes Figure 1 A partially enlarged plan view of part C, and Figure 7 yes Figure 1 A magnified plan view of part D.

[0095] Figure 5 and Figure 6 The illustration shows an example of a portion of the first line 200 arranged, positioned, or placed to the right of the virtual center line VCL. However, the embodiment is not limited to this, and this can be equivalently applied to the portion of the first line 200 arranged, positioned, or placed to the left of the virtual center line VCL. Figures 5 to 7 In this context, pixels can be arranged, positioned, or set within a pixel region (CA) that can be divided by dashed lines. Figures 5 to 7 The illustration shows the first line 200 and the second line 250 arranged, positioned, or set in the pixel regions CA of the first to fourth columns PXCj, PXCj+1, PXCj+2, and PXCj+3, which can be adjacent to each other, as well as the first row PXRi and the second row PXRi+1, which can be adjacent to each other.

[0096] Figure 5 The illustration shows the arrangement, layout, or placement of the first line 200 in a first portion 200a of a first sub-region SS1. However, the embodiment is not limited to this, and this can be equivalently applied to the arrangement, layout, or placement of the first line 200 in a third portion 200c of a third sub-region SS3.

[0097] refer to Figure 5 In the first sub-region SS1, the first portion 200a of the first line 200 may extend in a direction parallel to the first direction D1, and the first portion 200a may include a first branch or segment 211 protruding in the second direction D2.

[0098] The first branch 211 may protrude from the first portion 200a, centered on the first portion 200a of the first line 200. For example, the first branch 211 may protrude from the first portion 200a of the first line 200 extending in the first direction D1 toward at least one of the two sides along the second direction D2. In the first sub-region SS1, a pair of first branches 211 protruding from two adjacent first portions 200a arranged, positioned, or disposed parallel to each other may be arranged, positioned, or disposed on the same line. To prevent short circuits between the first lines 200, the end portions of the first branches 211 extending from two adjacent first portions 200a toward each other may be spaced apart to form a gap. In the first sub-region SS1, the first portions 200a and the first branches 211 may be arranged, positioned, or disposed in a pixel region CA in a predetermined pattern.

[0099] The third portion 200c of the first line 200 in the third sub-region SS3 may also extend in a direction parallel to the first direction D1, and the third portion 200c may include a first branch 211 protruding in the second direction D2.

[0100] The first portion 200a may extend parallel to the second data line DL2, and the third portion 200c may extend parallel to the first data line DL1. The first branch 211 may extend parallel to the scan line SL. The first branch 211 may overlap with the initialization voltage line VIL. The width of the initialization voltage line VIL may be greater than the width of the first branch 211. The initialization voltage line VIL may have a width that covers or completely covers the width of the first branch 211. The initialization voltage line VIL may be arranged, positioned, or disposed on a layer different from the layers of the scan line SL and the first branch 211. For example, the initialization voltage line VIL may be arranged, positioned, or disposed on a layer between the scan line SL and the first branch 211.

[0101] refer to Figure 6 In the second sub-region SS2, the second portion 200b of the first line 200 may extend in a direction parallel to the second direction D2, and the second portion 200b may include a second branch or segment 221 protruding in the first direction D1.

[0102] The second branch 221 may protrude from the second portion 200b of the first line 200, centered on the second portion 200b. For example, the second branch 221 may protrude from the second portion 200b of the first line 200 extending in the second direction D2 toward at least one of the two sides along the first direction D1. In the second sub-region SS2, a pair of second branches 221 protruding from two adjacent second portions 200b toward each other may be arranged, positioned, or placed on the same line. To prevent short circuits between the first lines 200, the end portions of the second branches 221 extending from two adjacent second portions 200b toward each other may be spaced apart to form gaps. In the second sub-region SS2, the second portions 200b and the second branch 221 may be arranged, positioned, or placed in a predetermined pattern within the pixel region CA.

[0103] The second portion 200b of the first line 200 may extend parallel to the scan line SL, and the second branch 221 may extend parallel to either the first data line DL1 or the second data line DL2. The second portion 200b may overlap with the initialization voltage line VIL. The width of the initialization voltage line VIL may be greater than the width of the second portion 200b. The initialization voltage line VIL may have a width that covers or completely covers the width of the second portion 200b. The initialization voltage line VIL may be arranged, positioned, or disposed on a layer different from the layer of the scan line SL and the second portion 200b. For example, the initialization voltage line VIL may be arranged, positioned, or disposed on a layer between the scan line SL and the second portion 200b.

[0104] The first line 200 can be electrically connected to the first data line DL1 and can transmit data signals from the pads of the pad area PADA to the first data line DL1. Since the second portion 200b of the first line 200 can be arranged, positioned, or configured parallel to the scan line SL, the scan signal transmitted to the scan line SL may distort the data signal transmitted to the first line 200. Due to the distortion of the data signal, diagonal stains may appear along the boundary between the second sub-region SS2 and the third sub-region SS3. In an embodiment, the first line 200 may overlap with the initialization voltage line VIL arranged, positioned, or configured on the layer between the first line 200 and the scan line SL, and can receive a constant voltage. Therefore, since the initialization voltage line VIL acts as a shield, it can block signal interference between the first line 200 and the scan line SL, thus minimizing or preventing the occurrence of parasitic capacitance, thereby minimizing or preventing the distortion of the data signal of the first line 200. For example, since the width of the initialization voltage line VIL can be greater than the width of the portion of the first line 200 that overlaps with the initialization voltage line VIL (e.g., the second portion 200b or the first branch 211), the spacing between the first line 200 and the scan line SL can be wider, thereby more effectively blocking signal interference between the first line 200 and the scan line SL.

[0105] refer to Figure 7The second wire 250 can be arranged, positioned, or disposed on the same layer as the first wire 200 in the second region S2. The second wire 250 may comprise the same or similar material as the first wire 200. The second wire 250 may be spaced apart from and electrically isolated from the first wire 200. The second wire 250 may extend in the second direction D2 and may include a third branch or segment 251 protruding in the first direction D1. The third branch 251 may protrude from the second wire 250 with the second wire 250 as its center. For example, the third branch 251 may protrude from the second wire 250 extending in the second direction D2 toward at least one side along the first direction D1. A pair of third branches 251 protruding from two adjacent second wires 250 toward each other in the second region S2 may be arranged, positioned, or disposed on the same line. To prevent short circuits between the second wires 250, the end portions of the third branches 251 extending from two adjacent second wires 250 toward each other may be spaced apart to form a gap.

[0106] The second line 250 may extend parallel to the scan line SL, and the third branch 251 may extend parallel to either the first data line DL1 or the second data line DL2. The second line 250 may overlap with the initialization voltage line VIL. The width of the initialization voltage line VIL may be greater than the width of the second line 250. The initialization voltage line VIL may have a width that covers or completely covers the width of the second line 250. The initialization voltage line VIL may be arranged, positioned, or disposed on a layer different from the layer of the scan line SL and the second line 250. For example, the initialization voltage line VIL may be arranged, positioned, or disposed on a layer between the scan line SL and the second line 250.

[0107] The illustration shows an example in which the patterns of the first branch 211, the second branch 221, and the third branch 251 for each pixel region CA can be the same or similar. In one or more embodiments, the patterns of the first branch 211, the second branch 221, and the third branch 251 can be different for each pixel region CA. For example, the length of the branches or segments and the spacing between facing branches can differ for each pixel region CA.

[0108] The first branch 211 may be a portion protruding and extending from a first portion 200a or a third portion 200c of the first line 200, the second branch 221 may be a portion protruding and extending from a second portion 200b of the first line 200, and the third branch 251 may be a portion protruding and extending from the second line 250. For example, since a branch can be part of a line, the first line 200 may refer to the first line 200 including the first branch 211 and the second branch 221, and the second line 250 may refer to the second line 250 including the third branch 251. However, the embodiments are not limited thereto.

[0109] Since a second line 250, similar to the first line 200 arranged, positioned, or placed in the first region S1, can be arranged, positioned, or placed in the second region S2, the light reflection (or scattering) characteristics become similar. Therefore, the first region S1 and the second region S2 can be identified without distinction.

[0110] like Figures 5 to 7 As illustrated, conductive patterns can be arranged, positioned, or disposed on the same layer as the first line 200 and the second line 250. The conductive patterns may include a first pattern 230. The first pattern 230 can serve as a shielding electrode, preventing signal interference between circuit elements arranged, positioned, or disposed on the lower layer of the first pattern 230 and pixel electrodes arranged, positioned, or disposed on the upper layer of the first pattern 230 in each pixel PX. The first pattern 230 can be electrically connected to a power supply voltage line PL (which can be electrically connected to the pixel PX) and can receive a first power supply voltage ELVDD. The conductive patterns may include a second pattern 240. The second pattern 240 can serve as a bridging electrode, electrically connecting circuit elements arranged, positioned, or disposed on the lower layer of the second pattern 240 to pixel electrodes arranged, positioned, or disposed on the upper layer of the second pattern 240 in each pixel PX.

[0111] Since the first pattern 230 and the second pattern 240 can be provided in the first region S1 and the second region S2, the first region S1 and the second region S2 can be identified differently, and the pattern density can be ensured, thereby providing manufacturing advantages.

[0112] Figure 8 This is a schematic diagram illustrating the layout of electrodes and lines according to an embodiment. Figure 9 It is along Figure 8 A schematic cross-sectional view of the display panel 10 taken by line I-I'. Figures 10A to 10E This is a schematic diagram illustrating a layer-based approach. Figure 8 The layout diagram of the components. Figure 11 This is a schematic plan view illustrating the pixel electrode PE and the shielding member 150.

[0113] exist Figure 8 The left-hand illustration shows the first pixel region CA1 in which the first portion 200a or the third portion 200c of the first line 200 can be arranged, positioned, or placed, and... Figure 8 The right side of the diagram illustrates the second pixel region CA2 in which the second part 200b of the first line 200 or the second line 250 can be arranged, positioned, or placed. Figure 9 The illustration shows the stacking relationship between the elements included in the pixels arranged, positioned or set in the display area DA of the substrate 100 and the lines connected to the pixels PX. Figure 9 Diagram and Figure 8 The diagram shows schematic cross-sections of the first transistor T1, the sixth transistor T6, the capacitor Cst, and the corresponding portions of the organic light-emitting diode (OLED). This will be referenced below. Figures 8 to 11 Described.

[0114] The substrate 100 may comprise various materials such as glass, metal, or plastic. In embodiments, the substrate 100 may be a flexible substrate. For example, the substrate 100 may comprise a polymer resin, such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate 100 may have a multilayer structure comprising an inorganic layer (not shown) and a layer comprising the aforementioned polymer resin. The buffer layer 110 may be arranged, disposed, or disposed on the substrate 100.

[0115] The buffer layer 110 may have a single-layer or multi-layer structure comprising an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. A barrier layer (not shown) that can prevent external air penetration may be included between the substrate 100 and the buffer layer 110. In embodiments, the buffer layer 110 may be omitted.

[0116] The semiconductor layer Act can be arranged, positioned, or disposed on the buffer layer 110. The semiconductor layer Act can include amorphous silicon, polycrystalline silicon, or organic semiconductor materials. The semiconductor layer Act can be bent into various shapes. Figure 10AAs illustrated, the semiconductor layer Act may include the channel region 131a of the first transistor T1, the channel region 131b of the second transistor T2, the channel regions 131c1 and 131c2 of the third transistor T3, the channel regions 131d1 and 131d2 of the fourth transistor T4, the channel region 131e of the fifth transistor T5, the channel region 131f of the sixth transistor T6, and the channel region 131g of the seventh transistor T7. For example, the corresponding channel regions of the first transistor T1 to the seventh transistor T7 may be partial regions of the semiconductor layer Act. Since the channel region 131a of the first transistor T1 may have folds, bends, or curves, the channel region 131a of the first transistor T1 may be formed as long relative to other elements. Therefore, the driving range of the gate voltage applied to the gate electrode can be widened. The channel region 131a of the first transistor T1 may have various shapes, such as, for example, " "", “S”, “M”, and “W”. However, embodiments are not limited thereto, and other shapes may be included within the spirit and scope of this disclosure. The channel region 131g of the seventh transistor T7 may be a portion of the semiconductor layer Act extending from the previous row. For example, Figure 8 The seventh transistor T7 in the diagram can be the seventh transistor T7 of the pixels arranged, positioned, or placed in the previous row.

[0117] The semiconductor layer Act of transistors T1 to T7 can include source and drain regions on both sides of each channel region. For example... Figure 10A As illustrated in the diagram, the semiconductor layer Act may include the source region 176a and drain region 177a of the first transistor T1, the source region 176b and drain region 177b of the second transistor T2, the source region 176c and drain region 177c of the third transistor T3, the source region 176d and drain region 177d of the fourth transistor T4, the source region 176e and drain region 177e of the fifth transistor T5, the source region 176f and drain region 177f of the sixth transistor T6, and the source region 176g and drain region 177g of the seventh transistor T7. In an embodiment, the source region and drain region may be the source electrode and drain electrode, respectively. For example, in Figure 10A In the semiconductor layer Act shown in the diagram, the source and drain electrodes of the first transistor T1 can correspond to the doped source region 176a and the doped drain region 177a near the channel region 131a, respectively. In embodiments, the positions of the source and drain regions can be changed. The first insulating layer 111 can be arranged, disposed, or positioned above the semiconductor layer Act.

[0118] like Figure 10BAs illustrated, the gate electrode 125a of the first transistor T1, the gate electrode 125b of the second transistor T2, the gate electrode 125c (including gate electrodes 125c1 and 125c2) of the third transistor T3, the gate electrode 125d (including gate electrodes 125d1 and 125d2) of the fourth transistor T4, the gate electrode 125e of the fifth transistor T5, the gate electrode 125f of the sixth transistor T6, and the gate electrode 125g of the seventh transistor T7 can be arranged, positioned, or disposed on the first insulating layer 111. The first scan line 121, the second scan line 122, and the emission control line 123 can be arranged, positioned, or disposed on the first insulating layer 111 and extend in the second direction D2. The first scan line 121, the second scan line 122, and the emission control line 123 can be arranged, positioned, or disposed on the same layer as the gate electrodes 125a to 125g of the first transistor T1 to the seventh transistor T7, and can include materials that are the same as or similar to the materials of the gate electrodes 125a to 125g of the first transistor T1 to the seventh transistor T7. The gate electrode 125a of the first transistor T1 can also be used as the lower electrode 125a of the capacitor Cst.

[0119] The gate electrode 125b of the second transistor T2 and the gate electrodes 125c1 and 125c2 of the third transistor T3 can be the portion of the first scan line 121 that intersects with the semiconductor layer Act, or the portion protruding from the first scan line 121. The gate electrodes 125d1 and 125d2 of the fourth transistor T4 and the gate electrode 125g of the seventh transistor T7 can be the portion of the second scan line 122 that intersects with the semiconductor layer Act, or the portion protruding from the second scan line 122. The gate electrode 125e of the fifth transistor T5 and the gate electrode 125f of the sixth transistor T6 can be the portion of the emitter control line 123 that intersects with the semiconductor layer Act, or the portion protruding from the emitter control line 123. The gate electrode 125a of the first transistor T1 can be provided as an island.

[0120] The gate electrodes 125a to 125g of the first transistor T1 to the seventh transistor T7 can be a single layer or multiple layers of at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The second insulating layer 112 can be arranged, disposed, or positioned above the gate electrodes 125a to 125g of the first transistor T1 to the seventh transistor T7.

[0121] like Figure 10CAs shown in the diagram, the upper electrode 127 of the capacitor Cst can be arranged, positioned, or disposed on the second insulating layer 112. An opening 27 can be formed in the upper electrode 127 of the capacitor Cst. Node electrode 174 (e.g.) Figure 10D (As shown in the middle diagram) The lower electrode 125a of capacitor Cst can be electrically connected to the drain region 177c of the third transistor T3 through opening 27. The upper electrode 127 of capacitor Cst can be a single layer or multiple layers comprising at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. Capacitor Cst can share the gate electrode 125a of the first transistor T1 as its lower electrode and can overlap with the first transistor T1.

[0122] The initialization voltage line 124 and the shielding electrode 129 may be arranged, positioned, or disposed on the same layer as the upper electrode 127 of the capacitor Cst on the second insulating layer 112. The initialization voltage line 124 and the shielding electrode 129 may comprise the same or similar material as the upper electrode 127 of the capacitor Cst. The initialization voltage line 124 may extend in the second direction D2. The shielding electrode 129 may overlap with the source region 176b of the second transistor T2 and the source region 176c and drain region 177c of the third transistor T3. The shielding electrode 129 may overlap with the source region 176c and drain region 177c between the two channel regions 131c1 and 131c2 of the third transistor T3.

[0123] The third insulating layer 113 can be arranged, positioned, or disposed on the upper electrode 127, initialization voltage line 124, and shielding electrode 129 of the capacitor Cst.

[0124] The first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be inorganic insulating layers comprising inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0125] like Figure 10DAs shown in the diagram, data lines 171 and power supply lines 172 extending in the first direction D1 can be arranged, positioned, or disposed on the third insulating layer 113. Data line 171 can be electrically connected to the source region 176b of the second transistor T2 via contact holes 164 formed in the first insulating layer 111, second insulating layer 112, and third insulating layer 113. Power supply line 172 can be electrically connected to the source region 176e of the fifth transistor T5 via contact holes 165 formed in the first insulating layer 111, second insulating layer 112, and third insulating layer 113. Power supply line 172 can be electrically connected to the upper electrode 127 of capacitor Cst via contact holes 168 formed in the third insulating layer 113. Power supply line 172 can be electrically connected to the shielding electrode 129 via contact holes 169 formed in the third insulating layer 113. Power supply line 172 may include a protrusion 172a projecting from the power supply line 172 in the extension direction of the second scan line 122. The protrusion 172a of the power supply voltage line 172 can overlap with the second scan line 122. (As along...) Figure 8 As illustrated in the enlarged view of the display panel 10 taken from line II-II', since the protrusion 172a of the power supply voltage line 172 can be arranged, positioned, or placed between the first line 200 and the second scan line 122, and can overlap with the first line 200 and the second scan line 122, the protrusion 172a of the power supply voltage line 172 can prevent electrical signal interference between the second scan line 122 and the portion of the first line 200 parallel to the second scan line 122 (the second portion 200b and the first branch 211), thereby reducing the parasitic capacitance between the first line 200 and the second scan line 122.

[0126] Each of the data line 171 and the power supply line 172 may include materials such as Mo, Al, Cu, or Ti, and may be a single layer or multiple layers. In an embodiment, each of the data line 171 and the power supply line 172 may have a Ti / Al / Ti multilayer structure.

[0127] Various conductive layers can be arranged, positioned, or disposed on the third insulating layer 113. For example, node electrode 174 and connecting electrodes 173 and 175 can be arranged, positioned, or disposed on the third insulating layer 113. One end of node electrode 174 can be electrically connected to the drain region 177c of the third transistor T3 and the drain region 177d of the fourth transistor T4 through contact holes 166 formed in the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113, and the other end of node electrode 174 can be electrically connected to the gate electrode 125a of the first transistor T1 through contact holes 167 formed in the second insulating layer 112 and the third insulating layer 113. For example, the other end of node electrode 174 can be electrically connected to the gate electrode 125a of the first transistor T1 through an opening 27 formed in the upper electrode 127 of capacitor Cst. One end of the connecting electrode 173 can be electrically connected to the initialization voltage line 124 through a contact hole 161 formed in the third insulating layer 113, and the other end of the connecting electrode 173 can be electrically connected to the source region 176d of the fourth transistor T4 through a contact hole 162 formed in the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The connecting electrode 175 can be electrically connected to the drain region 177f of the sixth transistor T6 through a contact hole 163 formed in the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0128] Each of the node electrode 174 and the connecting electrodes 173 and 175 may include Mo, Al, Cu, or Ti, and may be a single layer or multiple layers. In an embodiment, each of the node electrode 174 and the connecting electrodes 173 and 175 may have a Ti / Al / Ti multilayer structure.

[0129] The fourth insulating layer 114 can be arranged, positioned, or disposed on the data line 171 and the power supply line 172. The first line 200 and the second line 250 can be arranged, positioned, or disposed on the fourth insulating layer 114.

[0130] like Figure 10E As shown in the left-hand diagram, the first portion 200a of the first line 200, which can be parallel to the second data line DL2, and the first branch 211, which can be parallel to the second scan line 122 and overlap with the initialization voltage line 124, can be arranged, positioned, or disposed within the first pixel region CA1. Similarly, the third portion 200c of the first line 200, which can be parallel to the first data line DL1, and the first branch 211, which can be parallel to the second scan line 122 and overlap with the initialization voltage line 124, can be arranged, positioned, or disposed within the first pixel region CA1. Figure 10EAs shown in the right-hand diagram, the second portion 200b of the first line 200, which can be parallel to the second scan line 122 and overlap with the initialization voltage line 124, and the second branch 221, which can be parallel to the first data line DL1 or the second data line DL2, can be arranged, positioned, or disposed in the second pixel region CA2. Similarly, the second line 250, which can be parallel to the second scan line 122 and overlap with the initialization voltage line 124, and the third branch 251, which can be parallel to the first data line DL1 or the second data line DL2, can be arranged, positioned, or disposed in the second region S2. For example, the portion of the first line 200 extending in the second direction D2 (e.g., the second portion 200b and the first branch 211) and the second line 250 can overlap with the initialization voltage line 124.

[0131] As along Figure 8 As illustrated in the enlarged view of the display panel 10 taken by line II-II', the initialization voltage line 124 can be arranged, positioned, or disposed on the layer between the first line 200 and the second scan line 122, and on the layer between the second line 250 and the second scan line 122. The initialization voltage line 124 can block electrical signal interference between the first line 200 and the second scan line 122, thereby reducing the parasitic capacitance between the first line 200 and the second scan line 122. The width W1 of the initialization voltage line 124 ( Figure 10C () can be greater than the width W2 of the first line 200 and the second line 250 that overlap with the initialization voltage line 124. Figure 10E The second scan line 122 and the initialization voltage line 124 should be spaced apart from each other. Therefore, when the width W1 of the initialization voltage line 124 is greater than the width W2 of the first line 200, the spacing SD between the first line 200 and the second scan line 122 should be greater than the spacing SD. Figure 8 This can be increased, thereby enhancing the effect of blocking electrical signal interference between the first line 200 and the second scan line 122.

[0132] Each of the first line 200 and the second line 250 may be a single layer or multiple layers comprising at least one of Mo, Al, Cu, Ti, and any alloy thereof. In an embodiment, each of the first line 200 and the second line 250 may have a Ti / Al / Ti multilayer structure. The first line 200 and the second line 250 may overlap at least a portion of the power supply voltage line 172. The first pattern 230 and the second pattern 240 may be arranged, positioned, or disposed on the fourth insulating layer 114. The first pattern 230 and the second pattern 240 may comprise materials that are the same as or similar to the materials of the first line 200 and the second line 250. The first pattern 230 may be electrically connected to the power supply voltage line 172 through the contact hole 58 of the fourth insulating layer 114. The second pattern 240 may be electrically connected to the connecting electrode 175 through the contact hole 54 of the fourth insulating layer 114. The second pattern 240 may be electrically connected to the connecting electrode 175 through the contact hole 59 of the fifth insulating layer 115. Figure 8 The sixth transistor T6 and the pixel electrode PE are electrically connected to each other via the connection electrode 175 and the second pattern 240.

[0133] The fifth insulating layer 115 can be arranged, positioned, or placed on the first line 200, the second line 250, the first pattern 230, and the second pattern 240.

[0134] Each of the fourth insulating layer 114 and the fifth insulating layer 115 may be an organic insulating layer serving as a planarization insulating layer. Each of the fourth insulating layer 114 and the fifth insulating layer 115 may include an organic insulating material, such as a general polymer like polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and any blends thereof. In an embodiment, each of the fourth insulating layer 114 and the fifth insulating layer 115 may include polyimide.

[0135] Despite Figure 8 The middle part is omitted, such as Figure 9 As illustrated in the diagram, an organic light-emitting diode (OLED) used as a display element can be arranged, positioned, or disposed above the fifth insulating layer 115. The OLED may include a pixel electrode (PE), an emitter layer (EL), and a counter electrode (CE).

[0136] The pixel electrode PE can be arranged, disposed, or disposed on the fifth insulating layer 115, and can include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). In an embodiment, the pixel electrode PE can include a reflective film comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or any compound thereof. In an embodiment, the pixel electrode PE can include a layer comprising ITO, IZO, ZnO, or In2O3 above and / or below the reflective film described above. The pixel electrode PE can be electrically connected to the sixth transistor T6 via a second pattern 240 on the fourth insulating layer 114.

[0137] The shielding member 150 can be arranged, positioned, or disposed on the fifth insulating layer 115. For example... Figure 11 As illustrated, the shielding member 150 may extend along a portion of the edge of the pixel electrode PE in the second direction D2 so as not to overlap with the pixel electrode PE when viewed in a plan view, and may be arranged, positioned above and / or below each row. The shielding member 150 may extend linearly or zigzagly along the second direction D2 depending on the arrangement of the pixel electrodes PE in the same row. Figure 11 The illustration shows a shielding member 150 arranged, positioned, or disposed around pixel electrodes PE of the first to third pixels, wherein the pixel electrodes PE are arranged, positioned, or disposed in the first to fourth columns PXC1, PXC2, PXC3, and PXC4 of any row PXRi. The shielding member 150 can be arranged, positioned, or disposed in the non-emitting area NEA (Non-Emitting Area). Figure 9 )middle.

[0138] The shielding member 150 may include a light-shielding metal. For example, the shielding member 150 may include Mo, Al, Cu, or Ti, and may be a single layer or multiple layers comprising the aforementioned materials. In an embodiment, the shielding member 150 may be a multilayer of Ti / Al / Ti. The shielding member 150 may include a material that is the same as or similar to the material of the pixel electrode PE. The shielding members 150 may be spaced apart from each other and may be provided independently for each row. The shielding member 150 may be floating and may be electrically connected to a constant voltage line (e.g., power supply voltage line 172 or initialization voltage line 124, etc.) and may receive a constant voltage.

[0139] A sixth insulating layer 116 may be arranged, disposed, or positioned on the fifth insulating layer 115. Since the sixth insulating layer 116 may have an opening corresponding to each pixel, such as an opening OP exposing a portion of the pixel electrode PE, the sixth insulating layer 116 can serve as a pixel defining layer. The sixth insulating layer 116 may comprise organic materials such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisilane (HMDSO). Alternatively, the sixth insulating layer 116 may comprise inorganic materials. In the following, the opening OP of the sixth insulating layer or the area of ​​the pixel electrode PE exposed by the opening OP of the sixth insulating layer 116 may be defined as the emission region EA. The emission layer EA may be arranged, disposed, or positioned within the emission region EA. Figure 11 As illustrated, the emission regions EA1 of the first pixel, EA2 of the second pixel, and EA3 of the third pixel can have different sizes. The emission regions EA1 and EA3 of the first pixel can have columns that alternately repeat along a first direction D1, and the emission region EA2 of the second pixel can have columns that repeat along a second direction D2. For example, the emission regions EA1, EA2, EA3, and EA2 of the first pixel can repeat along the second direction D2. However, this disclosure is not limited thereto.

[0140] The periphery of the emitting region EA can be a non-emitting region NEA, and the non-emitting region NEA can surround the emitting region EA. For example, the display region DA can include the emitting region EA and the non-emitting region NEA surrounding the emitting region EA, and the peripheral region PA can include the non-emitting region NEA.

[0141] The emitting layer EL can be arranged, positioned, or disposed on the pixel electrode PE exposed by the opening OP of the sixth insulating layer 116. The emitting layer EL can include a high molecular weight organic material or a low molecular weight organic material that emits light of a certain color. The emitting layer EL can be a red emitting layer, a green emitting layer, or a blue emitting layer. In an embodiment, in order to emit white light, the emitting layer EL can have a multilayer structure in which the red emitting layer, the green emitting layer, and the blue emitting layer can be stacked, or a single-layer structure including red emitting material, green emitting material, and blue emitting material. In an embodiment, a first functional layer FL1 below the emitting layer EL and / or a second functional layer FL2 above the emitting layer EL can be included. The first functional layer FL1 and / or the second functional layer FL2 can include an integrated layer covering multiple pixel electrodes PE, or can include layers patterned corresponding to each pixel electrode PE.

[0142] The first functional layer FL1 can be a single layer or multiple layers. For example, when the first functional layer FL1 may include a high molecular weight material, the first functional layer FL1 may be a hole transport layer (HTL) with a single-layer structure, and may include poly(3,4-ethylenedioxythiophene) or polyaniline (PANI). When the first functional layer FL1 may include a low molecular weight material, the first functional layer FL1 may include a hole injection layer (HIL) and an HTL.

[0143] A second functional layer FL2 is not always required. For example, when each of the first functional layer FL1 and the emitter layer EL comprises a high molecular weight material, a second functional layer FL2 can be formed to improve the characteristics of the organic light-emitting diode (OLED). The second functional layer FL2 can be a single layer or multiple layers. The second functional layer FL2 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0144] The counter electrode CE can be arranged, positioned, or disposed facing the pixel electrode PE, with the emitter layer EL situated between the counter electrode CE and the pixel electrode PE. The counter electrode CE can include a conductive material with a low work function. For example, the counter electrode CE can include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or any alloy thereof. In embodiments, the counter electrode CE can include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer comprising the aforementioned materials. The counter electrode CE can be arranged, positioned, or disposed above the emitter layer EL and the sixth insulating layer 116. The counter electrode CE can be a common electrode that can be integrally formed in the organic light-emitting diode (OLED) in the display area DA and can face the pixel electrode PE.

[0145] Encapsulation layer 300 may be arranged, positioned, or disposed above an organic light-emitting diode (OLED). Encapsulation layer 300 may include at least one inorganic encapsulation layer comprising inorganic material and at least one organic encapsulation layer comprising organic material. The organic encapsulation layer may be thicker than the inorganic encapsulation layer. In embodiments, encapsulation layer 300 may have a structure in which a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer may be stacked. The inorganic material of the first inorganic encapsulation layer may be the same as or different from the inorganic material of the second inorganic encapsulation layer. The first inorganic encapsulation layer may have a bilayer structure comprising different inorganic materials. A capping layer (not shown) covering the counter electrode CE may be arranged, positioned, or disposed between the counter electrode CE of the OLED and encapsulation layer 300. In one or more embodiments, a sealing substrate (not shown) may be arranged, positioned, or disposed above the OLED facing the substrate 100 and may be bonded to the substrate 100 outside the display area DA by a sealing member such as a sealant or a frit.

[0146] Figure 12 This is a schematic cross-sectional view of a display device according to an embodiment. Figure 13 and Figure 14 These are schematic cross-sectional and plan views of the input sensing layer 400 on the display panel 10 according to the embodiment. Figures 15A to 15D This is a planar diagram of the layer-based input sensing layer 400. Figure 15E This is a plan view illustrating the layout of the shielding member 150 and the input sensing layer 400.

[0147] refer to Figure 12 The display device according to the embodiment may include a substrate 100 and a circuit layer CL, a display layer DPL, an encapsulation layer 300, and an input sensing layer 400 that may be arranged, disposed, or disposed on the substrate 100. The display panel 10 may include the substrate 100, the circuit layer CL, the display layer DPL, and the encapsulation layer 300.

[0148] The circuit layer CL may include an insulating layer, a conductive layer, and a semiconductor layer. The conductive layer may constitute the pixel circuit PC of the signal lines and / or pixels PX. The display layer DPL may include the organic light-emitting diode (OLED) of the pixels PX. The encapsulation layer 300 may cover the display area DA and may extend outside the display area DA.

[0149] The input sensing layer 400 can be arranged, positioned, or disposed on the encapsulation layer 300. For example... Figure 13 As illustrated in the diagram, the input sensing layer 400 may include a first conductive layer CML1 and a second conductive layer CML2 arranged, positioned, or disposed on the encapsulation layer 300. A lower insulating layer LIL may be arranged, positioned, or disposed between the first conductive layer CML1 and the encapsulation layer 300, an intermediate insulating layer MIL may be arranged, positioned, or disposed between the first conductive layer CML1 and the second conductive layer CML2, and an upper insulating layer HIL may be arranged, positioned, or disposed on the second conductive layer CML2.

[0150] Each of the first conductive layer CML1 and the second conductive layer CML2 may include a metal. For example, each of the first conductive layer CML1 and the second conductive layer CML2 may include Mo, Al, Cu, or Ti, and may be a single layer or multiple layers comprising the above materials. In an embodiment, each of the first conductive layer CML1 and the second conductive layer CML2 may have a Ti / Al / Ti multilayer structure.

[0151] In an embodiment, each of the lower insulating layer LIL and the intermediate insulating layer MIL may be an inorganic insulating layer such as silicon nitride, and the upper insulating layer HIL may be an organic insulating layer. Figure 13The illustration shows that the lower insulating layer LIL can be arranged, positioned, or disposed between the encapsulation layer 300 and the first conductive layer CML1. However, in one or more embodiments, the lower insulating layer LIL can be omitted, and the first conductive layer CML1 can be directly arranged, positioned, or disposed on the encapsulation layer 300 of the display panel 10. In one or more embodiments, each of the lower insulating layer LIL and the intermediate insulating layer MIL can be an organic insulating layer.

[0152] refer to Figure 14 The input sensing layer 400 may have a shape corresponding to the display panel 10. The input sensing layer 400 may have a display area DA and a peripheral area PA corresponding to the display area DA and peripheral area PA of the display panel 10, respectively. The input sensing layer 400 may include a first sensing electrode 410, first signal lines 415-1 to 415-4 connected to the first sensing electrode 410, a second sensing electrode 420, and second signal lines 425-1 to 425-5 connected to the second sensing electrode 420. The input sensing layer 400 may sense external input using mutual capacitance and / or self-capacitance methods.

[0153] The first sensing electrode 410 may be arranged, positioned, or disposed in the first direction D1, and the second sensing electrode 420 may be arranged, positioned, or disposed in the second direction D2. The first sensing electrodes 410 arranged, positioned, or disposed in the first direction D1 may be electrically connected to each other via first connecting electrodes 411 between adjacent first sensing electrodes 410, and may form first sensing lines 410C1 to 410C4. The second sensing electrodes 420 arranged, positioned, or disposed in the second direction D2 may be electrically connected to each other via second connecting electrodes 421 between adjacent second sensing electrodes 420, and may form second sensing lines 420R1 to 420R5. The first sensing lines 410C1 to 410C4 and the second sensing lines 420R1 to 420R5 may intersect each other. For example, the first sensing lines 410C1 to 410C4 and the second sensing lines 420R1 to 420R5 may be perpendicular to each other.

[0154] The first sensing lines 410C1 to 410C4 and the second sensing lines 420R1 to 420R5 can be arranged, positioned, or disposed on the display area DA, and can be electrically connected to the sensing signal pads 440 via the first signal lines 415-1 to 415-4 and the second signal lines 425-1 to 425-5 formed in the peripheral area PA, respectively. The first sensing lines 410C1 to 410C4 can be electrically connected to the first signal lines 415-1 to 415-4, and the second sensing lines 420R1 to 420R5 can be electrically connected to the second signal lines 425-1 to 425-5. Figure 14An exemplary illustration shows four first sensing lines 410C1 to 410C4 and five second sensing lines 420R1 to 420R5.

[0155] like Figure 15A As illustrated in the diagram, the first conductive layer CML1 may include a second connecting electrode 421. Figure 15C As illustrated, the second conductive layer CML2 may include a first sensing electrode 410, a first connecting electrode 411, and a second sensing electrode 420. The first sensing electrodes 410 can be electrically connected to each other via the first connecting electrode 411 formed on the same layer as the first sensing electrode 410. The second sensing electrodes 420 can be electrically connected to each other via the second connecting electrode 421 formed on a different layer than the second sensing electrode 420. Figure 14 and Figure 15B As shown in the figure, the second connection electrode 421 of the second sensing electrodes 420 that are electrically connected to each other can be electrically connected to the second sensing electrodes 420 that are adjacent to each other through the contact hole CH formed in the intermediate insulating layer MIL.

[0156] Each of the first sensing electrode 410 and the second sensing electrode 420 may have a substantially rhomboid shape or other shapes within the spirit and scope of the invention. Figure 15D yes Figure 15C An enlarged plan view of part E.

[0157] like Figure 15D As illustrated, the first sensing electrode 410 may include grid lines 410L of a grid structure containing aperture 410H. Aperture 410H may overlap with the emission region EA of pixel PX. Similarly, the second sensing electrode 420 may include grid lines 420L of a grid structure containing aperture 420H. Aperture 420H may overlap with the emission region EA of pixel PX. The emission region EA may have various sizes. The emission region EA1 of the first pixel, the emission region EA2 of the second pixel, and the emission region EA3 of the third pixel may have different sizes. For example, emission regions that can emit red light, emission regions that can emit green light, and emission regions that can emit blue light may have different sizes. Apertures 410H and 420H with the same size are... Figure 15D The image is shown in the figure. In one or more embodiments, the dimensions of the apertures 410H and 420H overlapping the emission region EA can vary depending on the size of the emission region EA. The grid lines 410L of the first sensing electrode 410 and the grid lines 420L of the second sensing electrode 420 can be arranged, positioned, or disposed in the non-emission region NEA surrounding the emission region EA. The grid lines 410L and 420L can have a linewidth of, for example, a few micrometers.

[0158] like Figure 15EAs shown in the figure, some of the grid lines 410L of the first sensing electrode 410 and the grid lines 420L of the second sensing electrode 420 can overlap with the shielding member 150.

[0159] Figures 16 to 19 This is a plan view illustrating the layout of the first line 200, the second line 250, and the sensing electrode according to an embodiment. Figures 16 to 19 For ease of illustration and explanation, some electrodes and lines have been omitted.

[0160] Figure 16 The diagram illustrates the arrangement, layout, or placement of the first line 200 within the first sub-region SS1 or the third sub-region SS3 of the first region S1 in the display area DA, specifically the first portion 200a or the third portion 200c. (Reference) Figure 16 The emission regions EA1, EA2, and EA3 may overlap with a portion of the first line 200. The grid lines 410L of the first sensing electrode 410 and 420L of the second sensing electrode 420 may overlap with the end portions of the first branches 211 of the first line 200 (e.g., the gaps between the first branches 211). Depending on the positions of the grid lines 410L of the first sensing electrode 410 and 420L of the second sensing electrode 420, a portion of the first line 200 may not have a linear shape but rather a substantially curved shape. Depending on the positions of the grid lines 410L of the first sensing electrode 410 and 420L of the second sensing electrode 420, the first branches 211 may protrude from one side or only one side of the first line 200, or the first branches 211 may protrude from both sides of the first line 200. Depending on the positions of the grid lines 410L of the first sensing electrode 410 and 420L of the second sensing electrode 420L, the length of the first branches 211 and the position of the gaps between the first branches 211 may be varied in the pixel region.

[0161] Figure 17 The illustration shows the arrangement, layout, or placement of the first line 200 in the second part 200b of the second sub-region SS2 of the first region S1, or the arrangement, layout, or placement of the second line 250 in the second region S2 of the display region DA. (Reference) Figure 17The emission regions EA1, EA2, and EA3 may overlap with portions of the first line 200 and the second line 250. The grid lines 410L of the first sensing electrode 410 and 420L of the second sensing electrode 420 may overlap with the end portions of the second branches 221 of the first line 200 (e.g., the gaps between the second branches 221) and the end portions of the third branches 251 of the second line 250 (e.g., the gaps between the third branches 251). Depending on the positions of the grid lines 410L of the first sensing electrode 410 and 420L of the second sensing electrode 420, portions of the first line 200 and the second line 250 may not have a linear shape but rather a substantially curved shape. Depending on the positions of the grid lines 410L of the first sensing electrode 410 and 420L of the second sensing electrode 420, the lengths of the second branches 221 and the third branches 251, as well as the positions of the gaps between the second branches 221 and the third branches 251, may be varied in the pixel region.

[0162] Figure 18 It is a plan view of the portion 200a of the first line 200 that can be bent to the second portion 200b, and Figure 19 This is a plan view of the portion where the second part 200b of the first line 200 can be bent to the third part 200c. (Reference) Figure 18 and Figure 19 The first portion 200a and the second portion 200b of the first line 200, or the third portion 200c and the second portion 200b of the first line 200, can be arranged, positioned, or placed together in a pixel region where the first line 200 can be bent. Figure 16 and Figure 17 Similarly, depending on the positions of the grid lines 410L of the first sensing electrode 410 and the grid lines 420L of the second sensing electrode 420, the length of the first branch 211, the position of the gap between the first branches 211, the length of the second branch 221, and the position of the gap between the second branches 221 can be changed in the pixel region.

[0163] like Figure 18 As illustrated in the diagram, the first portion 200a of the first line 200, parallel to the second data line DL2, and the second portion 200b of the first line 200, parallel to the second scan line 122 and overlapping with the initialization voltage line 124, can be arranged, positioned, or placed in the pixel region CAP1. In the pixel region CAP1, the first portion 200a of the first line 200 can be bent to the second portion 200b. (As shown in the diagram...) Figure 19As shown in the diagram, the third portion 200c of the first line 200, which is parallel to the first data line DL1, and the first branch 211 protruding from the third portion 200c of the first line 200, which is parallel to the second scan line 122 and overlaps with the initialization voltage line 124, can be arranged, positioned, or set in the pixel region CAP2, in which the second portion 200b of the first line 200 can be bent to the third portion 200c.

[0164] According to one or more embodiments, the connecting lines that can transmit data signals to the data lines can be arranged, positioned, or placed in the display area, thereby reducing the dead zone of the display device. As an example, by blocking electrical signal interference between the connecting lines and other lines affecting the connecting lines, variations in the data signals that the connecting lines can electrically connect to the data lines can be minimized, thereby preventing changes in image quality. However, the scope of this disclosure is not limited to these effects.

[0165] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended to be limiting. The description of features or aspects within the embodiments should generally be applied to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: A substrate includes a display area and a peripheral area outside the display area, wherein display elements are disposed in the display area; A data cable is disposed in the display area of ​​the substrate; The first voltage line extends parallel to the data line; The scan line extends in a direction perpendicular to the data line; The second voltage line extends parallel to the scan line; A line is disposed in the display area of ​​the substrate and extends parallel to the data line or the scan line, and includes a segment protruding in a direction perpendicular to the extension direction of the line; The first transistor includes a first semiconductor layer and a first gate electrode; The second transistor includes a second semiconductor layer and a second gate electrode, one end of the second semiconductor layer being electrically connected to the first gate electrode of the first transistor; A node electrode, electrically connected to the first gate electrode of the first transistor and one end of the second semiconductor layer of the second transistor; and An electrode pattern, electrically connected to the first voltage line and overlapping the node electrode, is disposed on the same layer as the line. The second voltage line is disposed on the layer between the scan line and the line, and A portion of the line parallel to the scan line overlaps with the second voltage line.

2. The display device according to claim 1, wherein, The segment of the line is a branch.

3. The display device according to claim 1, wherein the width of the second voltage line is greater than the width of the line.

4. The display device according to claim 1, wherein the second voltage line is spaced apart from the scan line.

5. The display device according to claim 1, wherein the first voltage line is disposed on a layer between the scan line and the line, and includes a protrusion that protrudes in the extension direction of the scan line and overlaps with the scan line.

6. The display device according to claim 1, wherein the first voltage line and the second voltage line are disposed on different layers.

7. The display device according to claim 2, further comprising a sensing electrode disposed above the line, wherein... The sensing electrode includes grid lines, and The grid lines overlap with the end portions of the segments of the lines.

8. A display device, comprising: A substrate includes a display area and a peripheral area outside the display area, wherein display elements are disposed in the display area; A data cable is disposed in the display area of ​​the substrate; The first voltage line extends parallel to the data line; The scan line extends in a direction perpendicular to the data line; The second voltage line extends parallel to the scan line; as well as A line, disposed in the display area of ​​the substrate, extends parallel to the data line and includes a segment that protrudes in a direction perpendicular to the data line and overlaps with the second voltage line. The second voltage line is disposed on the layer between the scan line and the line.

9. The display device according to claim 8, wherein the segment of the line is a branch.

10. The display device according to claim 8, wherein the width of the second voltage line is greater than the width of the line.

11. The display device according to claim 8, wherein the second voltage line is spaced apart from the scan line.

12. The display device of claim 8, wherein the first voltage line is disposed on a layer between the scan line and the line, and includes a protrusion that extends in the extension direction of the scan line and overlaps with the scan line.

13. The display device according to claim 8, wherein the first voltage line and the second voltage line are disposed on different layers.

14. The display device of claim 8, further comprising a sensing electrode disposed above the line, wherein... The sensing electrode includes grid lines, and The grid lines overlap with the end portions of the segments of the lines.

15. The display device according to claim 8, further comprising a second data line, the second data line being spaced apart from the data line. The line is electrically connected to the data line or the second data line.

16. A display device, comprising: A substrate includes a display area and a peripheral area outside the display area, wherein display elements are disposed in the display area; A data cable is disposed in the display area of ​​the substrate; The first voltage line extends parallel to the data line; The scan line extends in a direction perpendicular to the data line; The second voltage line extends parallel to the scan line; as well as A line, disposed in the display area of ​​the substrate, extends parallel to the scan line, overlaps with the second voltage line, and includes a segment protruding in a direction parallel to the data line. The second voltage line is disposed on the layer between the scan line and the line.

17. The display device of claim 16, wherein the segment of the line is a branch.

18. The display device according to claim 16, wherein the width of the second voltage line is greater than the width of the line.

19. The display device of claim 16, wherein the second voltage line is spaced apart from the scan line.

20. The display device of claim 16, wherein the first voltage line is disposed on a layer between the scan line and the line, and includes a protrusion that extends in the extension direction of the scan line and overlaps with the scan line.

21. The display device according to claim 16, wherein the first voltage line and the second voltage line are disposed on different layers.

22. The display device of claim 16, further comprising a sensing electrode disposed above the line, wherein... The sensing electrode includes grid lines, and The grid lines overlap with the end portions of the segments of the lines.

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