Substrate structure and method for manufacturing a semiconductor package

Abstract

The present disclosure relates to a substrate structure and a method for manufacturing a semiconductor package. The substrate structure includes a chip-attachment region and an upper plate edge surrounding the chip-attachment region. The upper plate edge includes an upper stress-release structure and an upper reinforcement structure. The upper stress-release structure surrounds the upper chip-attachment region. The upper reinforcement structure surrounds the upper stress-release structure. A stress-release capability of the upper stress-release structure is greater than a stress-release capability of the upper reinforcement structure. A structural strength of the upper reinforcement structure is greater than a structural strength of the upper stress-release structure.

Description

Technical Field

[0001] This disclosure generally relates to a substrate structure and a method for manufacturing a semiconductor package, and to a substrate structure having a small warpage and a method for manufacturing a semiconductor package using said substrate structure. Background Technology

[0002] Design trends in the semiconductor industry include reducing the weight and miniaturizing semiconductor products. However, technologies used for weight reduction and miniaturization can lead to manufacturing problems. For example, thinner semiconductor substrates are difficult to handle due to greater warpage. Consequently, the yield of such semiconductor products is lower. Therefore, reducing the warpage of semiconductor substrates during the manufacturing process is a critical issue. Summary of the Invention

[0003] According to one aspect of this disclosure, a substrate structure includes a chip attachment region and an upper edge surrounding the chip attachment region. The upper edge includes an upper stress-relieving structure and an upper reinforcing structure. The upper stress-relieving structure surrounds the upper chip attachment region. The upper reinforcing structure surrounds the upper stress-relieving structure. The stress-relieving capacity of the upper stress-relieving structure is greater than the stress-relieving capacity of the upper reinforcing structure. The structural strength of the upper reinforcing structure is greater than the structural strength of the upper stress-relieving structure.

[0004] According to one aspect of this disclosure, a substrate structure includes a first structure and a second structure. The first structure is located in a first region surrounding a chip attachment region. A first occupancy ratio is defined as the ratio of the area of ​​the first structure viewed from above to the area of ​​the entire first region viewed from above. The second structure is located in a second region surrounding the first region. A second occupancy ratio is defined as the ratio of the area of ​​the second structure viewed from above to the area of ​​the entire second region viewed from above. The second occupancy ratio differs from the first occupancy ratio.

[0005] According to another aspect of this disclosure, a method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attachment region and an upper edge surrounding the chip attachment region, the upper edge including an upper stress relief structure and an upper reinforcement structure, the upper stress relief structure surrounding the upper chip attachment region, the upper reinforcement structure surrounding the upper stress relief structure, wherein the stress relief capability of the upper stress relief structure is greater than the stress relief capability of the upper reinforcement structure, and the structural strength of the upper reinforcement structure is greater than the structural strength of the upper stress relief structure; (b) attaching at least one semiconductor chip to the chip attachment region; and (c) forming a package to cover the at least one semiconductor chip. Attached Figure Description

[0006] Figure 1 A top view illustrating a substrate structure according to some embodiments of the present disclosure.

[0007] Figure 2 Explanation along Figure 1 An enlarged cross-sectional view taken from line 2-2 in area "A".

[0008] Figure 3 illustrate Figure 1 A top view of the substrate structure, in which the upper and lower solder resist layers are omitted for clarity.

[0009] Figure 4 illustrate Figure 3 A magnified view of section "B" in the image.

[0010] Figure 5 Explanation along Figure 4 The enlarged cross-sectional view taken from line 5-5 in the figure.

[0011] Figure 6 illustrate Figure 1 A bottom view of the substrate structure, wherein a portion of the lower solder mask covering the lower edge of the board is omitted for clarity.

[0012] Figure 7 A top view illustrating a substrate structure according to some embodiments of the present disclosure.

[0013] Figure 8 Explanation along Figure 7 The enlarged cross-sectional view taken from line 8-8 in section "C".

[0014] Figure 9 A top view illustrating a substrate structure according to some embodiments of the present disclosure.

[0015] Figure 10 A top view illustrating a substrate structure according to some embodiments of the present disclosure.

[0016] Figure 11 An enlarged cross-sectional view illustrating a substrate structure according to some embodiments of the present disclosure.

[0017] Figure 12 illustrate Figure 11 A bottom view of the substrate structure.

[0018] Figure 13 A bottom view illustrating a substrate structure according to some embodiments of the present disclosure.

[0019] Figure 14 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0020] Figure 15 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0021] Figure 16 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0022] Figure 17 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0023] Figure 18 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0024] Figure 19 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0025] Figure 20 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0026] Figure 21 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0027] Figure 22 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0028] Figure 23 A partially enlarged view illustrating a substrate structure according to some embodiments of the present disclosure.

[0029] Figure 24 This describes one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0030] Figure 25 This describes one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0031] Figure 26 This describes one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0032] Figure 27 This describes one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0033] Figure 28 This describes one or more stages of an example of a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0034] Common reference numerals are used throughout the accompanying drawings and detailed descriptions to indicate the same or similar components. This disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Detailed Implementation

[0035] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these components and arrangements are merely examples and are not intended to be limiting. In this disclosure, references to a first feature being formed above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0036] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific situations. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0037] Figure 1 A top view illustrating a substrate structure 1 according to some embodiments of the present disclosure. Figure 2 Explanation along Figure 1 The enlarged cross-sectional view taken from line 2-2 in area "A" is shown. The substrate structure 1 includes a main body 10, a chip attachment area 2, an upper side rail 3, an upper metal layer 16, a bottom layout area 2a, a lower side rail 6, a lower metal layer 17, an upper solder mask layer 13, a lower solder mask layer 15, multiple conductive vias 18, and multiple positioning holes 103. (See attached image.) Figure 1 As shown, substrate structure 1 can be a strip type substrate; however, in other embodiments, substrate structure 1 can be a panel type substrate.

[0038] The material of the body 10 can be a dielectric material, which may include glass-reinforced epoxy resin (e.g., FR4), bismaleimide triazine (BT), epoxy resin, silicon, printed circuit board (PCB) material, glass, ceramic, or photoimageable dielectric (PID) material. The body 10 has an upper surface 101 and a lower surface 102 opposite to the upper surface 101. The upper surface 101 of the body 10 includes a chip attach area 2 and an upper edge 3 surrounding the chip attach area 2. The upper edge 3 may include a first region 31 surrounding the chip attach area 2 and a second region 32 surrounding the first region 31. A second boundary line 30 may be present between the second region 32 and the first region 31. In embodiments, the second boundary line 30 may be an imaginary cutting line. It should be noted that in some embodiments, the second boundary line 30 may be a solid line, that is, it may be an actual boundary.

[0039] The upper metal layer 16 is disposed adjacent to the upper surface 101 of the body 10 and is a patterned metal layer. It includes an upper circuit layer 12 located in the chip attachment region 2, a first structure 4 (e.g., an upper stress relief structure) located in the first region 31, and a second structure 5 (e.g., an upper reinforcement structure) located in the second region 32. In some embodiments, the upper circuit layer 12, the first structure 4 (e.g., the upper stress relief structure), and the second structure 5 (e.g., the upper reinforcement structure) are located in the same layer and are formed simultaneously in one process stage. The material of the upper metal layer 16 (including the upper circuit layer 12, the first structure 4 (e.g., the upper stress relief structure), and the second structure 5 (e.g., the upper reinforcement structure)) may include a metallic material, such as copper, gold, aluminum, or other suitable metals. In embodiments, the upper metal layer 16 may be the topmost metal layer, and one or more metal layers may exist below the upper metal layer 16 and embedded in the body 10.

[0040] The lower surface 102 of the body 10 includes a bottom wiring region 2a and a lower plate edge 6 surrounding the bottom wiring region 2a. The lower plate edge 6 may include a third region 61 surrounding the bottom wiring region 2a and a fourth region 62 surrounding the third region 61. A lower metal layer 17 is disposed adjacent to the lower surface 102 of the body 10 and is a patterned metal layer, which includes a lower circuit layer 14 located in the bottom wiring region 2a, a third structure 7 (e.g., a lower stress relief structure) located in the third region 61, and a fourth structure 8 (e.g., a lower reinforcement structure) located in the fourth region 62. In some embodiments, the lower circuit layer 14, the third structure 7 (e.g., the lower stress relief structure), and the fourth structure 8 (e.g., the lower reinforcement structure) are located in the same layer and are formed simultaneously in a process stage. The material of the lower metal layer 17 (including the lower circuit layer 14, the third structure 7 (e.g., the lower stress relief structure), and the fourth structure 8 (e.g., the lower reinforcement structure)) may include a metallic material, such as copper, gold, aluminum, or other suitable metals. In an embodiment, the lower metal layer 17 may be the bottommost metal layer, and one or more metal layers may exist above the lower metal layer 17 and embedded in the body 10.

[0041] The conductive via 18 can penetrate the main body 10. Therefore, the upper circuit layer 12 is electrically connected to the lower circuit layer 14 through the conductive via 18.

[0042] Chip attachment area 2 is used to attach at least one semiconductor chip 92 ( Figure 24 ) Placed on it. For example Figure 1 As shown, the chip attachment region 2 comprises multiple unit areas 21. For example, there are 2 * 8 = 16 unit areas 21. Each of the unit areas 21 is defined by a plurality of intersecting first boundary lines 20 and is at least one semiconductor chip 92. Figure 24 The location where the first boundary line 20 is placed. In embodiments, the first boundary line 20 may be an imaginary cutting line. It should be noted that in some embodiments, the first boundary line 20 may be a solid line, that is, it may be an actual boundary. Furthermore, after a subsequent molding process, a dicing process (or singulation process) may be performed along the first boundary line 20, such that each of the unit regions 21 is retained in each final product (that is, the semiconductor package 9). Figure 28 ))middle.

[0043] An upper solder mask 13 is located on the upper surface 101 of the body 10 to cover at least a portion of the upper metal layer 16. A lower solder mask 15 is located on the lower surface 102 of the body 10 to cover at least a portion of the lower metal layer 17. A positioning hole 103 penetrates the substrate structure 1 and is used for inserting a positioning pin. Therefore, the position of the substrate structure 1 is ensured during subsequent manufacturing processes.

[0044] Figure 3 illustrate Figure 1 A top view of the substrate structure 1, wherein the upper solder mask layer 13 and the lower solder mask layer 15 are omitted for clarity. Figure 3 As shown, the upper circuit layer 12 can be located in each of the unit regions 21, the first structure 4 (e.g., an upper stress-relieving structure) can be located in the first region 31, and the second structure 5 (e.g., an upper reinforcement structure) can be located in the second region 32. Therefore, the first structure 4 (e.g., the upper stress-relieving structure) surrounds the chip attachment region 2, and the second structure 5 (e.g., the upper reinforcement structure) surrounds the first structure 4 (e.g., the upper stress-relieving structure). The first structure 4 (e.g., the upper stress-relieving structure) is located between the chip attachment region 2 and the second structure 5 (e.g., the upper reinforcement structure).

[0045] Figure 4 illustrate Figure 3 A magnified view of section "B" in the image. Figure 5 Explanation along Figure 4 The image shows an enlarged cross-sectional view taken from line 5-5. The upper circuit layer 12 may include multiple conductive traces 121, multiple conductive pads 122, and multiple conductive fingers 123. In some embodiments, the wiring layout of the upper circuit layer 12 in all unit areas 21 may be identical. In an embodiment, the conductive fingers 123 may have an upper surface finish layer 191, such as an electroplated gold or tin plating. It should be understood that the upper surface finish layer 191 may be omitted. The upper circuit layer 12 is made of a metallic material, the upper stress-relieving structure is made of a metallic material, and the upper reinforcing structure is made of a metallic material. Similarly, the lower circuit layer 14 may include multiple conductive traces 141, multiple conductive pads 142, and multiple external connectors 143 (e.g., ball pads). In an embodiment, the external connectors 143 may have a lower surface finish layer 192, such as an electroplated gold or tin plating. The material of the lower circuit layer 14 can be the same as that of the upper circuit layer 12.

[0046] The first structure 4 (e.g., an upper stress-relieving structure) may be physically connected to the second structure 5 (e.g., an upper reinforcing structure). Alternatively, the first structure 4 (e.g., an upper stress-relieving structure) may be physically separate from the second structure 5 (e.g., an upper reinforcing structure). The first structure 4 (e.g., an upper stress-relieving structure) and the second structure 5 (e.g., an upper reinforcing structure) may have different functions. For example, the first structure 4 (e.g., an upper stress-relieving structure) may be used to relieve stress in the substrate structure 1 to reduce residual stress in the substrate structure 1. That is, the stress-relieving capacity of the first structure 4 (e.g., an upper stress-relieving structure) is greater than that of the second structure 5 (e.g., an upper reinforcing structure). In addition, the second structure 5 (e.g., an upper reinforcing structure) may be used to provide rigidity and stiffness to resist deformation of the substrate structure 1. That is, the structural strength of the second structure 5 (e.g., an upper reinforcing structure) is greater than that of the first structure 4 (e.g., an upper stress-relieving structure). These two functions can reduce warpage of the substrate structure 1 during the manufacturing process.

[0047] The pattern of the first structure 4 (e.g., the upper stress-relieving structure) may be the same as or different from the pattern of the second structure 5 (e.g., the upper reinforcing structure). Figure 4 As shown, the pattern of the first structure 4 (e.g., the upper stress-relief structure) is mesh-shaped when viewed from above. In an embodiment, the first structure 4 (e.g., the upper stress-relief structure) comprises a plurality of strips 40 that intersect each other to form a mesh shape. The width W4 of each of the strips 40 can be from about 0.1 mm to about 0.7 mm. The gap G between two adjacent strips 40 can be from about 0.4 mm to about 2.0 mm. Because the pattern of the first structure 4 (e.g., the upper stress-relief structure) can be grid-shaped, and the strips 40 are not parallel to the edges 11 of the substrate structure 1, most of the stress in the substrate structure 1 can be easily relieved through the first structure 4 (e.g., the upper stress-relief structure). Figure 4 As shown, the strip 40 defines a plurality of voids 43 arranged in two directions (e.g., a first direction 41 and a second direction 42). These two directions (e.g., the first direction 41 and the second direction 42) are neither perpendicular to nor parallel to the edge 11 of the substrate structure 1. Therefore, these two directions (e.g., the first direction 41 and the second direction 42) are the stress relief directions of the first structure 4 (e.g., the upper stress relief structure). The first structure 4 (e.g., the upper stress relief structure) may have at least two stress relief directions.

[0048] The second structure 5 (e.g., an upper reinforcing structure) may comprise at least one row of segments 50, which are generally parallel to the edge 11 of the substrate structure 1. Figure 4As shown, the second structure 5 (e.g., the upper reinforcing structure) may comprise three parallel rows of segments 50, such as multiple first segments 511 in the innermost row 51, multiple second segments 521 in the outermost row 52, ​​and multiple third segments 531 in the middle row 53. Each of the segments 50 (e.g., the first segments 511, the second segments 521, and the third segments 531) may be rectangular or square in shape. The size of each of the first segments 511 is approximately equal to the size of each of the second segments 521, and the size of each of the third segments 531 differs from the size of each of the first segments 511. For example, the width W1 of the first segment 511 may be equal to the width W2 of the second segment 521, which may be approximately 1 mm to approximately 2 mm. The width W3 of the third segment 531 may be equal to the width W2 of the second segment 521, which may be approximately 1 mm to approximately 2 mm. It should be noted that the width of segment 50 (e.g., the width W1 of the first segment 511, the width W2 of the second segment 521, and the width W3 of the third segment 531) is greater than the gap between the innermost row 51 and the middle row 53, or the gap between the outermost row 52 and the middle row 53 of the third segment 531. Furthermore, the length of the first segment 511 may be equal to the length L2 of the second segment 521, which may be approximately 2 mm to 4 mm. The length L3 of the third segment 531 may be approximately 1 mm to approximately 2 mm, and may be less than the length L2 of the second segment 521.

[0049] Furthermore, the first segment 511 is aligned with the second segment 521, while the third segment 531 is not aligned with the first segment 511 and the second segment 521. For example, two adjacent first segments 511 define a first gap 512, two adjacent second segments 521 define a second gap 522, and the center of the third segment 531 is located between the first gap 512 and the second gap 522. In one embodiment, the first gap 512 may be equal to the second gap 522, which may be approximately 0.1 mm to 0.7 mm.

[0050] Since the width of the segments 50 (e.g., the width W1 of the first segment 511, the width W2 of the second segment 521, and the width W3 of the third segment 531) is greater than the width W4 of each of the strips 40, and the segments 50 (e.g., the first segment 511, the second segment 521, and the third segment 531) are arranged parallel to the edge 11 of the substrate structure 1, the second structure 5 (e.g., the upper reinforcing structure) can be a rigid and hard structure.

[0051] like Figure 3 and Figure 4As shown, the first occupancy ratio is defined as the ratio of the area of ​​the solid portion of the first structure 4 (e.g., the upper stress-relief structure) viewed from above to the area of ​​the entire first region 31 viewed from above. The second occupancy ratio is defined as the ratio of the area of ​​the solid portion of the second structure 5 (e.g., the upper reinforcing structure) viewed from above to the area of ​​the entire second region 32 viewed from above. The second occupancy ratio may differ from the first occupancy ratio. For example, the second occupancy ratio may be greater than the first occupancy ratio. In one embodiment, the first structure 4 (e.g., the upper stress-relief structure) contains copper; therefore, the first occupancy ratio is the first residual copper ratio. Similarly, the second structure 5 (e.g., the upper reinforcing structure) contains copper; therefore, the second occupancy ratio is the second residual copper ratio. Therefore, the second residual copper ratio of the second structure 5 (e.g., the upper reinforcing structure) is greater than the first residual copper ratio of the first structure 4 (e.g., the upper stress-relief structure).

[0052] Figure 6 illustrate Figure 1 A bottom view of the substrate structure 1, wherein a portion of the lower solder mask 15 covering the lower board edge 6 is omitted for clarity. The bottom wiring region 2a corresponds to Figure 3 Chip attachment area 2. For example... Figure 6 As shown, the bottom wiring area 2a comprises a plurality of unit areas 21a. Each of the unit areas 21a corresponds to each of the unit areas 21 and is also defined by the first boundary line 20.

[0053] like Figure 2 , Figure 3 and Figure 6 As shown, the third structure 7 (e.g., the lower stress-relieving structure) may correspond to the first structure 4 (e.g., the upper stress-relieving structure). The pattern of the third structure 7 (e.g., the lower stress-relieving structure) may be the same as the pattern of the first structure 4 (e.g., the upper stress-relieving structure). That is, the pattern of the third structure 7 (e.g., the lower stress-relieving structure) may include multiple strips 70 that intersect each other to form a mesh shape.

[0054] The fourth structure 8 (e.g., a lower reinforcing structure) may correspond to the second structure 5 (e.g., an upper reinforcing structure). The pattern of the fourth structure 8 (e.g., the lower reinforcing structure) may be the same as the pattern of the second structure 5 (e.g., the upper reinforcing structure). That is, the fourth structure 8 (e.g., the lower reinforcing structure) may include at least one row of multiple segments 80 that are substantially parallel to the edge 11 of the substrate structure 1. Figure 2As shown, the fourth structure 8 (e.g., the lower reinforcing structure) may comprise three parallel rows of segments 80, such as the innermost first segment 811, the outermost second segment 821, and the middle third segment 831. The size and shape of each of the segments 80 (e.g., the first segment 811, the second segment 821, and the third segment 831) may be substantially equal to the size and shape of each of the segments 50 (e.g., the first segment 511, the second segment 521, and the third segment 531).

[0055] The third structure 7 (e.g., a lower stress-relieving structure) and the fourth structure 8 (e.g., a lower reinforcing structure) may have different functions. For example, the third structure 7 (e.g., a lower stress-relieving structure) can be used to relieve stress on the substrate structure 1. That is, the stress-relieving capacity of the third structure 7 (e.g., a lower stress-relieving structure) is greater than that of the fourth structure 8 (e.g., a lower reinforcing structure). Additionally, the fourth structure 8 (e.g., a lower reinforcing structure) can be used to provide rigidity and stiffness. That is, the structural strength of the fourth structure 8 (e.g., a lower reinforcing structure) is greater than that of the third structure 7 (e.g., a lower stress-relieving structure).

[0056] like Figure 5 and Figure 6 As shown, the third occupancy ratio is defined as the ratio of the area of ​​the solid portion of the third structure 7 (e.g., the lower stress-relief structure) viewed from below to the area of ​​the entire third region 61 viewed from below. The fourth occupancy ratio is defined as the ratio of the area of ​​the solid portion of the fourth structure 8 (e.g., the lower reinforcing structure) viewed from below to the area of ​​the entire fourth region 62 viewed from below. The fourth occupancy ratio may differ from the third occupancy ratio. For example, the fourth occupancy ratio may be greater than the third occupancy ratio. In the embodiment, the third structure 7 (e.g., the lower stress-relief structure) contains copper; therefore, the third occupancy ratio is the residual copper ratio. Similarly, the fourth structure 8 (e.g., the lower reinforcing structure) contains copper; therefore, the fourth occupancy ratio is the residual copper ratio. Therefore, the residual copper ratio of the fourth structure 8 (e.g., the lower reinforcing structure) is greater than the residual copper ratio of the third structure 7 (e.g., the lower stress-relief structure).

[0057] like Figure 5 and Figure 6As shown, the size of the lower plate edge 6 is approximately equal to the size of the upper plate edge 3. The sizes of the third region 61 and the fourth region 62 are approximately equal to the sizes of the first region 31 and the second region 32, respectively. Therefore, the size of the third structure 7 (e.g., the lower stress-relieving structure) of the lower plate edge 6 is approximately equal to the size of the first structure 4 (e.g., the upper stress-relieving structure) of the upper plate edge 3, and the size of the fourth structure 8 (e.g., the lower reinforcing structure) of the lower plate edge 6 is approximately equal to the size of the second structure 5 (e.g., the upper reinforcing structure) of the upper plate edge 3. However, in other embodiments, the size of the lower plate edge 6 may differ from the size of the upper plate edge 3. The sizes of the third region 61 and the fourth region 62 may differ from the sizes of the first region 31 and the second region 32, respectively. Therefore, the size of the third structure 7 (e.g., lower stress relief structure) of the lower plate edge 6 may be different from the size of the first structure 4 (e.g., upper stress relief structure) of the upper plate edge 3, and the size of the fourth structure 8 (e.g., lower reinforcing structure) of the lower plate edge 6 may be different from the size of the second structure 5 (e.g., upper reinforcing structure) of the upper plate edge 3.

[0058] exist Figures 1 to 6 In the embodiments described herein, the upper residual metal ratio is defined as the ratio of the area of ​​the upper metal layer 16 (including the upper circuit layer 12, the first structure 4 (e.g., the upper stress-relief structure), and the second structure 5 (e.g., the upper reinforcement structure)) viewed from above to the area of ​​the entire upper surface 101 of the body 10. Since the upper metal layer 16 may contain copper, the upper residual metal ratio is the upper residual copper ratio. It should be noted that the upper residual metal ratio (e.g., the upper residual copper ratio) can be adjusted by adjusting the first occupancy ratio (first residual copper ratio) of the first structure 4 (e.g., the upper stress-relief structure) and the second occupancy ratio (second residual copper ratio) of the second structure 5. Similarly, the lower residual metal ratio is defined as the ratio of the area of ​​the lower metal layer 17 (including the lower circuit layer 14, the third structure 7 (e.g., the lower stress-relief structure), and the fourth structure 8 (e.g., the lower reinforcement structure)) viewed from below to the area of ​​the entire lower surface 102 of the body 10. Since the lower metal layer 17 may contain copper, the lower residual metal ratio is the lower residual copper ratio. It should be noted that the lower residual metal ratio (e.g., the lower residual copper ratio) can be adjusted by adjusting the third occupancy ratio (third residual copper ratio) of the third structure 7 (e.g., the lower stress-relief structure) and the fourth occupancy ratio (fourth residual copper ratio) of the fourth structure 8. Therefore, the difference between the upper and lower residual metal ratios can be adjusted to be less than or equal to approximately 4%, approximately 3%, approximately 2%, approximately 1%, or approximately 0. This reduces the warpage of the substrate structure 1.

[0059] Furthermore, the upper solder resist cover ratio is defined as the ratio of the area of ​​the upper solder resist layer 13 viewed from above to the area of ​​the entire upper surface 101 of the body 10. The upper solder resist cover ratio is adjustable. Similarly, the lower solder resist cover ratio is defined as the ratio of the area of ​​the lower solder resist layer 15 viewed from below to the area of ​​the entire lower surface 102 of the body 10. The lower solder resist cover ratio is also adjustable. Therefore, the difference between the upper and lower solder resist cover ratios can be adjusted to be less than or equal to approximately 5%, approximately 4%, approximately 3%, approximately 2%, approximately 1%, or approximately 0. This further reduces the warpage of the substrate structure 1.

[0060] Figure 7 A top view illustrating a substrate structure 1a according to some embodiments of the present disclosure. Figure 8 Explanation along Figure 7 An enlarged cross-sectional view taken from line 8-8 in area "C". Except for the structures of the upper solder mask layer 13 and the lower solder mask layer 15, the substrate structure 1a is similar to... Figures 1 to 6 Substrate structure 1 in the example. Figure 7 and Figure 8 As shown, the upper solder mask 13 covers the upper circuit layer 12 and the second structure 5 (e.g., the upper reinforcement structure), but does not cover the first structure 4 (e.g., the upper stress relief structure). That is, the upper solder mask 13 exposes the first structure 4 (e.g., the upper stress relief structure). Similarly, the lower solder mask 15 covers the lower circuit layer 14 and the fourth structure 8 (e.g., the lower reinforcement structure), but does not cover the third structure 7 (e.g., the lower stress relief structure). That is, the lower solder mask 15 exposes the third structure 7 (e.g., the lower stress relief structure).

[0061] Figure 9 This illustration shows a top view of a substrate structure 1b according to some embodiments of the present disclosure. Except for the structures of the upper solder mask layer 13 and the lower solder mask layer 15, the substrate structure 1b is similar to... Figures 1 to 6 Substrate structure 1 in the example. Figure 9 As shown, the upper solder mask 13 covers the upper circuit layer 12 but does not cover the first structure 4 (e.g., the upper stress-relief structure) and the second structure 5 (e.g., the upper reinforcement structure). That is, the upper solder mask 13 exposes the first structure 4 (e.g., the upper stress-relief structure) and the second structure 5 (e.g., the upper reinforcement structure). Similarly, the lower solder mask 15 covers the lower circuit layer 14 but does not cover the third structure 7 (e.g., the lower stress-relief structure) and the fourth structure 8 (e.g., the lower reinforcement structure). That is, the lower solder mask 15 exposes the third structure 7 (e.g., the lower stress-relief structure) and the fourth structure 8 (e.g., the lower reinforcement structure).

[0062] Figure 10 This illustration shows a top view of a substrate structure 1c according to some embodiments of the present disclosure. Except for the structure of the second structure 5c (e.g., the upper reinforcing structure), the substrate structure 1c is similar to... Figure 9 Substrate structure 1b in the example. (e.g., ...) Figure 10 As shown, the pattern of the second structure 5c (e.g., the upper reinforcing structure) is a continuous ring when viewed from above. That is, the second region 32 of the upper plate edge 3 is filled with metallic material. The shape and size of the second structure 5c (e.g., the upper reinforcing structure) are conformal to the shape and size of the second region 32 of the upper plate edge 3. In addition, the first structure 4 (e.g., the upper stress relief structure) is solidly connected to the second structure 5c (e.g., the upper reinforcing structure).

[0063] Figure 11 An enlarged cross-sectional view of a substrate structure 1d according to some embodiments of the present disclosure is shown. Figure 12 illustrate Figure 11 A bottom view of substrate structure 1d. Except for the lower plate edge 6d, the third structure 7d (e.g., lower stress relief structure), and the fourth structure 8d (e.g., lower reinforcement structure), substrate structure 1d is similar to... Figure 10 The substrate structure 1c is shown. The lower edge 6d includes a third region 61d surrounding the bottom wiring region 2a and a fourth region 62d surrounding the third region 61d. The width of the third region 61d is greater than the width of the first region 31, and the width of the fourth region 62d is less than the width of the second region 32. That is, the second boundary 30' on the lower surface 102 of the body 10 is not aligned with the second boundary 30 on the upper surface 101 of the body 10.

[0064] like Figure 12 As shown, the third structure 7d (e.g., the lower stress-relieving structure) is located on the entire third zone 61d and includes intersecting strips 70. Furthermore, the pattern of the fourth structure 8d (e.g., the lower reinforcing structure) appears as a continuous ring when viewed from below. That is, the fourth zone 62d of the lower plate edge 6d is filled with metallic material. Therefore, the size (e.g., width) of the fourth structure 8d (e.g., the lower reinforcing structure) is smaller than the size (e.g., width) of the second structure 5c (e.g., the upper reinforcing structure).

[0065] Figure 13 A bottom view illustrating a substrate structure 1e according to some embodiments of the present disclosure is shown. Except for the structure of the fourth structure 8e (e.g., the lower reinforcement structure), the substrate structure 1e is similar to... Figure 11 and Figure 12 The substrate structure 1d in the image. For example... Figure 13 As shown, the fourth structure 8e (e.g., the lower reinforcing structure) appears as a discontinuous ring when viewed from below. Therefore, the fourth structure 8e (e.g., the lower reinforcing structure) comprises a single row of segments 80e.

[0066] Figure 14 This illustration shows a partially enlarged view of a substrate structure 1f according to some embodiments of the present disclosure. Except for the shape of the third segment 531f in the middle row 53f of the second structure 5f (e.g., the upper reinforcing structure), the substrate structure 1f is similar to... Figures 1 to 6 Substrate structure 1 in the example. Figure 14 As shown in the diagram, the third section 531f is diamond-shaped.

[0067] Figure 15 This illustration shows a partially enlarged view of a substrate structure 1g according to some embodiments of the present disclosure. Except for the shape of the third segment 531g in the middle row 53g of the second structure 5g (e.g., the upper reinforcing structure), the substrate structure 1g is similar to... Figures 1 to 6 Substrate structure 1 in the example. Figure 15 As shown in the image, the third segment, 531g, is star-shaped.

[0068] Figure 16 This illustration shows a partially enlarged view of a substrate structure 1h according to some embodiments of the present disclosure. Except for the shape of the third segment 531h in the middle row 53h of the second structure 5h (e.g., the upper reinforcing structure), the substrate structure 1h is similar to... Figures 1 to 6 Substrate structure 1 in the example. Figure 16 As shown in the figure, the third section 531h is hexagonal in shape.

[0069] Figure 17 This illustration shows a partially enlarged view of a substrate structure 1i according to some embodiments of the present disclosure. Except for the shape of the third segment 531i in the middle row 53i of the second structure 5i (e.g., the upper reinforcing structure), the substrate structure 1i is similar to... Figures 1 to 6 Substrate structure 1 in the example. Figure 17 As shown in the diagram, the third section 531i is cross-shaped.

[0070] Figure 18 This illustration shows a partially enlarged view of a substrate structure 1j according to some embodiments of the present disclosure. The substrate structure 1j is similar to, except for the structure of the second structure 5j (e.g., the upper reinforcing structure). Figures 1 to 6 Substrate structure 1 in the example. Figure 18 As shown, the second structure 5j (e.g., an upper reinforcing structure) comprises a row of segments 50j. The segments 50j are parallel to each other to form a zebra stripe pattern. In an embodiment, the length L5 of the segments 50j is approximately 2 mm to approximately 6 mm, the width W5 of the segments 50j is approximately 1 mm to approximately 2 mm, and the gap g5 between two adjacent segments 50j is approximately 0.1 mm to approximately 0.7 mm.

[0071] Figure 19This illustration shows a partially enlarged view of a substrate structure 1k according to some embodiments of the present disclosure. The substrate structure 1k is similar to, except for the structure of the second structure 5k (e.g., the upper reinforcing structure). Figures 1 to 6 Substrate structure 1 in the example. Figure 19 As shown, the second structure 5k (e.g., an upper reinforcing structure) comprises a row of segments 50k. Each of the segments 50k defines two openings 54. In one embodiment, the length L7 of the segment 50k is about 4 mm to about 8 mm, the width W7 of the segment 50k is about 2 mm to about 6 mm, and the length L8 of the opening 54 is about 2 mm to about 6 mm.

[0072] Figure 20 This illustration shows a partially enlarged view of a substrate structure 1m according to some embodiments of the present disclosure. The substrate structure 1m is similar to, except for the structure of the second structure 5m (e.g., the upper reinforcing structure). Figures 1 to 6 Substrate structure 1 in the example. Figure 20 As shown, the second structure 5m (e.g., the upper reinforcing structure) comprises a row of segments 50m. Each of the segments 50m is "H" shaped. In the embodiment, the length L9 of the segment 50m is approximately 4mm to approximately 8mm.

[0073] Figure 21 This illustration shows a partially enlarged view of a substrate structure 1n according to some embodiments of the present disclosure. The substrate structure 1n is similar to, except for the structure of the second structure 5n (e.g., the upper reinforcing structure). Figures 1 to 6 Substrate structure 1 in the example. Figure 21 As shown, the second structure 5n (e.g., an upper reinforcing structure) comprises a row of segments 50n. Each of the segments 50n is a combination of four bars 55. Two bars 55 intersect each other to form an "X" shape, and the other two bars 55 are located on the top and bottom portions of the "X" shape, respectively. In one embodiment, the length L of the segment 50n is... 10 It is about 4mm to about 8mm, and the width of each of the bars 55 is about 1mm to about 2mm.

[0074] Figure 22 This illustration shows a partially enlarged view of a substrate structure 1p according to some embodiments of the present disclosure. Except for the upper plate edge 3p, the first structure 4p (e.g., an upper stress-relieving structure), and the second structure 5p (e.g., an upper reinforcing structure), the substrate structure 1p is similar to... Figures 1 to 6Substrate structure 1. The upper plate edge 3p includes a first region 31p and a second region 32p surrounding the first region 31p. The width of the second region 32p is greater than the width of the first region 31p. The first structure 4p (e.g., an upper stress-relief structure) may include three parallel rows of segments, such as the first segment 411p of the innermost row 41p, the second segment 421p of the outermost row 42p, and the third segment 431p of the middle row 43p. Additionally, the second structure 5p (e.g., an upper reinforcement structure) may include three parallel rows of segments, such as the first segment 511p of the innermost row 51p, the second segment 521p of the outermost row 52p, and the third segment 531p of the middle row 53p. Therefore, the pattern of the first structure 4p (e.g., an upper stress-relief structure) is substantially the same as the pattern of the second structure 5p (e.g., an upper reinforcement structure). The width W of the first segment 511p of the second structure 5p is... 11 The width W of the second segment 421p, which is greater than the width of the first structure 4p, is... 12 For example, the width W of the first segment 511p of the second structure 5p. 11 The width W of the second segment 421p, which can be greater than that of the first structure 4p, is... 12 1.3 times, 1.5 times or 2 times.

[0075] Figure 23 This illustration shows a partially enlarged view of a substrate structure 1q according to some embodiments of the present disclosure. The substrate structure 1q is similar to, except for the structure of the second structure 5q (e.g., the upper reinforcing structure). Figures 1 to 6 Substrate structure 1 in the example. Figure 23 As shown, the second structure 5q (e.g., the upper reinforcing structure) comprises a plurality of strips 50q that intersect each other to form a mesh shape. Therefore, the pattern of the first structure 4 (e.g., the upper stress-relieving structure) is substantially the same as the pattern of the second structure 5q (e.g., the upper reinforcing structure). The width W of each of the strips 50q is... 13 The gap G' between two adjacent strips 50q can be greater than the width W4 of each of the strips 40, and the gap G' between two adjacent strips 40 can be greater than the gap G between two adjacent strips 40.

[0076] Figures 24 to 28 This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0077] refer to Figure 24 Substrate structure 1 is provided. Substrate structure 1 and... Figures 1 to 6The substrate structure 1 shown is generally the same as that described above. The substrate structure 1 includes a chip attachment region 2 and an upper edge 3 surrounding the chip attachment region 2. The upper edge 3 includes a first structure 4 (e.g., an upper stress-relieving structure) and a second structure 5 (e.g., an upper reinforcement structure). The first structure 4 (e.g., the upper stress-relieving structure) surrounds the chip attachment region 2, and the second structure 5 (e.g., the upper reinforcement structure) surrounds the first structure 4 (e.g., the upper stress-relieving structure). The stress-relieving capability of the first structure 4 (e.g., the upper stress-relieving structure) is greater than that of the second structure 5 (e.g., the upper reinforcement structure). The structural strength of the second structure 5 (e.g., the upper reinforcement structure) is greater than that of the first structure 4 (e.g., the upper stress-relieving structure). In some embodiments, the substrate structure 1 may be composed of... Figures 7 to 23 Substrate structures 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j, 1k, 1m, 1n, and 1p are replaced.

[0078] Next, at least one semiconductor chip 92 is attached to the chip attachment region 2. For example... Figure 24 As shown, the semiconductor chip 92 is electrically connected to the substrate structure 1 via wire bonding. That is, the back side of the semiconductor chip 92 is adhered to the upper solder mask 13 on the upper surface 101 of the body 10, and the active surface of the semiconductor chip 92 is electrically connected to the upper surface treatment layer 191 on the conductive fingers 123 of the upper circuit layer 12 via multiple bonding lines 94. In other embodiments, the semiconductor chip 92 may be electrically connected to the substrate structure 1 via flip-chip bonding.

[0079] refer to Figure 25 A molding mold 90 is provided. The molding mold 90 has a bottom surface 901 and an inner surface 903. The inner surface 903 defines a mold cavity 902. The inner surface 903 can be aligned with a first boundary line 20. Alternatively, the inner surface 903 can be aligned with a position within a first region 31.

[0080] refer to Figure 26The bottom surface 901 of the packaging mold 90 is pressed against the upper edge 3 of the substrate structure 1. Therefore, the chip attachment region 2, the semiconductor chip 92, and the bonding wire 94 are accommodated within the mold cavity 902. In other words, the bottom surface 901 of the packaging mold 90 firmly presses the first structure 4 (e.g., upper stress-relieving structure), the second structure 5 (e.g., upper reinforcing structure), and the first solder mask 13 on the first structure 4 and the second structure 5, thereby forming a closed space in the mold cavity 902. In some embodiments, the first solder mask 13 does not cover the first structure 4 and / or the second structure 5, and the bottom surface 901 of the packaging mold 90 can directly press the first structure 4 and / or the second structure 5.

[0081] refer to Figure 27 Package 96 (e.g., molding compound) is formed or filled in mold cavity 902 to cover chip attachment region 2, semiconductor chip 92, and bonding line 94. During the molding process, the pattern of first structure 4 (e.g., upper stress relief structure) prevents package 96 from overflowing. Package 96 is then cured. Next, the packaging mold 90 is removed.

[0082] refer to Figure 28 A monomerization process is performed along the first boundary line 20 to form multiple semiconductor packages 9. Each semiconductor package 9 contains a unit region 21. In addition, the upper edge 3 (and the lower edge 6) are discarded.

[0083] As used herein, the terms “generally,” “approximately,” “about,” and “approximately” are used to refer to and explain minor variations. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, the thickness of a film or layer being “generally uniform” may refer to a standard deviation of the average thickness of the film or layer less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces that are within 50 μm along the same plane (e.g., within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane). If, for example, two components overlap or overlap within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm, then the two components can be considered "substantially aligned." If the angle between two surfaces or components is, for example, 90° ± 10° (e.g., ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°), then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "substantially," "substantially," "approximately," and "about" can refer to situations where the event or situation occurs precisely or very approximately.

[0084] In the description of some embodiments, the component set "on" another component can cover a situation where the former component is directly on the latter component (e.g., in physical contact with the latter component) and a situation where one or more intervening components are located between the former component and the latter component.

[0085] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It is understood that this range format is used for convenience and brevity, and should be flexibly interpreted to include not only the numerical values ​​that are explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0086] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between process reproductions in this disclosure and actual apparatuses due to variables such as manufacturing processes. Other embodiments of this disclosure may exist that are not specifically described. This specification and the accompanying drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it will be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A substrate structure comprising: Chip attachment area; and The upper edge of the plate surrounds the chip attachment area and includes: An upper stress-relief structure surrounds the chip attachment area; and An upper reinforcing structure surrounds the upper stress-relieving structure, wherein the stress-relieving capacity of the upper stress-relieving structure is greater than the stress-relieving capacity of the upper reinforcing structure, and the structural strength of the upper reinforcing structure is greater than the structural strength of the upper stress-relieving structure, wherein the upper reinforcing structure comprises at least one row of segments.

2. The substrate structure according to claim 1, wherein the upper stress relief structure has at least two stress relief directions, and the stress relief directions are neither perpendicular to nor parallel to the edge of the substrate structure.

3. The substrate structure according to claim 1, wherein the upper stress relief structure comprises a plurality of strips that intersect each other to form a mesh shape.

4. The substrate structure according to claim 1, wherein the pattern of the upper reinforcing structure is a continuous ring when viewed from above.

5. The substrate structure of claim 1, wherein the at least one row of segments comprises a first segment of the innermost row, a second segment of the outermost row, and a third segment of the middle row; wherein the first segment is aligned with the second segment, and the third segment is not aligned with the first segment.

6. The substrate structure according to claim 1, wherein the upper stress relief structure comprises copper, the upper reinforcement structure comprises copper, and the residual copper ratio of the upper reinforcement structure is greater than the residual copper ratio of the upper stress relief structure.

7. The substrate structure according to claim 1, further comprising an upper solder resist layer covering the upper reinforcing structure.

8. The substrate structure of claim 1, further comprising a lower plate edge opposite to the upper plate edge, wherein the lower plate edge comprises: The lower stress relief structure corresponds to the upper stress relief structure; and A lower reinforcing structure surrounds the lower stress-relieving structure, wherein the stress-relieving capacity of the lower stress-relieving structure is greater than the stress-relieving capacity of the lower reinforcing structure, and the structural strength of the lower reinforcing structure is greater than the structural strength of the lower stress-relieving structure.

9. The substrate structure according to claim 8, further comprising: The main body has an upper surface and a lower surface opposite to the upper surface; An upper metal layer, disposed adjacent to the upper surface of the body, includes an upper circuit layer, an upper stress-relieving structure, and an upper reinforcement structure, wherein the upper circuit layer is located in the chip attachment region; wherein the upper residual metal ratio is defined as the ratio of the area of ​​the upper metal layer to the area of ​​the entire upper surface of the body; and A lower metal layer is disposed adjacent to the lower surface of the body and includes a lower circuit layer, a lower stress relief structure, and a lower reinforcement structure, wherein the lower circuit layer is disposed opposite to the upper circuit layer; wherein the lower residual metal ratio is defined as the ratio of the area of ​​the lower metal layer to the area of ​​the entire lower surface of the body, and the difference between the upper residual metal ratio and the lower residual metal ratio is less than or equal to 4%.

10. The substrate structure according to claim 1, further comprising: The main body has an upper surface and a lower surface opposite to the upper surface; An upper metal layer is disposed adjacent to the upper surface of the main body and includes an upper circuit layer, an upper stress relief structure, and an upper reinforcement structure, wherein the upper circuit layer is located in the chip attachment region; A lower metal layer is disposed adjacent to the lower surface of the main body and includes a lower circuit layer, a lower stress relief structure and a lower reinforcement structure. The lower circuit layer is disposed opposite to the upper circuit layer, and the lower reinforcement structure surrounds the lower stress relief structure. An upper solder resist layer covering at least a portion of the upper metal layer, wherein the upper solder resist coverage ratio is defined as the ratio of the area of ​​the upper solder resist layer to the area of ​​the entire upper surface of the body; and A lower solder resist layer that covers at least a portion of the lower metal layer, wherein the lower solder resist coverage ratio is defined as the ratio of the area of ​​the lower solder resist layer to the area of ​​the entire lower surface of the body, and the difference between the upper solder resist coverage ratio and the lower solder resist coverage ratio is less than or equal to 5%.

11. A substrate structure comprising: A first structure is located in a first region surrounding the chip attachment area, wherein a first occupancy ratio is defined as the ratio of the area of ​​the first structure as viewed from above to the area of ​​the entire first region as viewed from above, wherein the first structure comprises a plurality of strips that intersect each other to form a mesh shape. and A second structure is located in a second region surrounding the first region, wherein the second occupancy ratio is defined as the ratio of the area of ​​the second structure as viewed from above to the area of ​​the entire second region as viewed from above, and the second occupancy ratio is different from the first occupancy ratio.

12. The substrate structure of claim 11, wherein the second occupancy ratio is greater than the first occupancy ratio.

13. The substrate structure of claim 11, wherein the second structure comprises at least one row of segments.

Images