Device structure and method of manufacturing the same

Abstract

The present disclosure relates to a device structure and a method for manufacturing a device structure. The device structure includes a stack structure, a dielectric material, and an electrode via. The stack structure includes a first metal oxide layer, a second metal oxide layer, and a metal layer. The second metal oxide layer is opposite the first metal oxide layer. The metal layer is interposed between the first metal oxide layer and the second metal oxide layer. The dielectric material traverses the first metal oxide layer. The electrode via traverses the dielectric material and is electrically connected to the metal layer.

Description

Technical Field

[0001] This disclosure relates to a device structure and a method of manufacturing it, and to a device structure including an electrode via and a method for manufacturing the device structure. Background Technology

[0002] Fabrication of embeddable passive components is typically based on multi-layer materials. For example, multi-layer materials can be used to form embedded capacitors. To form the anode and cathode of an embedded capacitor, numerous through holes are needed to create conductive vias. Laser drilling is commonly used to create these through holes because laser energy can penetrate the metal oxide layer and dielectric layer of the multi-layer material. During laser drilling, the laser energy creates a lower opening for the through hole after penetrating the metal oxide layer, and simultaneously creates a higher opening for the through hole in the dielectric layer. However, the laser energy is too high for the dielectric layer; therefore, when the lower opening reaches the desired size, the upper opening will be larger than the desired size due to over-etching of the upper portion of the dielectric layer by the higher laser energy. Summary of the Invention

[0003] In some embodiments, a device structure includes a stacked structure, a dielectric material, and an electrode via. The stacked structure includes a first metal oxide layer, a second metal oxide layer, and a metal layer. The second metal oxide layer is opposite to the first metal oxide layer. The metal layer is inserted between the first metal oxide layer and the second metal oxide layer. The dielectric material penetrates the first metal oxide layer. The electrode via penetrates the dielectric material and is electrically connected to the metal layer.

[0004] In some embodiments, a device structure includes a stacked structure, a dielectric material, electrode vias, and a first redistribution structure. The stacked structure includes a first metal oxide layer, a second metal oxide layer, and a metal layer. The second metal oxide layer is opposite to the first metal oxide layer. The metal layer is inserted between the first metal oxide layer and the second metal oxide layer. The dielectric material penetrates the first metal oxide layer. The electrode vias penetrate the dielectric material and are electrically connected to the metal layer. The first redistribution structure is disposed on the stacked structure and is electrically connected to the stacked structure.

[0005] In some embodiments, a method for manufacturing a device structure includes: (a) providing a stacked structure comprising: a first metal oxide layer; a second metal oxide layer opposite to the first metal oxide layer; a metal layer inserted between the first metal oxide layer and the second metal oxide layer; a first electrode structure disposed adjacent to the first metal oxide layer; and a first dielectric structure covering the first electrode structure; (b) forming at least one central through-hole penetrating the first dielectric structure, the first electrode structure, and the first metal oxide layer to expose a portion of the metal layer; (c) forming a dielectric material in the central through-hole and on the exposed portion of the metal layer; (d) forming a central opening penetrating the dielectric material to expose a portion of the exposed portion of the metal layer; and (e) forming electrode vias in the central opening and on the exposed portion of the metal layer. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure can be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 Cross-sectional views showing the apparatus structure of some embodiments of this disclosure.

[0008] Figure 2 Cross-sectional views showing the apparatus structure of some embodiments of this disclosure.

[0009] Figure 3 Cross-sectional views showing the apparatus structure of some embodiments of this disclosure.

[0010] Figure 4 Cross-sectional views showing the apparatus structure of some embodiments of this disclosure.

[0011] Figure 5 Cross-sectional views showing the apparatus structure of some embodiments of this disclosure.

[0012] Figure 6 Cross-sectional views showing the apparatus structure of some embodiments of this disclosure.

[0013] Figure 7 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0014] Figure 8 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0015] Figure 9This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0016] Figure 10 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0017] Figure 11 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0018] Figure 12 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0019] Figure 13 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0020] Figure 14 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0021] Figure 15 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0022] Figure 16 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0023] Figure 17 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0024] Figure 18 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0025] Figure 19 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0026] Figure 20 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0027] Figure 21 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0028] Figure 22 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0029] Figure 23This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0030] Figure 24 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures.

[0031] Figure 25 This disclosure shows one or more stages of some embodiments of the method for manufacturing device structures. Detailed Implementation

[0032] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0033] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0034] At least some embodiments of this disclosure provide device structures that can adjust the via size to a desired size. In some embodiments, the device structure includes an electrode via penetrating a dielectric material and electrically connected to a metal layer. At least some embodiments of this disclosure further provide techniques for manufacturing the device structure to prevent the electrode via from being larger than a desired size.

[0035] Figure 1 A cross-sectional view of a device structure 1, representing some embodiments of the present disclosure, is shown. Device structure 1 includes a stacked structure 10, dielectric material (including, for example, dielectric material 20, dielectric material 20a, dielectric material 20b, and dielectric material 20c), electrode vias 30, a plurality of first inner vias 40, a plurality of outer vias 50, and a plurality of second inner vias 60. In some embodiments, device structure 1 may be a capacitor.

[0036] The stacked structure 10 includes a first metal oxide layer 11, a second metal oxide layer 12, a metal layer 13, a first electrode structure 14, a second electrode structure 15, a first dielectric structure 16, and a second dielectric structure 17. The first metal oxide layer 11 may be made of, for example, aluminum oxide (Al₂O₃). The second metal oxide layer 12 is opposite to the first metal oxide layer 11. The second metal oxide layer 12 may also be made of, for example, aluminum oxide (Al₂O₃). The metal layer 13 is inserted between the first metal oxide layer 11 and the second metal oxide layer 12. The metal layer 13 may be made of, for example, aluminum (Al). Figure 1 As shown, a first metal oxide layer 11 is disposed on the upper surface of the metal layer 13, and a second metal oxide layer 12 is disposed on the lower surface of the metal layer 13.

[0037] The first electrode structure 14 is configured adjacent to the first metal oxide layer 11. In some embodiments, the first electrode structure 14 may include an insulating layer 141 disposed on the first metal oxide layer 11 and an electrode layer 142 disposed on the insulating layer 141. The insulating layer 141 may be made of, for example, a polymer. The electrode layer 142 may be made of, for example, copper. The electrode layer 142 may define an opening 143 that penetrates the electrode layer 142 to expose the insulating layer 141. The opening 143 may not penetrate the insulating layer 141.

[0038] The second electrode structure 15 is configured adjacent to the second metal oxide layer 12. In some embodiments, the second electrode structure 15 may include an insulating layer 151 disposed on the second metal oxide layer 12 and an electrode layer 152 disposed on the insulating layer 151. The insulating layer 151 may be made of, for example, a polymer. The electrode layer 152 may be made of, for example, copper. The electrode layer 152 may define an opening 153 that penetrates the electrode layer 152 to expose the insulating layer 151. The opening 153 may not penetrate the insulating layer 151.

[0039] A first dielectric structure 16 covers a first electrode structure 14. In some embodiments, the first dielectric structure 16 may include a first dielectric layer 161, at least one second dielectric layer 162, and multiple fibers 163. The first dielectric layer 161 covers the electrode layer 142 and extends into the opening 143. The material of the first dielectric layer 161 may be, for example, an ajinomoto build-up film (ABF). The second dielectric layer 162 is disposed on the first dielectric layer 161. In some embodiments, the material of the second dielectric layer 162 may be different from the material of the first dielectric layer 161. The material of the second dielectric layer 162 may be, for example, polypropylene (PP). Fibers 163 (e.g., glass fibers) are embedded in the second dielectric layer 162 to improve the material strength of the second dielectric layer 162.

[0040] The second dielectric structure 17 covers the second electrode structure 15. In some embodiments, the second dielectric structure 17 may include a first dielectric layer 171, at least one second dielectric layer 172, and a plurality of fibers 173. The first dielectric layer 171 covers the electrode layer 152 and extends into the opening 153. The material of the first dielectric layer 171 may be, for example, an Ajinomoto laminate (ABF). The second dielectric layer 172 is disposed on the first dielectric layer 171. In some embodiments, the material of the second dielectric layer 172 may be different from the material of the first dielectric layer 171. The material of the second dielectric layer 172 may be, for example, polypropylene (PP). The fibers 173 (e.g., glass fibers) are embedded in the second dielectric layer 172 to improve the material strength of the second dielectric layer 172.

[0041] The stacked structure 10 may define a central through hole 191, a plurality of outer through holes 192, a plurality of first inner through holes 193, and a plurality of second inner through holes 194. The central through hole 191 penetrates the first dielectric structure 16, the first electrode structure 14, and the first metal oxide layer 11 to expose a portion of the metal layer 13.

[0042] In some embodiments, the openings 143 of electrode layer 142 and 153 of electrode layer 152 may correspond to the central through-hole 191. The first dielectric layer 161 of the first dielectric structure 16 and the first dielectric layer 171 of the second dielectric structure 17 may respectively cover the openings 143 of dielectric layer 142 and 153 of electrode layer 152. Figure 1 As shown, a central perforation 191 is disposed within the opening 143 of the electrode layer 142. In some embodiments, a portion of the fiber 163 of the first dielectric structure 16 extends into the central perforation 191. That is, the end of the fiber 163 may be exposed in the central perforation 191.

[0043] An external perforation 192 penetrates the stacked structure 10. That is, the external perforation 192 penetrates the first metal oxide layer 11, the second metal oxide layer 12, the metal layer 13, the first electrode structure 14, the second electrode structure 15, the first dielectric structure 16, and the second dielectric structure 17.

[0044] The first internal perforation 193 is located between the central perforation 191 and the external perforation 192 and extends through the first dielectric structure 16 to expose a portion of the first electrode structure 14 (e.g., a portion of the electrode layer 142). In some embodiments, a portion of the fiber 163 of the first dielectric structure 16 extends into the first internal perforation 193. That is, the end of the fiber 163 may be exposed in the first internal perforation 193.

[0045] The second internal perforation 194 extends through the second dielectric structure 17 to expose a portion of the second electrode structure 15 (e.g., a portion of the electrode layer 152). In some embodiments, a portion of the fiber 173 of the second dielectric structure 17 extends into the second internal perforation 194. That is, the end of the fiber 163 may be exposed in the second internal perforation 194.

[0046] Dielectric materials (including, for example, dielectric materials 20, 20a, 20b, 20c) are disposed in the central through-hole 191, the outer through-hole 192, the first inner through-hole 193, and the second inner through-hole 194. For example... Figure 1 As shown, dielectric material 20 is disposed in the central through-hole 191, dielectric material 20a is disposed in the outer through-hole 192, dielectric material 20b is disposed in the first inner through-hole 193, and dielectric material 20c is disposed in the second inner through-hole 194.

[0047] Dielectric material 20 penetrates the first dielectric structure 16, the first electrode structure 14, and the first metal oxide layer 11. Dielectric material 20 covers the exposed portion of the metal layer 13 and defines a central opening 21 that penetrates the dielectric material 20 to expose a portion of the exposed portion of the metal layer 13. Additionally, dielectric material 20 covers the portion of fiber 163 extending into the central perforation 191. In some embodiments, the dielectric material 20 also gradually decreases in size downwards as the central perforation 191 gradually decreases in size downwards. Furthermore, the central opening 21 also gradually decreases in size downwards.

[0048] Dielectric material 20a extends through the stacked structure 10 and defines an external opening 22 that extends through the dielectric material 20a in each external through-hole 192.

[0049] Dielectric material 20b penetrates the first dielectric structure 16. Dielectric material 20b covers the exposed portion of the first electrode structure 14 (i.e., the exposed portion of the electrode layer 142) and defines a first internal opening 23 that penetrates the dielectric material 20b in each first internal perforation 193 to expose a portion of the exposed portion of the first electrode structure 14 (i.e., the exposed portion of the electrode layer 142). Additionally, dielectric material 20b covers the portion of fiber 163 extending into the first internal perforation 193. In some embodiments, the dielectric material 20b also gradually decreases in size downwards as the first internal perforation 193 gradually decreases in size. Furthermore, the first internal opening 23 also gradually decreases in size downwards. In some embodiments, the direction in which the dielectric material 20b in the first internal perforation 193 gradually decreases in size may be the same as the direction in which the dielectric material 20 in the central perforation 191 gradually decreases in size; for example, both dielectric material 20b and dielectric material 20 gradually decrease in size downwards.

[0050] Dielectric material 20c penetrates the second dielectric structure 17. Dielectric material 20c covers the exposed portion of the second electrode structure 15 (i.e., the exposed portion of the electrode layer 152) and defines a second internal opening 24 that penetrates the dielectric material 20c in each second internal perforation 194 to expose a portion of the exposed portion of the second electrode structure 15 (i.e., the exposed portion of the electrode layer 152). Additionally, dielectric material 20c covers the portion of the fiber 173 extending into the second internal perforation 194. In some embodiments, the decreasing direction of the dielectric material 20c in the second internal perforation 194 may differ from the decreasing direction of the dielectric material 20b in the first internal perforation 193; for example, the dielectric material 20c decreases upwards while the dielectric material 20b decreases downwards.

[0051] During the formation of the central through-hole 191, the external through-hole 192, the first internal through-hole 193, and the second internal through-hole 194, the dimensions of the central through-hole 191, the first internal through-hole 193, and the second internal through-hole 194 may be larger than the desired dimensions due to over-etching of the upper portion of the first dielectric structure 16 and the lower portion of the second dielectric structure 17 by laser drilling energy or due to processing tolerances. Furthermore, the dimension of the external through-hole 192 may be larger than the desired dimension due to processing errors or tolerances caused by mechanical drilling. Dielectric materials (including, for example, dielectric materials 20, 20a, 20b, and 20c) can be filled into the aforementioned through-holes 191, 192, 193, and 194 to adjust the dimensions of the openings 21, 22, 23, and 24 to the desired dimensions.

[0052] An electrode via 30 is disposed in the central opening 21 and electrically connected to the exposed portion of the metal layer 13. In some embodiments, the electrode via 30 may penetrate the dielectric material 20, and the direction in which the electrode via 30 gradually decreases may be the same as the direction in which the dielectric material 20 gradually decreases. In some embodiments, the electrode via 30 may be the anode of a capacitor.

[0053] The first internal via 40 is disposed in the first internal opening 23 and is electrically connected to the exposed portion of the first electrode structure 14 (i.e., the exposed portion of the electrode layer 142). In some embodiments, the direction in which the first internal via 40 gradually decreases may be the same as the direction in which the dielectric material 20b in the first internal through-hole 193 gradually decreases.

[0054] An external via 50 is disposed in the external opening 22 and is electrically connected to the first internal via 40. In some embodiments, the external via 50 may be electrically connected to the first internal via 40 via a circuit layer 95 formed on the upper surface of the first dielectric structure 16.

[0055] The second internal via 60 is disposed in the second internal opening 24 and is electrically connected to the exposed portion of the second electrode structure 15 (i.e., the exposed portion of the electrode layer 152) and the external via 50. In some embodiments, the second internal via 60 can be electrically connected to the external via 50 via a circuit layer 96 formed on the lower surface of the second dielectric structure 17. In some embodiments, the direction in which the second internal via 60 gradually decreases can be the same as the direction in which the dielectric material 20c in the second internal through-hole 194 gradually decreases. Figure 1 As shown, the electrode guide hole 30, the first internal guide hole 40, the external guide hole 50, and the second internal guide hole 60 can be formed simultaneously.

[0056] Since the dimensions of the central through-hole 191, external through-hole 192, first internal through-hole 193, and second internal through-hole 194 can be adjusted using dielectric materials (including dielectric material 20, dielectric material 20a, dielectric material 20b, and dielectric material 20c), the dimensions of the electrode via 30, first internal via 40, external via 50, and second internal via 60 can be reduced to achieve the desired dimensions. Furthermore, since dielectric materials 20, 20a, 20b, and 20c can cover the exposed portion of the fiber 163, the yield and quality of the electrode via 30, first internal via 40, external via 50, and second internal via 60 can be improved.

[0057] In some embodiments, the first internal guide hole 40, the external guide hole 50, and the second internal guide hole 60 can constitute the cathode of the capacitor.

[0058] Figure 2A cross-sectional view of a device structure 1a, showing some embodiments of the present disclosure, is shown. Device structure 1a is similar to... Figure 1 The illustrated device structure 1 differs in that it further includes a first redistribution structure 71, a second redistribution structure 72, a first protective layer 81, and a second protective layer 82. In some embodiments, the device structure 1a may include... Figure 1 The substrate of the device structure 1 (e.g., a capacitor).

[0059] A first re-fabricated structure 71 is disposed on the stacked structure 10 and electrically connected to the stacked structure 10. In some embodiments, the first re-fabricated structure 71 may be disposed on the first dielectric structure 16 of the stacked structure 10 and electrically connected to the electrode via 30, the first internal via 40, and the external via 50. Similarly, a second re-fabricated structure 72 may be disposed on the second dielectric structure 17 of the stacked structure 10 and electrically connected to the second internal via 60 and the external via 50.

[0060] In some embodiments, the first redistribution structure 71 may include at least one dielectric layer 711 disposed on the first dielectric structure 16 and a redistribution layer 712 in contact with the dielectric layer 711. The redistribution layer 712 may be electrically connected to the electrode via 30, the first internal via 40, and the external via 50. In some embodiments, the redistribution layer 712 may include a plurality of bonding pads 713 disposed on the dielectric layer 711.

[0061] In some embodiments, the second redistribution structure 72 may include at least one dielectric layer 721 disposed on the second dielectric structure 17 and a redistribution layer 722 in contact with the dielectric layer 721. The redistribution layer 722 may be electrically connected to the second internal via 60 and the external via 50. In some embodiments, the redistribution layer 722 may include a plurality of bonding pads 723 disposed on the dielectric layer 721.

[0062] A first protective layer 81 (e.g., a solder resist layer) covers the dielectric layer 711 and bonding pads 713 of the first resilient structure 71 and defines a plurality of openings 812 to expose a portion of each bonding pad 713. A second protective layer 82 (e.g., a solder resist layer) covers the dielectric layer 721 and bonding pads 723 of the second resilient structure 72 and defines a plurality of openings 822 to expose a portion of each bonding pad 723.

[0063] Figure 3 A cross-sectional view of device structure 1b, showing some embodiments of the present disclosure, is shown. Device structure 1b is similar to... Figure 2 The illustrated device structure 1a differs in that device structure 1b further includes at least one semiconductor element 91 and an encapsulant 92. In some embodiments, device structure 1b may be a package structure. The semiconductor element 91 may be, for example, a semiconductor die or a semiconductor chip. The semiconductor element 91 is electrically connected to the redistribution layer 712 of the first redistribution structure 71. For example, the semiconductor element 91 may be bonded to the bonding pad 713 of the redistribution layer 712 via flip-chip bonding. Additionally, the encapsulant 92 is disposed on the first protective layer 81 to cover the semiconductor element 91. The material of the encapsulant 92 may be a molding compound with or without fillers.

[0064] Figure 4 A cross-sectional view of a device structure 1c, illustrating some embodiments of the present disclosure, is shown. Device structure 1c is similar to... Figure 1 The device structure 1 shown differs from device structure 1c in that dielectric materials 20, 20b, and 20c are omitted. Therefore, electrode vias 30 fill the central through-hole 191, external vias 50 fill the external through-hole 192, the first internal via 40 fills the first internal through-hole 193, and the second internal via 60 fills the second internal through-hole 194. Furthermore, the material of the second dielectric layer 162 can be the same as the material of the first dielectric layer 161; therefore, there may be no boundary between the first dielectric layer 161 and the second dielectric layer 162. Further, the material of the second dielectric layer 172 can be the same as the material of the first dielectric layer 171; therefore, there may be no boundary between the first dielectric layer 171 and the second dielectric layer 172. In some embodiments, the materials of the second dielectric layer 162 and the first dielectric layer 161 may be Ajinomoto ABF (abbreviated as Ajinomoto layered film), and the materials of the second dielectric layer 172 and the first dielectric layer 171 may also be Ajinomoto ABF (abbreviated as Ajinomoto layered film).

[0065] Figure 5 A cross-sectional view of a device structure 1d, showing some embodiments of the present disclosure, is shown. Device structure 1d is similar to... Figure 1The device structure 1 shown differs in the shapes of the dielectric materials 20, 20b, and 20c in device structure 1d. In some embodiments, the dielectric materials 20, 20b, and 20c may be gourd-shaped. In some embodiments, the materials of the second dielectric layer 162 and the first dielectric layer 161 may be Ajinomoto ABF (abbreviated as Ajinomoto layered film), and the materials of the second dielectric layer 172 and the first dielectric layer 171 may also be Ajinomoto ABF.

[0066] Figure 6 A cross-sectional view of a device structure 1e, showing some embodiments of the present disclosure, is shown. Device structure 1e is similar to... Figure 1 The device structure 1 shown differs in the shapes of the dielectric materials 20, 20b, and 20c. In some embodiments, the middle portion of the dielectric material 20 may be convex, the lower portion of the dielectric material 20b may be convex, and the upper portion of the dielectric material 20c may be convex. In some embodiments, the materials of the first dielectric layer 161 and the first dielectric layer 171 may be Ajinomoto laminate (ABF), and the materials of the second dielectric layer 162 and the second dielectric layer 172 may be polypropylene (PP).

[0067] Figures 7 to 12 This disclosure shows one or more stages of some embodiments of a method for manufacturing an apparatus structure. In some embodiments, the method is used to manufacture, for example... Figure 1 The device structure shown is 1.

[0068] refer to Figures 7 to 8 Provides a stacked structure 10. (See reference) Figure 7 A sheet material 10' is provided. The sheet material 10' includes a first metal oxide layer 11, a second metal oxide layer 12, a metal layer 13, a first electrode structure 14, a second electrode structure 15, a first dielectric layer 161, and a first dielectric layer 171.

[0069] The first metal oxide layer 11 can be made of, for example, aluminum oxide (Al₂O₃). The second metal oxide layer 12 is opposite to the first metal oxide layer 11. The second metal oxide layer 12 can also be made of, for example, aluminum oxide (Al₂O₃). A metal layer 13 is inserted between the first metal oxide layer 11 and the second metal oxide layer 12. The metal layer 13 can be made of, for example, aluminum (Al).

[0070] The first electrode structure 14 is configured adjacent to the first metal oxide layer 11. In some embodiments, the first electrode structure 14 may include an insulating layer 141 formed on the first metal oxide layer 11 and an electrode layer 142 formed on the insulating layer 141. The insulating layer 141 may be made of, for example, a polymer. The electrode layer 142 may be made of, for example, copper. The electrode layer 142 may define an opening 143 that penetrates the electrode layer 142.

[0071] The second electrode structure 15 is configured adjacent to the second metal oxide layer 12. In some embodiments, the second electrode structure 15 may include an insulating layer 151 formed on the second metal oxide layer 12 and an electrode layer 152 formed on the insulating layer 151. The insulating layer 151 may be made of, for example, a polymer. The electrode layer 152 may be made of, for example, copper. The electrode layer 152 may define an opening 153 that penetrates the electrode layer 152.

[0072] The first dielectric layer 161 covers the first electrode structure 14. The material of the first dielectric layer 161 may be, for example, Ajinomoto layered film (ABF). The first dielectric layer 171 covers the second electrode structure 15. The material of the first dielectric layer 171 may be, for example, Ajinomoto layered film (ABF).

[0073] refer to Figure 8 A second dielectric layer 162 is formed on the first dielectric layer 161 to form a first dielectric structure 16, and a second dielectric layer 172 is formed on the first dielectric layer 171 to form a second dielectric structure 17. In some embodiments, the material of the second dielectric layer 162 may be different from the material of the first dielectric layer 161. The material of the second dielectric layer 162 may be, for example, polypropylene (PP). In some embodiments, multiple fibers 163 may be embedded or dispersed in the second dielectric layer 162 to improve the material strength of the second dielectric layer 162 after curing. In some embodiments, the material of the second dielectric layer 172 may be different from the material of the first dielectric layer 171. The material of the second dielectric layer 172 may be, for example, polypropylene (PP). In some embodiments, multiple fibers 173 may be embedded or dispersed in the second dielectric layer 172 to improve the material strength of the second dielectric layer 172 after curing.

[0074] Therefore, the first metal oxide layer 11, the second metal oxide layer 12, the metal layer 13, the first electrode structure 14, the second electrode structure 15, the first dielectric structure 16, and the second dielectric structure 17 can constitute a stacked structure 10.

[0075] refer to Figure 9At least one central through-hole 191 is formed, for example, by laser drilling, the central through-hole 191 penetrating the first dielectric structure 16, the first electrode structure 14, and the first metal oxide layer 11 to expose a portion of the metal layer 13; a plurality of external through-holes 192 are formed, for example, by mechanical drilling, the external through-holes 192 penetrating the stacked structure 10; a plurality of first internal through-holes 193 are formed, for example, by laser drilling, the first internal through-holes 193 penetrating the first dielectric structure 16 to expose a portion of the first electrode structure 14 (e.g., a portion of the electrode layer 142); and a plurality of second internal through-holes 194 are formed, for example, by laser drilling, the second internal through-holes 194 penetrating the second dielectric structure 17 to expose a portion of the second electrode structure 15 (e.g., a portion of the electrode layer 152). In some embodiments, the central through-hole 191 must penetrate the first metal oxide layer 11, therefore, the laser energy is relatively high. Therefore, the size of the central through-hole 191 is relatively large. Additionally, the laser may not remove the portion of fiber 163 located in the central perforation 191, the first internal perforation 193, and the second internal perforation 194. Therefore, the portion (or end) of fiber 163 will remain in the central perforation 191, the first internal perforation 193, and the second internal perforation 194, which will adversely affect subsequent metal plating processes.

[0076] refer to Figure 10 Simultaneously, dielectric materials (including dielectric material 20, dielectric material 20a, dielectric material 20b, and dielectric material 20c) are formed in the central through-hole 191, the outer through-hole 192, the first internal through-hole 193, and the second internal through-hole 194. For example... Figure 10 As shown, dielectric material 20 is disposed in the central through-hole 191 and on the exposed portion of the metal layer 13. Dielectric material 20a is disposed in the external through-hole 192. Dielectric material 20b is disposed in the first internal through-hole 193 and on the exposed portion of the first electrode structure 14 (i.e., the exposed portion of the electrode layer 142). Dielectric material 20c is disposed in the second internal through-hole 194 and on the exposed portion of the second electrode structure 15 (i.e., the exposed portion of the electrode layer 152).

[0077] refer to Figure 11A central opening 21 is formed, for example, by laser drilling, penetrating the dielectric material 20 in a central through-hole 191 to expose a portion of the exposed portion of the metal layer 13; an external opening 22 is formed, for example, by mechanical drilling or laser drilling, penetrating the dielectric material 20a in each external through-hole 192; a first internal opening 23 is formed, for example, by laser drilling, penetrating the dielectric material 20b in each first internal through-hole 193 to expose a portion of the exposed portion of the first electrode structure 14 (i.e., the exposed portion of the electrode layer 142); and a second internal opening 24 is formed, for example, by laser drilling, penetrating the dielectric material 20c in each second internal through-hole 194 to expose a portion of the exposed portion of the second electrode structure 15 (i.e., the exposed portion of the electrode layer 152). In some embodiments, since the laser used to form the central opening 21 is only used to remove a portion of the soft dielectric material 20, the laser energy used to form the central opening 21 is less than that used to form the central through-hole 191. Figure 9 The laser energy is used to determine the size of the central opening 21. Therefore, the size of the central opening 21 is smaller than the size of the central perforation 191, and the size of the central opening 21 may be the desired size. For example, the diameter of the top portion (i.e., the largest portion) of the central perforation 191 may be 40 μm to 50 μm, and the diameter of the top portion (i.e., the largest portion) of the central opening 21 may be about 10 μm.

[0078] refer to Figure 12 Electrode vias 30 are formed in the central opening 21 and on the exposed portion of the metal layer 13; a plurality of external vias 50 are formed in the external opening 22; a plurality of first internal vias 40 are formed in the first internal opening 23 and on the exposed portion of the first electrode structure 14 (i.e., the exposed portion of the electrode layer 142); and a plurality of second internal vias 60 are formed in the second internal opening 24 and on the exposed portion of the second electrode structure 15 (i.e., the exposed portion of the electrode layer 152). In some embodiments, a circuit layer 95 may be formed on the upper surface of the first dielectric structure 16 to electrically connect the first internal vias 40 and the external vias 50, and a circuit layer 96 may be formed on the lower surface of the second dielectric structure 17 to electrically connect the second internal vias 60 and the external vias 50. In some embodiments, electrode vias 30, external vias 50, first internal vias 40, second internal vias 60, circuit layer 95, and circuit layer 96 may be formed simultaneously.

[0079] Then, a single process is performed to obtain multiple... Figure 1 Device structure 1.

[0080] Figures 13 to 16 This disclosure shows one or more stages of some embodiments of a method for manufacturing an apparatus structure. In some embodiments, the method is used to manufacture, for example... Figure 2 The apparatus structure 1a is shown. The initial stages of the described process are related to... Figures 7 to 12 The stages described are the same or similar. Figure 13 Depicting Figure 12 The stage following the stage described.

[0081] refer to Figures 13 to 15 A first re-lay structure 71 is formed on the first dielectric structure 16, and a second re-lay structure 72 is formed on the second dielectric structure 17.

[0082] refer to Figure 13 At least one dielectric layer 711 is formed on the first dielectric structure 16 (i.e., the upper surface of the first dielectric structure 16), and at least one dielectric layer 721 is formed on the second dielectric structure 17 (i.e., the lower surface of the second dielectric structure 17).

[0083] refer to Figure 14 Multiple openings 714 are formed, which penetrate the dielectric layer 711 to expose a portion of the circuit layer 95, and multiple openings 724 are formed, which penetrate the dielectric layer 721 to expose a portion of the circuit layer 96.

[0084] refer to Figure 15 A redistribution layer 712 is formed in the opening 714 and on the dielectric layer 711, and a redistribution layer 722 is formed in the opening 724 and on the dielectric layer 721. Therefore, the dielectric layer 711 and the redistribution layer 712 can constitute a first redistribution structure 71, and the dielectric layer 721 and the redistribution layer 722 can constitute a second redistribution structure 72. In some embodiments, the redistribution layer 712 may include a plurality of bonding pads 713 formed on the dielectric layer 711, and the redistribution layer 722 may include a plurality of bonding pads 723 formed on the dielectric layer 721.

[0085] refer to Figure 16 A first protective layer 81 is formed on the first repetitive fabric structure 71 to cover the bonding pad 713 and defines a plurality of openings 812 to expose a portion of each bonding pad 713; and a second protective layer 82 is formed on the second repetitive fabric structure 72 to cover the bonding pad 723 and defines a plurality of openings 822 to expose a portion of each bonding pad 723.

[0086] Then, a single process is performed to obtain multiple... Figure 2 The device structure 1a.

[0087] Figures 17 to 18 This disclosure shows one or more stages of some embodiments of a method for manufacturing an apparatus structure. In some embodiments, the method is used to manufacture, for example... Figure 3 The apparatus structure 1b is shown. The initial stages of the process described are related to... Figures 7 to 16 The stages described are the same or similar. Figure 17 Depicting Figure 16 The stage following the stage described.

[0088] refer to Figure 17 At least one semiconductor element 91 is disposed on the first protective layer 81, and the semiconductor element 91 is electrically connected to the first relay structure 71. The semiconductor element 91 may be, for example, a semiconductor die or a semiconductor chip. The semiconductor element 91 is bonded to the bonding pad 713 of the relay layer 712 by flip-chip bonding.

[0089] refer to Figure 18 A package 92 is formed or disposed on the first protective layer 81 to cover the semiconductor element 91. The material of the package 92 may be a molding compound with or without filler.

[0090] Then, a single process is performed to obtain multiple... Figure 3 Device structure 1b.

[0091] Figures 19 to 25 This disclosure shows one or more stages of some embodiments of a method for manufacturing an apparatus structure. In some embodiments, the method is used to manufacture, for example... Figure 4 The apparatus structure 1c shown. The initial stage of the process described is related to... Figure 7 The stages described are the same or similar. Figure 19 Depicting Figure 7 The stage following the stage described.

[0092] refer to Figure 19 A double-layer film comprising a second dielectric layer 162 and a metal layer 181 formed on the second dielectric layer 162 is attached to the first dielectric layer 161 to form a first dielectric structure 16; and a double-layer film comprising a second dielectric layer 172 and a metal layer 182 formed on the second dielectric layer 172 is attached to the first dielectric layer 171 to form a second dielectric structure 17. The materials of the metal layers 181 and 182 may be, for example, copper. In some embodiments, the materials of the second dielectric layer 162 and the first dielectric layer 161 may be fibrous-free Ajinomoto augmented layer film (ABF). The materials of the second dielectric layer 172 and the first dielectric layer 171 may also be fibrous-free Ajinomoto augmented layer film (ABF).

[0093] refer to Figure 20Multiple openings 183 are formed, which penetrate the metal layer 181 to expose a portion of the second dielectric layer 162; and multiple openings 184 are formed, which penetrate the metal layer 182 to expose a portion of the second dielectric layer 172.

[0094] refer to Figure 21 At least one central through-hole 191 and a plurality of first internal through-holes 193 are formed by, for example, laser drilling through an opening 183 in the metal layer 181. The central through-hole 191 penetrates the first dielectric structure 16, the first electrode structure 14, and the first metal oxide layer 11 to expose a portion of the metal layer 13. The first internal through-holes 193 penetrate the first dielectric structure 16 to expose a portion of the first electrode structure 14 (e.g., a portion of the electrode layer 142). Further, a plurality of second internal through-holes 194 are formed by, for example, laser drilling through an opening 184 in the metal layer 182. The second internal through-holes 194 penetrate the second dielectric structure 17 to expose a portion of the second electrode structure 15 (e.g., a portion of the electrode layer 152). In addition, a plurality of external through-holes 192 are formed by, for example, mechanical drilling, penetrating the stacked structure 10.

[0095] refer to Figure 22 Remove metal layers 181 and 182.

[0096] refer to Figure 23 Dielectric material 20a is formed in the external perforation 192.

[0097] refer to Figure 24 External openings 22 are formed, for example by mechanical drilling or laser drilling, and the external openings 22 penetrate the dielectric material 20a in each external perforation 192.

[0098] refer to Figure 25 Electrode vias 30 are formed in the central through-hole 191 and on the exposed portion of the metal layer 13; a plurality of external vias 50 are formed in the external opening 22; a plurality of first internal vias 40 are formed in the first internal through-hole 193 and on the exposed portion of the first electrode structure 14 (i.e., the exposed portion of the electrode layer 142); and a plurality of second internal vias 60 are formed in the second internal through-hole 194 and on the exposed portion of the second electrode structure 15 (i.e., the exposed portion of the electrode layer 152). In some embodiments, a circuit layer 95 may be formed on the upper surface of the first dielectric structure 16 to electrically connect the first internal vias 40 and the external vias 50, and a circuit layer 96 may be formed on the lower surface of the second dielectric structure 17 to electrically connect the second internal vias 60 and the external vias 50.

[0099] Then, a single process is performed to obtain multiple... Figure 4 The device structure 1c.

[0100] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantage of the embodiments of this disclosure is not affected by such arrangement.

[0101] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to examples in which the event or situation clearly occurred and examples in which the event or situation is very close to occurring. For example, when used in conjunction with numerical values, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same or equal.

[0102] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0103] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0104] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials are generally those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0105] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0106] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A device structure including an electrode via, comprising: The stacked structure includes: First metal oxide layer; A second metal oxide layer is opposite to the first metal oxide layer; A metal layer inserted between the first metal oxide layer and the second metal oxide layer; A first electrode structure is configured to be adjacent to the first metal oxide layer; A first dielectric structure covering the first electrode structure; and A central perforation extends through the first dielectric structure, the first electrode structure, and the first metal oxide layer to expose a portion of the metal layer; A dielectric material disposed in the central through-hole and covering an exposed portion of the metal layer, wherein the dielectric material defines a central opening penetrating the dielectric material to expose a portion of the exposed portion of the metal layer; and An electrode via is disposed in the central opening and is electrically connected to the metal layer.

2. The device structure according to claim 1, wherein the first electrode structure includes an insulating layer disposed on the first metal oxide layer and an electrode layer disposed on the insulating layer, the electrode layer defining an opening that penetrates the electrode layer and corresponds to the central through-hole, and the first dielectric structure includes a first dielectric layer that covers the electrode layer and the opening.

3. The device structure according to claim 1, wherein the first dielectric structure includes a first dielectric layer, at least one second dielectric layer disposed on the first dielectric layer, and a plurality of fibers embedded in the second dielectric layer, and a portion of the fibers extends into the central perforation.

4. The device structure according to claim 3, wherein the dielectric material covers the portion of the fiber extending into the central perforation.

5. The device structure according to claim 3, wherein the material of the second dielectric layer is different from the material of the first dielectric layer.

6. The device structure according to claim 5, wherein the material of the first dielectric layer comprises an Ajinomoto layered film, and the material of the second dielectric layer comprises polypropylene.

7. The device structure according to claim 1, wherein the dielectric material in the central perforation is gourd-shaped.

8. The device structure of claim 1, wherein the stacked structure further defines a plurality of external through-holes and a plurality of first internal through-holes, the external through-holes penetrating the stacked structure, and the first internal through-holes being located between the central through-hole and the external through-holes and penetrating the first dielectric structure to expose a portion of the first electrode structure.

9. The device structure of claim 8, wherein the dielectric material is further disposed in the external perforation and the first internal perforation and covers the exposed portion of the first electrode structure, the dielectric material further defining an external opening and a first internal opening, the external opening penetrating the dielectric material in each of the external perforations, and the first internal opening penetrating the dielectric material in each of the first internal perforations to expose a portion of the exposed portion of the first electrode structure, further comprising: A first internal guide hole is disposed in the first internal opening and is electrically connected to the exposed portion of the first electrode structure; as well as An external guide hole is disposed in the external opening and is electrically connected to the first internal guide hole.

10. A device structure including an electrode via, comprising: The stacked structure includes: First metal oxide layer; A second metal oxide layer is opposite to the first metal oxide layer; A metal layer inserted between the first metal oxide layer and the second metal oxide layer; A first electrode structure is configured to be adjacent to the first metal oxide layer; A first dielectric structure covering the first electrode structure; and A central perforation extends through the first dielectric structure, the first electrode structure, and the first metal oxide layer to expose a portion of the metal layer; A dielectric material disposed in the central through-hole and covering the exposed portion of the metal layer, wherein the dielectric material defines a central opening that extends through the dielectric material to expose a portion of the exposed portion of the metal layer; An electrode via is disposed in the central opening and electrically connected to the metal layer; and A first re-fabricated structure is disposed on the stacked structure and electrically connected to the electrode via.

11. The device structure according to claim 10, wherein the first redistribution structure comprises at least one dielectric layer disposed on the first dielectric structure and a redistribution layer in contact with the dielectric layer.

12. The device structure of claim 10, wherein the stacked structure further comprises a second electrode structure disposed adjacent to the second metal oxide layer and a second dielectric structure covering the second electrode structure, the device structure further comprising a second redistribution structure disposed on the second dielectric structure, and the second redistribution structure comprising at least one dielectric layer disposed on the second dielectric structure and a redistribution layer in contact with the dielectric layer.

13. The device structure of claim 12, wherein the first dielectric structure comprises a first dielectric layer, at least one second dielectric layer disposed on the first dielectric layer, and a plurality of fibers embedded in the second dielectric layer, and a portion of the fibers extends into the central perforation.

14. The device structure according to claim 11, further comprising: A first protective layer covering the dielectric layer of the first re-laid structure; at least one semiconductor element electrically connected to the re-laid layer of the first re-laid structure; And a package disposed on the first protective layer to cover the semiconductor element.

15. The device structure of claim 10, wherein the stacked structure further defines a plurality of external through-holes and a plurality of first internal through-holes, the external through-holes penetrating the stacked structure, the first internal through-holes being located between the central through-hole and the external through-holes and penetrating the first dielectric structure to expose a portion of the first electrode structure, wherein the dielectric material is further disposed in the external through-holes and the first internal through-holes and covers the exposed portion of the first electrode structure, the dielectric material further defining an external opening and a first internal opening, the external opening penetrating the dielectric material in each of the external through-holes, the first internal opening penetrating the dielectric material in each of the first internal through-holes to expose a portion of the exposed portion of the first electrode structure, further comprising: A first internal guide hole is disposed in the first internal opening and is electrically connected to the exposed portion of the first electrode structure; as well as An external guide hole is disposed in the external opening and is electrically connected to the first internal guide hole.

16. The device structure according to claim 15, wherein the first re-fabricated structure is further electrically connected to the first internal guide hole and the external guide hole.

17. The device structure according to claim 15, wherein the direction in which the first internal guide hole gradually decreases is the same as the direction in which the electrode guide hole gradually decreases.

18. The device structure according to claim 15, wherein the dielectric material in the first internal perforation is gourd-shaped.

19. The device structure according to claim 10, wherein the middle portion of the dielectric material in the central perforation is convex.

20. A method for manufacturing an apparatus structure, comprising: (a) A stacked structure is provided, the stacked structure comprising: a first metal oxide layer; a second metal oxide layer opposite to the first metal oxide layer; a metal layer inserted between the first metal oxide layer and the second metal oxide layer; a first electrode structure configured adjacent to the first metal oxide layer; and a first dielectric structure covering the first electrode structure; (b) Forming at least one central through-hole, a plurality of external through-holes and a plurality of first internal through-holes, the central through-hole penetrating the first dielectric structure, the first electrode structure and the first metal oxide layer to expose a portion of the metal layer, the external through-holes penetrating the stacked structure, and the first internal through-holes penetrating the first dielectric structure to expose a portion of the first electrode structure; (c) Forming dielectric material in the central perforation, on the exposed portion of the metal layer, in the external perforation, in the first internal perforation, and on the exposed portion of the first electrode structure; (d) Forming a central opening, an outer opening, and a first inner opening, the central opening penetrating the dielectric material in the central through-hole to expose a portion of the exposed portion of the metal layer, the outer opening penetrating the dielectric material in each of the outer through-holes, and the first inner opening penetrating the dielectric material in each of the first inner through-holes to expose a portion of the exposed portion of the first electrode structure; and (e) forming electrode vias in the central opening and on the exposed portion of the metal layer, forming a plurality of external vias in the external opening, and forming a plurality of first internal vias in the first internal opening and on the exposed portion of the first electrode structure.

21. The method of claim 20, wherein in (a), the stacked structure further comprises a second electrode structure configured adjacent to the second metal oxide layer and a second dielectric structure covering the second electrode structure.

22. The method of claim 21, wherein (b) further comprises: (b2) A plurality of second internal through-holes are formed, the second internal through-holes penetrating the second dielectric structure to expose a portion of the second electrode structure; Wherein (c) further includes: (c2) Forming the dielectric material in the second internal perforation; wherein (d) further includes: (d2) Forming a second internal opening, the second internal opening penetrating the dielectric material in each of the second internal through-holes; wherein (e) further includes: (e2) A plurality of second internal guide holes are formed in the second internal opening.

23. The method of claim 20, wherein (b) comprises: (b1) The central perforation is formed by laser drilling; Where (d) includes: (d1) The central opening is formed by laser drilling, wherein the laser energy used to form the central opening is less than the laser energy used to form the central perforation.

24. The method of claim 20, wherein (b) comprises: (b1) The first internal perforation is formed by laser drilling; Where (d) includes: (d1) The first internal opening is formed by laser drilling.

25. The method of claim 20, wherein after (e), the method further comprises: (f) A first re-woven structure is formed on the first dielectric structure, wherein the first re-woven structure is electrically connected to the electrode via, the first internal via, and the external via.

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