Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first dielectric fin, a first semiconductor fin, and a second dielectric fin on a substrate. The first semiconductor fin is between the first dielectric fin and the second dielectric fin. The semiconductor structure also includes a first gate electrode surrounding the first dielectric fin, a channel region of the first semiconductor fin, and the second dielectric fin, and a first source / drain structure on a source / drain portion of the first semiconductor fin, in contact with the first dielectric fin and the second dielectric fin, and interposed between the first dielectric fin and the second dielectric fin.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure having dielectric fins. Background Technology

[0002] Integrated circuits (ICs) have become increasingly important. Millions of people use applications that utilize ICs. These applications include mobile phones, smartphones, tablets, laptops, personal computers, PDAs, wireless email terminals, MP3 audio and video players, and portable wireless web browsers. Integrated circuits increasingly encompass powerful and efficient on-board data storage and logic circuits for signal control and processing.

[0003] The recent trend of IC miniaturization has produced smaller devices that consume less power, while still offering higher speeds and more functionality than before. Miniaturization processes have also led to various developments in IC design and / or manufacturing processes to ensure the required throughput and expected performance. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor structure to solve at least one of the above-mentioned problems.

[0005] This disclosure provides a semiconductor structure. The semiconductor structure includes a first dielectric fin, a first semiconductor fin, and a second dielectric fin located on a substrate. The first semiconductor fin is located between the first dielectric fin and the second dielectric fin. The semiconductor structure also includes a first gate electrode surrounding the first dielectric fin, a channel region of the first semiconductor fin, and the second dielectric fin, and a first source / drain structure located on the source / drain portion of the first semiconductor fin, contacting the first dielectric fin and the second dielectric fin, and inserted between the first dielectric fin and the second dielectric fin.

[0006] This disclosure provides a semiconductor structure. The semiconductor structure includes a first P-type well region, an N-type well region, and a second P-type well region located on a substrate. The N-type well region is located between the first P-type well region and the second P-type well region. The semiconductor structure also includes a static random access memory (SRAM) cell located on the substrate. The SRAM cell includes a first pull-up transistor and a second pull-up transistor located on the N-type well region; and includes a first pull-down transistor located on the second P-type well region. The first pull-up transistor and the first pull-down transistor share a first gate electrode. The SRAM cell also includes a second pull-down transistor located on the first P-type well region. The second pull-up transistor and the second pull-down transistor share a second gate electrode. The SRAM cell further includes a first dielectric fin located between the second pull-down transistor and the second pull-up transistor, and a second gate electrode extending across the first dielectric fin. Furthermore, the SRAM cell includes a second dielectric fin located between the first pull-up transistor and the first pull-down transistor. The first gate electrode extends across the second dielectric fin, and the first and second dielectric fins extend across the aforementioned SRAM cell.

[0007] This disclosure provides a method for forming a static random access memory (SRAM) cell. The method includes forming a first P-type well region, an N-type well region, and a second P-type well region in a substrate; forming a first fin on the first P-type well region; forming a second and a third fin on the N-type well region; and forming a fourth fin on the second P-type well region. The method also includes forming an insulating pad on the first P-type well region, the N-type well region, and the second P-type well region. The first, second, third, and fourth fins protrude from the insulating pad. The method further includes forming a first dielectric fin, a second dielectric fin, and a third dielectric fin on the insulating pad. The first dielectric fin is located between the first and second fins, the second dielectric fin is located between the second and third fins, and the third dielectric fin is located between the third and fourth fins. Furthermore, the method for forming an SRAM cell includes forming a first dummy gate structure spanning a first fin, a first dielectric fin, a second fin, a second dielectric fin, a third fin, a third dielectric fin, and a fourth fin; and epitaxially growing a plurality of source / drain structures in the first fin, the second fin, the third fin, and the fourth fin adjacent to and on the opposite side of the first dummy gate structure. The plurality of source / drain structures directly contact the sidewalls of the first dielectric fin, the second dielectric fin, and the third dielectric fin. Attached Figure Description

[0008] The present disclosure will be better understood from the following embodiments and accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clear illustration.

[0009] Figure 1 This is a simplified drawing of a static random access memory (SRAM) according to some embodiments of the present disclosure.

[0010] Figure 2A It is a single-port SRAM cell shown in some embodiments of this disclosure.

[0011] Figure 2B As shown in some embodiments of this disclosure, Figure 2A Alternative diagram for SRAM cells.

[0012] Figure 3 As shown in some embodiments of this disclosure, Figure 1 The layout of a group GP in SRAM.

[0013] Figures 4A to 4J This is a perspective view of various stages of forming a semiconductor structure for an SRAM cell, as shown in some embodiments of this disclosure.

[0014] Figure 5A As shown in some embodiments of this disclosure, the semiconductor structure of the SRAM cell follows... Figure 4J Cross-sectional view of the midline segment A-AA.

[0015] Figure 5B As shown in some embodiments of this disclosure, the semiconductor structure of the SRAM cell follows... Figure 4J Cross-sectional view of the midline segment B-BB.

[0016] Figure 6 As shown in some embodiments of this disclosure, Figure 1 The layout of the SRAM.

[0017] Figure 7A As shown in some embodiments of this disclosure, the semiconductor structure of the SRAM cell follows... Figure 6 Cross-sectional view of the midline segment A-AA.

[0018] Figure 7B As shown in some embodiments of this disclosure, the semiconductor structure of the SRAM cell follows... Figure 6 Cross-sectional view of the midline segment B-BB.

[0019] Figure 8 This is the layout of the IC shown according to some embodiments of this disclosure.

[0020] Figure 9As shown in some embodiments of this disclosure, the logic cell array is along... Figure 8 Cross-sectional view of the midline segment C-CC.

[0021] The attached figures are labeled as follows:

[0022] 10: SRAM cell

[0023] 20A: Strip unit

[0024] 20B: Edge Unit

[0025] 30:SRAM

[0026] GP: Group

[0027] BL: Bitline

[0028] BLB: Complementary Bit Line

[0029] WL: Character Line

[0030] PG-1, PG-2: Transmission gate transistors

[0031] IS-1, IS-2: Isolation transistors

[0032] N1, N2: Nodes

[0033] INV-1, INV-2: Inverters

[0034] VDD: Power supply node

[0035] VSS: Grounding

[0036] PU-1, PU-2: Pull-up transistors

[0037] PD-1, PD-2: Pull-down transistors

[0038] PW1: P-type well area

[0039] NW1: N-type well area

[0040] PW2: P-type well area

[0041] NW2: N-type well area

[0042] PW3: P-type well area

[0043] 10_1~10_4: SRAM cells

[0044] 103a~103d: Fins

[0045] 109a~109e: Dielectric fins

[0046] 143a~143d: Gate electrode

[0047] 161a~161h: Contact

[0048] 100: Semiconductor Structure

[0049] 101:Substrate

[0050] 107: Insulating Pad Material

[0051] 108: Opening

[0052] 109: Dielectric layer

[0053] 107': Remaining insulating pad material

[0054] 107”: Insulating gasket

[0055] 110: Opening

[0056] 115a, 115b: Virtual gate structure

[0057] 121: Gate spacer

[0058] 130: Opening

[0059] 135: S / D Structure

[0060] 139: ILD layer

[0061] 147: Hard Mask

[0062] 151: Dielectric Structure

[0063] A-AA, B-BB: line segments

[0064] W1, W2, W3: Width

[0065] H1a, H1b, H2, H3: Height

[0066] 103a1, 103a2, 103d1, 103d2: Fins

[0067] 200: Semiconductor Structure

[0068] 135': Merging S / D structures

[0069] 50: Logic cell array

[0070] 10⁵~10⁸: SRAM cells

[0071] 103e~103h: Fins

[0072] 109f~109i: Dielectric fins

[0073] 40_1~40_10: Logic Units

[0074] 170a~170n: Dielectric-based virtual gate

[0075] C-CC: Line segment

[0076] 103b': The lower part

[0077] 103b”: Upper part

[0078] 141: Gate dielectric layer

[0079] 143: Gate electrode

[0080] 161:Contact

[0081] 171: Spacer

[0082] 177: Hard Mask Detailed Implementation

[0083] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of the components and arrangements of this disclosure are described below for simplification. Naturally, these examples are not intended to limit this disclosure. For example, if the description states that a first feature is formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition is for simplification and clarity and does not inherently define the relationships between the various embodiments and / or configurations discussed.

[0084] This disclosure describes some variations of the embodiments. Throughout the various figures and the described embodiments, similar reference numerals are used to denote similar elements. It should be noted that additional operations may be provided before, during, and / or after the disclosed method, and some of the described operations may be substituted or removed for embodiments of the method.

[0085] Furthermore, this disclosure may use spatial relative terms such as “below,” “below,” “lower than,” “above,” “higher than,” and similar words to describe the relationship between one element or feature and other elements or features in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover the different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0086] This disclosure provides various semiconductor structures for integrated circuits (ICs) including static random access memory (SRAM) structures, based on various exemplary embodiments. Variations on some embodiments are discussed. Throughout the various drawings and illustrative embodiments, similar reference numerals are used to indicate similar elements.

[0087] This disclosure provides embodiments of a semiconductor structure. The semiconductor structure includes a first P-type well region, a second P-type well region, an N-type well region, and an SRAM cell on a substrate. The N-type well region is located between the first P-type well region and the second P-type well region. The SRAM cell includes a first and a second pull-up transistor on the N-type well region, a first pull-down transistor on the second P-type well region, and a second pull-down transistor on the first P-type well region. The first pull-up transistor, the second pull-up transistor, the first pull-down transistor, and the second pull-down transistor each include a first fin, a second fin, a third fin, and a fourth fin, respectively. The semiconductor structure also includes a first dielectric fin between the second fin and the fourth fin, a second dielectric fin between the first fin and the second fin, and a third dielectric fin between the first fin and the third fin. By placing the aforementioned dielectric fins (i.e., virtual fins) between adjacent fins (i.e., active fins), unwanted bridging problems between source / drain (S / D) structures can be prevented when the size of the source / drain (S / D) structure reaches its maximum value.

[0088] Figure 1 The following is a simplified drawing of SRAM 30 according to some embodiments of the present disclosure. SRAM 30 may be a standalone device or may be implemented in an IC (e.g., a System-on-Chip, SOC). SRAM 30 includes a cell array formed by a plurality of SRAM cells (or bit cells) 10, and the SRAM cells 10 are arranged in multiple rows and columns in the cell array.

[0089] In the fabrication of SRAM cells, a cell array may be surrounded by a plurality of strip cells 20A and a plurality of edge cells 20B, wherein the strip cells 20A and edge cells 20B are dummy cells for the cell array. In some embodiments, the strip cells 20A are arranged horizontally around the cell array, while the edge cells 20B are arranged vertically around the cell array. The shape and size of the strip cells 20A and edge cells 20B are determined according to the specific application.

[0090] In some embodiments, the strip cells 20A and edge cells 20B have the same shape and size as the SRAM cell 10. In some embodiments, the strip cells 20A, edge cells 20B, and SRAM cell 10 have different shapes and sizes. Furthermore, in the SRAM 30, each SRAM cell 10 has the same rectangular shape / area; for example, the width and height of the SRAM cell 10 are the same. The configuration of the SRAM cell 10 will be described below.

[0091] In the SRAM 30 cell array, although Figure 1 Only one group GP is shown, but SRAM cell 10 can be divided into multiple group GPs, and each group GP includes four adjacent SRAM cells 10. The group GPs will be described in detail below.

[0092] Figure 2A According to some embodiments of this disclosure, a single-port SRAM cell 10 is shown. The SRAM cell 10 includes a pair of cross-coupled inverters INV-1 and INV-2, two pass-gate transistors PG-1 and PG-2, and two isolation transistors IS-1 and IS-2. Inverters INV-1 and INV-2 are cross-coupled between nodes N1 and N2, forming a latch.

[0093] Transmission gate transistor PG-1 is coupled between bit line BL and node N1, while transmission gate transistor PG-2 is coupled between complementary bit line BLB and node N2, wherein complementary bit line BLB is complementary to bit line BL. The gates of transmission gate transistors PG-1 and PG-2 are coupled to the same word line WL. The effect of isolation transistors IS-1 and IS-2 on the operation of SRAM cell 10 is negligible because there is no current flowing from node N1 and node N2 via isolation transistors IS-1 or IS-2. Furthermore, transmission gate transistors PG-1 and PG-2 can be NMOS transistors, while isolation transistors IS-1 and IS-2 can be PMOS transistors.

[0094] Figure 2B As shown in some embodiments of this disclosure, Figure 2A Alternative diagram for SRAM cells. (See attached diagram.) Figure 2B As shown, Figure 2AThe inverter INV-1 includes a pull-up transistor PU-1 and a pull-down transistor PD-1. Pull-up transistor PU-1 is a PMOS transistor, while pull-down transistor PD-1 is an NMOS transistor. The drains of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled to node N1, which connects to the transmission gate transistor PG-1. The gates of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled to node N2, which connects to the transmission gate transistor PG-2. Furthermore, the source of pull-up transistor PU-1 is coupled to the power supply node VDD, while the source of pull-down transistor PD-1 is coupled to ground VSS.

[0095] Similarly, such as Figure 2B As shown, Figure 2A The inverter INV-2 in the circuit includes a pull-up transistor PU-2 and a pull-down transistor PD-2. Pull-up transistor PU-2 is a PMOS transistor, while pull-down transistor PD-2 is an NMOS transistor. The drains of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled to node N2, which connects to the transmission gate transistor PG-2. The gates of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled to node N1, which connects to the transmission gate transistor PG-1. Furthermore, the source of pull-up transistor PU-2 is coupled to the power supply node VDD, while the source of pull-down transistor PD-2 is coupled to ground VSS.

[0096] In some embodiments, the transmission gate transistors PG-1 and PG-2, the isolation transistors IS-1 and IS-2, the pull-up transistors PU-1 and PU-2, and the pull-down transistors PD-1 and PD-2 in the SRAM cell 10 are finfield effect transistors (FinFETs).

[0097] In some embodiments, the transmission gate transistors PG-1 and PG-2, the isolation transistors IS-1 and IS-2, the pull-up transistors PU-1 and PU-2, and the pull-down transistors PD-1 and PD-2 in the SRAM cell 10 are planar MOS devices.

[0098] Figure 3 As shown in some embodiments of this disclosure, Figure 1The layout of a group GP of SRAM 30 is shown. The group GP includes four SRAM cells: SRAM cells 10_1, 10_2, 10_3, and 10_4. In some embodiments, the transistors in SRAM cells 10_1, 10_2, 10_3, and 10_4 are FinFETs located in N-type well regions NW1 and NW2 and in P-type well regions PW1, PW2, and PW3. N-type well region NW1 is formed between P-type well regions PW1 and PW2 and is adjacent to P-type well regions PW1 and PW2, while N-type well region NW2 is formed between P-type well regions PW2 and PW3 and is adjacent to P-type well regions PW2 and PW3.

[0099] Two adjacent SRAM cells 10_1 and 10_3 are arranged in the same column of the SRAM 30 cell array. Two adjacent SRAM cells 10_1 and 10_2 are arranged in the same row of the SRAM 30 cell array. Two adjacent SRAM cells 10_3 and 10_4 are arranged in the same row of the SRAM 30 cell array. In other words, two adjacent SRAM cells 10_2 and 10_4 are arranged in the same column of the SRAM 30 cell array. Figure 3 In this context, each of SRAM cells 10_1, 10_2, 10_3, and 10_4 has the same rectangular shape / area, with a width along the X direction and a height along the Y direction, the height being less than the width. It should be noted that... Figure 3 The SRAM structure shown is merely an example and is not intended to limit the SRAM cell 10 of SRAM 30.

[0100] In SRAM 30, any suitable method can be used to pattern the fins (i.e., semiconductor fins). For example, one or more photolithography processes can be used to pattern the fins, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing the created patterns to have smaller pitches, for example, smaller than those achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers are used to pattern the semiconductor fin structure.

[0101] In SRAM cell 10_1, a transfer gate transistor PG-1 is formed at the intersection of fin 103d and gate electrode 143b on the P-type well region PW2. A pull-down transistor PD-1 is formed at the intersection of fin 103d and gate electrode 143d on the P-type well region PW2. A transfer gate transistor PG-2 is formed at the intersection of fin 103a and gate electrode 143c on the P-type well region PW1. A pull-down transistor PD-2 is formed at the intersection of fin 103a and gate electrode 143a on the P-type well region PW1.

[0102] Furthermore, in SRAM cell 10_1, pull-up transistor PU-1 is formed at the intersection of fin 103c and gate electrode 143d on the N-type well region NW1. Pull-up transistor PU-2 is formed at the intersection of fin 103b and gate electrode 143a on the N-type well region NW1. Isolation transistor IS-1 is formed at the intersection of fin 103c and gate electrode 143a on the N-type well region NW1. Isolation transistor IS-2 is formed at the intersection of fin 103b and gate electrode 143d on the N-type well region NW1.

[0103] Various contacts and corresponding interconnect vias can be used to electrically connect components in each of the SRAM cells 10_1 to 10_4. A bit line (BL) (not shown) can be electrically connected to the source of the transmission gate transistor PG-1 via contact 161c, while a complementary bit line (BLB) (not shown) can be electrically connected to the source of the transmission gate transistor PG-2 via contact 161f. Similarly, a contact and / or via of a word line (WL) (not shown) can be electrically connected to the gate electrode 143b of the transmission gate transistor PG-1, and another contact and / or via of the word line (not shown) can be electrically connected to the gate electrode 143c of the transmission gate transistor PG-2.

[0104] Furthermore, the contacts and / or vias of the power supply node VDD (not shown) can be electrically connected to the source of the pull-up transistor PU-1 via contact 161g, while another contact and / or via (not shown) of the power supply node VDD can be electrically connected to the source of the pull-up transistor PU-2 via contact 161b. The contacts and / or vias of the ground VSS (not shown) can be electrically connected to the source of the pull-down transistor PD-1 via contact 161h, while another contact and / or via of the ground VSS (not shown) can be electrically connected to the source of the pull-down transistor PD-2 via contact 161a.

[0105] In addition, contact 161e is configured to electrically connect the drain of pull-up transistor PU-1 and the drain of pull-down transistor PD-1, while contact 161d is configured to electrically connect the drain of pull-up transistor PU-2 and the drain of pull-down transistor PD-2.

[0106] like Figure 3 As shown, the X1 direction is opposite to the X direction, and the Y direction is perpendicular to both the X and X1 directions. In some embodiments, the gate electrode 143a is shared by the pull-down transistor PD-2, the pull-up transistor PU-2, and the isolation transistor IS-1 of the SRAM cell 10_1; the gate electrode 143b is shared by the transmission gate transistor PG-1 of the SRAM cells 10_1 and 10_3; the gate electrode 143c is shared by the transmission gate transistor PG-2 of the SRAM cell 10_1 and another adjacent SRAM cell (not shown) disposed along the X1 direction from the SRAM cell 10_1; and the gate electrode 143d is shared by the pull-down transistor PD-1, the pull-up transistor PU-1, and the isolation transistor IS-2 of the SRAM cell 10_1.

[0107] It should be noted that SRAM cell 10_1 includes multiple dielectric fins (e.g., dielectric fins 109a, 109b, 109c, 109d, and 109e), and each of the dielectric fins is located between an adjacent pair of fins (e.g., fins 103a, 103b, 103c, and 103d), such as... Figure 3 According to some embodiments, dielectric fin 109a is located between fin 103a in SRAM cell 10_1 and another fin in SRAM cell 10_1, which is disposed from SRAM cell 10_1 along the X1 direction. That is, dielectric fin 109a is located at the boundary (or interface, junction) between SRAM cell 10_1 and the SRAM cell (i.e., shared by adjacent SRAM cells).

[0108] In some embodiments, dielectric fin 109b is located between fins 103a and 103b, dielectric fin 109c is located between fins 103b and 103c, and dielectric fin 109d is located between fins 103c and 103d. In some embodiments, dielectric fin 109b is located at the boundary between P-type well region PW1 and N-type well region NW1, dielectric fin 109c is located in N-type well region NW1, and dielectric fin 109d is located at the boundary between N-type well region NW1 and P-type well region PW2. Furthermore, similar to dielectric fin 109a, dielectric fin 109e is located at the boundary between SRAM cell 10_1 and SRAM cell 10_3 (i.e., shared by SRAM cells 10_1 and 10_3).

[0109] In some embodiments, SRAM cell 10_2 is a copy of SRAM cell 10_1 but flipped on the X-axis, SRAM cell 10_3 is a copy of SRAM cell 10_1 but flipped on the Y-axis, and SRAM cell 10_4 is a copy of SRAM cell 10_3 but flipped on the X-axis. Common contacts (e.g., contact 161h that electrically connects the source of pull-down transistor PD-1 in SRAM cells 10_1 to 10_4 to ground VSS) are combined to save space.

[0110] As feature sizes continue to shrink, adjacent source / drain (S / D) structures of different transistors may connect during epitaxial processing, leading to undesirable bridging problems. In some embodiments, dielectric fins (e.g., dielectric fins 109a to 109e) formed between adjacent fins (e.g., fins 103a to 103d) are used to address the bridging problem of the S / D structures. The S / D structures formed on the fins can grow in the region confined by the dielectric fins, allowing the S / D structures to contact the dielectric fins. Therefore, undesirable bridging problems can be prevented when the size of the S / D structures reaches their maximum value. As a result, the contact resistance between the S / D structures and the contacts (e.g., contacts 161a to 161h) covering the S / D structures is reduced, and the performance and operating speed of the transistors in the group GP of the SRAM 30 can be enhanced.

[0111] Figures 4A to 4J SRAM cells are formed according to some embodiments of this disclosure (e.g.: Figure 3 Perspective view of various stages of the semiconductor structure 100 of the SRAM cell 10_1.

[0112] A substrate 101 is provided. The substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 101 may include a basic semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of elemental semiconductor materials may include, but are not limited to: crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to: silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, the substrate 101 includes an epitaxial layer. For example, the substrate 101 has an epitaxial layer covering a bulk semiconductor.

[0113] According to some embodiments, an N-type well region NW1 and two P-type well regions, PW1 and PW2, are formed in the substrate 101. A fin 103a is formed on the P-type well region PW1, two fins, fins 103b and fin 103c, are formed on the N-type well region NW1, and a fin 103d is formed on the P-type well region PW2. Figure 4A As shown. In some embodiments, N-type well region NW1 is located between P-type well region PW1 and P-type well region PW2, and is adjacent to both P-type well region PW1 and P-type well region PW2.

[0114] In some embodiments, N-type well regions NW1, P-type well regions PW1, and P-type well regions PW2 are formed by ion implantation. More specifically, according to some embodiments, N-type well region NW1 is doped with an n-type dopant such as phosphorus or arsenic, while P-type well regions PW1 and P-type well regions PW2 are doped with a p-type dopant such as boron or BF2.

[0115] In some embodiments, the longitudinal directions of fins 103a, 103b, 103c, and 103d are substantially parallel to each other. Throughout this specification, the term "substantially" means preferably at least 90%. Furthermore, in some embodiments, fins 103a to 103d are formed by deposition, patterning, and etching processes. For example, a dielectric layer (not shown), a mask layer (not shown), and a patterned photoresist layer (not shown) are formed on substrate 101.

[0116] Patterned photoresist layers can be formed through deposition processes and subsequent patterning processes. Deposition processes for forming patterned photoresist layers may include chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), spin-on coating, sputtering, or other suitable processes. Patterning processes for forming patterned photoresist layers may include photolithography and etching processes. Photolithography may include photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). Etching processes may include dry etching or wet etching.

[0117] Furthermore, the dielectric layer may serve as a buffer layer between the substrate 101 and the mask layer. In some embodiments, the dielectric layer is used as a stop layer when the mask layer is removed, and it may also serve as an adhesion layer formed between the substrate 101 and the mask layer. The dielectric layer may be made of silicon oxide. The mask layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. The dielectric layer and the mask layer may be formed by a deposition process, which may include chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), spin coating, sputtering, or other suitable processes.

[0118] According to some embodiments, after forming a patterned photoresist layer, a dielectric layer and a mask layer are patterned using the patterned photoresist layer as a mask. This results in a patterned dielectric layer and a patterned mask layer. The patterned photoresist layer is then removed. Next, using the patterned dielectric layer and the patterned mask layer as masks, an etching process is performed on the substrate 101 to form fins 103a to 103d. The etching process can be a dry etching process or a wet etching process.

[0119] In some embodiments, the substrate 101 is etched using a dry etching process. The dry etching process includes using a fluorine-based etchant gas, such as SF6 or C20. x F y NF3 or a combination thereof. The etching process may be a time-controlled process and continues until the fins 103a to 103d reach a predetermined height. Furthermore, in some embodiments, the width of each of the fins 103a to 103d decreases from bottom to top.

[0120] According to some embodiments, after the fins 103a to 103d are formed, the patterned dielectric layer and the patterned mask layer are removed, such as... Figure 4A As shown. However, in some embodiments, the patterned dielectric layer and the patterned mask layer are removed only after performing some subsequent processes, which will be described below.

[0121] Subsequently, according to some embodiments, an insulating lining material 107 is formed to cover P-type well areas PW1 and PW2, N-type well area NW1, and fins 103a to 103d, such as Figure 4BAs shown. In some embodiments, insulating pad material 107 covers the top surface and sidewalls of fins 103a to 103d. More specifically, in some embodiments, insulating pad material 107 conformally pads the space between fins 103a to 103d, and a plurality of openings 108 are formed on insulating pad material 107 and between adjacent pairs of fins in fins 103a to 103d. Furthermore, in some embodiments, after the fins 103a to 103d are formed, a patterned dielectric layer and a patterned mask layer remain on the fins 103a to 103d, and insulating pad material 107 covers the patterned dielectric layer and the patterned mask layer.

[0122] The insulating pad material 107 can be made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-k dielectric materials. The insulating pad material 107 can be deposited using atomic layer deposition (ALD), CVD, flowable CVD (FCVD), spin-coating glass deposition, or other suitable processes.

[0123] According to some embodiments, after forming the insulating pad material 107, a dielectric layer 109 is formed on the insulating pad material 107, such as... Figure 4C As shown. In some embodiments, the dielectric layer 109 completely fills the opening 108 (e.g., Figure 4B (as shown), and covers the portion of the insulating pad material 107 located on the top surface and sidewalls of the fins 103a to 103d.

[0124] In some embodiments, the dielectric layer 109 is made of silicon oxide, a nitrogen-containing material, a carbon-containing material, a carbon and nitrogen-containing material, or a metal oxide. For example, the dielectric layer 109 is made of the following materials: SiO2, SiN, SiOC, SiON, SiCN, SiOCN, HfO2, Ta2O5, TiO2, ZrO2, Al2O3, Y2O3, other suitable materials, or combinations thereof. The dielectric layer 109 can be deposited by an ALD process, a CVD process, or other suitable processes. In some embodiments, the insulating liner material 107 is not the same material as the dielectric layer 109, and the dielectric constant of the dielectric layer 109 is higher than that of the insulating liner material 107.

[0125] According to some embodiments, after forming the dielectric layer 109, for Figure 4C The structure shown undergoes a polishing process, such as... Figure 4DAs shown. In some embodiments, a thin layer above fins 103a to 103d is removed by a polishing process such as chemical mechanical polishing (CMP) to expose fins 103a to 103d. More specifically, the dielectric layer 109 and the insulating pad material 107 above fins 103a to 103d are removed sequentially by the polishing process, thereby exposing fins 103a, fin 103b, fin 103c, and fin 103d. Furthermore, the patterned dielectric layer and patterned mask layer remaining on the top surface of fins 103a to 103d after their formation, as well as the patterned dielectric layer and patterned mask layer, are removed by the polishing process.

[0126] After the polishing process, dielectric fins 109a, 109b, 109c, 109d, and 109e form the remainder of dielectric layer 109, and are surrounded by the remaining insulating pad material 107'. Each of dielectric fins 109a to 109e has a strip shape similar to that of each of fins 103a to 103d, and the longitudinal direction of dielectric fins 109a to 109e is substantially parallel to the longitudinal direction of fins 103a to 103d. Therefore, dielectric fins 109a to 109e can be referred to as dummy fins or hybrid fins, while fins 103a to 103d can be referred to as active fins.

[0127] According to some embodiments, after the fins 103a to 103d are exposed by a grinding process, the remaining insulating pad material 107' is further recessed to form insulating pad 107'", such as Figure 4E As shown. In some embodiments, a portion of the remaining insulating pad material 107' is removed by an etching process to form an opening 110 above the insulating pad 107', and the opening 110 is formed between adjacent fins 103a to 103d and dielectric fins 109a to 109e. For example, the etching process may be a dry etching process, a wet etching process, or a combination thereof.

[0128] In some embodiments, the remaining insulating pad material 107' has etch selectivity relative to the dielectric fins 109a to 109e. That is, in some embodiments, the etch rate of the remaining insulating pad material 107' is much higher than the etch rate of the dielectric fins 109a to 109e during the etching process. Therefore, the dielectric fins 109a to 109e are essentially not removed during the etching process that forms the insulating pad 107' and the opening 110.

[0129] Next, according to some embodiments, dummy gate structures 115a and 115b are formed on insulating pad 107” and extend across fins 103a to 103d and dielectric fins 109a to 109e, as shown. Figure 4F As shown. Virtual gate structures 115a and 115b extend into the opening 110 between fins 103a to 103d and dielectric fins 109a to 109e. Each of virtual gate structures 115a and 115b may include a virtual gate dielectric layer (not shown) and a virtual gate electrode layer (not shown) on the virtual gate dielectric layer.

[0130] Furthermore, according to some embodiments, gate spacers 121 are formed on the opposing sidewalls of each of the dummy gate structures 115a and 115b, and openings 130 are formed between adjacent gate spacers 121, such as... Figure 4F As shown. The gate spacer 121 may be made of the following materials: silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or other suitable materials.

[0131] According to some embodiments, after forming the virtual gate structures 115a and 115b, portions of fins 103a to 103d exposed via opening 130 are tunneled in. More specifically, in some embodiments, fins 103a to 103d are tunneled in by an etching process such that the top surface of the tunneled portion of fins 103a to 103d is lower than the top surface of dielectric fins 109a to 109e. In some embodiments, the top surface of the tunneled portion of fins 103a to 103d is lower than the top surface of insulating pad 107". Then, according to some embodiments, a source / drain (S / D) structure 135 is formed on the tunneled portion of fins 103a to 103d, such as... Figure 4G As shown.

[0132] In some embodiments, strained material is grown on the excavated portions of fins 103a to 103d using an epitaxial process to form an S / D structure 135. The S / D structure 135 can apply stress or strain to the channel regions beneath the dummy gate structures 115a and 115b to enhance the carrier mobility of the substantially formed transistor and improve transistor performance. In some embodiments, the S / D structure 135 is formed on the opposite sidewalls of the corresponding dummy gate structures 115a or 115b.

[0133] In some embodiments, the S / D structure 135 includes Si, Ge, SiGe, SiP, SiC, SiPC, SiAs, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, etc. More specifically, in some embodiments, the S / D structure 135 is made of N-type semiconductor material of substantially formed NMOS transistors (e.g., pull-down transistors PD-1, PD-2 and transmission gate transistors PG-1, PG-2), and the S / D structure 135 may include epitaxially grown Si, SiP, SiC, SiPC, SiAs, combinations thereof, or other semiconductor materials suitable for epitaxial growth.

[0134] In some embodiments, the S / D structure 135 is made of the P-type semiconductor material of substantially formed PMOS transistors (e.g., pull-up transistors PU-1, PU-2 and isolation transistors IS-1, IS-2), and the S / D structure 135 may include epitaxially grown Si, Ge, SiGe, SiGeC, combinations thereof or other semiconductor materials suitable for epitaxial growth.

[0135] Subsequently, according to some embodiments, an inter-layer dielectric (ILD) layer 139 is formed on the S / D structure 135, such as... Figure 4H As shown. The ILD layer 139 may comprise multiple thin layers made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. The ILD layer 139 may be formed by CVD, ALD, physical vapor deposition (PVD), spin coating, or other suitable processes.

[0136] In some embodiments, the ILD layer 139 fills the opening 130 (shown in...). Figure 4G The dummy gate structures 115a and 115b and the gate spacer 121 are then extended on the ILD layer 139, according to some embodiments. Subsequently, according to some embodiments, a planarization process such as CMP is performed on the ILD layer 139 until the top surfaces of the dummy gate structures 115a and 115b are exposed. In some embodiments, the space defined by the insulating pad 107", the S / D structure 135, and the dielectric fins 109a to 109e may not be completely filled by the dielectric material of the ILD layer 139.

[0137] According to some embodiments, after the formation of the ILD layer 139, the dummy gate structures 115a and 115b are removed and replaced by a gate structure, which includes a gate dielectric layer 141 and a gate electrode material (not shown) located on the gate dielectric layer 141. The top portion of the gate structure is replaced by a hard mask 147, while some portions of the gate structure are replaced by a dielectric structure 151 between gate electrodes 143a, 143b, 143c, and 143d, wherein the gate electrodes 143a, 143b, 143c, and 143d are obtained from the aforementioned gate electrode material, as shown in Figure 4I. In some embodiments, the gate electrodes 143a, 143b, 143c, and 143d are covered by the hard mask 147, and details of the gate electrodes 143a to 143d are shown in Figure 4I. Figure 3 Layout and Figure 5A The cross-sectional view will be described in detail below.

[0138] In some embodiments, the dummy gate structures 115a and 115b are removed by an etching process, such as a dry etching process or a wet etching process. The gate dielectric layer 141 may be a single thin layer or multiple thin layers. Furthermore, in some embodiments, the gate dielectric layer 141 is made of materials such as silicon oxide, silicon nitride, silicon oxynitride (SiON), and dielectric materials with a high dielectric constant (high k-value), such as metal oxides. Examples of high k-value dielectric materials may include hafnium oxide (HfO2), silicon hafnium oxide (HfSiO), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, or other suitable dielectric materials. In some embodiments, the gate dielectric layer 141 may be formed by processes such as CVD, PVD, ALD, plasma-enhanced chemical vapor deposition (PECVD), spin coating, or other suitable processes.

[0139] In some embodiments, each of the gate electrodes 143a, 143b, 143c, and 143d includes a work-function metal layer (not shown) and a metal conductor layer (not shown) on the work-function metal layer. In some embodiments, the metal conductor layer is made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the metal conductor layer may be formed by processes such as CVD, PVD, ALD, HDPCVD, PECVD, or metal-organic CVD (MOCVD).

[0140] The work function metal layer may include an N-type work function metal or a P-type work function metal. N-type work function metals may include W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function metals, or combinations thereof. P-type work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, other suitable P-type work function metals, or combinations thereof. In some embodiments, the work function metal layer of each gate electrode 143a to 143d is identical. In some embodiments, the work function metal layers of some gate electrodes 143a to 143d are different.

[0141] Furthermore, hard mask 147 is used as a mask to perform a self-aligned etching process to form contacts electrically connected to S / D structure 135, which will be discussed below. Figure 4J As described in the description. In some embodiments, the hard mask 147 is made of the following materials: silicon oxide, silicon nitride, silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), or SiLK. It should be noted that the material of the hard mask 147 is different from the material of the ILD layer 139. In some embodiments, the hard mask 147 is formed by a deposition process, such as a CVD process, an ALD process, or other suitable processes.

[0142] Furthermore, dielectric structure 151 is a gate-cut structure for gate electrodes 143a, 143b, 143c, and 143d. In some embodiments, dielectric structure 151 is formed by a cut metal gate (CMG) process. In some embodiments, the structure of Figure 4I is used to form Figure 3 A perspective view of an intermediate stage of SRAM cell 10_1, wherein gate electrode 143a is shared by pull-down transistor PD-2, pull-up transistor PU-2, and isolation transistor IS-1, while gate electrode 143d is shared by pull-down transistor PD-1, pull-up transistor PU-1, and isolation transistor IS-2. Gate electrodes 143a and 143b are separated by one of dielectric structures 151, while gate electrodes 143c and 143d are separated by the other of dielectric structures 151. That is, dielectric structure 151 is a gate cleavage structure for gate electrodes 143a and 143b and for gate electrodes 143c and 143d.

[0143] In some embodiments, the dielectric structure 151 is made of silicon oxide, silicon nitride, SiON, SiCN, SiOCN, other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric structure 151 is formed by an etching process and a subsequent deposition process. The dielectric structure 151 may be formed before, during, or after the formation of the hard mask 147. In some embodiments, the dielectric structure 151 and the hard mask 147 are made of the same material and are formed simultaneously together.

[0144] Subsequently, according to some embodiments, a portion of the ILD layer 139 on the S / D structure 135 is removed, and multiple contacts are formed on the S / D structure 135: contacts 161a, 161b, 161c, 161d, 161e, 161f, 161g, and 161h, as shown. Figure 4J As shown. In some embodiments, the ILD layer 139 is penetrated by contacts 161a to 161h, and each of contacts 161a to 161h is electrically connected to the corresponding S / D structure 135 below.

[0145] More specifically, in some embodiments, a portion of the ILD layer 139 on the S / D structure 135 is removed by an etching process to form a contact opening (not shown), followed by a deposition process to fill the contact opening with contacts 161a to 161h. In some embodiments, contacts 161a to 161h are made of the following materials: W, Co, Ti, Al, Cu, Ta, Pt, Mo, Ag, Mn, Zr, Ru, or other suitable materials. In some embodiments, the deposition process for forming contacts 161a to 161h includes CVD, PVD, ALD, plating, or other suitable processes. After forming contacts 161a to 161h, an SRAM cell (e.g., SRAM cell) is obtained. Figure 3 The semiconductor structure 100 of the SRAM cell 10_1).

[0146] In some embodiments, SRAM cells (e.g.: Figure 3 The semiconductor structure 100 of the SRAM cell 10_1 includes dielectric fins 109a to 109e (i.e., virtual fins) between adjacent fins 103a to 103d (i.e., active fins). Therefore, when the size of the S / D structure 135 reaches its maximum value, undesirable bridging problems between the S / D structures 135 can be prevented. In this way, the contact resistance between the S / D structure 135 and the contacts 161a to 161h covering the S / D structure 135 is reduced, and the performance and operating speed of the semiconductor structure 100 of the SRAM cell are enhanced. Although Figure 4JEach dielectric fin 109a to 109e shown comprises a single thin layer, but each dielectric fin 109a to 109e may comprise multiple thin layers made of a variety of dielectric materials, and the interface between the various dielectric materials may be vertical and / or horizontal relative to the top surface of the dielectric fin 109a to 109e.

[0147] Figure 5A As shown in some embodiments of this disclosure, the semiconductor structure 100 of the SRAM cell follows... Figure 4J The cross-sectional view of the midline segment A-AA, and Figure 5B As shown in some embodiments of this disclosure, the semiconductor structure 100 of the SRAM cell follows... Figure 4J A cross-sectional view of the midline segment B-BB. In some embodiments, the above-mentioned SRAM cell is... Figure 1 SRAM cell 10_1.

[0148] According to some embodiments, each of fins 103a, 103b, 103c, and 103d has a width W1; each dielectric fin directly below the dielectric structure 151 (e.g., dielectric fins 109a and 109d) has a width W2; and each dielectric fin covered by gate electrodes 143a, 143b, 143c, and 143d (e.g., dielectric fins 109b, 109c, and 109e) has a width W3. Figure 5A As shown. In some embodiments, widths W2 and W3 are greater than width W1.

[0149] More specifically, in some embodiments, the ratio of width W2 to width W1 (W2 / W1) and the ratio of width W3 to width W1 (W3 / W1) are greater than about 1.2. If the ratios (W2 / W1 and W3 / W1) are too small (i.e., less than 1.2), then widths W2 and W3 will be too small, and the dielectric fins 109a to 109e may break down.

[0150] Furthermore, according to some embodiments, widths W2 and W3 are in the range of about 4 nm to about 40 nm. In some embodiments, widths W2 and W3 are substantially the same. Additionally, in some embodiments, the ratio of the width of the dielectric fin located at the boundary of an adjacent SRAM cell to the width of the dielectric fin located within the SRAM cell is greater than about 1.1.

[0151] In some embodiments, semiconductor structure 100 corresponds to Figure 3The SRAM cell 10_1 has fins 103a, 103b, 103c and 103d corresponding to the pull-down transistor PD-2, pull-up transistor PU-2, isolation transistor IS-1 and transmission gate transistor PG-1 respectively, and all fins 103a, 103b, 103c and 103d are made of silicon.

[0152] In some embodiments, each fin of the PMOS transistor (e.g., fins 103b and 103c of pull-up transistor PU-2 and isolation transistor IS-1) includes an upper portion (not shown) above an insulating pad 107” and a lower portion (not shown) below the upper portion, the upper portion being made of SiGe and having a Ge atomic percentage in the range of about % to about 35%, while the lower portion is made of Si.

[0153] Furthermore, each upper portion of the fin of the PMOS transistor has a height H1a, and each lower portion of the fin of the PMOS transistor has a height H1b. In some embodiments, the height H1a is in the range of about 40 nm to about 70 nm, while the height H1b is in the range of about 50 nm to about 200 nm.

[0154] In addition, each of the dielectric fins directly beneath the dielectric structure 151 (e.g., dielectric fins 109a and 109d) has a height H2, and each of the dielectric fins covered by the gate electrodes 143a, 143b, 143c, and 143d (e.g., dielectric fins 109b and 109c) has a height H3. In some embodiments, height H3 is greater than height H2 because the top portion of the dielectric fins directly beneath the dielectric structure 151 may be removed during the dicing metal gate (CMG) process. More specifically, the difference between height H3 and height H2 is in the range of about 3 nm to about 30 nm.

[0155] According to some embodiments, the S / D structure 135 contacts the sidewalls of dielectric fins 109a, 109b, 109c, 109d, and 109e, and contacts 161d and 161e are formed on the corresponding lower S / D structure 135 and electrically connected to the corresponding lower S / D structure 135, such as... Figure 5BAs shown. The S / D structure 135 formed on the recessed portions of fins 103a to 103d can be grown in the region defined by dielectric fins 109a to 109e, which allows the S / D structure 135 to contact the dielectric fins 109a to 109e. Therefore, when the size of the S / D structure 135 reaches its maximum value, undesirable bridging problems between the S / D structures 135 can be prevented. In this way, the contact resistance between the S / D structure 135 and contacts 161d and 161e is reduced, and the performance and operating speed of the transistors in the SRAM cell (e.g., SRAM cell 10_1) are enhanced.

[0156] Figure 6 As shown in some embodiments of this disclosure, Figure 1 SRAM layout, Figure 7A As shown in some embodiments of this disclosure, the semiconductor structure 200 of the SRAM cell 10_1 follows... Figure 6 The cross-sectional view of the midline segment A-AA, and Figure 7B As shown in some embodiments of this disclosure, the semiconductor structure 200 of the SRAM cell 10_1 follows... Figure 6 Cross-sectional view of the midline segment B-BB. The details of semiconductor structure 200 are similar to those of semiconductor structure 100, and will not be repeated here for the sake of simplicity.

[0157] although Figure 6 The layout only shows two SRAM cells: SRAM cell 10_1 and SRAM cell 10_2, but other SRAM cells can still be used with... Figure 6 The layout is combined. For example, with... Figure 3 Similarly, the copied SRAM cells of SRAM cell 10_1 flipped on the Y-axis and SRAM cell 10_2 flipped on the Y-axis can be compared with... Figure 6 The layout is combined.

[0158] In some embodiments, the transistors in SRAM cells 10_1 and 10_2 are fin transistors in N-type well region NW1 and P-type well regions PW1 and PW2. N-type well region NW1 is located between and adjacent to P-type well regions PW1 and PW2. Figure 6 The layout is similar to Figure 3 The layout is different in that Figure 6The NMOS transistors (i.e., pull-down transistor PD-1, pull-down transistor PD-2, transmission gate transistor PG-1, and transmission gate transistor PG-2) are dual-fin transistors. In some embodiments, each of the above-mentioned NMOS transistors includes multiple fins, while each PMOS transistor (i.e., pull-up transistor PU-1, pull-up transistor PU-2, isolation transistor IS-1, and isolation transistor IS-2) includes a single fin.

[0159] More specifically, according to some embodiments, pull-down transistor PD-2 and transmission gate transistor PG-2 share fins 103a1 and 103a2, while pull-down transistor PD-1 and transmission gate transistor PG-1 share fins 103d1 and 103d2, such as... Figure 6 As shown. In some embodiments, the gate electrode 143a is shared by the pull-down transistor PD-2, the pull-up transistor PU-2, and the isolation transistor IS-1, and the gate electrode 143a extends across fins 103a1, 103a2, 103b, and 103c. In some embodiments, the gate electrode 143b of the transmission gate transistor PG-1 extends across fins 103d1 and 103d2.

[0160] Furthermore, in some embodiments, the gate electrode 143c of the transmission gate transistor PG-2 extends across fins 103a1 and 103ad2. Additionally, the gate electrode 143d is shared by the isolation transistor IS-2, the pull-up transistor PU-1, and the pull-down transistor PD-1, and extends across fins 103b, 103c, 103d1, and 103d2.

[0161] According to some embodiments, a combined S / D structure 135' is formed on the recessed portions of fins 103a1 and 103a2, while another combined S / D structure 135' is formed on the recessed portions of fins 103d1 and 103d2, such as... Figure 7B As shown. In some embodiments, each of dielectric fins 109b and 109d is sandwiched between one of the merged S / D structures 135' and one of the S / D structures 135. Furthermore, each of contacts 161d and 161e covers one of the merged S / D structures 135' and one of the S / D structures 135.

[0162] Figure 8 This is a layout of an IC according to some embodiments of the present disclosure. According to some embodiments, the IC includes a logic cell array 50 and an SRAM 30, such as... Figure 8As shown. SRAM 30 includes multiple SRAM cells on P-type well areas PW1, PW2 and PW3 and N-type well areas NW1 and NW2: SRAM cells 10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7 and 10_8.

[0163] In some embodiments, the SRAM 30 also includes a plurality of fins: fins 103a, 103b, 103c, 103d, 103e, 103f, 103g, and 103h, and a plurality of dielectric fins: dielectric fins 109a, 109b, 109c, 109d, 109e, 109f, 109g, 109h, and 109i. It should be noted that, according to some embodiments, because... Figure 8 The SRAM 30 shown has single-fin transistors, so adjacent pairs of fins 103a to 103h are separated from each other by corresponding dielectric fins 109a to 109i. In some embodiments, some transistors of the SRAM 30 (e.g., PMOS transistors) have multiple fins. The details of the SRAM 30 may be similar to... Figure 3 The semiconductor structure 100 is described, and for the sake of simplicity, it will not be repeated here.

[0164] Furthermore, the logic unit array 50 includes multiple logic units: logic units 40_1, 40_2, 40_3, 40_4, 40_5, 40_6, 40_7, 40_8, 40_9, and 40_10. In some embodiments, logic units 40_1 to 40_10 are standard units (e.g., inverters (INV), AND, OR, NAND, NOR, flip-flops, SCAN, etc.), combinations thereof, or specific functional units. The logic functions of logic units 40_1 to 40_10 may be the same or different. For example, logic units 40_1 to 40_10 may be standard units corresponding to the same or different logic gates. Furthermore, each of logic units 40_1 to 40_10 may include multiple transistors. In some embodiments, logic units 40_1 to 40_10 corresponding to the same function or operation may have the same circuit configuration, wherein the circuit configuration has different semiconductor sizes and / or different semiconductor structures.

[0165] In addition, logic units 40_1, 40_3, 40_5, 40_7, and 40_9 are arranged in the same row, while logic units 40_2, 40_4, 40_6, 40_8, and 40_10 are arranged in the same row. In logic units 40_1, 40_3, 40_5, 40_7, and 40_9, NMOS transistors are formed on P-type well regions PW1, and PMOS transistors are formed on N-type well regions NW1. In logic units 40_2, 40_4, 40_6, 40_8, and 40_10, PMOS transistors are formed on N-type well regions NW1, and NMOS transistors are formed on P-type well regions PW2.

[0166] The logic cell array 50 also includes multiple fins: fins 103a, 103b, 103c, and 103d, and multiple dielectric fins: dielectric fins 109a, 109b, 109c, 109d, and 109e. Similar to the SRAM 30, according to some embodiments, adjacent pairs of fins among fins 103a to 103d are separated from each other by corresponding dielectric fins 109a to 109e.

[0167] In addition, according to some embodiments, the logic cell array 50 also includes a plurality of dielectric-based virtual gates: dielectric-based virtual gates 170a, 170b, 170c, 170d, 170e, 170f, 170g, 170h, 170i, 170j, 170k, 170l, 170m and 170n, extending along the X direction and disposed on the boundaries of logic cells 40_1 to 40_10, such as Figure 8 As shown. In some embodiments, dielectric-based virtual gates 170a to 170n are used to isolate adjacent logic cells 40_1 to 40_10 along the Y direction. For example, logic cells 40_1 and 40_3 are isolated (or separated) from each other by dielectric-based virtual gate 170c, while logic cells 40_2 and 40_4 are isolated (or separated) from each other by dielectric-based virtual gate 170d. Details of dielectric-based virtual gates 170a to 170n will be provided below. Figure 9 The following description is provided. It should be noted that the gate electrodes in the logic cell array 50 are not shown. Figure 8 middle.

[0168] In some embodiments, the dielectric fins 109a to 109e of the logic cell array 50 and the dielectric fins 109a to 109i of the SRAM 30 have widths along the X direction, and the widths of the dielectric fins 109a to 109e of the logic cell array 50 are greater than the widths of the dielectric fins 109a to 109i of the SRAM 30. In some embodiments, the ratio of the width of the dielectric fins 109a to 109e of the logic cell array 50 to the width of the dielectric fins 109a to 109i of the SRAM 30 is greater than about 1.2.

[0169] Figure 9 As shown in some embodiments of this disclosure, the logic cell array 50 is along... Figure 8 Cross-sectional view of the middle segment C-CC. According to some embodiments, multiple PMOS transistors are formed on the N-type well region NW1, such as... Figure 9 As shown.

[0170] It should be noted that fins 103b and 103c are used as channel regions for the PMOS transistors of the logic cells in the logic cell array 50. For example, fin 103b is used as the channel region for the PMOS transistors of logic cells 40_1 and 40_3, such as... Figure 9 As shown. In some embodiments, each of fins 103b and 103c includes an upper portion and a lower portion located below the upper portion. For example, fin 103b includes an upper portion 103b” and a lower portion 103b’, as shown. Figure 9 As shown. More specifically, in some embodiments, the upper portion of the fins of the PMOS transistors in the logic cell array 50 is made of SiGe, the lower portion of the fins of the PMOS transistors in the logic cell array 50 is made of Si, and the fins of the PMOS transistors in the SRAM 30 are made entirely of Si to reduce leakage current.

[0171] Furthermore, according to some embodiments, dielectric-based virtual gates 170a, 170c, and 170e extend into the fin 103b, a hard mask 177 is formed on the dielectric-based virtual gates 170a, 170c, and 170e, and spacers 171 are formed on the opposite sidewalls of the dielectric-based virtual gates 170a, 170c, and 170e, such as... Figure 9 As shown. Some materials used to form the hard mask 177 and the spacer 171 may be similar to or the same as the materials used to form the hard mask 147 and the gate spacer 121 described above, and will not be repeated here.

[0172] Apart from this, the details of the gate dielectric layer 141, hard mask 147, gate spacer 121, S / D structure 135, insulating pad 107, and ILD layer 139 are similar to those of the others. Figure 4J , Figure 5A and Figure 5B The semiconductor structure 100 is described above, and for the sake of simplicity, it will not be repeated here. Some materials used to form the gate electrode 143 and the contact 161 may be similar to or the same as those previously described. Figure 4J , Figure 5A and Figure 5B The materials used to form the gate electrodes 143a to 143d and the contacts 161a to 161h, as described in the document, will not be repeated here.

[0173] This disclosure provides embodiments of a semiconductor structure and methods for forming the same. The semiconductor structure includes a first P-type well region, a second P-type well region, an N-type well region, and an SRAM cell located on a substrate. The N-type well region is located between the first and second P-type well regions. The SRAM cell includes first and second pull-up transistors located on the N-type well region, a first pull-down transistor located on the second P-type well region, and a second pull-down transistor located on the first P-type well region. The first pull-up transistor, the second pull-up transistor, the first pull-down transistor, and the second pull-down transistor each include a first fin, a second fin, a third fin, and a fourth fin, respectively. The semiconductor structure also includes a first dielectric fin located between the second and fourth fins, a second dielectric fin located between the first and second fins, and a third dielectric fin located between the first and third fins. By providing dielectric fins (i.e., virtual fins) between adjacent fins (i.e., active fins), unwanted bridging problems between S / D structures can be prevented when the size of the S / D structure reaches its maximum value. In this way, the contact resistance between the S / D structure and the junctions above the S / D structure is reduced, and the performance and operating speed of the SRAM cell's semiconductor structure are enhanced.

[0174] Furthermore, the SRAM cell in the semiconductor structure has continuous fins spanning the entire SRAM cell. These continuous fins are used to form continuous dielectric fins that span the entire SRAM cell, or even span adjacent SRAM cells and are shared by adjacent SRAM cells. As a result, shrinkage that commonly occurs at the ends of the fins can be reduced, making fin alignment easier, and the process of forming the fins becomes easier due to fewer patterning steps.

[0175] In addition, compared with discontinuous fins (e.g., discontinuous fins of pull-up transistors), the continuous fins of the present disclosure embodiments have lower well resistance (e.g., N-type well resistance), which can achieve a better soft error rate (SER) and provide better latch-up prevention, which is beneficial for saving the area of ​​the cell array.

[0176] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first dielectric fin, a first semiconductor fin, and a second dielectric fin located on a substrate. The first semiconductor fin is located between the first dielectric fin and the second dielectric fin. The semiconductor structure also includes a first gate electrode surrounding the first dielectric fin, a channel region of the first semiconductor fin, and the second dielectric fin, and a first source / drain structure located on the source / drain portion of the first semiconductor fin, contacting and inserting into the first and second dielectric fins.

[0177] In one or more embodiments, the semiconductor structure further includes a first contact covering a portion of the first source / drain structure and the second dielectric fin. In one or more embodiments, the semiconductor structure further includes a second semiconductor fin and a third dielectric fin located on a substrate, wherein the second semiconductor fin is located between the second and third dielectric fins, and a first gate electrode surrounds a channel region of the second semiconductor fin; a second source / drain structure is located on the source / drain portion of the second semiconductor fin; and an interlayer dielectric layer covering the second source / drain structure. In one or more embodiments, the semiconductor structure further includes a third semiconductor fin and a fourth dielectric fin located on a substrate, wherein the third semiconductor fin is located between the third and fourth dielectric fins; a second gate electrode surrounds the channel region of the third semiconductor fin and the fourth dielectric fin; a third source / drain structure is located on the source / drain portion of the third semiconductor fin; and a second contact covering a portion of the third source / drain structure and the third dielectric fin. In one or more embodiments, the semiconductor structure further includes a dielectric structure aligned on the third dielectric fin and interposing the first gate electrode and the second gate electrode. In one or more embodiments, the semiconductor structure further includes a fourth semiconductor fin and a fifth dielectric fin located on the substrate, wherein the fourth semiconductor fin is located between the first dielectric fin and the fifth dielectric fin, and wherein the first gate electrode surrounds the channel region of the fourth semiconductor fin; a fourth source / drain structure located on the source / drain portion of the fourth semiconductor fin; and a third contact covering the fourth source / drain structure and the fifth dielectric fin. In one or more embodiments, the semiconductor structure further includes a static random access memory (SRAM) cell located on the substrate, comprising: a pull-down transistor including a channel region of a fourth semiconductor fin and a first gate electrode and a fourth source / drain structure; a pull-up transistor including a channel region of a first semiconductor fin and a first gate electrode and a first source / drain structure; an isolation transistor including a channel region of a second semiconductor fin and a first gate electrode and a second source / drain structure; and a transmission gate transistor including a channel region of a third semiconductor fin and a second gate electrode and a third source / drain structure.

[0178] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first P-type well region, an N-type well region, and a second P-type well region located on a substrate. The N-type well region is located between the first P-type well region and the second P-type well region. The semiconductor structure also includes a static random access memory (SRAM) cell located on the substrate. The SRAM cell includes a first pull-up transistor and a second pull-up transistor located on the N-type well region; and includes a first pull-down transistor located on the second P-type well region. The first pull-up transistor and the first pull-down transistor share a first gate electrode. The SRAM cell also includes a second pull-down transistor located on the first P-type well region. The second pull-up transistor and the second pull-down transistor share a second gate electrode. The SRAM cell further includes a first dielectric fin located between the second pull-down transistor and the second pull-up transistor, and a second gate electrode extending across the first dielectric fin. Furthermore, the SRAM cell includes a second dielectric fin located between the first pull-up transistor and the first pull-down transistor. The first gate electrode extends across the second dielectric fin, and the first and second dielectric fins extend across the aforementioned SRAM cell.

[0179] In one or more embodiments, a first dielectric fin is sandwiched between the source / drain structure of the second pull-down transistor and the source / drain structure of the second pull-up transistor, while a second dielectric fin is sandwiched between the source / drain structure of the first pull-down transistor and the source / drain structure of the first pull-up transistor. In one or more embodiments, the semiconductor structure further includes an insulating pad located on the first P-type well region, the N-type well region, and the second P-type well region, wherein the first and second dielectric fins protrude from the insulating pad, and the bottom surfaces of the first and second dielectric fins are higher than the bottom surface of the insulating pad. In one or more embodiments, the semiconductor structure further includes a first transmission gate transistor located on a second P-type well region; a second transmission gate transistor located on a first P-type well region; a first isolation transistor and a second isolation transistor located on an N-type well region, wherein a first gate electrode is shared by a first pull-up transistor and a second isolation transistor, and a second gate electrode is shared by a second pull-up transistor and a first isolation transistor; and wherein a first dielectric fin is sandwiched between the first gate electrode and a third gate electrode of the second transmission gate transistor, and a second dielectric fin is sandwiched between the second gate electrode and a fourth gate of the first transmission gate transistor. In one or more embodiments, the semiconductor structure further includes a dielectric structure located on the first dielectric fin and between the first gate electrode and the third gate electrode, wherein the top surface of the second dielectric fin is directly covered by the first gate electrode, and the top surface of the second dielectric fin is higher than the interface between the dielectric structure and the first dielectric fin. In one or more embodiments, the semiconductor structure further includes a third dielectric fin located between the first pull-up transistor and the second pull-up transistor, wherein the first gate electrode and the second gate electrode extend across the third dielectric fin; and wherein the first pull-up transistor includes a single fin, and the first pull-down transistor includes multiple fins. In one or more embodiments, the semiconductor structure further includes a logic unit located on the substrate, wherein the logic unit includes: a first fin and a second fin located on the substrate; and a fourth dielectric fin located between the first fin and the second fin, wherein the width of the fourth dielectric fin is greater than the width of the first dielectric fin in the SRAM cell.

[0180] In some embodiments, a method for forming a static random access memory (SRAM) cell is provided. The method includes forming a first P-type well region, an N-type well region, and a second P-type well region in a substrate; forming a first fin on the first P-type well region; forming a second and a third fin on the N-type well region; and forming a fourth fin on the second P-type well region. The method also includes forming an insulating pad on the first P-type well region, the N-type well region, and the second P-type well region. The first, second, third, and fourth fins protrude from the insulating pad. The method further includes forming a first dielectric fin, a second dielectric fin, and a third dielectric fin on the insulating pad. The first dielectric fin is located between the first and second fins, the second dielectric fin is located between the second and third fins, and the third dielectric fin is located between the third and fourth fins. Furthermore, the method for forming an SRAM cell includes forming a first dummy gate structure spanning a first fin, a first dielectric fin, a second fin, a second dielectric fin, a third fin, a third dielectric fin, and a fourth fin; and epitaxially growing a plurality of source / drain structures in the first fin, the second fin, the third fin, and the fourth fin adjacent to and on the opposite side of the first dummy gate structure. The plurality of source / drain structures directly contact the sidewalls of the first dielectric fin, the second dielectric fin, and the third dielectric fin.

[0181] In one or more embodiments, the method of forming an SRAM cell further includes forming an insulating pad material covering the first fin, the second fin, the third fin, and the fourth fin before forming the first dielectric fin, wherein a plurality of openings are formed between adjacent pairs of the first fin, the second fin, the third fin, and the fourth fin; forming a dielectric layer on the insulating pad material, wherein the dielectric layer extends into the openings; and grinding the dielectric layer and the insulating pad material such that the first dielectric fin, the second dielectric fin, and the third dielectric fin are formed from the remaining portion of the dielectric layer in the openings. In one or more embodiments, the method of forming an SRAM cell further includes partially removing the insulating pad material to form an insulating pad after the formation of the first dielectric fin, such that the first fin, the second fin, the third fin, the fourth fin, the first dielectric fin, the second dielectric fin, and the third dielectric fin protrude from the insulating pad. In one or more embodiments, the method of forming an SRAM cell further includes replacing the first dummy gate structure with a first gate electrode material; removing a portion of the first gate electrode material located on the first dielectric fin; and forming a first dielectric structure on the first dielectric fin such that the first gate and the second gate are separated by the first dielectric structure. In one or more embodiments, a portion of the first dielectric fin is removed during the removal of a portion of the first gate electrode material. In one or more embodiments, the method of forming an SRAM cell further includes forming a second dummy gate structure parallel to the first dummy gate structure and spanning the first fin, the first dielectric fin, the second fin, the second dielectric fin, the third fin, the third dielectric fin, and the fourth fin; replacing the second dummy gate structure with a second gate electrode material; removing a portion of the second gate electrode material located on the third dielectric fin; and forming a second dielectric structure on the fourth dielectric fin such that the third gate and the fourth gate are separated by the second dielectric structure.

[0182] The foregoing outlines the features of various embodiments or examples to enable those skilled in the art to better understand the manner of this disclosure. Those skilled in the art should understand that they can readily design or modify other processes and structures based on this disclosure to achieve the same purpose and / or attain the same advantages as the embodiments or examples described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

Claims

1. A semiconductor structure, comprising: A first dielectric fin, a first semiconductor fin, and a second dielectric fin are located on a substrate, wherein the first semiconductor fin is located between the first dielectric fin and the second dielectric fin. A first gate electrode surrounds the channel region of the first dielectric fin, the first semiconductor fin, and the second dielectric fin; A first source / drain structure is located on the source / drain portion of the first semiconductor fin, in contact with the first dielectric fin and the second dielectric fin, and inserted between the first dielectric fin and the second dielectric fin. A first contact, covering a first portion of the upper surface of the first source / drain structure and the second dielectric fin; as well as An interlayer dielectric layer covers a second portion of the upper surface of the second dielectric fin.

2. The semiconductor structure as described in claim 1, further comprising: A second semiconductor fin and a third dielectric fin are located on the substrate, wherein the second semiconductor fin is located between the second and third dielectric fins, and the first gate electrode surrounds the channel region of the second semiconductor fin; and A second source / drain structure is located on the source / drain portion of the second semiconductor fin; and The aforementioned interlayer dielectric layer covers the aforementioned second source / drain structure.

3. The semiconductor structure as described in claim 2, further comprising: A third semiconductor fin and a fourth dielectric fin are located on the substrate, wherein the third semiconductor fin is located between the third dielectric fin and the fourth dielectric fin. A second gate electrode surrounds the channel region of the third semiconductor fin and the fourth dielectric fin; A third source / drain structure is located on the source / drain portion of the aforementioned third semiconductor fin; and A second contact covers a portion of the aforementioned third source / drain structure and the aforementioned third dielectric fin.

4. The semiconductor structure as described in claim 3, further comprising: A dielectric structure is aligned above the third dielectric fin and inserted between the first gate electrode and the second gate electrode.

5. The semiconductor structure as described in claim 4, further comprising: A fourth semiconductor fin and a fifth dielectric fin are located on the substrate, wherein the fourth semiconductor fin is located between the first dielectric fin and the fifth dielectric fin, and wherein the first gate electrode surrounds the channel region of the fourth semiconductor fin. A fourth source / drain structure is located on the source / drain portion of the aforementioned fourth semiconductor fin; and A third contact covers the aforementioned fourth source / drain structure and the aforementioned fifth dielectric fin.

6. The semiconductor structure of claim 5, further comprising: A static random access memory cell, located on the aforementioned substrate, includes: A pull-down transistor includes the channel region of the fourth semiconductor fin and the first gate electrode and the fourth source / drain structure. A pull-up transistor includes the channel region of the first semiconductor fin and the first gate electrode and the first source / drain structure. An isolation transistor, including the channel region of the second semiconductor fin and the first gate electrode and the second source / drain structure; and A transmission gate transistor includes the channel region of the third semiconductor fin and the second gate electrode and the third source / drain structure.

7. The semiconductor structure of claim 3, wherein the second contact covers a first portion of the upper surface of the third dielectric fin, and the interlayer dielectric layer covers a second portion of the upper surface of the third dielectric fin.

8. A semiconductor structure, comprising: A first P-type well region, an N-type well region, and a second P-type well region are located on a substrate, wherein the N-type well region is located between the first P-type well region and the second P-type well region. A static random access memory (SRAM) cell is located on the substrate, wherein the SRAM cell includes: A first pull-up transistor and a second pull-up transistor are located on the aforementioned N-type well region; A first pull-down transistor is located on the second P-type well region, wherein the first pull-up transistor and the first pull-down transistor share a first gate electrode; A second pull-down transistor is located on the first P-type well region, wherein the second pull-up transistor and the second pull-down transistor share a second gate electrode; A first dielectric fin is located between the second pull-down transistor and the second pull-up transistor, wherein the second gate electrode extends across the first dielectric fin; and A second dielectric fin is located between the first pull-up transistor and the first pull-down transistor, wherein the first gate electrode extends across the second dielectric fin, and both the first and second dielectric fins extend across the static random access memory (SRAM) cell; and An insulating pad is located on the first P-type well region, the N-type well region, and the second P-type well region, wherein the bottom portion of the first dielectric fin is embedded in the insulating pad, and the upper portion of the first dielectric fin protrudes from the insulating pad.

9. The semiconductor structure of claim 8, wherein the first dielectric fin is sandwiched between the source / drain structure of the second pull-down transistor and the source / drain structure of the second pull-up transistor, and the second dielectric fin is sandwiched between the source / drain structure of the first pull-down transistor and the source / drain structure of the first pull-up transistor.

10. The semiconductor structure of claim 8, further comprising: A first transmission gate transistor is located on the aforementioned second P-type well region; A second transmission gate transistor is located on the aforementioned first P-type well region; A first isolation transistor and a second isolation transistor are located on the aforementioned N-type well region, wherein the first gate electrode is shared by the first pull-up transistor and the second isolation transistor, and the second gate electrode is shared by the second pull-up transistor and the first isolation transistor; and The first dielectric fin is sandwiched between the first gate electrode and a third gate electrode of the second transmission gate transistor, while the second dielectric fin is sandwiched between the second gate electrode and a fourth gate of the first transmission gate transistor.

11. The semiconductor structure of claim 10, further comprising: A dielectric structure is located on the first dielectric fin and between the first gate electrode and the third gate electrode, wherein the top surface of the second dielectric fin is directly covered by the first gate electrode, and the top surface of the second dielectric fin is higher than the interface between the dielectric structure and the first dielectric fin.

12. The semiconductor structure of claim 8, further comprising: A third dielectric fin is located between the first pull-up transistor and the second pull-up transistor, wherein the first gate electrode and the second gate electrode extend across the third dielectric fin; and The first pull-up transistor mentioned above includes a single fin, while the first pull-down transistor mentioned above includes multiple fins.

13. The semiconductor structure of claim 8, further comprising: A logic unit is located on the substrate, wherein the logic unit includes: A first fin and a second fin are located on the aforementioned substrate; and A fourth dielectric fin is located between the first fin and the second fin, wherein the width of the fourth dielectric fin is greater than the width of the first dielectric fin in the static random access memory unit.

14. The semiconductor structure of claim 8, wherein the first dielectric fin overlaps with a boundary portion between the first P-type well region and the N-type well region.

15. A method for forming a semiconductor structure, comprising: A first P-type well region, an N-type well region, and a second P-type well region are formed in a substrate; A first fin is formed on the first P-type well region, a second fin and a third fin are formed on the N-type well region, and a fourth fin is formed on the second P-type well region. An insulating pad is formed on the first P-type well area, the N-type well area and the second P-type well area. A first dielectric fin, a second dielectric fin, and a third dielectric fin are formed on the aforementioned insulating liner, wherein the first dielectric fin is located between the first fin and the second fin, the second dielectric fin is located between the second fin and the third fin, and the third dielectric fin is located between the third fin and the fourth fin. The insulating pad is partially removed, wherein after the insulating pad is partially removed, the upper surface of the insulating pad is lower than the upper surface of the first dielectric fin and higher than the bottom surface of the first dielectric fin. A first virtual gate structure is formed spanning the first fin, the first dielectric fin, the second fin, the second dielectric fin, the third fin, the third dielectric fin, and the fourth fin; and Adjacent to and on the opposite side of the first virtual gate structure, a plurality of source / drain structures are epitaxially grown in the first fin, the second fin, the third fin, and the fourth fin, wherein the source / drain structures directly contact the sidewalls of the first dielectric fin, the second dielectric fin, and the third dielectric fin.

16. The method for forming a semiconductor structure as described in claim 15, further comprising: Before forming the first dielectric fin, an insulating pad material is formed covering the first fin, the second fin, the third fin, and the fourth fin, wherein a plurality of openings are formed between adjacent pairs of the first fin, the second fin, the third fin, and the fourth fin. A dielectric layer is formed on the aforementioned insulating liner material, wherein the dielectric layer extends into the aforementioned opening; and The dielectric layer and the insulating pad material are ground so that the first dielectric fin, the second dielectric fin and the third dielectric fin are formed from the remaining portion of the dielectric layer in the opening, and the insulating pad is formed from the remaining portion of the insulating pad material.

17. The method for forming a semiconductor structure as described in claim 15, further comprising: The first virtual gate structure is replaced with a first gate electrode material; Remove a portion of the first gate electrode material located on the first dielectric fin; and A first dielectric structure is formed on the first dielectric fin, such that a first gate and a second gate are separated by the first dielectric structure.

18. The method of forming a semiconductor structure as claimed in claim 17, wherein a portion of the first dielectric fin is removed during the removal of the portion of the first gate electrode material.

19. The method for forming a semiconductor structure as described in claim 17, further comprising: Before forming the first dielectric structure, a hard mask layer is formed on the first gate electrode material, wherein the first dielectric structure is formed to pass through the hard mask layer and the first gate electrode material.

20. The method for forming a semiconductor structure as described in claim 15, further comprising: A second virtual gate structure is formed, which is parallel to the first virtual gate structure and spans the first fin, the first dielectric fin, the second fin, the second dielectric fin, the third fin, the third dielectric fin, and the fourth fin. The second virtual gate structure is replaced with a second gate electrode material; Remove a portion of the second gate electrode material located on the third dielectric fin; and A second dielectric structure is formed on the third dielectric fin, such that a third gate and a fourth gate are separated by the second dielectric structure.

21. A semiconductor structure, comprising: A first dielectric fin, a first semiconductor fin, and a second dielectric fin are located on a substrate, wherein the first semiconductor fin is inserted between the first dielectric fin and the second dielectric fin, and is spaced apart from the first dielectric fin and the second dielectric fin. A first source / drain structure is located on the source / drain portion of the first semiconductor fin; An interlayer dielectric layer covers a first portion of the upper surface of the first source / drain structure and the upper surface of the second dielectric fin. as well as A first contact is located in the interlayer dielectric layer and covers a second portion of the upper surface of the first source / drain structure and the upper surface of the first dielectric fin.

22. The semiconductor structure of claim 21, wherein the bottom surface of the first source / drain structure is lower than the upper surface of the first dielectric fin and higher than the bottom surface of the first dielectric fin.

23. The semiconductor structure of claim 21, further comprising: A first insulating pad separates the first dielectric fin from the first semiconductor fin; as well as A second insulating pad separates the second dielectric fin from the first semiconductor fin.

24. The semiconductor structure of claim 23, wherein the bottom surface of the first source / drain structure is lower than the upper surface of the first insulating pad.

25. The semiconductor structure of claim 21, wherein the first source / drain structure contacts both the first dielectric fin and the second dielectric fin.

26. The semiconductor structure of claim 21, further comprising: A gate-cut structure is located on the aforementioned first dielectric fin; as well as A gate electrode is in contact with the gate dicing structure and extends continuously across the channel region of the first semiconductor fin and the second dielectric fin.

27. The semiconductor structure of claim 21, further comprising: A second semiconductor fin and a third dielectric fin are located on the substrate, wherein the second semiconductor fin is located between the second dielectric fin and the third dielectric fin. A second source / drain structure is located on the source / drain portion of the second semiconductor fin, wherein the interlayer dielectric layer covers a first portion of the upper surface of the second source / drain structure; as well as A second contact is located in the interlayer dielectric layer and covers a second portion of the upper surface of the second source / drain structure and the upper surface of the third dielectric fin.

28. The semiconductor structure of claim 27, further comprising: A first well region and a second well region are located on the substrate, wherein the first semiconductor fin is formed on the first well region, the second semiconductor fin is formed on the second well region, and the first well region and the second well region have different conductivity types.

29. The semiconductor structure of claim 28, wherein the second dielectric fin overlaps with a boundary portion between the first well region and the second well region.

30. A semiconductor structure comprising: A pull-up transistor is located on a substrate, the pull-up transistor including a first channel region of a first semiconductor fin and a first source / drain structure on the first semiconductor fin; A pull-down transistor is adjacent to the pull-up transistor, and the pull-down transistor includes a first channel region of a second semiconductor fin and a second source / drain structure on the second semiconductor fin. A first isolation transistor is adjacent to the pull-up transistor, the first isolation transistor including a first channel region of a third semiconductor fin; A first transmission gate transistor is adjacent to the first isolation transistor, the first transmission gate transistor including a first channel region of a fourth semiconductor fin; A first gate electrode surrounds the first channel region of the first semiconductor fin, the first channel region of the second semiconductor fin, and the first channel region of the third semiconductor fin. A second gate electrode surrounds the first channel region of the fourth semiconductor fin; An insulating pad is located between the first semiconductor fin and the second semiconductor fin; A first dielectric fin is inserted between the pull-up transistor and the pull-down transistor, and includes a bottom portion embedded in the insulating pad; A second dielectric fin is inserted between the pull-up transistor and the first isolation transistor. A third dielectric fin is inserted between the first isolation transistor and the first transmission gate transistor; and A dielectric structure is located on the third dielectric fin and separates the first gate electrode from the second gate electrode.

31. The semiconductor structure of claim 30, wherein the dielectric fin contacts both the first source / drain structure and the second source / drain structure.

32. The semiconductor structure of claim 30, further comprising: One contact is electrically connected to both the first source / drain structure and the second source / drain structure.

33. The semiconductor structure of claim 32, wherein the contact covers the upper surface of the first dielectric fin.

34. The semiconductor structure of claim 30, wherein the pull-up transistor is formed on an N-type well region and the pull-down transistor is formed on a P-type well region.

35. The semiconductor structure of claim 30, further comprising: A second isolation transistor, located on the substrate, includes a second channel region of the first semiconductor fin and a third gate electrode surrounding the second channel region of the first semiconductor fin; and A second transmission gate transistor is adjacent to the second isolation transistor. The second transmission gate transistor includes a second channel region of the second semiconductor fin and a fourth gate electrode including the second channel region surrounding the second semiconductor fin, wherein the first dielectric fin is inserted between the third gate electrode and the fourth gate electrode.

36. A method for forming a semiconductor structure, comprising: A first semiconductor fin and a second semiconductor fin are formed on a substrate; An insulating material is formed on the first semiconductor fin and the second semiconductor fin; A dielectric layer is formed on the insulating material and fills a gap between the first semiconductor fin and the second semiconductor fin. The dielectric layer and the insulating material are ground until the first semiconductor fin and the second semiconductor fin are exposed, wherein the remaining portion of the dielectric layer forms a dielectric fin. The insulating material is excavated to expose the plurality of sidewalls of the dielectric fins; Forming a virtual gate structure spanning the first semiconductor fin, the dielectric fin, and the second semiconductor fin; and A first source / drain structure is formed on the first semiconductor fin, and a second source / drain structure is formed on the second semiconductor fin.

37. The method of forming a semiconductor structure as claimed in claim 36, wherein the first source / drain structure is formed until the first source / drain structure contacts the dielectric fin, and the second source / drain structure is formed until the second source / drain structure contacts the dielectric fin.

38. The method for forming a semiconductor structure as described in claim 36, further comprising: An inter-dielectric layer is formed on the first source / drain structure and the second source / drain structure described above; as well as A contact is formed, which passes through the interlayer dielectric layer and is located on the first source / drain structure, the dielectric fin, and the second source / drain structure.

39. The method for forming a semiconductor structure as described in claim 36, further comprising: Remove the aforementioned virtual gate structure; A gate electrode is formed spanning the first semiconductor fin, the dielectric fin, and the second semiconductor fin; as well as A dielectric structure is formed, which passes through the gate electrode and is located on the dielectric fin.

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