Integrated circuit and method for forming an integrated circuit

Abstract

An integrated circuit and a method for forming an integrated circuit, the integrated circuit device includes a semiconductor substrate having a memory region and a logic region. The memory cell in the memory region includes a select gate, and the select gate is separated from the floating gate by a floating gate spacer. The select gate spacer is formed on a side of the select gate opposite the floating gate. The select gate spacer has a uniform thickness over a majority of the select gate. The first layer of the select gate spacer may be formed by oxidizing the select gate electrode. The second layer of the select gate spacer may be formed by atomic layer deposition. When the spacer is formed in the logic region adjacent to the logic gate, the memory region may be covered with a protective layer.

Description

Technical Field

[0001] The present disclosure relates to embedded memory technology, which integrates memory devices and logic devices on the same semiconductor chip. Background Art

[0002] The integrated circuit (IC) manufacturing industry has experienced exponential growth over the past few decades. As integrated circuits have evolved, functional density (i.e., the number of interconnected devices per chip area) has increased while feature size has decreased. Other advances include the introduction of embedded memory technology and high-k dielectrics. K ) Metal Gate (HKMG) technology. Embedded memory technology is the integration of memory devices and logic devices on the same semiconductor chip. This memory device supports the operation of the logic device and improves the performance of the memory device compared to using separate chips for different types of devices. High-k Metal Gate (HKMG) technology is the manufacture of semiconductor devices using metal gate electrodes and high-k gate dielectric layers. Summary of the invention

[0003] Some embodiments of the present disclosure provide an integrated circuit (IC) comprising: a semiconductor substrate, a plurality of flash memory cells, and a plurality of logic gates. The semiconductor substrate comprises a memory region and a logic region. A plurality of flash memory cells are in the memory region; each of the flash memory cells comprises a floating gate, a control gate, and a select gate; each of the select gates comprises a select gate electrode, a select gate dielectric, and a select gate spacer; the select gate dielectric is adjacent to the semiconductor substrate below the select gate electrode; the select gate spacer is on one side of the select gate electrode relative to the floating gate. A plurality of logic gates are in the logic region, each of the logic gates comprises a logic gate electrode, and a logic gate spacer on either side of the logic gate electrode. Wherein the composition of the select gate spacer is different from the composition of the logic gate spacer.

[0004] Other embodiments of the present disclosure provide an integrated circuit (IC) comprising: a semiconductor substrate, a memory cell, a select gate spacer, a logic gate, and a logic gate spacer. The semiconductor substrate comprises a memory region and a logic region. The memory cell is in the memory region and comprises a select gate electrode, the select gate electrode being separated from the floating gate electrode by a floating gate spacer. The select gate spacer is on a side of the select gate electrode opposite to the floating gate electrode. The logic gate is in the logic region. The logic gate spacer is adjacent to the logic gate. The select gate spacer has a uniform thickness over a majority of the select gate electrode.

[0005] Still other embodiments of the present disclosure provide a method for forming an integrated circuit (IC), the method comprising: forming a floating gate stack above a memory region and a logic region of a semiconductor substrate; removing the floating gate stack from the logic region; forming a control gate stack above the floating gate stack in the memory region; patterning to form a control gate from the control gate stack; forming a plurality of control gate sidewall spacers adjacent to the control gate; patterning the floating gate stack to form a plurality of floating gates; forming a plurality of floating gate sidewall spacers adjacent to the floating gate; forming a select gate dielectric layer on the semiconductor substrate; forming a select gate layer above the select gate dielectric layer, the floating gate, and the control gate; etching the select gate layer to form a plurality of select gate electrodes; and oxidizing the select gate electrodes to form a first select gate spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure can be best understood by the following detailed description and reading in conjunction with the accompanying drawings. In accordance with standard industry practice, the various features are not drawn to scale. In addition, the sizes of the various features in the individual drawings may be arbitrarily increased or decreased relative to each other for ease of illustration and emphasis.

[0007] Figure 1A depicts a cross-sectional view of an integrated circuit (IC) according to some aspects of the present disclosure;

[0008] Figure 1B Draw Figure 1A An enlarged view of region 1A;

[0009] Figures 2 to 45 depicts a series of cross-sectional views of an integrated circuit according to some aspects of the present disclosure during a manufacturing process according to some aspects of the present disclosure;

[0010] Fig.46A and Fig.46B A flow chart of a manufacturing process according to some aspects of the present disclosure is presented.

[0011]

Explanation of symbols

[0012] 1: Integrated Circuit Devices

[0013] 1000: Section view

[0014] 101: Maximum thickness

[0015] 102: minimum thickness

[0016] 103:Thickness

[0017] 11: Control gate spacer

[0018] 1100: Section view

[0019] 1101: control gate dielectric layer

[0020] 1102: Control gate electrode layer

[0021] 1103: Control gate hard mask layer

[0022] 1105: Control gate stack

[0023] 1106: Lower oxide layer

[0024] 1107: Intermediate nitride layer

[0025] 1108: Upper oxide layer

[0026] 1110: first nitride layer

[0027] 1111: Oxide layer

[0028] 1112: second nitride layer

[0029] 12: Select gate dielectric structure

[0030] 1200: Section view

[0031] 1201: Control gate hard mask

[0032] 1203: Photoresist layer

[0033] 13: Control gate dielectric

[0034] 1300: Section view

[0035] 14: Floating gate electrode

[0036] 1400: Section view

[0037] 1401: floating gate spacer

[0038] 15: Floating Gate Dielectric

[0039] 1500: Section view

[0040] 1501: Photoresist layer

[0041] 1502: shared source / drain gap

[0042] 1600: Section view

[0043] 17:Siliconized pad

[0044] 1700: Section view

[0045] 18: Erase the gate electrode

[0046] 1800: Section view

[0047] 1801: Photoresist layer

[0048] 1802: Inter-unit gap

[0049] 19: Erase gate dielectric

[0050] 1900: Section view

[0051] 1A: Area

[0052] 2: Metal wire

[0053] 200: Section view

[0054] 2000: Section View

[0055] 2001: Selecting the gate electrode layer

[0056] 2002: Anti-reflective coating for memory

[0057] 201: pad oxide layer

[0058] 202: pad nitride layer

[0059] 203: Photoresist

[0060] 21: Memory source / drain region

[0061] 2100: Section view

[0062] 22: Spacer

[0063] 2200: Section view

[0064] 2201: Select gate hard mask layer

[0065] 2202: Gate Stack

[0066] 23: Select gate electrode

[0067] 2300: Section view

[0068] 2301: Select gate hard mask

[0069] 2302: Erase gate hard mask

[0070] 2303: Side wall

[0071] 2304: Select gate gap

[0072] 24: Select gate dielectric layer

[0073] 2400: Section view

[0074] 2401:Light-resistance mask

[0075] 25: Memory area

[0076] 2500: Section view

[0077] 2501: Second anti-reflective coating

[0078] 26: Memory source / drain region

[0079] 2600: Section view

[0080] 2600A: Cross-section view

[0081] 27: Memory source / drain region

[0082] 2700: Section view

[0083] 2701:Memory Overlay

[0084] 2702: Bottom anti-reflective coating

[0085] 2703: Lining

[0086] 28: Second selection gate dielectric layer

[0087] 2800: Section view

[0088] 29: ILD0 (Interlayer Dielectric 0) Layer

[0089] 2900: Section view

[0090] 2901:Mask

[0091] 3: Dielectric

[0092] 30:Siliconized pad

[0093] 300: Section view

[0094] 3000: Section view

[0095] 31: Guide hole

[0096] 3100: Section view

[0097] 3101: Oxide layer

[0098] 3102: High dielectric constant dielectric layer

[0099] 3103: Virtual gate electrode layer

[0100] 3104: Virtual gate hard mask layer

[0101] 3105: Virtual Gate Stack

[0102] 32: First selection gate spacer

[0103] 3200: Section view

[0104] 3201: Photoresist

[0105] 3202: Virtual gate electrode

[0106] 3203: Virtual Gate

[0107] 33: Contact Etch Stop Layer

[0108] 3300: Section view

[0109] 3400: Section view

[0110] 3500: Section view

[0111] 36: Second selection gate spacer

[0112] 3600: Section view

[0113] 3601: Photoresist

[0114] 3700: Section view

[0115] 38: Second sidewall spacer

[0116] 3800: Section view

[0117] 3801: Second anti-reflective coating

[0118] 39: Sidewall spacer

[0119] 3900: Section view

[0120] 400: Section view

[0121] 4000: Section view

[0122] 4100: Section view

[0123] 4200: Section view

[0124] 43:Substrate

[0125] 4300: Section view

[0126] 4301: Photoresist

[0127] 4302: Gap area

[0128] 4400: Section view

[0129] 4500: Section view

[0130] 4501:Hard Mask

[0131] 4600:Process

[0132] 4601: Action

[0133] 4602: Action

[0134] 4603: Action

[0135] 4604:Action

[0136] 4605:Action

[0137] 4606: Action

[0138] 4607:Action

[0139] 4608: Action

[0140] 4609:Action

[0141] 4610: Action

[0142] 4611: Action

[0143] 4612: Action

[0144] 4613: Action

[0145] 4614: Action

[0146] 4615: Action

[0147] 4616: Action

[0148] 4617: Action

[0149] 4618: Action

[0150] 4619: Action

[0151] 4620: Action

[0152] 4621: Action

[0153] 4622: Action

[0154] 4623: Action

[0155] 4624: Action

[0156] 4625: Action

[0157] 4626: Action

[0158] 4627: Action

[0159] 4628: Action

[0160] 4629: Action

[0161] 4630: Action

[0162] 4631: Action

[0163] 4633: Action

[0164] 4634: Action

[0165] 4635:Action

[0166] 4636: Action

[0167] 4637: Action

[0168] 4638: Action

[0169] 4639: Action

[0170] 4640: Action

[0171] 4641: Action

[0172] 4642: Action

[0173] 4643: Action

[0174] 4644:Action

[0175] 4645:Action

[0176] 4646:Action

[0177] 4647:Action

[0178] 4648: Action

[0179] 4649:Action

[0180] 4650: Action

[0181] 4651: Action

[0182] 4652: Action

[0183] 5: ILD1 (Interlayer Dielectric 1) Layer

[0184] 500: Section view

[0185] 57:Metal gate electrode

[0186] 59: Deep Well Implant

[0187] 600: Section view

[0188] 62:Logical Area

[0189] 63: Source / drain region

[0190] 65: Source / drain region

[0191] 66: Logic gate sidewall spacer structure

[0192] 67:Siliconized pad

[0193] 68:Oxide dielectric

[0194] 69: High dielectric constant dielectric

[0195] 7: Control gate electrode

[0196] 70: High dielectric constant metal gate

[0197] 700: Section view

[0198] 701: Photoresist

[0199] 73: Split-gate flash memory cell

[0200] 8: Select gate spacer structure

[0201] 800: Section view

[0202] 81: pad oxide layer

[0203] 82: pad nitride layer

[0204] 84: Oxide layer

[0205] 85: Isolation Area

[0206] 86: Nitride capping layer

[0207] 87: Oxide cover

[0208] 9:Siliconized pad

[0209] 90: Memory area

[0210] 900: Section view

[0211] 901: floating gate electrode layer

[0212] 902: floating gate dielectric layer

[0213] 903:Border area

[0214] 904: Boundary Isolation Structure

[0215] 91: Surrounding area DETAILED DESCRIPTION

[0216] The present disclosure provides many different embodiments or examples to implement different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. These are of course only examples and are not intended to be limiting. For example, in the subsequent description, a second feature is formed above or on a first feature, which may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact.

[0217] Spatially relative terms, such as "below," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship between one element or feature and another element or feature as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of a device or apparatus in use or operation in addition to the orientation depicted in the accompanying drawings. A device or apparatus may have other orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein may be interpreted accordingly. The terms "first," "second," "third," "fourth," and the like are merely general identification terms, and therefore may be interchangeable in various embodiments. For example, in some embodiments, an element (e.g., an opening) may be referred to as a "first" element, which may be referred to as a "second" element in other embodiments.

[0218] The present disclosure provides structures and manufacturing processes for embedding split gate flash memory into an integrated circuit (IC) including a logic gate. The integrated circuit includes a split gate flash memory cell disposed on or above a semiconductor substrate in a memory region, and a logic device disposed on or above the substrate in a logic region. The logic device may include an address decoder and / or a read / write circuit system and / or a microcontroller, and may control the operation of the memory cell and / or perform other tasks. An isolation region having an isolation structure may separate the memory region from the logic region.

[0219] The memory cells may include a control gate formed above the floating gate. Due to this stacked configuration, the memory cells may be taller than the logic devices. If the memory cells have the same pitch as the logic devices, the gaps between the memory cells will have a higher aspect ratio than the gaps between the logic devices. In some embodiments, the gaps between the memory cells may have a high aspect ratio, in part as a result of being bounded by a select gate electrode formed adjacent to the floating gate / control gate stack using a mask defined by spacer patterning techniques. The gap may be further reduced when sidewall spacers are formed. Narrow gaps with high aspect ratios can make operations such as dielectric fill more difficult.

[0220] The present disclosure provides structures and methods that can make the gap between memory cells larger without increasing the pitch. According to the present disclosure, a major portion of each select gate sidewall spacer is formed by oxidation of the select gate electrode. The oxidation process produces a first select gate sidewall spacer without substantially narrowing the gap between cells. The oxidation process may also increase the thickness of the select gate dielectric in a manner that makes the select gate dielectric thicker on the end away from the floating gate than on the end close to the floating gate. This structure allows the select gate sidewall spacer to be made thinner without increasing gate-induced drain leakage.

[0221] The second select gate sidewall spacer may be formed via deposition. In some of the present teachings, the second select gate sidewall spacer is formed via atomic layer deposition (ALD). Allowing a portion of the entire select gate sidewall spacer to be formed via deposition (particularly via atomic layer deposition) is advantageous because an oxide layer is routinely deposited over the entire memory area to provide an etch stop layer for removing a protective layer that covers the memory area when the logic gate is patterned. The second select gate sidewall spacer may be very thin. In some of the present teachings, the select gate spacer formed via deposition is thinner than the select gate spacer formed via oxidation.

[0222] Both the oxidation process and the atomic layer deposition process have the property of forming the sidewall spacers without reducing the verticality of the sidewalls that define the gaps between adjacent memory cells. These processes tend to produce sidewall spacers that are uniform in thickness. Uniformity is maintained over most of the select gates. Some thickening of the sidewall spacers may occur near the substrate because oxidation occurs under the select gate spacers and has a particularly high ratio at the corners where the side surface meets the bottom surface.

[0223] In the prior art, it is typical to remove the protective layer from the memory area before forming the logic gate spacer. In some aspects of the present teachings, the protective layer is not removed until after the logic gate spacer has been formed. This allows the select gate spacer to have a different composition than the logic gate spacer. In some aspects of the present teachings, the logic gate spacer includes a nitride layer, but the select gate spacer does not include a nitride layer. In some aspects of the present teachings, the select gate spacer is thinner than the logic gate spacer.

[0224] Figure 1A A cross-sectional view of selected portions of an integrated circuit device 1 according to some aspects of the present teachings is provided. These portions include a portion of a memory region 25 and a portion of a logic region 62, both formed on a substrate 43. The logic region 62 includes a high-k metal gate 70, and the memory region 25 includes a split-gate flash memory cell 73.

[0225] The split gate flash memory cell 73 includes a floating gate electrode 14 (separated from the substrate 43 by a floating gate dielectric 15), a control gate electrode 7 (separated from the floating gate electrode 14 by a control gate dielectric 13), an erase gate electrode 18 (separated from the substrate 43 by an erase gate dielectric 19), and a select gate electrode 23 (separated from the substrate 43 by a select gate dielectric structure 12). A control gate spacer 11 is formed on the side of the control gate electrode 7. A floating gate sidewall spacer 22 is formed on the side of the floating gate electrode 14. The floating gate sidewall spacer 22 separates the floating gate electrode 14 from the select gate electrode 23.

[0226] Figure 1B Provided in Figure 1A Magnified view of the region identified in 1A. Figure 1B As can be seen more easily in FIG. 1 , select gate spacer structure 8 is formed on a side of select gate electrode 23 opposite to floating gate dielectric 15. Select gate spacer structure 8 includes first select gate spacer 32 and second select gate spacer 36. First select gate spacer 32 is an oxidation product of the material forming select gate electrode 23, which may be polysilicon or the like. In some of these teachings, first select gate spacer 32 has a thickness from about 100 nm to about 100 nm. arrive In some of these teachings, the first select gate spacer 32 has a thickness ranging from arrive In some of these teachings, the first select gate spacer 32 has a thickness that is greater than that which can be produced by native oxide formation. The native oxide formation process is self-limiting, resulting in or less maximum thickness.

[0227] In some of these teachings, the second select gate spacer 36 is an oxide formed by a deposition process. More generally, the second select gate spacer 36 may be an oxide, a nitride, or the like. In some of these teachings, the second select gate spacer 36 has a thickness from arrive In some of these teachings, the second select gate spacer 36 has a thickness ranging from arrive The thickness is within the range of .

[0228] In some of these teachings, the total thickness 103 of the select gate spacer structure 8 at its mid-height is arrive In some of these teachings, the thickness 103 is in the range of arrive A heavily doped memory source / drain region 26 is formed in the substrate 43 by doping aligned with the select gate spacer structure 8 .

[0229] Select gate gap 2304, which is a gap between select gate spacer structures 8, has substantially vertical sidewalls 2303. Substantially vertical sidewalls are sidewalls that are within twenty degrees of vertical relative to the surface of substrate 43. Sidewalls 2303 are within ten degrees of vertical relative to the surface of substrate 43.

[0230] The select gate dielectric structure 12 includes a first select gate dielectric layer 24 and a second select gate dielectric layer 28. In some of these teachings, the thickness of the first select gate dielectric layer 24 is in the range of arrive In some of these teachings, the thickness of the first select gate dielectric layer 24 is within a range of arrive The first select gate dielectric layer 24 may be an oxide, other suitable dielectric, or the like. In some of these teachings, the first select gate dielectric layer 24 is an oxidation product of the material forming the substrate 43. The second select gate dielectric layer 28 is an oxidation product of the material forming the select gate electrode 23.

[0231] In some of these teachings, the select gate dielectric structure 12 has a dielectric greater than The minimum thickness and less than In some of these teachings, the thickness is arrive In some of these teachings, the select gate dielectric structure 12 has a thickness that increases relative to the distance from the floating gate electrode 14. In some of these teachings, the select gate dielectric structure 12 has a maximum thickness 101 that increases from to is greater than the minimum thickness 102 of the select gate dielectric structure 12. In some of these teachings, the difference is in arrive In some of these teachings, the difference is in arrive within the range.

[0232] The high-k metal gate (HKMG) gate 70 includes a high-k dielectric 69 and a metal gate electrode 57. A logic gate sidewall spacer structure 66 is formed on the side of the metal gate electrode 57. The logic gate sidewall spacer structure 66 may include any suitable combination of materials with any suitable thickness. In some embodiments, the logic gate sidewall spacer structure 66 includes a first sidewall spacer 39 and a second sidewall spacer 38, respectively. In some embodiments, the first sidewall spacer 39 is a nitride or the like. In some embodiments, the first sidewall spacer 39 has a thickness from arrive In some embodiments, the first sidewall spacer 39 has a thickness ranging from arrive In some embodiments, the second sidewall spacer 38 is an oxide, or the like. In some embodiments, the second sidewall spacer 38 has a thickness ranging from arrive In some embodiments, the second sidewall spacer 38 has a thickness ranging from arrive In some embodiments, the logic gate sidewall spacer structure 66 is thicker than the total thickness 103 of the select gate spacer structure 8. arrive In some embodiments, the logic gate sidewall spacer structure 66 is thicker than the total thickness 103 of the select gate spacer structure 8. arrive

[0233] The high-k dielectric may be a metal oxide or silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), or the like. Examples of high-k dielectrics include TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, and ZrSiO2, or the like. The high-k dielectric 69 has a dielectric constant of about to about In some of these teachings, the high dielectric constant dielectric 69 has a thickness ranging from about to about The high-k dielectric 69 may be separated from the substrate 43 by an oxide dielectric 68. The oxide dielectric 68 is a non-high-k dielectric. The integrated circuit device 1 may include different high-k metal gate gates 70, and different high-k metal gate gates 70 have different thicknesses of oxide dielectric 68. Some high-k metal gate gates may have oxide dielectric 68 with a thickness ranging from about to about Other high-k metal gate-type gates may have an oxide dielectric 68 with a thickness ranging from about to about The metal gate electrode 57 may have any suitable thickness. In some of these teachings, the thickness of the metal gate electrode 57 is in the range of to within the range.

[0234] The high-k metal gate gate 70 may be formed over the deep well implant 59. The lightly doped high-k metal gate source / drain regions 63 and the heavily doped high-k metal gate source / drain regions 65 may provide source / drain regions for the high-k metal gate gate 70 and may be aligned with the sidewall spacers 39 and the second sidewall spacers 38, respectively. The heavily doped high-k metal gate source / drain regions 65 may have a silicide pad 67 at its surface. The high-k metal gate gate 70 may be formed via a gate-last process. Therefore, the high-k metal gate gate 70 is not subjected to the conditions required to anneal the implants in the heavily doped high-k metal gate source / drain regions 65. If the high-k metal gate 70 is subjected to such conditions, the high-k dielectric 69 and the metal gate electrode 57 may interact in a manner that changes the threshold voltage of the high-k metal gate 70 .

[0235] Various metallization layers may be formed above the split gate flash memory cell 73 and the high dielectric constant metal gate gate 70. These include a first metallization layer, which includes metal lines 2 formed in a dielectric 3. The dielectric 3 may be a low dielectric constant dielectric. Additional metallization layers may be formed above the one shown. The metallization layers are coupled to the source / drain regions via vias 31. The vias 31 pass through the dielectric layers, which include an ILD0 (interlayer dielectric 0) layer 29 at the height of the split gate flash memory cell 73 and the high dielectric constant metal gate gate 70, and an ILD1 (interlayer dielectric 1) layer 5, the ILD0 (interlayer dielectric 0) layer 29 being at the height of the split gate flash memory cell 73 and the high dielectric constant metal gate gate 70, while the ILD1 (interlayer dielectric 1) layer 5 being higher than the split gate flash memory cell 73 and the high dielectric constant metal gate gate 70.

[0236] The substrate 43 is a semiconductor and may be or include, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a III-V substrate, or other suitable semiconductor substrates. The substrate 43 may be a binary semiconductor substrate (e.g., GaAs), a ternary semiconductor substrate (e.g., AlGaAs), or a higher-order semiconductor substrate.

[0237] Figures 2 to 45 A series of cross-sectional views 600 to 4500 are provided, which illustrate an integrated circuit device according to the present disclosure at different stages of manufacture according to a process according to the present disclosure. Figures 2 to 45 The description is about a series of actions, it should be understood that in some cases, the order of the actions may be changed, and this series of actions is applicable to other structures besides the illustrated structure. In some embodiments, some of these actions may be omitted in whole or in part. In addition, Figures 2 to 45 Described as a series of actions, it should be understood that Figures 2 to 45 The structure shown in is not limited to a method of manufacturing, but is a structure that may exist independently of the method.

[0238] Figure 2 A cross-sectional view 200 is provided, which illustrates an initial step in which a pad oxide layer 201 and a pad nitride layer 202 are formed over a substrate 43. A photoresist 203 may be formed and patterned to cover the pad nitride layer 202 in the surrounding area 91. The photoresist 203 may be used to selectively etch the pad nitride layer 202 from the memory area 90, such as Figure 3 As shown in the cross-sectional view 300 of FIG. Figure 3As further illustrated in the cross-sectional view 300 of , after stripping the photoresist 203, an oxidation process may then be performed to recess the substrate 43 in the memory region 90. Although the split-gate flash memory cell 73 has a greater height, the substrate 43 in the memory region 90 is recessed so that the top of the split-gate flash memory cell 73 is aligned with the top of the high-k metal gate 70. The oxidation process produces an oxide layer 84. The oxidation process may be a wet oxidation process. Alternatively, the oxidation may be accomplished by dry oxidation, steam oxidation, or some other suitable process.

[0239] The oxide layer 84 may be thinned to approximate the thickness of the pad oxide layer 201, as shown in the cross-sectional view 400 of FIG. 4. The original pad oxide layer 201 and pad nitride layer 202 may then be stripped and replaced with the pad oxide layer 81 and pad nitride layer 82, as shown in the cross-sectional view 500 of FIG. 5. The isolation region 85 may then be formed by depositing an oxide or oxide precursor to form the oxide of the isolation region 85 by placing a patterned mask, etching through the pad oxide layer 81, the pad nitride layer 82, and etching into the substrate 43. After the oxide is formed, chemical mechanical polishing (CMP) may be used to produce the level surface shown in the cross-sectional view 500 of FIG. 5.

[0240] like Figure 6 As shown in the cross-sectional view 600 of FIG. 6 , a nitride capping layer 86 and an oxide capping layer 87 may then be formed. The oxide capping layer 87 may be a resist protective oxide, or some other suitable type of oxide. Alternative processes that do not include a nitride capping layer 86 or an oxide capping layer 87 are also possible.

[0241] like Figure 7 As shown in the cross-sectional view 700 of FIG. 1 , when the pad layer is removed from the memory region 90, a photoresist 701 may be used to protect the surrounding region 91. The photoresist 701 may then be stripped, followed by deposition of a floating gate dielectric layer 902 and a floating gate electrode layer 901, and chemical mechanical polishing (CMP) to remove these layers and the oxide capping layer 87 from the surrounding region 91, as shown in FIG. Figure 8 800. The floating gate dielectric layer 902 may be any suitable dielectric layer. The floating gate dielectric layer 902 may be grown on the substrate 43 or deposited on the substrate 43. The floating gate electrode layer 901 may be conformally deposited on the floating gate dielectric layer 902 and may be doped polysilicon or the like. The floating gate electrode layer 901 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or the like.

[0242] like Fig. 9As shown in the cross-sectional view 900 of FIG. 9 , an etching process may then be performed to thin the floating gate electrode layer 901 to a desired thickness. This etch back may be accomplished by dry etching and hydrofluoric acid (HF) immersion or the like. Fig. 9 The memory region 90 and the surrounding region 91 are shown separated by a boundary region 903 , and the boundary region 903 has a boundary isolation structure 904 . Fig. 9 Memory region 25 is also identified and is an exemplary region within memory region 90 . Fig. 9 A logic region 62 is further defined, which is an exemplary region within the surrounding region 91 . Fig.10 Drawing and Fig. 9 The cross-sectional view 1000 corresponds to the cross-sectional view 900 , except that it only focuses on these two areas, and the same is true for subsequent cross-sectional views.

[0243] like Fig.11 As shown in the cross-sectional view 1100 of , a control gate stack 1105 may be formed above the floating gate electrode layer 901. The control gate stack 1105 includes a control gate dielectric layer 1101, a control gate electrode layer 1102, and a control gate hard mask layer 1103. The control gate dielectric layer 1101 may include one or more layers of oxide, nitride, other suitable dielectrics, or the like. The control gate dielectric layer 1101 may include multiple layers of different dielectrics. In some embodiments, the control gate dielectric layer 1101 is a charge trapping dielectric. In some embodiments, the control gate dielectric layer 1101 includes an ONO film having a lower oxide layer 1106, an intermediate nitride layer 1107 covering the lower oxide layer 1106, and an upper oxide layer 1108 covering the intermediate nitride layer 1107. The control gate dielectric layer 1101 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), other suitable deposition processes, any combination thereof, or the like.

[0244] The control gate dielectric layer 1101 is very thin. The lower oxide layer 1106 may have a thickness in the range of 10 to 1000 angstroms. In some embodiments, the lower oxide layer 1106 has a thickness in the range of 20 to 50 angstroms, for example, about 40 angstroms. The middle nitride layer 1107 may have a thickness in the range of 25 to 200 angstroms. In some embodiments, the middle nitride layer 1107 has a thickness in the range of 50 to 100 angstroms, for example, about 80 angstroms. The upper oxide layer 1108 may have a thickness in the range of 10 to 100 angstroms. In some embodiments, the upper oxide layer 1108 has a thickness in the range of 20 to 50 angstroms, for example, about 40 angstroms. In some embodiments, the total thickness of the control gate dielectric layer 1101 is in the range of 25 to 400 angstroms. In some embodiments, the total thickness of the control gate dielectric layer 1101 is in the range of 50 to 200 angstroms.

[0245] The control gate electrode layer 1102 may be formed conformally and may be formed of doped polysilicon or the like. In some embodiments, the process of forming the control gate electrode layer 1102 includes depositing a material, implanting a dopant into the material, and annealing to activate the dopant. The material of the control gate electrode layer 1102 may be deposited via chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes. In some embodiments, the control gate electrode layer 1102 has a thickness in a range from 600 to 2000 angstroms. In some embodiments, the control gate electrode layer 1102 has a thickness in a range from 300 to 1000 angstroms. In some embodiments, the control gate electrode layer 1102 has a thickness of approximately 600 angstroms.

[0246] The control gate hard mask layer 1103 may include multiple layers of different materials. The control gate hard mask layer 1103 may include oxide, nitride, or other suitable materials. In some embodiments, the control gate hard mask layer 1103 includes an oxide layer 1111 above the first nitride layer 1110. In some embodiments, the thickness of these layers ranges from 100 to 1400 angstroms. In some embodiments, the thickness of these layers ranges from 200 to 700 angstroms, for example. In some embodiments, these layers are about 400 angstroms thick. In some embodiments, the control gate hard mask layer 1103 also includes a second nitride layer 1112 above the oxide layer 1111. The control gate hard mask layer 1103 may be formed via chemical vapor deposition (CVD), physical vapor deposition (PVD), other suitable deposition processes, any combination of the above, or the like.

[0247] like Fig.121200, a selective etch may be performed to remove portions of the control gate stack 1105 from the memory region 25, thereby forming a control gate hard mask 1201, a control gate electrode 7, and a control gate dielectric 13 above the floating gate electrode layer 901. In some embodiments, the process for performing the selective etch includes forming and patterning a photoresist layer 1203. The photoresist layer 1203 may be patterned to cover portions of the logic region 62 and the memory region 25, which portions of the memory region 25 form a negative image of the control gate electrode 7. An etching process may then be applied with the photoresist layer 1203 in place until the floating gate electrode layer 901 is exposed. The photoresist layer 1203 may then be stripped.

[0248] like Fig.13 As shown in the cross-sectional view 1300 of , the control gate spacer 11 may be formed adjacent to the control gate hard mask 1201. The control gate spacer 11 covers the sidewalls of the control gate electrode 7. The control gate spacer 11 may be formed by depositing a layer of spacer material and then etching. The control gate spacer 11 may have any suitable composition. The control gate spacer 11 may include one or more layers of oxide, nitride, other suitable dielectric, or the like. In some embodiments, the control gate spacer 11 includes an ONO film, for example, a lower oxide layer, an intermediate nitride layer, and an upper oxide layer. The spacer material may be deposited via chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition process. The etching process may include plasma etching or any other suitable etching process that selectively removes the spacer material where the spacer material is thinnest relative to the vertical direction. For ease of illustration, a control gate spacer 11 with vertical sidewalls is shown. The etching process for spacer formation may produce rounded corners and smoothly tapered sidewalls.

[0249] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , etching may be performed to the floating gate electrode layer 901 and the floating gate dielectric layer 902 (see FIG. 1 ). Fig.13 ) to form the floating gate electrode 14 and the floating gate dielectric 15. The control gate spacer 11 and the control gate hard mask 1201 may be used as a mask for this etching. Fig.14 As further shown in the cross-sectional view 1200 of FIG. 1 , a floating gate spacer 1401 may be formed on the sidewalls of the floating gate electrode 14 and on the sidewalls of the control gate spacer 11. The floating gate spacer 1401 may be an oxide, other suitable dielectric, or the like. The process of forming the floating gate spacer 1401 may include: Fig.14A floating gate spacer layer is deposited over the structure depicted in the cross-sectional view 1400 of FIG. 1 , followed by plasma etching or any other suitable etching process that selectively removes the floating gate spacer layer where the floating gate spacer layer is thinnest relative to the vertical direction. The conformal deposition of the floating gate spacer layer may be via chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition process.

[0250] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , lightly doped memory source / drain regions 21 may be formed in the substrate 43 laterally between the plurality of floating gate electrodes 14. The process of forming the heavily (the common source is a high dose implant) doped memory source / drain regions 21 may include forming and patterning a photoresist layer 1501 that covers portions of the logic region 62 and the memory region 25 outside of the common source / drain gap 1502. Ion implantation or other suitable doping processes may be performed with the photoresist layer 1501 in place. The photoresist layer 1501 may be patterned using lithography.

[0251] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , the floating gate spacer 1401 within the common source / drain gap 1502 may be removed. The process for removing the floating gate spacer 1401 may include etching the photoresist layer 1501 in place. The photoresist layer 1501 may then be stripped.

[0252] like Fig.17 As shown in the cross-sectional view 1700 of , an erase gate dielectric 19 may be formed to cover the memory source / drain regions 21 and the sidewalls of the floating gate electrode 14 and the control gate spacer 11 that are lined within the common source / drain gap 1502. The erase gate dielectric 19 may be formed of an oxide, a nitride, or other suitable dielectric. The process of forming the erase gate dielectric 19 may include high temperature oxidation (HTO), in-situ steam generation (ISSG) oxidation, other suitable deposition or growth processes, any combination of the above, or the like. In some embodiments, the erase gate dielectric 19 is formed by an oxide deposition process followed by an oxide growth process. In some embodiments, the erase gate dielectric 19 develops a curved or spherical surface profile due to ion implantation in the memory source / drain regions 21. The central region of the memory source / drain region 21 receives a larger dose of dopants and, therefore, experiences more damage than the surrounding regions of the memory source / drain region 21. Therefore, the oxide may grow faster in the central region than in the surrounding regions.

[0253] like Fig.18As shown in the cross-sectional view 1800 of FIG. 1 , a photoresist layer 1801 may be formed to cover portions of the logic region 62 and the memory region 25 outside the inter-cell gap 1802, and the photoresist layer 1801 is used to remove the floating gate spacer 1401 from within the inter-cell gap 1802. Fig.19 1900, after removing the photoresist layer 1801, a first select gate dielectric layer 24 and an erase gate sidewall spacer 22 may then be formed in the inter-cell gap 1802. The first select gate dielectric layer 24 and the erase gate sidewall spacer 22 may be one or more layers of oxide, nitride, or other suitable dielectrics, or the like. The first select gate dielectric layer 24 and the erase gate sidewall spacer 22 may be formed via high temperature oxidation (HTO), in-situ steam generation (ISSG) oxidation, other suitable deposition or growth processes, any combination of the above, or the like.

[0254] Also by Fig. 20 As shown in the cross-sectional view 2000 of FIG. 2 , a select gate electrode layer 2001 may be formed to cover the first select gate dielectric layer 24 and other structures in the logic region 62 and the memory region 25. The select gate electrode layer 2001 may be formed of doped polysilicon or the like, or other suitable conductive materials, and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes. Fig. 20 The cross-sectional view 2000 also depicts a memory anti-reflective coating (ARC) 2002 formed above the select gate electrode layer 2001. The memory anti-reflective coating 2002 may be formed, for example, from a flowable organic material applied via a spin coating process, wherein the wafer of the substrate 43 is rotated about the center of the wafer while the liquid anti-reflective coating is applied on the wafer surface. Due to the flowability of the liquid anti-reflective coating, the liquid anti-reflective coating tends to develop a horizontal surface. After the liquid anti-reflective coating is spin-coated, a baking step may be performed to harden the memory anti-reflective coating 2002.

[0255] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 2 , a process may be performed to remove the memory anti-reflective coating 2002 (see FIG. Fig. 20) and thin the selection gate electrode layer 2001. This process forms the erase gate electrode 18. The removal and thinning may be performed with an etching process that has approximately equal tolerance to the memory anti-reflective coating 2002 and the selection gate electrode layer 2001. The memory anti-reflective coating 2002 may be etched back until the selection gate electrode layer 2001 is exposed, after which the selection gate electrode layer 2001 and the memory anti-reflective coating 2002 may be etched back together until the memory anti-reflective coating 2002 is completely removed. The selection gate electrode layer 2001 may then be etched back until the top surface of the selection gate electrode layer 2001 is approximately flush with the top surface of the control gate electrode 7. The etching process causes the recessed selection gate electrode layer 2001 to have a substantially flat surface. Dopants may be implanted into or with the selection gate electrode layer 2001, followed by annealing to activate the dopants. Photoresist masks may be used to vary the dopant type between n-type and p-type, or to vary the doping for different regions and device types.

[0256] like Fig. 22 As shown in the cross-sectional view 2200 of Fig.21 A memory select gate hard mask layer 2201 is conformally formed over the structure shown in the cross-sectional view 2100 of FIG. The memory select gate hard mask layer 2201 may be formed of nitride, oxide, or other suitable hard mask materials. The memory select gate hard mask layer 2201 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes.

[0257] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 1 , etching may be used to select the gate hard mask layer 2201 from the memory (see FIG. 1 ). Fig. 22 ) to form a select gate hard mask 2301 and an erase gate hard mask 2302. The first part of this etching process forms the select gate hard mask 2301 and the erase gate hard mask 2302. The select gate hard mask 2301 develops into a spacer shape. The spacer shape comes from the select gate hard mask layer 2201 being deposited on the gate stack 2202 (see Fig. 22 ) is then etched using an anisotropic etching process. The same or another anisotropic etching process may then be used to pattern the select gate electrode layer 2001 to form a select gate gap 2304 while retaining the area covered by the select gate hard mask 2301 to form the select gate electrode 23. The etching process may be a plasma etch or the like. The select gate gap 2304 has a sidewall 2303 that is substantially perpendicular to the adjacent select gate electrode 23. The sidewall 2303 is within ten degrees of perpendicular relative to the surface of the substrate 43.

[0258] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 24, etching may be performed with a photoresist mask 2401 covering the illustrated portion of the memory region 25. This additional etching may terminate the conductive lines formed by some of the illustrated structures in the page direction. This etching may thin the control gate hard mask layer 1103 above the logic region 62.

[0259] like Fig.25 As shown in the cross-sectional view 2500, it is possible to Fig.24 A second anti-reflective coating 2501 is formed on the structure shown in the cross-sectional view 2400 of FIG. The second anti-reflective coating 2501 may be formed with a flat or substantially flat top surface. The second anti-reflective coating 2501 may be used in conjunction with a non-selective etch back process to allow the Fig.24 The top portion of the structure depicted in the cross-sectional view 2400 is recessed to produce Fig.26A The etch-back process may stop on or in the control gate hard mask layer 1103, the control gate hard mask 1201, and the select gate hard mask 2301. After the etch-back process, the second anti-reflective coating 2501 may be removed, such as Fig.26A As shown in cross-sectional view 2600.

[0260] like Fig.26B 26, an oxidation process is performed to oxidize a surface layer of the select gate electrode 23 to form a first select gate spacer 32. This process maintains the verticality of the sidewalls 2303 of the select gate gap 2304 and does not significantly narrow the select gate gap 2304. Some of the oxidant that forms the first select gate spacer 32 may diffuse through the first select gate dielectric layer 24 to oxidize the bottom of the select gate electrode 23 and form the second select gate dielectric layer 28. The oxidation process may be a wet oxidation process, high temperature oxidation (HTO), in situ steam generation (ISSG), other suitable oxidation processes, or the like. In some of these teachings, the oxidation process is a wet oxidation process. In some of these teachings, the oxidation process is a dry oxidation process.

[0261] like Fig. 27 As shown in the cross-sectional view 2700 of Fig.26BA liner 2703, a memory cap layer 2701, and a bottom anti-reflective coating (BARC) 2702 are formed over the structure depicted in the cross-sectional view 2600A of FIG. Memory cap layer 2701 is a protective layer because it is a temporary layer that protects the structure in the memory region 25 through a series of processing steps directed to other areas of substrate 43, and memory cap layer 2701 is subsequently removed. Memory cap layer 2701 may be polysilicon or the like. Liner layer 2703 may have a composition that is suitable for providing an etch stop when memory cap layer 2701 is subsequently removed. In some of these teachings, liner layer 2703 is an oxide or the like. According to some aspects of the present teachings, a portion of liner layer 2703 will remain in integrated circuit device 1 to provide a portion of select gate spacer structure 8.

[0262] The liner 2703 may be formed via any suitable process. In some of these teachings, the liner 2703 is formed via a process that maintains the verticality of the sidewalls 2303 of the select gate gap 2304. A suitable process for this purpose is atomic layer deposition (ALD) or the like. Atomic layer deposition is a cyclic process including the following stages, in which the surface to be coated is saturated with reactants used to form the coating. Another stage in this cycle causes a reaction, through which a layer of coating is formed by a reaction containing the reactants. Saturation allows the reactants to be evenly distributed before the reaction. The atomic layer deposition process maintains the verticality of the sidewalls 2303 and provides control over the thickness of the liner 2703, which helps to provide sufficient thickness to the select gate spacer structure 8 without unnecessarily narrowing the select gate gap 2304.

[0263] The memory cap layer 2701 may be formed via chemical vapor deposition (CVD), physical vapor deposition (PVD), other suitable deposition processes, any combination of the above, or the like. The memory cap layer 2701 may be partially conformal to the surface it covers. The bottom anti-reflective coating 2702 helps level the memory cap layer 2701. The bottom anti-reflective coating 2702 may be formed from a liquid coating that is spin-coated over the memory cap layer 2701 to provide a flat or substantially flat top surface. After the bottom anti-reflective coating 2702 is spin-coated, a baking step may be performed to harden the bottom anti-reflective coating 2702.

[0264] like Fig.28 As shown in cross-sectional view 2800 of FIG. 28 , a process may be performed to remove the bottom anti-reflective coating 2702 (see FIG. Fig. 27) and leaves the memory cap layer 2701 with a concave and relatively horizontal surface. This process may be an etch under which the bottom anti-reflective coating 2702 and the memory cap layer 2701 have very similar etching rates. Initially, the etching proceeds through the bottom anti-reflective coating 2702 until the memory cap layer 2701 is exposed. The etching continues to etch the bottom anti-reflective coating 2702 and the memory cap layer 2701 simultaneously until the bottom anti-reflective coating 2702 is completely removed. This etching process may leave the memory cap layer 2701 with a well-defined thickness above the memory region 25.

[0265] like Fig.29 As shown in cross-sectional view 2900 of , a photoresist mask 2901 may be formed and patterned over the memory cap layer 2701 in the memory region 25. Similar to other photoresist masks, the photoresist mask 2901 may be formed via a process that includes spin coating, or forming a photoresist on a surface of a structure, selectively exposing the photoresist to light through a reticle or other lithographic mask, and using a chemical developer to remove the exposed or unexposed portions. With the mask 2901 in place, etching may be performed to remove the control gate electrode layer 1102 and the control gate hard mask layer 1103 from the logic region 62. After etching, the photoresist mask 2901 may be removed. Similar to other photoresist masks, the photoresist mask 2901 may be removed via full exposure and development, etching, ashing, or any other suitable removal process. As shown in FIG. Fig.30 As shown in cross-sectional view 3000 of , additional etching may be performed to remove the control gate dielectric layer 1101 and the nitride capping layer 86 from the logic region 62 .

[0266] like Fig.31 As shown in the cross-sectional view 3100 of Fig.30 A dummy gate stack 3105 is formed over the structure depicted in the cross-sectional view 3000 of FIG. The dummy gate stack 3105 may include an oxide layer 3101, a high-k dielectric layer 3102, a dummy gate electrode layer 3103, and a dummy gate hard mask layer 3104. In general, the dummy gate stack dielectric may include any suitable number and combination of dielectric layers, and may be made with thicknesses and / or compositions that vary between different devices in the logic region 62. The dummy gate electrode layer 3103 may be polysilicon or the like or other suitable material. The dummy gate hard mask layer 3104 may be a nitride, an oxide, polysilicon, or the like. The conformal formation of these layers of the dummy gate stack 3105 may be via chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, other suitable growth or deposition processes, any combination of the foregoing, or the like. The oxide layer 3101 may be grown on the substrate 43.

[0267] like Fig.32 3200, a photoresist 3201 may be used to define a dummy gate 3203 in the logic region 62, while removing the oxide layer 3101, the high-k dielectric layer 3102, the dummy gate electrode layer 3103, and the dummy gate hard mask layer 3104 from other locations. This etch forms an oxide dielectric 68 from the oxide layer 3101, a high-k dielectric 69 from the high-k dielectric layer 3102, and a dummy gate electrode 3202 from the dummy gate electrode layer 3103. This process may effectively remove the high-k dielectric layer 3102 from areas outside the logic region 62.

[0268] like Fig.33 As shown in the cross-sectional view 3300 of , sidewall spacers 39 may then be formed on the sides of the dummy gate 3203. The sidewall spacers 39 may be oxides, nitrides, other suitable dielectrics, any combination of the foregoing, or the like. The sidewall spacers 39 may be formed via a spacer patterning technique that includes depositing over a mandrel provided by the dummy gate 3203 and etching to remove the spacer material where the spacer material is thinnest relative to the vertical direction. Conformally depositing the spacer material may be via chemical vapor deposition (CVD), physical vapor deposition (PVD), other suitable deposition processes, any combination of the foregoing, or the like. The spacer material may be etched via any suitable etching process to form the sidewall spacers 39. A suitable etching process may be anisotropic plasma etching, or the like.

[0269] like Fig.34 3400. Dopants may be implanted to form lightly doped logic source / drain regions 63 in logic region 62. Lightly doped logic source / drain regions 63 may be formed aligned with sidewall spacers 39. Photoresist masks may be used to provide varying doping types and concentrations between logic region 62 and other regions in surrounding region 91 (see FIG. Fig. 9 ).

[0270] like Fig.35 As shown in the cross-sectional view 3500 of , second sidewall spacers 38 may then be formed adjacent to the dummy gate 3203. These spacers may also be formed via spacer patterning techniques. The second sidewall spacers 38 may be oxide or the like.

[0271] like Fig.363600, the photoresist 3601 may then be used to mask the logic region 62 while the memory cap layer 2701 is etched from the memory region 25. The liner 2703 may provide an etch stop for this removal process. An anisotropic etch process may be performed to remove the liner 2703 and the first select gate dielectric layer 24 from the bottom of the select gate gap 2304. Dopants may then be implanted to form lightly doped memory source / drain regions 27.

[0272] like Fig.37 As shown in the cross-sectional view 3700 of , additional dopants may be implanted to form heavily doped memory source / drain regions 26 in the memory region 25 and heavily doped high-k metal gate source / drain regions 65 in the logic region 62. The heavily doped memory source / drain regions 26 may be formed aligned with the liner 2703. The heavily doped high-k metal gate source / drain regions 65 are formed aligned with the second sidewall spacers 38. Doping may be performed in a series of steps, masking various regions and sub-regions to provide a range of doping concentrations and types for various devices. After doping, annealing may be performed to activate the dopants within the substrate 43. By Fig.37 As further shown in the cross-sectional view 3700 of , a silicide metal deposition (salicidation) process may be performed to form silicide pads 30 and silicide pads 67 on the heavily doped memory source / drain regions 26 and the heavily doped high-k metal gate source / drain regions 65, respectively. The silicide may be nickel silicide, titanium silicide, cobalt silicide, other silicides, or the like, and may be formed via any suitable silicide process.

[0273] like Fig.38 As shown in the cross-sectional view 3800, it is then possible to Fig.37 A second anti-reflective coating 3801 is formed on the structure shown in the cross-sectional view 3700 of FIG. The second anti-reflective coating 3801 may be formed to have a flat or substantially flat top surface. The process of forming the second anti-reflective coating 3801 may include spin coating an organic anti-reflective coating coating. Fig.39 3900, then a process may be performed to obtain Fig.38 The top layer is removed from the structure depicted in the cross-sectional view 3800 of FIG. This process forms the second select gate spacer 36 from the liner 2703. The removal process is a chemical mechanical polishing process. However, in some embodiments, the removal is accomplished by etching using a process for which the various materials removed have similar susceptibilities so that the top surface remains substantially flat. A suitable etching process may be a dry etch including plasma from a fluorocarbon and He etchant.

[0274] like Fig.40 The second anti-reflective coating 3801 may then be removed, and then formed as shown in the cross-sectional view 4000 of Fig.41 The cross-sectional view 4100 of FIG. 4 shows the contact etch stop layer 33 and the ILD0 (interlayer dielectric 0) layer 29. The ILD0 (interlayer dielectric 0) layer 29 may be an oxide, a low-k dielectric, other suitable dielectrics, any combination thereof, or the like. Removal of the second anti-reflective coating 3801 may be by etching or any other suitable removal process. The process of forming the ILD0 (interlayer dielectric 0) layer 29 may include chemical vapor deposition, physical vapor deposition, sputtering, or any other suitable process. Fig.42 As shown in the cross-sectional view 4200 of , the ILD0 layer 29 may be planarized and its top surface may be recessed to expose the dummy gate electrode 3202. The planarization and recessing may be performed by chemical mechanical polishing or any other suitable process or combination of processes.

[0275] like Fig.43 As shown in the cross-sectional view 4300 of , while etching is performed to remove the dummy gate electrode 3202, a photoresist 4301 may be used to cover the memory region 25, leaving a void region 4302. Fig.44 As shown in the cross-sectional view 4400 of FIG. 4 , a metal gate electrode 57 may then be formed by filling the void region 4302. Filling may include forming one or more layers of various metals by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, or other suitable growth or deposition processes. The metal deposited or grown outside the void region 4302 may then be removed by planarization. The planarization process may be chemical mechanical polishing or the like.

[0276] As in Fig.45 As shown in the cross-sectional view 4500 of FIG. 4 , a hard mask 4501 may be formed and patterned to cover the logic region 62 and the control gate electrode 7, while forming a silicide pad 9 and a silicide pad 17 on the select gate electrode 23 and the erase gate electrode 18, respectively. The silicide may be nickel silicide, other silicides, or the like, and may be formed by any suitable silicide process.

[0277] Additional processing may be performed to form Figure 1A Additional processes form the ILD1 (interlayer dielectric 1) layer 5, dielectric 3, vias 31, and metal lines 2. These may be formed by any suitable process or combination of processes, including, for example, a damascene process, a dual damascene process, and the like.

[0278] Fig.46A and Fig.46BA flow chart of a process 4600 according to some aspects of the present disclosure is provided, which may be used to produce an integrated circuit device according to the present disclosure. Although process 4600 is illustrated and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be interpreted in a restrictive sense. For example, some actions may occur in a different order and / or occur simultaneously with actions or events other than those shown and / or described herein. In addition, not all of the actions shown are necessary to implement one or more aspects or embodiments of the present description. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0279] Process 4600 begins with action 4601 to form a pad layer, which may be a pad oxide layer 201 and a pad nitride layer 202 on a substrate 43, such as Figure 2 The process 4600 continues with action 4602, which removes the pad oxide layer 201 and the pad nitride layer 202 from the memory region 90, as shown in FIG. Figure 3 As shown in FIG. 4603, the substrate 43 in the memory area 90 is recessed, as shown in FIG. Figure 3 as shown in .

[0280] Action 4604 is to remove the pad oxide layer 201 and the pad nitride layer 202. Action 4605 is to form a new pad oxide layer 81 and a new pad nitride layer 82, as shown in FIG. 5. Action 4606 is to form an isolation region 85, as shown in FIG. Figure 8 as shown in .

[0281] Action 4607 is to form a nitride capping layer 86 and an oxide capping layer 87, such as in Figure 6 Action 4608 is to remove the nitride capping layer 86 and the oxide capping layer 87 from the memory region 90, as shown in Figure 7 As shown in . Action 4609 is to form a floating gate stack, the floating gate stack includes a floating gate dielectric layer 902 and a floating gate electrode layer 901. Action 4610 is planarization to remove the floating gate from the surrounding area 91, as shown in Figure 8 Action 4611 is to thin the floating gate electrode layer 901 to a desired thickness, as shown in Fig. 9 and Fig.10 as shown in .

[0282] Action 4612 is to form a control gate stack 1105, the control gate stack 1105 including a control gate dielectric layer 1101, a control gate electrode layer 1102, and a control gate hard mask layer 1103, as in Fig.11Action 4613 is patterning to define a control gate, the control gate comprising a control gate dielectric 13, a control gate electrode 7, and a control gate hard mask 1201, as shown in Fig.12 Action 4614 is to form a control gate spacer 11, as in Fig.13 as shown in .

[0283] Action 4615 is etching to define a floating gate, the floating gate comprising a floating gate dielectric 15 and a floating gate electrode 14. Action 4616 is doping to provide memory source / drain regions 21 in the memory region 25, as in Fig.15 Action 4617 is to form an erase gate dielectric 19, as shown in Fig.17 Action 4618 is to form a floating gate spacer 22, as in Fig.19 As shown in . Action 4619 is to form a first select gate dielectric layer 24, also as in Fig.19 As shown in . Action 4620 is to deposit the select gate electrode layer 2001, as in Fig. 20 Action 4621 is to etch back the select gate electrode layer 2001 to approximately the height of the control gate electrode 7, defining the erase gate electrode 18, as shown in Fig.21 as shown in .

[0284] Action 4622 is to form a select gate hard mask layer 2201, such as in Fig. 22 Action 4623 is etching to define a select gate hard mask 2301 from the select gate hard mask layer 2201 and a select gate electrode 23 from the select gate electrode layer 2001, as shown in Fig.23 . Action 4623 first forms a select gate hard mask 2301 from the select gate hard mask layer 2201, and then uses the select gate hard mask 2301 as a mask to etch through the select gate electrode layer 2001. Actions 4622 and 4623 form the select gate hard mask 2301 according to the spacer patterning technique. Action 4624 is a stripe removal etch. This results in a thinning of the control gate hard mask layer 1103 in the logic region 62, as shown in FIG. Fig.24 This strip removal etch may occur elsewhere in the process 4600. Action 4625 is to form a second anti-reflective coating 2501, as in Fig.25 Action 4626 is a planarization etch that reduces the height of the memory stack, as shown in Fig.26A as shown in .

[0285] Action 4627 is an oxidation process to form a first select gate spacer 32 by oxidizing the select gate electrode 23, as in Fig.26BThe oxidation process may also form a second select gate dielectric layer 28. Action 4628 is atomic layer deposition to form a liner 2703, as shown in Fig. 27 Action 4629 is to deposit the memory cap layer 2701 and the virtual bottom anti-reflective coating 2702, as in Fig. 27 Action 4630 is a planarization etch that removes the virtual bottom anti-reflective coating 2702, as shown in Fig.28 Action 4631 is to remove the memory cell stack from the logic area 62, as shown in Fig.29 and Fig.30 as shown in .

[0286] Then continue to Fig.46B 4, the process 4600 continues with action 4633 to remove the pad nitride layer 82 and the pad oxide layer 81 from the logic region 62, as shown in Fig.30 Action 4634 is to form a deep well implant in the logic region 62, as in Fig.30 as shown in .

[0287] Action 4635 is to form a dummy gate stack 3105, as in Fig.31 . The dummy gate stack 3105 may include an oxide layer 3101, a high-k dielectric layer 3102, a dummy gate electrode layer 3103, and a dummy gate hard mask layer 3104. Action 4636 is patterning to remove the dummy gate stack 3105 from the memory region 25 while defining a dummy gate 3203 in the logic region 62, as shown in Fig.32 as shown in .

[0288] Action 4637 is to form sidewall spacers 39 adjacent to dummy gate 3203, as in Fig.34 As shown in FIG. 4638, lightly doped high-k metal gate source / drain regions 63 are implanted, as shown in FIG. Fig.34 The number of masks and doping steps depends on the desired number of different source / drain doping types and concentrations.

[0289] Action 4639 is to form a second sidewall spacer 38, such as in Fig.35 Action 4640 is to remove memory overlay 2701 from memory region 25, as shown in Fig.36 Action 4641 is to implant heavily doped memory source / drain regions 26 and heavily doped high-k metal gate source / drain regions 65, as shown in Fig.37. Again, the number of masks and doping steps depends on the desired number of different source / drain doping types and concentrations. Action 4642 is annealing. Annealing repairs damage to substrate 43 caused by the fabric plant and activates the fabric plant. Action 4643 is siliciding to form silicide pads 30 and 67 in memory region 25 and logic region 62, respectively.

[0290] Action 4644 is to remove the select gate hard mask 2301, the control gate hard mask 1201, and the erase gate hard mask 2302 from the memory region 25. This may be done as in Fig.38 , and performing non-selective etching to recess the resulting surface, as shown in Fig.39 The second anti-reflective coating 3801 may be removed later, as shown in Fig.40 as shown in .

[0291] Action 4645 is to deposit a first interlayer dielectric layer, namely, ILD0 (interlayer dielectric 0) layer 29, as in Fig.41 This is followed by action 4646, exposing the virtual gate electrode 3202. This may be done as shown in Fig.42 Action 4647 is to remove the dummy gate electrode 3202, as shown in Fig.43 as shown in .

[0292] Action 4648 is to deposit and / or grow metal for high-k metal gate 70. Next is action 4649, chemical mechanical polishing, to remove excess metal, leaving only the metal forming the metal gate electrode 57, as in Fig.44 as shown in .

[0293] Action 4650 is saliciding to form silicide pads 9 and 17 on the select gate electrode 23 and the erase gate electrode 18, respectively, as shown in FIG. Fig.45 A mask may be used to prevent silicide from forming on the control gate electrode 7.

[0294] Action 4651 is to form a first metal interconnect layer, which includes vias 31, metal lines 2, and ILD1 (interlayer dielectric 1) layer 5, as in Figure 1A 4652 is an additional process to complete the formation of the integrated circuit device, including further back-end-of-line (BEOL) processes. It is understood that process 4600 is a replacement gate or gate-last process.

[0295] Some aspects of the present teachings relate to an integrated circuit comprising a semiconductor substrate having a memory region and a logic region. A plurality of flash memory cells are in the memory region. Each of the flash memory cells comprises a floating gate, a control gate, and a select gate. Each of the select gates comprises a select gate electrode, a select gate dielectric adjacent to the substrate below the select gate electrode, and a select gate spacer on a side of the select gate opposite to the floating gate. A plurality of logic gates form a logic region. Each of the logic gates comprises a logic gate electrode, a logic gate dielectric adjacent to the substrate below the logic gate electrode, and a logic gate spacer on either side of the logic gate electrode. The composition of the select gate spacer is different from the composition of the logic gate spacer.

[0296] In some of these teachings, the select gate spacer comprises a first oxide layer grown from the select gate electrode. In some of these teachings, the select gate spacer comprises a second oxide layer formed via deposition. In some of these teachings, the select gate dielectric comprises an oxide layer grown from the select gate electrode. In some of these teachings, the select gate dielectric is thicker on a side adjacent to the select gate spacer than on a side of the select gate dielectric distal from the select gate spacer.

[0297] Some aspects of the present teachings relate to an integrated circuit comprising a semiconductor substrate having a memory region and a logic region. A memory cell in the memory region comprises a select gate separated from a floating gate by a floating gate spacer. The select gate spacer is formed on a side of the select gate opposite to the floating gate. The select gate spacer has a uniform thickness over a majority of the select gate. A logic gate spacer may be formed in the logic region adjacent to the logic gate.

[0298] In some aspects of the present teachings, the logic gate spacer has a composition different from that of the select gate spacer. In some aspects of the present teachings, the logic gate spacer is thicker than the select gate spacer. In some aspects of the present teachings, the logic gate spacer includes an oxide layer and a nitride layer, and the select gate spacer includes only an oxide layer. In some aspects of the present teachings, the select gate spacer is substantially vertical. In some aspects of the present teachings, there is a select gate dielectric between the select gate and the substrate, and the select gate dielectric has a thickness that increases relative to a distance from the floating gate.

[0299] Some aspects of the present teachings relate to a method of forming an integrated circuit, the method comprising forming a floating gate stack above a memory region and a logic region of a semiconductor substrate. Removing the floating gate stack from the logic region, forming a control gate stack above the floating gate stack in the memory region, patterning to form a control gate from the control gate stack, forming a control gate sidewall spacer adjacent to the control gate, patterning the floating gate stack to form a floating gate, forming a floating gate sidewall spacer adjacent to the floating gate, forming a select gate dielectric layer on the substrate, forming a select gate layer above the select gate dielectric layer, the floating gate, and the control gate, etching the select gate layer to form a select gate, and oxidizing the select gate to form a first select gate spacer. In some of these teachings, oxidizing the select gate to form the first select gate spacer increases the thickness of the select gate dielectric layer.

[0300] In some of these teachings, the method also includes, after forming the first select gate spacer, covering the memory region with a protective layer, forming a logic gate stack, patterning the logic gate stack to form a logic gate, which may be a dummy gate, forming a spacer layer over the protective layer and the logic gate, etching the spacer layer to form a spacer adjacent to the logic gate, and removing the protective layer from the memory region.

[0301] In some of these teachings, the method includes depositing an oxide over the first select gate spacer to form a second select gate spacer before depositing the protective layer. In some of these teachings, the second select gate spacer is formed via atomic layer deposition.

[0302] In some of these teachings, the method includes depositing a select gate hard mask layer over a mandrel formed in part by a control gate using a conformal deposition process, and etching the select gate hard mask layer to form a select gate hard mask. In these teachings, etching the select gate layer to form the select gate includes etching through the select gate layer in an area adjacent to the select gate hard mask.

[0303] Some embodiments of the present disclosure provide an integrated circuit (IC) comprising: a semiconductor substrate, a plurality of flash memory cells, and a plurality of logic gates. The semiconductor substrate comprises a memory region and a logic region. A plurality of flash memory cells are in the memory region; each of the flash memory cells comprises a floating gate, a control gate, and a select gate; each of the select gates comprises a select gate electrode, a select gate dielectric, and a select gate spacer; the select gate dielectric is adjacent to the semiconductor substrate below the select gate electrode; the select gate spacer is on one side of the select gate electrode relative to the floating gate. A plurality of logic gates are in the logic region, each of the logic gates comprises a logic gate electrode, and a logic gate spacer on either side of the logic gate electrode. Wherein the composition of the select gate spacer is different from the composition of the logic gate spacer.

[0304] In some implementations, in an integrated circuit, a logic gate spacer is thicker than a select gate spacer.

[0305] In some embodiments, in an integrated circuit, a logic gate spacer includes an oxide layer and a nitride layer; and a select gate spacer includes only an oxide layer.

[0306] In some embodiments, in an integrated circuit, a select gate spacer includes a first oxide layer grown from a select gate electrode.

[0307] In some embodiments, in an integrated circuit, the first oxide layer is thicker than the native oxide layer.

[0308] In some embodiments, in an integrated circuit, the select gate spacer further includes a second oxide layer formed by deposition; and the first oxide layer is thicker than the second oxide layer.

[0309] In some implementations, in an integrated circuit, a select gate dielectric includes an oxide layer grown from a select gate electrode.

[0310] In some implementations, in an integrated circuit, a select gate dielectric is thicker on a side of the select gate dielectric adjacent to the select gate spacers than on a side of the select gate dielectric distal from the select gate spacers.

[0311] In some implementations, in an integrated circuit, select gate spacers have a more vertical profile than logic gate spacers.

[0312] Other embodiments of the present disclosure provide an integrated circuit (IC) comprising: a semiconductor substrate, a memory cell, a select gate spacer, a logic gate, and a logic gate spacer. The semiconductor substrate comprises a memory region and a logic region. The memory cell is in the memory region and comprises a select gate electrode, the select gate electrode being separated from the floating gate electrode by a floating gate spacer. The select gate spacer is on a side of the select gate electrode opposite to the floating gate electrode. The logic gate is in the logic region. The logic gate spacer is adjacent to the logic gate. The select gate spacer has a uniform thickness over a majority of the select gate electrode.

[0313] In some implementations, in an integrated circuit, a logic gate spacer has a set of compositions that is different than a set of compositions of a select gate spacer.

[0314] In some embodiments, in an integrated circuit, wherein the logic gate spacer is thicker than the select gate spacer.

[0315] In some embodiments, the integrated circuit further comprises: a select gate dielectric interposed between the select gate electrode and the semiconductor substrate; wherein the select gate dielectric has a thickness that increases relative to a distance from the floating gate electrode.

[0316] In some implementations, in an integrated circuit, a semiconductor substrate includes source / drain regions aligned with select gate spacers.

[0317] Still other embodiments of the present disclosure provide a method for forming an integrated circuit (IC), the method comprising: forming a floating gate stack above a memory region and a logic region of a semiconductor substrate; removing the floating gate stack from the logic region; forming a control gate stack above the floating gate stack in the memory region; patterning to form a control gate from the control gate stack; forming a plurality of control gate sidewall spacers adjacent to the control gate; patterning the floating gate stack to form a plurality of floating gates; forming a plurality of floating gate sidewall spacers adjacent to the floating gate; forming a select gate dielectric layer on the semiconductor substrate; forming a select gate layer above the select gate dielectric layer, the floating gate, and the control gate; etching the select gate layer to form a plurality of select gate electrodes; and oxidizing the select gate electrodes to form a first select gate spacer.

[0318] In some embodiments, the method of forming an integrated circuit further includes: after forming the first selection gate spacer, covering the memory area with a protective layer; forming a logic gate stack; patterning the logic gate stack to form a plurality of logic gates, which may be a plurality of virtual gates; forming a spacer layer above the protective layer and these logic gates; etching the spacer layer to form a spacer adjacent to the logic gate; and removing the protective layer from the memory area.

[0319] In some embodiments, the method of forming an integrated circuit further includes depositing an oxide to form a second select gate spacer over the first select gate spacer before depositing the protection layer.

[0320] In some implementations, the method of forming an integrated circuit further includes forming a second select gate spacer over the first select gate spacer via atomic layer deposition.

[0321] In some embodiments, the method of forming an integrated circuit further includes: depositing a select gate hard mask layer over a core shaft formed in part by a control gate using a conformal deposition process; and etching the select gate hard mask layer to form a select gate hard mask; wherein etching the select gate layer to form a select gate electrode includes etching through the select gate layer in an area adjacent to the select gate hard mask.

[0322] In some embodiments, in a method of forming an integrated circuit, oxidizing a select gate electrode to form a first select gate spacer increases a thickness of a select gate dielectric layer.

[0323] Several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments or examples described herein. Those skilled in the art will also understand that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they may make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, characterized in that: Include: A semiconductor substrate comprising a memory area and a logic area; a plurality of flash memory cells, each of the flash memory cells in the memory region including a floating gate, a control gate, and a select gate, each of the select gates including a select gate electrode, a select gate dielectric adjacent to the semiconductor substrate below the select gate electrode, and a select gate spacer on a side of the select gate electrode opposite to the floating gate; as well as a plurality of logic gates in the logic region, each of the logic gates comprising a logic gate electrode and logic gate spacers on either side of the logic gate electrode; wherein a set of compositions of the select gate spacers is different from a set of compositions of the logic gate spacers; The select gate dielectric is thicker on a side adjacent to the select gate spacer than on a side of the select gate dielectric away from the select gate spacer.

2. The integrated circuit according to claim 1, characterized in that The logic gate spacer is thicker than the select gate spacer.

3. The integrated circuit according to claim 1, characterized in that in: The logic gate spacers include an oxide layer and a nitride layer; and The select gate spacer includes only an oxide layer.

4. The integrated circuit according to claim 1, characterized in that The select gate spacer includes a first oxide layer grown from the select gate electrode.

5. The integrated circuit according to claim 4, characterized in that The first oxide layer is thicker than a native oxide layer.

6. The integrated circuit according to claim 4, characterized in that in: The select gate spacer further includes a second oxide layer formed by deposition; and the first oxide layer is thicker than the second oxide layer.

7. The integrated circuit according to claim 1, characterized in that The select gate dielectric includes an oxide layer grown from the select gate electrode.

8. The integrated circuit according to claim 1, characterized in that The select gate spacer has a more vertical profile than the logic gate spacer.

9. An integrated circuit, characterized in that: Include: A semiconductor substrate comprising a memory area and a logic area; a memory cell, in the memory region, comprising a select gate electrode separated from a floating gate electrode by a floating gate spacer; a select gate spacer on a side of the select gate electrode opposite the floating gate electrode; a select gate dielectric interposed between the select gate electrode and the semiconductor substrate, wherein the select gate dielectric has a thickness that increases with respect to a distance from the floating gate electrode; a logic gate in the logic region; and a logic gate spacer adjacent to the logic gate; The selection gate spacer has a uniform thickness above the selection gate electrode.

10. The integrated circuit according to claim 9, characterized in that The logic gate spacer has a composition that is different from a composition of the select gate spacer.

11. The integrated circuit according to claim 9, characterized in that The logic gate spacer is thicker than the select gate spacer.

12. The integrated circuit according to claim 9, characterized in that The semiconductor substrate includes a source / drain region aligned with the select gate spacer.

13. A method for forming an integrated circuit, characterized in that The method includes: forming a floating gate stack over a memory region and a logic region of a semiconductor substrate; removing the floating gate stack from the logic region; forming a control gate stack above the floating gate stack in the memory region; patterning to form a control gate from the control gate stack; forming a plurality of control gate sidewall spacers adjacent to the control gates; patterning the floating gate stack to form a plurality of floating gates; forming a plurality of floating gate sidewall spacers adjacent to the floating gates; forming a select gate dielectric layer on the semiconductor substrate; forming a select gate layer over the select gate dielectric layer, the floating gates, and the control gates; etching the select gate layer to form a plurality of select gate electrodes; and The select gate electrodes are oxidized to form a first select gate spacer.

14. The method for forming an integrated circuit according to claim 13, characterized in that: Also includes: After forming the first select gate spacer, covering the memory region with a protective layer; forming a logic gate stack; patterning the logic gate stack to form a plurality of logic gates, which may be a plurality of dummy gates; forming a spacer layer above the protection layer and the logic gates; etching the spacer layer to form spacers adjacent to the logic gates; and The protection layer is removed from the memory region.

15. The method for forming an integrated circuit according to claim 14, characterized in that: Further comprising depositing an oxide to form a second select gate spacer over the first select gate spacer before depositing the protection layer.

16. The method for forming an integrated circuit according to claim 14, wherein: Further comprising forming a second select gate spacer over the first select gate spacer via atomic layer deposition.

17. The method for forming an integrated circuit according to claim 16, characterized in that: Also includes: depositing a select gate hard mask layer over the mandrels formed in part by the control gate using a conformal deposition process; and etching the select gate hard mask layer to form a select gate hard mask; Wherein etching the select gate layer to form a select gate electrode includes etching through the select gate layer in an area adjacent to the select gate hard mask.

18. The method for forming an integrated circuit according to claim 13, wherein: Oxidation of the select gate electrodes to form the first select gate spacer increases a thickness of the select gate dielectric layer.

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