Semiconductor element and method of forming the same

Abstract

A semiconductor element and a method for forming the same, the semiconductor element comprising a pixel array, the pixel array comprising a first pixel and a second pixel. The semiconductor element comprises a metal structure, the metal structure overlaying a portion of a substrate between the first pixel and the second pixel. The semiconductor element comprises a first barrier layer adjacent to a sidewall of the metal structure. The semiconductor element comprises a passivation layer adjacent to a sidewall of the first barrier layer. The first barrier layer is located between the passivation layer and the metal structure.

Description

Technical Field

[0001] The present application relates to a semiconductor device and a method for forming the same. Background Art

[0002] A semiconductor device such as a complementary metal-oxide-semiconductor (CMOS) image sensor includes a pixel array for detecting radiation, such as light, impinging on pixels of the pixel array. The CMOS image sensor includes a grid array defining optical paths through which radiation is directed toward each pixel. Filter material is disposed within the optical paths between grid structures of the grid array to filter radiation so that only certain wavelengths of radiation reach each pixel. Summary of the invention

[0003] Embodiments of the present disclosure include a semiconductor device including a pixel array, a metal structure, a first barrier layer, and a passivation layer. The pixel array includes a first pixel and a second pixel. The metal structure overlies a portion of a substrate between the first pixel and the second pixel. The first barrier layer is adjacent to a sidewall of the metal structure. The passivation layer is adjacent to a sidewall of the first barrier layer, wherein the first barrier layer is between the passivation layer and the metal structure.

[0004] Embodiments of the present disclosure also include a semiconductor device including a pixel array, a first barrier layer, a metal structure, and a second barrier layer. The pixel array includes a first pixel and a second pixel. The first barrier layer overlies a portion of a substrate between the first pixel and the second pixel. The metal structure overlies the first barrier layer and overlies a portion of the substrate between the first pixel and the second pixel. The second barrier layer is adjacent to a sidewall of the metal structure and contacts a sidewall of the first barrier layer.

[0005] Embodiments of the present disclosure further include a method of forming a semiconductor device, the method comprising forming a metal structure on a first dielectric layer and a portion of an overlying substrate between a first pixel and a second pixel. The method further comprises forming a first barrier layer on the metal structure and the first dielectric layer. The method further comprises removing a portion of the first barrier layer on the first dielectric layer to expose a top surface of the first dielectric layer. The method also comprises forming a filter on the top surface of the first dielectric layer after removing the portion of the first barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1J is a perspective view of a semiconductor structure according to some embodiments;

[0008] FIG. 2A to FIG. 2I is an illustration of a cross-sectional view of a semiconductor device at various stages of fabrication according to some embodiments;

[0009] Figure 3 is an illustration of a cross-sectional view of a semiconductor device according to some embodiments;

[0010] Figure 4 is an illustration of a cross-sectional view of a semiconductor device according to some embodiments;

[0011] Figure 5 is an illustration of a cross-sectional view of a semiconductor device according to some embodiments;

[0012] Figure 6 is an illustration of a cross-sectional view of a semiconductor device according to some embodiments;

[0013] Figure 7 is an illustration of a cross-sectional view of a semiconductor device according to some embodiments.

[0014]

Explanation of symbols

[0015] 100:Semiconductor components

[0016] 101:Substrate

[0017] 102: Dorsal

[0018] 103: Isolation Area

[0019] 104: first dielectric layer

[0020] 104': first dielectric structure

[0021] 105: Pixel Array

[0022] 106: First barrier layer

[0023] 106': First barrier structure

[0024] 107: Pixels

[0025] 108:Metal layer

[0026] 108':Metal structure

[0027] 109:Front

[0028] 110: second dielectric layer

[0029] 110': second dielectric structure

[0030] 111: third dielectric layer

[0031] 111': third dielectric structure

[0032] 112: Grid structure

[0033] 113: Interconnection structure

[0034] 114: Direction of Radiation Travel

[0035] 115: Conducting wire

[0036] 116: Conductor / Contact

[0037] 117: Optical Path

[0038] 118: Second barrier layer

[0039] 119:Part of the substrate

[0040] 122: passivation layer

[0041] 130: First filter material

[0042] 132: Second filter material

[0043] 200:Semiconductor components

[0044] 202: Grid structure

[0045] 208: Second barrier layer

[0046] 208': Part of the second barrier layer

[0047] 216: passivation layer

[0048] 230: First filter material

[0049] 232: Second filter material

[0050] 300:Semiconductor components

[0051] 302: Part of the second barrier layer

[0052] 400:Semiconductor components

[0053] 500:Semiconductor components

[0054] 502: Width

[0055] 504: Width

[0056] 600:Semiconductor components

[0057] 700:Semiconductor components

[0058] 701: Average width of the first dielectric structure

[0059] 702: Average width of the first barrier structure

[0060] 703: Average width of metal structure

[0061] 704: Average width of the second dielectric structure

[0062] 705: average width of the third dielectric structure DETAILED DESCRIPTION

[0063] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, in various examples, the disclosure may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity, and does not itself define the relationship between the various embodiments and / or configurations discussed.

[0064] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0065] In some embodiments, a semiconductor device including a pixel array is provided. In some embodiments, the semiconductor device includes a grid array formed on the pixel array. In some embodiments, the grid array includes a grid structure formed on and between pixels of the pixel array. The grid structure also includes a metal structure that reflects radiation to create an optical path for directing radiation to the pixels. In some embodiments, a first barrier layer is formed adjacent to one or more sidewalls of each metal structure. In some embodiments, the first barrier layer is further disposed on each of the metal structures. In some embodiments, the semiconductor device includes a second barrier layer under each of the metal structures. In some embodiments, the semiconductor device includes a passivation layer adjacent to the sidewalls of the first barrier layer, such that the first barrier layer is between the passivation layer and the metal structure. In some embodiments, the semiconductor device includes a complementary metal oxide semiconductor image sensor, such as a backside illuminated complementary metal oxide semiconductor image sensor.

[0066] In some embodiments, the first barrier layer reduces diffusion within the metal within the metal structure into the optical path between the grid structure. In some embodiments, the first barrier layer provides improved adhesion between the metal structure and surrounding non-metallic materials such as a passivation layer.

[0067] Figures 1A to 1J FIG. 1 is a cross-sectional view of a semiconductor device 100 having a second barrier layer 118 formed thereon according to some embodiments. In some embodiments, the semiconductor device 100 comprises a complementary metal-oxide-semiconductor (CMOS) image sensor, such as a backside illuminated CMOS image sensor.

[0068] See also Figure 1AAccording to some embodiments, a substrate 101 including a pixel array 105 is provided. The substrate 101 has a front side 109 and a back side 102. In some embodiments, the substrate 101 is a single crystal silicon substrate, a doped substrate including single crystal silicon (having <100> crystalline direction) or other suitable materials. The pixel array 105 includes a plurality of pixels 107, such as photodiodes, phototransistors, etc., formed in the substrate 101 or on the front side 109 of the substrate. In some embodiments, the pixels 107 are used to sense radiation, such as incident light, projected from the back side 102 toward the substrate 101. The radiation entering the substrate 101 through the back side 102 is detected by one or more of the pixels 107. In some embodiments, the pixels 107 include pinned layer photodiodes, photogates, reset transistors, source follower transistors, transfer transistors, etc. The pixels 107 may vary from one another to have different interface depths, thicknesses, widths, etc. Even though two pixels are depicted, any number of pixels may be formed in the substrate 101. In some embodiments, isolation regions 103, such as backside isolation regions, are disposed between pixels 107 such that isolation regions 103 are offset from pixels 107 in a direction perpendicular to a direction 114 of radiation travel to enter substrate 101 and be detected by pixels 107. In some embodiments, isolation regions 103 are shallow trench isolation (STI) structures.

[0069] According to some embodiments, interconnect structure 113 is formed on front side 109 of substrate 101. In some embodiments, interconnect structure 113 includes a plurality of patterned dielectric layers and conductive layers that provide interconnections between various doped features, circuit systems, and input / output terminals of semiconductor device 100, such as wiring. In some embodiments, interconnect structure 113 includes interlayer dielectrics and multilayer interconnect structures, such as contacts, vias, metal lines, etc. For illustration purposes, interconnect structure 113 includes Figure 1A The conductive lines 115 and vias / contacts 116 shown in the drawings are exemplary only, and the actual positioning and configuration may vary depending on design requirements.

[0070] In some embodiments, additional layers are formed between the interconnect structure 113 and the front side 109 of the substrate 101. For example, interlayer dielectrics, thermal dielectrics, metal blocks, redistribution layers, etc. may be present between the interconnect structure 113 and the front side 109 of the substrate 101. In some embodiments, additional layers are formed on a surface of the interconnect structure 113 facing away from the substrate 101, such as interlayer dielectrics, thermal dielectrics, redistribution layers, application specific integrated circuits, etc. In some embodiments, a carrier substrate is bonded to the substrate 101 via the interconnect structure 113 and any additional layers present on the front side 109 of the substrate 101, so that processing of the back side 102 of the substrate 101 can be performed as described below.

[0071] In some embodiments, the semiconductor device 100 may include Figure 1A For example, when semiconductor device 100 is a backside illuminated complementary metal oxide semiconductor (CMOS) image sensor, the backside illuminated complementary metal oxide semiconductor (CMOS) image sensor may include a pixel region (at least a portion of which is shown), a peripheral region (not shown), a contact pad region (not shown), a black level calibration region (not shown), a backside scribe line region (not shown), etc.

[0072] Figures 1B to 1J is a cross-sectional view of a grid array formed on a substrate 101. Figure 1B According to some embodiments, a first dielectric layer 104 is formed on substrate 101. In some embodiments, first dielectric layer 104 includes a material that is substantially optically transparent to the wavelength of radiation intended to be received by pixel 107. In some embodiments, first dielectric layer 104 includes SiO2 or a low-k material. Low-k dielectric materials have a k value (dielectric constant) less than about 3.9. Some low-k dielectric materials have a k value less than about 3.5, and may have a k value less than about 2.5.

[0073] See also Figure 1C According to some embodiments, the first barrier layer 106 is formed on the first dielectric layer 104. In some embodiments, the first barrier layer 106 includes a metal material. Examples of metal materials include, but are not limited to, tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), alloys thereof, or other suitable metal materials. In some embodiments, the first barrier layer 106 includes a dielectric material. Examples of dielectric materials include, but are not limited to, silicon oxide (SiO x ), Silicon Nitride (SiN x ), Silicon Carbide (SiC x ), titanium nitride (TiN x ), Tantalum Nitride (TaN x ), hafnium oxide (HfOx ), tantalum oxide (TaO x ), aluminum oxide (AlO x ) or other suitable dielectric materials, wherein x is a value greater than or equal to 1. In some embodiments, the first barrier layer 106 includes a single material layer. In some embodiments, the first barrier layer 106 includes multiple material layers. For example, the first barrier layer 106 may include silicon nitride (SiN x ) layer, silicon oxide (SiO x ) layer and another silicon nitride (SiN x )layer.

[0074] See also Figure 1D According to some embodiments, a metal layer 108 is formed on the first barrier layer 106. In some embodiments, the metal layer 108 includes tungsten or other suitable metal materials. Figure 1E According to some embodiments, a second dielectric layer 110 is formed on the metal layer 108, and a third dielectric layer 111 is formed on the second dielectric layer 110. In some embodiments, the material composition of the second dielectric layer 110 is different from the material composition of the third dielectric layer 111. In some embodiments, the second dielectric layer 110 comprises SiO2 or a low-k material. In some embodiments, the second dielectric layer 110 has the same material composition as the first dielectric layer 104. In some embodiments, the third dielectric layer 111 comprises a high-k dielectric material. As used herein, the term "high-k dielectric" refers to a material having a dielectric constant k greater than or equal to about 3.9 (which is the k value of SiO2). The material of the high-k dielectric layer may be any suitable material. Examples of the material of the high-k dielectric layer include, but are not limited to, Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2O x N y , HfO x N y 、ZrO x N y 、La2O x N y 、TiO x N y 、SrTiO x N y 、LaAlO x N y 、Y2O x N y 、SiON、SiN x Silicates thereof and alloys thereof. Each x value is independently from 0.5 to 3, and each y value is independently from 0 to 2.

[0075] Although the example embodiment illustrates two dielectric layers 110, 111 as being formed on the metal layer 108, any number of dielectric layers may be formed on the metal layer 108. For example, in some embodiments, the second dielectric layer 110 but not the third dielectric layer 111 is formed on the metal layer 108. Furthermore, in some embodiments, neither the second dielectric layer 110 nor the third dielectric layer 111 is formed on the metal layer 108, and thus the description of the dielectric layer 110 is skipped. Figure 1E Describe the process.

[0076] See also Figure 1F According to some embodiments, the first dielectric layer 104, the first barrier layer 106, the metal layer 108, the second dielectric layer 110, and the third dielectric layer 111 are removed to define the grid structures 112. In some embodiments, each of the grid structures 112 includes at least one of a first dielectric structure 104' defined from the first dielectric layer 104, a first barrier structure 106' defined from the first barrier layer 106, a metal structure 108' defined from the metal layer 108, a second dielectric structure 110' defined from the second dielectric layer 110, and a third dielectric structure 111' defined from the third dielectric layer 111. In some embodiments, each grid structure 112 is disposed between two adjacent pixels such that the first dielectric structure 104′, the first barrier structure 106′, the metal structure 108′, the second dielectric structure 110′, and the third dielectric structure 111′ of a first grid structure 112 overlie a portion 119 of the substrate 101 between the first pixel 107 and the second pixel 107. In some embodiments, between each grid structure 112 and each pixel 107 is an optical path 117 through which radiation is guided from an adjacent grid structure 112 to a pixel 107 between adjacent grid structures 112.

[0077] In some embodiments, portions of the first dielectric layer 104, the first barrier layer 106, the metal layer 108, the second dielectric layer 110, and the third dielectric layer 111 are removed by an etching process. In some embodiments, the etching process includes forming a photoresist layer on the third dielectric layer 111 and patterning the photoresist layer so that some portions of the underlying third dielectric layer 111 are covered by the photoresist layer, while other portions of the third dielectric layer 111 are uncovered or exposed.

[0078] In some embodiments, after patterning of the photoresist layer, the portion of the third dielectric layer 111 not covered by the photoresist layer is exposed to an etchant, which removes or etches away the portion of the third dielectric layer 111, as well as the second dielectric layer 110, the metal layer 108, the first barrier layer 106, and the portion of the first dielectric layer 104 under the uncovered portion of the third dielectric layer 111. In some embodiments, depending on the material composition of the layers 104, 106, 108, 110, and 111 and the etching selectivity of the layers 104, 106, 108, 110, and 111, the etching process may be performed in multiple stages using different etching chemistries or different etching methods to remove portions of the first dielectric layer 104, the first barrier layer 106, the metal layer 108, the second dielectric layer 110, and the third dielectric layer 111.

[0079] In some embodiments, the sidewalls of the grid structure 112 are vertical or in a plane perpendicular to the top surface of the substrate 101. In some embodiments, the sidewalls of the grid structure 112 taper (e.g., Figure 6 ). In some embodiments, different layers of the grid structure 112 have different sidewall angles, such as where the third dielectric structure 111' has a different sidewall angle than at least one of the second dielectric structure 110', the metal structure 108', the first barrier structure 106', or the first dielectric structure 104'. In some embodiments, at least one layer is contracted (such as Figure 7 ), such that the width of the middle portion of the at least one layer is less than the width of an upper portion of the at least one layer above the middle portion, and less than the width of a lower portion of the at least one layer below the middle portion. In some embodiments, the sidewalls of the various layers are vertical, coplanar with each other, uniformly taper, shrink, or have various tapered angles (resulting in one or more of the structures 104', 106', 108', 110', 111' having different sidewall angles), depending on the manner in which the etching process or processes are performed.

[0080] In some embodiments, after the etching process(es), portions of the substrate 101 overlying the pixels 107 remain covered or hidden by at least a portion of the first dielectric layer 104. Thus, after the grid structure 112 is formed, the pixels 107 continue to be under the first dielectric layer 104. In some embodiments, portions of the substrate 101 overlying the pixels 107 are exposed as a result of the etching process(es).

[0081] See also Figure 1GAccording to some embodiments, a second barrier layer 118 is formed on the grid structure 112. In some embodiments, the second barrier layer 118 is further formed on the first dielectric layer 104. In some embodiments, the second barrier layer 118 is conformally formed on the grid structure 112 and the first dielectric layer 104. In some embodiments, the second barrier layer 118 may be formed in a non-conformal manner. In some embodiments, the second barrier layer 118 contacts the sidewalls of at least one of the third dielectric structure 111', the second dielectric structure 110', the metal structure 108', the first barrier structure 106', or the first dielectric structure 104'. In some embodiments, the second barrier layer 208 contacts the sidewalls of the first dielectric layer 104 (such as the sidewalls of the first dielectric structure 104') and the top surface of the first dielectric layer 104. In some embodiments, the thickness of the second barrier layer 208 is non-uniform. For example, as shown by Figure 5 As shown, the width 502 of the second barrier layer 118 closest to the middle sidewall portion of the grid structure 112 is smaller than the width 504 of the second barrier layer 118 closest to the lower sidewall portion of the grid structure 112. In some embodiments, the second barrier layer 118 comprises SiOx, SiN x 、SiC x 、TiN x 、TaN x , HfO x 、TaO x 、AlO x In some embodiments, the second barrier layer 118 has the same material composition as the first barrier layer 106 .

[0082] In some embodiments, the second barrier layer 118 includes multiple layers, such as a first TiN layer that provides isolation for the metal structure 108', and then a second Ti layer that provides improved adhesion with a subsequently formed passivation layer 122. In some embodiments, the first TiN layer has a thickness of about 35 angstroms. In some embodiments, the second Ti layer has a thickness of about 100 angstroms. In some embodiments, the second barrier layer 118 has a thickness between about 10 angstroms and 2,000 angstroms.

[0083] In some embodiments where the portion of the substrate 101 overlying the pixel 107 remains hidden by the first dielectric layer 104 after the etching process(es), the first dielectric layer 104 separates the second barrier layer 118 from the portion of the substrate 101 overlying the pixel 107, and thereby from the pixel 107. In some embodiments where the portion of the substrate 101 overlying the pixel 107 is exposed after the etching process(es), the second barrier layer 118 may contact the portion of the substrate 101 overlying the pixel 107.

[0084] See also Figure 1H, according to some embodiments, a portion of the second barrier layer 118 is removed. In some embodiments, a portion of the second barrier layer 118 overlying the first dielectric layer 104 and between the grid structures 112 is removed by an etching process. In some embodiments where a portion of the substrate 101 overlying the pixel 107 is covered by the first dielectric layer 104, the removal of the portion of the second barrier layer 118 exposes the first dielectric layer 104. In some embodiments where a portion of the substrate 101 overlying the pixel 107 is not covered by the first dielectric layer 104, the removal of the portion of the second barrier layer 118 exposes a portion of the substrate 101 overlying the pixel 107. In some embodiments, a portion of the second barrier layer 118 overlying the third dielectric layer 111 is also removed by the etching process. In some embodiments, the second etching process is a blanket etching process without using a photoresist mask.

[0085] See also Fig. 1I According to some embodiments, the passivation layer 122 is formed on the grid structure 112. In some embodiments where the portion of the substrate 101 overlying the pixel 107 is covered by the first dielectric layer 104, the passivation layer 122 is formed on the first dielectric layer 104. In some embodiments where the portion of the substrate 101 overlying the pixel 107 is covered by the first dielectric layer 104, the passivation layer 122 contacts the top surface of the first dielectric layer 104. In some embodiments where the portion of the substrate 101 overlying the pixel 107 is not covered by the first dielectric layer 104, the passivation layer 122 contacts the back side of the portion of the substrate 101 overlying the pixel 107. In some embodiments, the passivation layer 122 contacts the sidewalls of the second barrier layer 118.

[0086] In some embodiments, passivation layer 122 is formed using a conformal deposition process to deposit a material having a material composition different from the material composition of second barrier layer 118. In some embodiments, passivation layer 122 has a thickness between about 10 angstroms and about 2,000 angstroms. In some embodiments, passivation layer 122 comprises a material that is substantially optically transparent to the wavelengths of radiation intended to be received by pixel 107.

[0087] See also Figure 1JAccording to some embodiments, filter materials 130, 132 are formed in the optical path 117 between the grid structures 112. In some embodiments, the first filter material 130 is deposited between a first pair of adjacent grid structures 112 and overlying the first pixel 107 so as to filter radiation of certain wavelengths (colors) that are channeled through the first filter material 130 to the first pixel 107. In some embodiments, the second filter material 132 is deposited between a second pair of adjacent grid structures 112 and overlying the second pixel 107 so as to filter radiation of certain wavelengths (colors) that are channeled through the second filter material 132 to the second pixel 107. In some embodiments, the first filter material 130 and the second filter material 132 have different material compositions to enable different wavelengths to be filtered. In some embodiments, the passivation layer 122 is disposed between the filter materials 130, 132 and the first dielectric layer 104, or between the filter materials 130, 132 and a portion of the substrate 101 overlying the pixel 107.

[0088] In some embodiments, the second barrier layer 118 provides isolation between the metal structure 108' and the passivation layer 122. In some embodiments, the second barrier layer 118 provides improved adhesion to the passivation layer 122 relative to a structure that does not provide the second barrier layer 118. In some embodiments, by providing isolation and adhesion, diffusion of the metal structure 108' through the passivation layer 122 is reduced, thereby reducing the possibility of the metal structure 108' causing interference with the optical path 117.

[0089] FIG. 2A to FIG. 2I FIG. 2 is a cross-sectional view of a semiconductor device 200 having a second barrier layer 208 formed thereon according to some embodiments. In some embodiments, the semiconductor device 200 includes a CMOS image sensor, such as a backside illuminated CMOS image sensor.

[0090] See also Figure 2AAccording to some embodiments, a substrate 101 including a pixel array 105 is provided. The substrate 101 has a front side 109 and a back side 102. The pixel array 105 includes a plurality of pixels 107, such as photodiodes, phototransistors, etc., formed in the substrate 101. In some embodiments, the pixels 107 are used to sense radiation, such as incident light, projected from the back side 102 toward the substrate 101. The radiation entering the substrate 101 through the back side 102 is detected by one or more of the pixels 107. In some embodiments, the pixels 107 include pinned layer photodiodes, photogates, reset transistors, source follower transistors, transfer transistors, etc. The pixels 107 can vary from one another to have different interface depths, thicknesses, widths, etc. Even though 2 pixels are depicted, any number of pixels can be formed in the substrate 101. In some embodiments, isolation regions 103, such as backside isolation regions, are disposed between pixels 107 such that isolation regions 103 are offset from pixels 107 in a direction perpendicular to a direction 114 of radiation travel to enter substrate 101 and be detected by pixels 107. In some embodiments, isolation regions 103 are shallow trench isolation (STI) structures.

[0091] According to some embodiments, an interconnect structure 113 is formed on the front side 109 of the substrate 101. In some embodiments, the interconnect structure 113 includes a plurality of patterned dielectric layers and conductive layers that provide interconnections between various doped features, circuit systems, and input / output terminals of the semiconductor device 100, such as wiring. In some embodiments, the interconnect structure 113 includes an interlayer dielectric and multiple layers of interconnect structures, such as contacts, vias, metal lines, etc. For illustration purposes, the interconnect structure 113 includes Figure 2A The conductive lines 115 and vias / contacts 116 shown in the drawings are exemplary only, and the actual positioning and configuration may vary depending on design requirements.

[0092] FIG. 2B to FIG. 2I is a cross-sectional view of a grid array formed on a substrate 101. Figure 2B According to some embodiments, a first dielectric layer 104 is formed on substrate 101. In some embodiments, first dielectric layer 104 comprises a material that is substantially optically transparent to the wavelength of radiation intended to be received by pixel 107. In some embodiments, first dielectric layer 104 comprises SiO2 or a low-k material.

[0093] See also Figure 2CAccording to some embodiments, a first barrier layer 106 is formed on the first dielectric layer 104. In some embodiments, the first barrier layer 106 comprises a metal material. Examples of metal materials include, but are not limited to, W, Cu, Al, Co, Ni, Ti, Ta, alloys thereof, or other suitable metal materials. In some embodiments, the first barrier layer 106 comprises a dielectric material. Examples of dielectric materials include, but are not limited to, SiO x 、SiN x 、SiC x 、TiN x 、TaN x , HfO x 、TaO x 、AlO x or other suitable dielectric materials, wherein x is a value greater than or equal to 1. In some embodiments, the first barrier layer 106 comprises a single material layer. In some embodiments, the first barrier layer 106 comprises a plurality of material layers. For example, the first barrier layer 106 may comprise a SiN x Layer, SiO x layer and another SiN x layer.

[0094] See also Figure 2D According to some embodiments, a metal layer 108 is formed on the first barrier layer 106. In some embodiments, the metal layer 108 includes tungsten or other suitable metal materials. Figure 2E According to some embodiments, the first dielectric layer 104, the first barrier layer 106, and the metal layer 108 are removed to define the grid structures 202. In some embodiments, each of the grid structures 202 includes at least one of a first dielectric structure 104' defined from the first dielectric layer 104, a first barrier structure 106' defined from the first barrier layer 106, and a metal structure 108' defined from the metal layer 108. In some embodiments, each grid structure 202 is disposed between two adjacent pixels such that the first dielectric structure 104', the first barrier structure 106', and the metal structure 108' of a first grid structure 112 overlie a portion 119 of the substrate 101 between the first pixel 107 and the second pixel 107. In some embodiments, between each grid structure 202 and each pixel 107 is an optical path 117 through which radiation is directed from an adjacent grid structure 202 to a pixel 107 between adjacent grid structures 202. In some embodiments, the etching process includes a photolithography and etching process to define the grid structure 202 .

[0095] In some embodiments, portions of the first dielectric layer 104, the first barrier layer 106, and the metal layer 108 are removed by an etching process. In some embodiments, the etching process includes forming a photoresist layer on the metal layer 108 and patterning the photoresist layer so that some portions of the underlying metal layer 108 are covered by the photoresist layer, while other portions of the metal layer 108 are uncovered or exposed.

[0096] In some embodiments, after patterning of the photoresist layer, the portion of the metal layer 108 not covered by the photoresist layer is exposed to an etchant, which removes or etches away portions of the metal layer 108, as well as portions of the first barrier layer 106 and the first dielectric layer 104 under the uncovered portions of the metal layer 108. In some embodiments, depending on the material composition of the layers 104, 106, and 108 and the etching selectivity of the layers 104, 106, and 108, the etching process may be performed in multiple stages using different etching chemistries or different etching methods to remove portions of the first dielectric layer 104, the first barrier layer 106, and the metal layer 108.

[0097] In some embodiments, the sidewalls of the grid structure 202 are vertical or in a plane perpendicular to the top surface of the substrate 101. In some embodiments, the sidewalls of the grid structure 202 taper (e.g., Figure 6 ). In some embodiments, different layers of the grid structure 202 have different sidewall angles, such as where the metal structure 108' has a different sidewall angle than at least one of the first barrier structure 106' or the first dielectric structure 104'. In some embodiments, at least one layer is constricted (such as Figure 7 ), such that the width of the middle portion of the at least one layer is less than the width of an upper portion of the at least one layer above the middle portion, and less than the width of a lower portion of the at least one layer below the middle portion. In some embodiments, the sidewalls of the various layers are vertical, coplanar with each other, uniformly taper, converge, or have various tapered angles (resulting in one or more of the structures 104', 106', 108' having different sidewall angles), as a function of the manner in which the etching process or processes are performed.

[0098] In some embodiments, after the etching process(es), portions of the substrate 101 overlying the pixels 107 remain covered or hidden by at least a portion of the first dielectric layer 104. Thus, after the grid structure 202 is formed, the pixels 107 continue to be under the first dielectric layer 104. In some embodiments, portions of the substrate 101 overlying the pixels 107 are exposed as a result of the etching process(es).

[0099] See also Figure 2FAccording to some embodiments, a second barrier layer 208 is formed on the grid structure 202. In some embodiments, the second barrier layer 208 is further formed on the first dielectric layer 104. In some embodiments, the second barrier layer 208 is conformally formed on the grid structure 202 and the first dielectric layer 104. In some embodiments, the second barrier layer 208 may be formed in a non-conformal manner. In some embodiments, the second barrier layer 208 contacts the sidewalls of the metal structure 108'. In some embodiments, the second barrier layer 208 contacts the sidewalls of the first dielectric layer 104 (such as the sidewalls of the first dielectric structure 104') and the top surface of the first dielectric layer 104. In some embodiments, the second barrier layer 208 comprises SiOx, SiN x 、SiC x 、TiN x 、TaN x , HfO x 、TaO x 、AlO x In some embodiments, the second barrier layer 208 has the same material composition as the first barrier layer 106 .

[0100] In some embodiments, the second barrier layer 208 includes multiple layers, such as a first TiN layer that provides isolation for the metal structure 108', and then a second Ti layer that provides improved adhesion with a subsequently formed passivation layer 216. In some embodiments, the first TiN layer has a thickness of about 35 angstroms. In some embodiments, the second Ti layer has a thickness of about 100 angstroms. In some embodiments, the second barrier layer 208 has a thickness between about 10 angstroms and 2,000 angstroms.

[0101] In some embodiments where the portion of the overlying pixel 107 of the substrate 101 remains hidden by the first dielectric layer 104 after the etching process(es), the first dielectric layer 104 separates the second barrier layer 208 from the portion of the overlying pixel 107 of the substrate 101. In some embodiments where the portion of the overlying pixel 107 of the substrate 101 is exposed after the etching process(es), the second barrier layer 208 may contact the portion of the overlying pixel 107 of the substrate 101.

[0102] See also Figure 2G, according to some embodiments, a portion of the second barrier layer 208 is removed. In some embodiments, a portion of the second barrier layer 208 overlying the first dielectric layer 104 and between the grid structures 202 is removed by an etching process. In some embodiments where a portion of the substrate 101 overlying the pixel 107 is covered by the first dielectric layer 104, the removal of the portion of the second barrier layer 208 exposes the first dielectric layer 104. In some embodiments where a portion of the substrate 101 overlying the pixel 107 is not covered by the first dielectric layer 104, the removal of the portion of the second barrier layer 208 exposes a portion of the substrate 101 overlying the pixel 107. In some embodiments, the etching process utilizes a photoresist mask to protect a portion of the second barrier layer 208 overlying the metal structure 108' from being etched by the etching process. In some embodiments, due to the use of the photoresist mask for the etching process, a portion 208' of the second barrier layer 208 overlies the pixel 107.

[0103] See also Figure 2H According to some embodiments, a passivation layer 216 is formed on the grid structure 202. In some embodiments where the portion of the substrate 101 overlying the pixel 107 is covered by the first dielectric layer 104, the passivation layer 216 is formed on the first dielectric layer 104. In some embodiments where the portion of the substrate 101 overlying the pixel 107 is covered by the first dielectric layer 104, the passivation layer 216 contacts the top surface of the first dielectric layer 104. In some embodiments where the portion of the substrate 101 overlying the pixel 107 is not covered by the first dielectric layer 104, the passivation layer 216 contacts the back side of the portion of the substrate 101 overlying the pixel 107. In some embodiments, the passivation layer 216 contacts the sidewalls and the top surface of the second barrier layer 208.

[0104] In some embodiments, passivation layer 216 is formed using a conformal deposition process to deposit a material having a material composition different from the material composition of second barrier layer 208. In some embodiments, passivation layer 216 has a thickness between about 10 angstroms and about 2,000 angstroms. In some embodiments, passivation layer 216 comprises a material that is substantially optically transparent to the wavelengths of radiation intended to be received by pixel 107.

[0105] See also Fig.2IAccording to some embodiments, filter materials 130, 132 are formed in the optical path 117 between the grid structures 202. In some embodiments, a first filter material 230 is deposited between a first pair of adjacent grid structures 202 and overlying a first pixel 107 so as to filter radiation of certain wavelengths (colors) that are channeled through the first filter material 230 to the first pixel 107. In some embodiments, a second filter material 232 is deposited between a second pair of adjacent grid structures 202 and overlying a second pixel 107 so as to filter radiation of certain wavelengths (colors) that are channeled through the second filter material 232 to the second pixel 107. In some embodiments, the first filter material 230 and the second filter material 232 have different material compositions to enable different wavelengths to be filtered. In some embodiments, a passivation layer 122 is disposed between the filter materials 130, 132 and the first dielectric layer 104, or between the filter materials 130, 132 and a portion of the substrate 101 overlying the pixel 107.

[0106] In some embodiments, the second barrier layer 208 provides isolation between the metal structure 108' and the passivation layer 216. In some embodiments, the second barrier layer 208 provides improved adhesion to the passivation layer 216 relative to a structure that does not provide the second barrier layer 208. In some embodiments, by providing isolation and adhesion, diffusion of the metal structure 108' through the passivation layer 216 is reduced, thereby reducing the possibility of the metal structure 108' causing interference with the optical path 117.

[0107] Figure 3 FIG. 1 is a cross-sectional view of a semiconductor device 300 having a second barrier layer 118 formed thereon according to some embodiments. Figure 1J The difference between the semiconductor device 100 shown in FIG. 1 is that the second barrier layer 118 is based on the Figure 2G The described process etches such that the second barrier layer 118 is disposed between the top surface of the third dielectric structure 111' and the bottom surface of the passivation layer 122. Furthermore, in some embodiments, a portion 302 of the second barrier layer 118 overlies the pixel 107 due to the use of a photoresist mask for the etching process.

[0108] Figure 4 FIG. 4 is a cross-sectional view of a semiconductor device 400 having a second barrier layer 208 formed thereon according to some embodiments. Fig.2I The difference between the semiconductor device 200 shown in FIG. 2 is that the second barrier layer 208 is based on the Figure 1H The described etching process causes the second barrier layer 208 to be removed from the top surface of the metal structure 108 ′ and the top surface of the first dielectric layer 104 .

[0109] Figure 5FIG. 5 is a cross-sectional view of a semiconductor device 500 having a second barrier layer 118 formed thereon according to some embodiments. Figure 1J 1 is different from the semiconductor device 100 illustrated in FIG. 1 in that the second barrier layer 118 is non-conformally formed on the grid structure 112, such that a width 502 of a first portion of the second barrier layer 118 is different from a width 504 of a second portion of the second barrier layer 118. In some embodiments, the width 504 near the bottom or top of the second barrier layer 118 is greater than the width 502 of the second barrier layer 118 near a middle portion of the second barrier layer 118. It should be understood that while the example embodiments illustrate the second barrier layer 118 as being non-conformally formed during the formation of the semiconductor device 500 similar to the semiconductor device 100, the second barrier layer 118 may also be non-conformally formed during the formation of any of the semiconductor devices 200, 300, 400.

[0110] Figure 6 6 is a cross-sectional view of a semiconductor device 600 formed with a metal structure 108' having a constricted configuration due to an etching process that removes a portion of the metal layer 108 to form the metal structure 108'. For example, in some embodiments, a width 602 in a middle portion of the metal structure 108' is smaller than a width 604 in a lower portion of the metal structure 108' below the middle portion, and smaller than a width 606 in an upper portion of the metal structure 108' above the middle portion. In some embodiments where the metal structure 108' has a constricted configuration, the second barrier layer 118 may be formed in a non-conformal manner such that a width of the second barrier layer 118 adjacent to the middle portion of the metal structure 108' is greater than a width of the second barrier layer 118 adjacent to the first barrier structure 106', the second dielectric structure 110', the third dielectric structure 111', etc. In some embodiments where the metal structure 108' has a contracted configuration, the second barrier layer 118 can be formed in a conformal manner, and the width of the passivation layer 122 or the width of the filters 130, 132 adjacent to the middle portion of the metal structure 108' is greater than the width of the passivation layer 122 or the width of the filters 130, 132 adjacent to the first barrier structure 106', the second dielectric structure 110', the third dielectric structure 111', etc.

[0111] Figure 71 is a cross-sectional view of a semiconductor device 700 having a grid structure 112 formed therein, the grid structure 112 having a tapered configuration due to the etching process(es). In some embodiments, the average width 701 of the first dielectric structure 104' is greater than the average width 702 of the first barrier structure 106'. In some embodiments, the average width 702 of the first barrier structure 106' is greater than the average width 703 of the metal structure 108'. In some embodiments, the average width 703 of the metal structure 108' is greater than the average width 704 of the second dielectric structure 110'. In some embodiments, the average width 704 of the second dielectric structure 110' is greater than the average width 705 of the third dielectric structure 111'.

[0112] In some embodiments, a semiconductor device is provided, which includes a pixel array, a metal structure, a first barrier layer, and a passivation layer. The pixel array includes a first pixel and a second pixel. The metal structure overlies a portion of a substrate between the first pixel and the second pixel. The first barrier layer is adjacent to a sidewall of the metal structure. The passivation layer is adjacent to a sidewall of the first barrier layer, wherein the first barrier layer is between the passivation layer and the metal structure.

[0113] In some embodiments, the semiconductor device further includes a second barrier layer, and the second barrier layer is located under the metal structure.

[0114] In some embodiments, the second barrier layer comprises the same material composition as the first barrier layer.

[0115] In some embodiments, the first barrier layer covers the metal structure.

[0116] In some embodiments, the passivation layer overlies the first barrier layer.

[0117] In some embodiments, the first barrier layer contacts a sidewall of the metal structure, and the passivation layer contacts a sidewall of the first barrier layer.

[0118] In some embodiments, the first barrier layer contacts a sidewall of the metal structure, and the passivation layer contacts a top surface of the metal structure.

[0119] In some embodiments, the semiconductor device further includes a dielectric layer, the dielectric layer covers the first pixel and is located below the metal structure, and the passivation layer contacts the dielectric layer.

[0120] In some embodiments, the first barrier layer contacts a sidewall of the dielectric layer.

[0121] In some embodiments, the semiconductor device further includes a dielectric layer, the dielectric layer is located above the metal structure, and the first barrier layer is adjacent to a sidewall of the dielectric layer.

[0122] In some embodiments, the semiconductor device further includes a color filter material, the color filter material overlying the first pixel and adjacent to a sidewall of the passivation layer.

[0123] In some embodiments, a semiconductor device is provided, which includes a pixel array, a first barrier layer, a metal structure, and a second barrier layer. The pixel array includes a first pixel and a second pixel. The first barrier layer overlies a portion of a substrate between the first pixel and the second pixel. The metal structure overlies the first barrier layer and overlies a portion of the substrate between the first pixel and the second pixel. The second barrier layer is adjacent to a sidewall of the metal structure and contacts a sidewall of the first barrier layer.

[0124] In some embodiments, the first barrier layer and the second barrier layer include the same material composition.

[0125] In some embodiments, the semiconductor device further includes a passivation layer, and the second barrier layer is between the metal structure and the passivation layer.

[0126] In some embodiments, the semiconductor device further includes a first dielectric layer, wherein the first dielectric layer is located below the first barrier layer.

[0127] In some embodiments, the semiconductor device further includes a passivation layer, and the passivation layer and the second barrier layer contact the first dielectric layer.

[0128] In some embodiments, the first barrier layer contacts the first dielectric layer.

[0129] In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a metal structure on a first dielectric layer and a portion of an overlying substrate between a first pixel and a second pixel. The method also includes forming a first barrier layer on the metal structure and the first dielectric layer. The method further includes removing a portion of the first barrier layer on the first dielectric layer to expose a top surface of the first dielectric layer. The method also includes forming a filter on the top surface of the first dielectric layer after removing the portion of the first barrier layer.

[0130] In some embodiments, the method further includes forming a passivation layer on a top surface of the first dielectric layer after removing a portion of the first barrier layer and before forming the filter.

[0131] In some embodiments, the method further includes removing a portion of the first barrier layer on the metal structure, and forming a passivation layer on the metal structure after removing the portion of the first barrier layer on the metal structure.

[0132] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processing procedures and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may be variously modified, substituted, and altered without departing from the spirit and scope of the present disclosure.

[0133] Various operations of the embodiments are provided herein. The order in which some or all of the operations are described should not be interpreted as implying that such operations are necessarily related to the order. It should be understood that there are alternative arrangements prepared by the present description. In addition, it should be understood that not all operations are necessarily present in each embodiment provided herein. Again, it should be understood that not all operations are necessary.

[0134] It should be understood that the layers, features, elements, etc. depicted herein are illustrated by specific dimensions (such as structural size or orientation) relative to each other, for example, for the purpose of simplicity and ease of understanding, and in one or more embodiments, their actual dimensions are substantially different from the dimensions illustrated herein. In addition, there are a variety of techniques for forming the layers, features, elements, etc. mentioned herein, such as etching techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques (such as magnetron or ion beam sputtering), growth techniques (such as thermal growth) or deposition techniques (such as CVD, PVD, PECVD or ALD).

[0135] In addition, "exemplary" is used herein to mean serving as an example, an instance, an example, etc., and is not necessarily advantageous. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, "a and an" as used in this application and the appended claims are generally interpreted as meaning "one or more", unless otherwise specified or it is obvious from the context that it is directed to a singular form. Again, at least one of A and B and / or the like generally means A or B or both A and B. In addition, with respect to the use of "including", "having, has", "with" or variations thereof, these terms are intended to be inclusive in a manner similar to the term "comprising". Again, unless otherwise specified, "first", "second" or the like are not intended to imply a temporal aspect, a spatial aspect, an order, etc. On the contrary, these terms are used only as identifiers, names, etc. for features, elements, items, etc. For example, the first element and the second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0136] Again, although the present disclosure has been shown and described with respect to one or more implementations, equivalent substitutions and modifications will occur to others skilled in the art based on the reading and understanding of this specification and the accompanying drawings. The present disclosure includes all such modifications and changes and is not limited only by the scope of the claims. In detail, with respect to the various functions performed by the components (e.g., elements, resources, etc.) described above, unless otherwise indicated, the terms used to describe such components are intended to correspond to any component (e.g., a functionally equivalent component) that performs the specified functions of the described components, even if structurally not equivalent to the disclosed structure. In addition, although a particular feature of the present disclosure may have been disclosed with respect to only one of several implementations, this feature may be combined with one or more other features of other implementations that may be necessary and advantageous for any given or specific application.

Claims

1. A semiconductor element, characterized in that: Include: A pixel array comprising a first pixel and a second pixel; a metal structure overlying a portion of a substrate between the first pixel and the second pixel; a second barrier layer adjacent to a sidewall of the metal structure; as well as A passivation layer is adjacent to a side wall of the second barrier layer, wherein the second barrier layer is between the passivation layer and the metal structure.

2. The semiconductor device according to claim 1, characterized in that Also includes: A first barrier layer is located under the metal structure.

3. The semiconductor device according to claim 2, characterized in that The second barrier layer and the first barrier layer include the same material composition.

4. The semiconductor device according to claim 1, wherein: The second barrier layer covers the metal structure.

5. The semiconductor device according to claim 1, wherein: The passivation layer covers the second barrier layer.

6. The semiconductor device according to claim 1, wherein: The second barrier layer contacts the sidewall of the metal structure; and The passivation layer contacts the sidewall of the second barrier layer.

7. The semiconductor device according to claim 1, wherein: The second barrier layer contacts the sidewall of the metal structure; and The passivation layer contacts a top surface of the metal structure.

8. The semiconductor device according to claim 1, wherein: Also includes: A dielectric layer covers the first pixel and is located below the metal structure. The passivation layer contacts the dielectric layer.

9. The semiconductor device according to claim 8, characterized in that The second barrier layer contacts a side wall of the dielectric layer.

10. The semiconductor device according to claim 1, wherein: Also includes: A dielectric layer is located above the metal structure, and the second barrier layer is adjacent to a side wall of the dielectric layer.

11. The semiconductor device according to claim 1, wherein: Also includes: A color filter material covers the first pixel and is adjacent to a side wall of the passivation layer.

12. A semiconductor device, characterized in that: Include: A pixel array comprising a first pixel and a second pixel; a first barrier layer covering a portion of a substrate between the first pixel and the second pixel; a metal structure overlying the first barrier layer and overlying a portion of a substrate between the first pixel and the second pixel; as well as A second barrier layer is adjacent to a side wall of the metal structure and contacts a side wall of the first barrier layer. A top surface of the metal structure is lower than a top surface of the second barrier layer.

13. The semiconductor device according to claim 12, characterized in that The first barrier layer and the second barrier layer include a same material composition.

14. The semiconductor device according to claim 12, characterized in that Also includes: A passivation layer, wherein the second barrier layer is between the metal structure and the passivation layer.

15. The semiconductor device according to claim 12, characterized in that Also includes: A first dielectric layer is located under the first barrier layer.

16. The semiconductor device according to claim 15, characterized in that Also includes: A passivation layer is provided. The passivation layer and the second barrier layer are in contact with the first dielectric layer.

17. The semiconductor device according to claim 16, characterized in that The first barrier layer contacts the first dielectric layer.

18. A method for forming a semiconductor device, characterized in that: Include: forming a metal structure on a first dielectric layer and overlying a portion of a substrate between a first pixel and a second pixel; forming a first barrier layer on the metal structure and the first dielectric layer, wherein the first barrier layer is composed of a TiN layer and a Ti layer; removing a portion of the first barrier layer on the first dielectric layer to expose a top surface of the first dielectric layer; as well as A filter is formed on the top surface of the first dielectric layer after removing the portion of the first barrier layer.

19. The method according to claim 18, characterized in that Also includes: A passivation layer is formed on the top surface of the first dielectric layer after removing the portion of the first barrier layer and before forming the filter.

20. The method according to claim 18, characterized in that Also includes: removing a portion of the first barrier layer on the metal structure; and After removing the portion of the first barrier layer on the metal structure, a passivation layer is formed on the metal structure.

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