A vertical chip structure of a micro light-emitting diode, a preparation method thereof, and an application thereof

Abstract

The present invention discloses a vertical chip structure of a micro - light emitting diode (micro - LED), a preparation method thereof, and an application. The vertical chip structure includes an epitaxial structure, and the epitaxial structure includes a first semiconductor layer, an active region, and a second semiconductor layer sequentially arranged along a set direction; the first and second semiconductor layers are respectively cooperated with a first electrode and a second electrode, and the first electrode is distributed around the first semiconductor layer and forms an electrical contact with the side wall of the first semiconductor layer. The micro - LED vertical chip structure of the present invention can avoid the absorption of the light emitted by the LED chip due to the electrode being arranged on the light - emitting surface by adopting a side - wall electrode structure, increase the light - emitting efficiency of the device, and at the same time can also play a role in light reflection, thereby further improving the light extraction efficiency and brightness of the device, and can also reduce the light crosstalk between chips, avoid color coordinate shift, improve the display color purity, and further, the chip size can be further reduced to improve the display resolution.

Description

Technical Field

[0001] The present invention relates to an LED chip, and particularly to a vertical chip structure of a micro light emitting diode (micro-LED), a preparation method thereof, and an application thereof. Background Art

[0002] With the development requirements of applications such as ultra-high-definition small-pitch large-screen commercial displays, and the rise of new display applications such as AR (Augmented Reality), VR (Virtual Reality), and MR (Mixed Reality Technology), challenges have been posed to the miniaturization of the size of LED light sources. In particular, in order to improve the display resolution, it is usually required that the size of the LED chip is less than dozens of micrometers, or even 1-5 μm. In addition, the development of visible light communication also requires the size of the LED chip to move towards the micro size. However, since the LED chip needs two electrodes, a positive electrode and a negative electrode, to work, when preparing such a tiny chip, due to the limitation of the electrode size, the vertical structure is an ideal choice. However, the electrode on the light-emitting surface of the LED in the vertical structure seriously affects the light-emitting efficiency of the LED, resulting in a brightness loss of the LED. Although there is no brightness loss caused by the electrode on the light-emitting surface of the LED flip-chip structure, since this structure needs to prepare two electrodes, a positive electrode and a negative electrode, on the same side of the LED, the size of the LED chip is limited, and it is difficult to achieve an LED smaller than 5 μm. Summary of the Invention

[0003] The purpose of the present invention is to provide a vertical chip structure of a micro light emitting diode, a preparation method thereof, and an application thereof, so as to overcome the deficiencies in the prior art.

[0004] To achieve the above purpose, the present invention provides the following technical solutions:

[0005] Some embodiments of the present invention provide a vertical chip structure of a micro light emitting diode, which includes an epitaxial structure. The epitaxial structure includes a first semiconductor layer, an active region, and a second semiconductor layer arranged in sequence along a set direction. Among them, the first semiconductor layer and the second semiconductor layer are respectively matched with a first electrode and a second electrode, and the first electrode is distributed around the first semiconductor layer and forms an electrical contact with the side wall of the first semiconductor layer.

[0006] In some embodiments, the first electrode is arranged around the first semiconductor layer to form an optical barrier structure.

[0007] In some embodiments, a heavily doped region is formed continuously around the side wall of the first semiconductor layer, and the heavily doped region forms an ohmic contact with the first electrode.

[0008] Some embodiments of the present invention also provide a method for preparing the vertical chip structure of the micro light-emitting diode, which includes:

[0009] The step of providing an epitaxial structure for fabricating an LED chip, the epitaxial structure including a first semiconductor layer, an active region, and a second semiconductor layer stacked in sequence along a set direction;

[0010] The step of fabricating a first electrode and a second electrode that cooperate with the epitaxial structure;

[0011] Further, the step of fabricating the first electrode includes:

[0012] Etching a pattern channel in a selected area of the first semiconductor layer;

[0013] At least arranging a first metal layer in the pattern channel, and forming a first electrode on the sidewall of the first semiconductor layer by using the first metal layer.

[0014] In some embodiments, the step of fabricating the first electrode further includes: arranging a mask corresponding to the pattern channel on the first semiconductor layer, exposing the selected area of the first semiconductor layer from the mask, then performing a heavy doping process on the selected area, and then etching the pattern channel in the selected area, and arranging the pattern channel to surround the remaining heavily doped area.

[0015] In some embodiments, the step of fabricating the first electrode further includes: after forming the first electrode, thinning the first semiconductor layer again until the top height of the first semiconductor layer is lower than the top height of the first electrode, so that the first electrode is formed into an optical barrier structure surrounding the first semiconductor layer.

[0016] Some embodiments of the present invention also provide the use of the vertical chip structure of the micro light-emitting diode in preparing products such as optical components.

[0017] Compared with the prior art, in the vertical chip structure of the micro light-emitting diode proposed in the above embodiments of the present invention, by adopting the chip sidewall electrode structure, it is possible to avoid the absorption of the light emitted by the micro-LED chip due to the electrode being arranged on the light-emitting surface, increase the light-emitting efficiency of the micro-LED chip, and at the same time, it can also play a role in light reflection, thereby further improving the light extraction efficiency and brightness of the micro light-emitting diode, and it can also reduce the light crosstalk between micro-LED chips, avoid color coordinate shift, improve the display color purity, and further, it can also further reduce the size of the micro-LED chip, and then further improve the integration degree of the micro light-emitting diode device and improve the display resolution. At the same time, it is also possible to realize a wafer-level array chip, avoid mass transfer, simplify the process, and save costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 is a schematic diagram of a vertical chip structure of a micro light-emitting diode in Embodiment 1 of the present invention;

[0020] Figure 2a is a schematic diagram of an epitaxial structure of an LED chip in Embodiment 1 of the present invention;

[0021] Figure 2b is in Figure 2a a schematic diagram of setting a mask on the epitaxial structure shown;

[0022] Figure 2c is for Figure 2b a schematic diagram of patterning the mask in;

[0023] Figure 2d is in Figure 2c a schematic diagram of forming a p-type heavily doped region in the first semiconductor layer in;

[0024] Figure 2e is in Figure 2d a schematic diagram of forming a graphic channel in the first semiconductor layer in;

[0025] Figure 2f is to planarize the surface of the device shown in Figure 2e with photoresist;

[0026] Figure 2g is for Figure 2f a schematic diagram of evaporating a metal layer on the surface of the device shown after photolithography;

[0027] Figure 2h is for Figure 2g a schematic diagram of forming a first electrode by lift-off of the metal on the device shown;

[0028] Figure 2i is in Figure 2h a schematic diagram of forming an insulating isolation structure in the device shown;

[0029] Figure 2j is in Figure 2i a schematic diagram of forming a second electrode on the substrate in the device shown;

[0030] Figure 3 It is a schematic diagram of a vertical chip structure of a micro light-emitting diode in Embodiment 2 of the present invention;

[0031] Figure 4 It is a schematic diagram of a vertical chip structure of a micro light-emitting diode in Embodiment 3 of the present invention;

[0032] Figure 5 It is a schematic diagram of a vertical chip structure of a micro light-emitting diode in Embodiment 4 of the present invention;

[0033] Figure 6 It is a schematic diagram of a vertical chip structure of a micro light-emitting diode in Embodiment 5 of the present invention;

[0034] Figure 7a It is a schematic diagram of an epitaxial structure of an LED chip in Embodiment 5 of the present invention;

[0035] Figure 7b It is on Figure 7a A schematic diagram of evaporating a metal layer for making a second electrode on the epitaxial structure shown;

[0036] Figure 7c It is on Figure 7b A schematic diagram of setting a mask on the first semiconductor layer of the device shown;

[0037] Figure 7d It is for Figure 7c A schematic diagram of patterning the mask in;

[0038] Figure 7e It is on Figure 7d A schematic diagram of forming an n-type heavily doped region in the first semiconductor layer in;

[0039] Figure 7f It is on Figure 7e A schematic diagram of forming a patterned channel in the first semiconductor layer in;

[0040] Figure 7g It is using photoresist to Figure 7f A schematic diagram of planarizing the surface of the device shown;

[0041] Figure 7h It is after Figure 7g A schematic diagram of evaporating a metal layer for making a first electrode on the surface of the device shown after photolithography;

[0042] Figure 7i It is for Figure 7h A schematic diagram of forming a first electrode by lift-off of the metal on the device shown;

[0043] Figure 7j It is on Figure 7i A schematic diagram of forming an insulating isolation structure in the device shown;

[0044] Figure 7k is a schematic diagram of forming a second electrode on a substrate in the device shown; Figure 7j A schematic diagram of forming a second electrode on a substrate in the device shown;

[0045] Figure 8 is a schematic diagram of a vertical chip structure of a micro light-emitting diode in Embodiment 6 of the present invention;

[0046] Figure 9 is a schematic diagram of a vertical chip structure of a micro light-emitting diode in Embodiment 7 of the present invention. Detailed implementation manners

[0047] As described above, due to the deficiencies of the prior art, the industry has been difficult to overcome the following micro-LED technology bottlenecks, namely: the brightness loss caused by electrode light absorption in the vertical structure, which requires a substantial increase in the brightness of the LED light source; the light crosstalk between different pixel points, which seriously affects the color coordinates and color purity of the display; and, due to the chip size limitation of the flip-chip structure of the micro-LED, the display resolution cannot be further improved.

[0048] In view of this, through long-term research and practice, the inventors of this case have been able to propose the technical solution of the present invention, which will be explained in detail below.

[0049] A vertical chip structure of a micro light-emitting diode provided in one aspect of the embodiments of the present invention includes an epitaxial structure, and the epitaxial structure includes a first semiconductor layer, an active region, and a second semiconductor layer sequentially arranged along a set direction; wherein, the first semiconductor layer and the second semiconductor layer cooperate with a first electrode and a second electrode respectively, and the first electrode is distributed around the first semiconductor layer and forms electrical contact with the side wall of the first semiconductor layer.

[0050] Further, the surface of the first semiconductor layer away from the active region is set as the light-emitting surface of the vertical chip structure of the micro light-emitting diode.

[0051] Wherein, by arranging the first electrode on the side wall of the first semiconductor layer, it can not only form good electrical contact with the first semiconductor layer, but also prevent it from occupying the light-emitting surface, eliminating its absorption and blocking of the light emitted by the LED, and improving the light-emitting efficiency of the device.

[0052] Wherein, the set direction may be the thickness direction of the epitaxial structure.

[0053] In some embodiments, the first electrode is arranged around the first semiconductor layer to form an optical barrier structure. In this way, not only can the lateral light emission of the LED be reflected, further improving the light extraction efficiency of the micro light-emitting diode, but also the light crosstalk between each LED chip can be reduced.

[0054] More preferably, the inner ring surface of the optical barrier structure is a mirror surface structure.

[0055] In some embodiments, the first electrode forms an ohmic contact with the sidewall of the first semiconductor layer.

[0056] Furthermore, a heavily doped region is formed continuously and circumferentially around the sidewall of the first semiconductor layer, and the heavily doped region forms an ohmic contact with the first electrode.

[0057] Among them, the conductive property of the heavily doped region is the same as that of the first semiconductor layer, that is, it can be p-type or n-type.

[0058] Among them, the radial cross-sectional shape of the heavily doped region can be an annular shape, a rectangular shape or other regular or irregular shapes, and is not limited thereto.

[0059] In some embodiments, the micro light-emitting diode vertical chip structure further includes a light conversion structure, and the light conversion structure is disposed on the first semiconductor layer.

[0060] Furthermore, the light conversion structure includes a quantum dot light conversion material layer covering the first semiconductor layer.

[0061] Of course, the light conversion structure can also adopt other light conversion structures known in the art, such as thin films, encapsulation glue layers, etc. formed by phosphor, fluorescent nanoparticles, etc., but is not limited thereto.

[0062] In addition, the light conversion structure can directly cover the surface of the first semiconductor layer, or can adopt a remote light conversion (such as quantum dots or phosphor) block or film, etc., and is not limited thereto. Its advantage is that it can achieve RGB full-color display without a large number of chip transfers, thus effectively saving costs.

[0063] Furthermore, the conductive types of the first semiconductor layer and the second semiconductor layer are different. For example, either the first semiconductor layer or the second semiconductor layer is p-type, and the other is n-type.

[0064] In some embodiments, a carrier blocking layer (such as an electron or hole blocking layer) is further disposed between the first semiconductor layer and the active region, and the first electrode is disposed on the carrier blocking layer.

[0065] In some embodiments, the first semiconductor layer is a p-type layer, and an electron blocking layer (EBL) is further disposed between the first semiconductor layer and the active region. The first electrode is disposed on the electron blocking layer. Further, the electron blocking layer is also p-type. Alternatively, the first semiconductor layer is an n-type layer, and a hole blocking layer is further disposed between the first semiconductor layer and the active region. The first electrode is disposed on the hole blocking layer. Correspondingly, the hole blocking layer is also n-type.

[0066] In some embodiments, the first semiconductor layer and the second semiconductor layer are a p-type layer and an n-type layer respectively. A conductive substrate is distributed between the second semiconductor layer and the second electrode. Alternatively, the second electrode is disposed on the second semiconductor layer and forms an ohmic contact with the second semiconductor layer. Further, the conductive substrate has the same conductivity type as the second semiconductor.

[0067] In some embodiments, the first semiconductor layer is an n-type layer, and the first electrode is disposed on the active layer. Further, the first electrode is disposed to surround the first semiconductor layer.

[0068] Further, the first semiconductor layer and the second semiconductor layer are an n-type layer and a p-type layer respectively. The second electrode is disposed on the second semiconductor layer and forms an ohmic contact with the second semiconductor layer.

[0069] In some embodiments, the active region includes a multi-quantum well active region.

[0070] In some embodiments, the micro light-emitting diode vertical chip structure further includes an insulating isolation structure, and the insulating isolation structure at least surrounds the first semiconductor layer and the active region.

[0071] Further, the insulating isolation structure can be formed of various insulating dielectric materials such as silicon dioxide, aluminum oxide, silicon nitride, etc., or can be formed of air, etc., and is not limited thereto.

[0072] More preferably, the insulating isolation structure can be formed of an opaque insulating material.

[0073] In the above embodiments of the present invention, the material of the epitaxial structure can be selected from III-V group semiconductor materials or other semiconductor materials known in the art. For example, GaN, AlN, InN, AlGaN, InGaN, GaAs, AlGaAs, AlGaInP, InP, GaP, InGaAsP, etc. can be selected, and is not limited thereto. And, the epitaxial structure can be grown and formed by epitaxial growth technologies such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), etc. known in the art.

[0074] Further, other structural layers known in the art, such as a nucleation layer and a buffer layer, may also be included in the epitaxial structure.

[0075] In the above embodiments of the present invention, the first electrode and the second electrode may be formed of various materials with good conductivity known in the art, such as ITO, Au, Ti, Al, Ag, Cu, Ni, Cr, etc. or their alloys, and are not limited thereto. Moreover, the first electrode and the second electrode may be fabricated by methods known in the art, such as metal sputtering, plasma-enhanced chemical vapor deposition (PECVD), electron beam evaporation (e-beam), etc., and are not limited thereto.

[0076] Another aspect of the embodiments of the present invention also provides an optical component, which includes a plurality of light-emitting units, and at least one of the light-emitting units has the above-mentioned vertical micro light-emitting diode chip structure.

[0077] In some embodiments, the radial dimension of the light-emitting unit is less than 5 μm. Of course, the radial dimension of the light-emitting unit may also be greater than 5 μm, for example, adjusted to dozens of microns or even hundreds of microns. However, it is more preferably controlled to be less than 5 μm.

[0078] In some embodiments, each of the plurality of light-emitting units has the above-mentioned vertical micro light-emitting diode chip structure.

[0079] In some embodiments, the plurality of light-emitting units are integrally arranged, for example, arranged in an array form.

[0080] Further, the plurality of light-emitting units are formed by etching on the same epitaxial wafer, so that the optical component is presented as a wafer-level device.

[0081] In some embodiments, the plurality of light-emitting units are discrete from each other.

[0082] Further, the optical component may be various optical modules applied to display devices, optical communication devices, etc., and is not limited thereto.

[0083] Another aspect of the embodiments of the present invention also provides a method for fabricating the above-mentioned vertical micro light-emitting diode chip structure, which includes:

[0084] A step of providing an epitaxial structure for fabricating an LED chip, the epitaxial structure including a first semiconductor layer, an active region, and a second semiconductor layer stacked in sequence along a set direction; and

[0085] A step of fabricating a first electrode and a second electrode that cooperate with the epitaxial structure;

[0086] Further, the step of fabricating the first electrode includes:

[0087] Etch a patterned channel in a selected region of the first semiconductor layer;

[0088] Dispose a first metal layer at least in the patterned channel, and form a first electrode on the sidewalls of the first semiconductor layer by using the first metal layer.

[0089] In some embodiments, the step of fabricating the first electrode includes: disposing a mask corresponding to the patterned channel on the first semiconductor layer, exposing a selected region of the first semiconductor layer from the mask, then performing a heavy doping process on the selected region, thereafter etching the patterned channel in the selected region, and arranging the patterned channel to surround the remaining heavily doped region.

[0090] Wherein, the manner for performing the heavy doping process on the selected region can be selected from ion implantation, plasma treatment, thermal diffusion and other manners known in the art, and is not limited thereto.

[0091] According to the different conductivity types of the first semiconductor layer, the heavy doping process can be a p-type or n-type heavy doping process. By arranging the patterned channel to surround the remaining heavily doped region, when fabricating the first electrode in the patterned channel, the heavily doped region can be utilized to form a better ohmic contact between the first electrode and the first semiconductor layer.

[0092] In some embodiments, the step of fabricating the first electrode further includes: fabricating and forming the first electrode by adopting a metal lift-off technology in a manner known in the art.

[0093] For example, by coating a photoresist, and after exposure and development, a photoresist film with a required pattern can be formed on the first semiconductor layer (only exposing the region corresponding to the first electrode), and using this photoresist film as a mask, evaporating and depositing the required metal with the film, and then while removing the mask, stripping the metal on the film together, thereby forming the first electrode on the first semiconductor layer.

[0094] Alternatively, a metal layer can also be deposited at the patterned channel by first adopting a metal lift-off technology, and then during the process of fabricating an insulating isolation structure, etching and removing the metal layer distributed in the region corresponding to the insulating isolation structure, thereby forming the first electrode.

[0095] In some embodiments, the preparation method further includes: etching the first semiconductor layer and the active region at the patterned channel until the bottom of the formed etching trench reaches or enters the second semiconductor layer, thereby forming the insulating isolation structure.

[0096] Further, when the region corresponding to the etching trench on the first semiconductor layer is directly exposed, etching can be directly performed on the first semiconductor layer to form the etching trench. When a metal layer for forming the first electrode is covered on the region corresponding to the etching trench on the first semiconductor layer, etching can be sequentially performed on the metal layer and the first semiconductor layer in this region to form the etching trench.

[0097] Further, in a manner known in the art, insulating media such as silicon dioxide, silicon nitride, aluminum oxide, etc. can be filled in the etching trench by using a photolithography process and atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or a combination of both to form the insulating isolation structure.

[0098] Further, if an opaque insulating material is used to form the insulating isolation structure, optical crosstalk between the LED chips can be better avoided.

[0099] In some embodiments, the manufacturing method further includes: after forming the first electrode, thinning the first semiconductor layer until the top height of the first semiconductor layer is lower than the top height of the first electrode, so that the first electrode is formed into an optical barrier structure surrounding the first semiconductor layer.

[0100] Further, the first semiconductor layer can be thinned in a manner known in the art, such as photolithography and dry or wet etching, and is not limited thereto.

[0101] In some embodiments, the manufacturing method further includes: providing a light conversion structure on the first semiconductor layer. The material and the providing manner of the light conversion structure are as described above.

[0102] In some embodiments, the second semiconductor layer is grown on a substrate, and the step of fabricating the second electrode includes:

[0103] Separating the substrate from the second semiconductor layer, and then fabricating the second electrode on the second semiconductor layer;

[0104] Or, fabricating the second electrode on the substrate.

[0105] Further, if the substrate is an insulating substrate or an opaque substrate, the substrate can be separated from the second semiconductor layer, and then the second electrode can be fabricated on the second semiconductor layer.

[0106] Further, if the substrate is a transparent conductive substrate, the substrate can be thinned, and then the second electrode can be fabricated on the substrate.

[0107] Further, the second electrode may be in full-surface contact with the substrate or the second semiconductor layer to improve the uniformity of current injection.

[0108] Among them, the substrate can be selected from sapphire substrates, Si substrates, GaN substrates, SiC substrates, AlN substrates, gallium oxide substrates, GaAs substrates, GaP substrates, InP substrates, etc. known in the art, and is not limited thereto.

[0109] The method for preparing the vertical chip structure of the micro light-emitting diode provided by the above embodiments of the present invention is compatible with the existing semiconductor device manufacturing processes, and can realize a wafer-level micro light-emitting diode array chip, which is simpler, more efficient, lower in cost, and higher in yield than the existing micro light-emitting diode manufacturing process, and thus has better application prospects.

[0110] Next, the technical solutions in the embodiments of the present invention will be described in detail with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. It should be noted that in the following embodiments, unless otherwise specified, various reagents and various processing and testing equipment used are known in the art and can be obtained through market channels, and various processing methods adopted, such as lithography, dry or wet etching, lift-off process, physical or chemical deposition process, etc., can be implemented in accordance with the known methods in the art.

[0111] Example 1: Please refer to Figure 1 As shown, a vertical chip structure of a micro light-emitting diode provided in this embodiment includes an epitaxial structure formed on an n-type conductive substrate 107 (such as GaN, etc.). The epitaxial structure includes a second semiconductor layer 105 (such as GaN), an active region 103 (such as In x Ga 1-x N / GaN multiple quantum well, 0 < x < 1), an electron blocking layer 102 (such as Al x Ga 1-x N, 0 < x < 1), and a first semiconductor layer 101 (such as GaN) grown sequentially from bottom to top. The first semiconductor layer 101 and the electron blocking layer 102 are both p-type (such as doped with Mg), while the second semiconductor layer 105 is n-type (such as doped with Si), and the active region 103 adopts a multiple quantum well active region (MQW). Among them, a third semiconductor layer 104 (such as Al y Ga 1-yN, where 0 ≦ y ≦ 1), the third semiconductor layer 104 is also p-type and can be formed by epitaxial growth with the first semiconductor layer 101 and the electron blocking layer 102 at one time. Of course, the third semiconductor layer 104 can also be omitted. The first semiconductor layer 101 and the second semiconductor layer 105 are respectively matched with the first electrode 106 (such as Ti / Al / Ni / Au) and the second electrode 110 (such as Ti / Al / Ni / Au or / Al / Ni / Au). The first electrode is disposed around the first semiconductor layer. A p-type heavily doped region 108 is formed at the sidewall of the first semiconductor layer. The p-type heavily doped region forms an ohmic contact with the first electrode. The radial cross-section of the first electrode and the p-type heavily doped region can be circular, rectangular or other shapes. A conductive substrate 107 can be disposed between the second electrode 110 and the second semiconductor layer 105. Among them, at least the first electrode is a metal electrode (such as Ti / Al / Ni / Au). Further, an insulating isolation structure 109 is also disposed around the first semiconductor layer to the active region. The insulating isolation structure includes an isolation groove disposed around the first semiconductor layer to the active region. The bottom of the isolation groove reaches or enters the second semiconductor layer. An insulating medium such as silicon oxide can also be filled in the isolation groove. By using this insulating isolation structure, the vertical chip structure of the micro light-emitting diode can be electrically isolated from other vertical chip structures of the micro light-emitting diode, and at the same time, it can also play a role in optical isolation between chips to a certain extent. The aforementioned second electrode 110 can also adopt a patterned discrete electrode.

[0112] When the vertical chip structure of the micro light-emitting diode is in use, the light generated by the active layer can be emitted from the first semiconductor layer (as shown by the arrow in the figure). Since the first electrode is disposed around the first semiconductor layer, it does not occupy the effective light-emitting surface, thereby increasing the light-emitting efficiency and brightness of the vertical chip structure of the micro light-emitting diode, and can also block the lateral propagation of light to a certain extent, reducing the optical crosstalk between the vertical chip structures of the micro light-emitting diodes.

[0113] A method for fabricating the vertical chip structure of the micro light-emitting diode includes the following steps:

[0114] S1. Epitaxially grow the second semiconductor layer 105, the active region 103, the third semiconductor layer 104, the electron blocking layer 102, the first semiconductor layer 101, etc. on the conductive substrate 107 in sequence to obtain an LED chip epitaxial structure, as Figure 2a shown;

[0115] S2. As Figure 2b shown, a mask 111 (such as silicon oxide SiO 2and other materials, but not limited to this), and use photolithography, dry or wet etching processes, etc. to form the required patterns in the mask, so as to expose the selected area 114 of the first semiconductor layer, as Figure 2c shown;

[0116] S3. As Figure 2d shown, use the ion implantation method to perform p-type heavy doping on the selected area of the first semiconductor layer to form a p-type heavily doped region 108, which is beneficial to forming an ohmic contact between the first electrode and the sidewall of the first semiconductor in subsequent processes;

[0117] S4. As Figure 2e shown, continue to use processes such as photolithography, dry or wet etching, etc. to etch the selected area of the first semiconductor layer to form the required graphic channel 113, but retain part of the p-type heavily doped region 108 in the area surrounded by the graphic channel;

[0118] S5. Use the lift-off process to form the first electrode 106 on the sidewall of the first semiconductor layer. Specifically, as Figure 2f shown, a photoresist 112 can be first coated on the first semiconductor layer, planarized, and patterned exposure and development are performed on the selected area to expose the graphic channel 113, and then a metal layer 106' is evaporated on the first semiconductor layer and other areas on the chip surface (as Figure 2g shown), and the first electrode is formed by peeling (as Figure 2h shown);

[0119] S6. Continue to use processes such as photolithography and dry etching to process the epitaxial structure, so as to form an insulating isolation structure 109 between the vertical chip structures of each micro light-emitting diode (as Figure 2i shown), which plays the role of isolating and passivating the sidewalls of the chip. The insulating dielectric material used in the insulating isolation structure can be silicon nitride, SiO 2 etc., and can be formed by ALD, PECVD, etc., and is not limited to this;

[0120] S7. Thin the conductive substrate 107, and then form the second electrode 110 on the conductive substrate by evaporation, sputtering, etc., as Figure 2j shown. Further, the second electrode 110 can be further processed into a patterned discrete electrode. Or, a second electrode 110 with a patterned discrete structure can also be directly evaporated or sputtered on the conductive substrate.

[0121] In this embodiment, the vertical chip structures of each micro light-emitting diode can also be separated by mechanical, laser scribing, etc. to form discrete light-emitting units.

[0122] Example 2: A vertical chip structure of a micro light-emitting diode provided in this example is basically the same as that in Example 1, except that: Please refer to Figure 3 As shown, the top height of the first electrode 106' is higher than the top height of the first semiconductor layer 101', thereby forming an optical barrier structure surrounding the first semiconductor layer. Preferably, the inner ring surface of the optical barrier structure can be set as a mirror structure. In this way, not only can the problem caused by the first electrode occupying the effective light-emitting surface on the front of the micro light-emitting diode be eliminated, but also the first electrode can be used to play a role in light reflection, thereby further improving the light extraction efficiency and brightness of the vertical chip structure of the micro light-emitting diode, increasing the forward light emission, and at the same time better reducing and even eliminating the light crosstalk between the vertical chip structures of the micro light-emitting diodes.

[0123] The manufacturing process of the vertical chip structure of the micro light-emitting diode in this example is also basically the same as that in Example 1, except that it further includes:

[0124] S8. Continue to process the first semiconductor layer by using processes such as photolithography, dry etching or wet etching, etc., to thin it (that is, to reduce its top height) until a certain height difference is formed between the top of the first electrode and the top of the first semiconductor layer, and then the first electrode forms the optical barrier structure.

[0125] Example 3: A vertical chip structure of a micro light-emitting diode provided in this example is basically the same as that in Example 2 and is a deep ultraviolet light chip, except that: Please refer to Figure 4 As shown, a quantum dot light conversion material layer 115 is further provided on the first semiconductor layer. In particular, red, green, and blue quantum dot light conversion material layers can be provided at intervals on the first semiconductor layers of adjacent vertical chip structures of micro light-emitting diodes, thereby realizing full-color display. The advantages of this example are at least: there is no need for massive chip transfer, and compared with the full-color display technology of red, green, and blue micro light-emitting diodes, the process is simplified and the cost can be saved.

[0126] Correspondingly, the manufacturing process of the vertical chip structure of the micro light-emitting diode in this example is also basically the same as that in Example 2, except that it further includes:

[0127] S9. Coat a red, green or blue quantum dot light conversion material layer on the first semiconductor layer by methods such as photolithography or inkjet printing, spin coating, etc.

[0128] Example 4: A vertical chip structure of a micro light-emitting diode provided in this example is basically the same as that in Example 1, except that: Please refer to Figure 5 As shown, the second electrode 110 is directly formed on the second semiconductor layer 105.

[0129] Correspondingly, the manufacturing process of the micro light-emitting diode vertical chip structure in this embodiment is also basically the same as that in Embodiment 1, except that:

[0130] In step S1, an absorbent substrate (such as Si, etc.) is used;

[0131] In step S7, first, the substrate is peeled off from the second semiconductor layer in a manner known in the art, and then a second electrode is formed on the second semiconductor layer 105 by means of electron beam evaporation (e-beam), PECVD, magnetron sputtering (Sputter), etc.

[0132] Furthermore, the manufacturing process of this embodiment may further include the operations of steps S8 and S9 in the foregoing Embodiments 2 and 3.

[0133] Embodiment 5: Please refer to Figure 6 As shown, a micro light-emitting diode vertical chip structure provided in this embodiment includes an epitaxial structure, and the epitaxial structure includes a first semiconductor layer 205, an active region 203, a third semiconductor layer 204, an electron blocking layer 202, and a second semiconductor layer 201 that are sequentially grown from bottom to top. The second semiconductor layer 201, the third semiconductor layer 204, and the electron blocking layer 202 are all p-type, while the first semiconductor layer 205 is n-type. The active region 203 adopts a multi-quantum well active region (MQW). The second semiconductor layer 201 and the first semiconductor layer 205 cooperate with the second electrode 206 and the first electrode 210 respectively. The first electrode is disposed around the first semiconductor layer, and an n-type heavily doped region 208 is formed at the sidewall of the first semiconductor layer. The n-type heavily doped region forms an ohmic contact with the first electrode. The radial cross-sections of the first electrode and the n-type heavily doped region may be circular, rectangular, or other shapes. The first electrode and the second electrode can both adopt metal electrodes. Furthermore, an insulating isolation structure 209 is also disposed around the first semiconductor layer to the active region. The insulating isolation structure includes an isolation groove disposed around the first semiconductor layer to the active region. The bottom of the isolation groove reaches or enters the second semiconductor layer, and an insulating medium such as silicon dioxide may be filled in the isolation groove.

[0134] When the micro light-emitting diode vertical chip structure is in use, the light generated by the active layer can be emitted from the first semiconductor layer (as shown by the arrow in the figure). Since the first electrode is disposed around the first semiconductor layer, it does not occupy the effective light-emitting surface, thereby increasing the light-emitting efficiency and brightness of the micro light-emitting diode vertical chip structure, and can also block the lateral propagation of light to a certain extent and reduce the light crosstalk between the micro light-emitting diode vertical chip structures.

[0135] A method for manufacturing the micro light-emitting diode vertical chip structure includes the following steps:

[0136] S1. Sequentially epitaxially grow a first semiconductor layer 205, an active region 203, a third semiconductor layer 204, an electron blocking layer 202, a second semiconductor layer 201, etc. on a substrate 207 to obtain an LED chip epitaxial structure, as Figure 7a shown;

[0137] S2. In a manner known in the art, form a metal layer 206' for fabricating a second electrode 206 on the substrate 207 by means of electron beam evaporation (e-beam), PECVD, magnetron sputtering, etc., as Figure 7b shown;

[0138] S3. Flip the epitaxial structure, and strip the substrate 207 from the first semiconductor layer 205 in a manner known in the art. Then, set a mask 211 (such as a material like silicon dioxide SiO 2 and so on, and not limited to this, as Figure 7c shown) on the first semiconductor layer, and form a required pattern in the mask by means of photolithography, etching process, etc., to expose a selected area 214 of the first semiconductor layer, as Figure 7d shown;

[0139] S4. Perform n-type heavy doping on the selected area 214 of the first semiconductor layer by means of ion implantation, etc. to form an n-type heavily doped region 208, as Figure 7e shown, so as to facilitate the formation of an ohmic contact between the first electrode and the sidewall of the first semiconductor in subsequent processes;

[0140] S5. Continue to etch the selected area of the first semiconductor layer by means of photolithography, dry or wet etching, etc. to form a required pattern channel 213, but retain a part of the n-type heavily doped region 208 within the area surrounded by the pattern channel, as Figure 7f shown;

[0141] S6. Form a first electrode 210 on the sidewall of the first semiconductor layer by means of a lift-off process. Specifically, a photoresist 212 can be first coated on the first semiconductor layer and planarized, as Figure 7g shown, and then perform patterned exposure and development on the selected area to expose the pattern channel 213. Then, deposit a metal 210' on the first semiconductor layer and other areas on the chip surface, as Figure 7h shown, and strip to form the first electrode, as Figure 7i shown;

[0142] S7. Process the epitaxial structure by means of photolithography, etching, etc. to form an insulating isolation structure 209 between the vertical chip structures of each micro light-emitting diode, which plays a role in isolating and passivating the sidewalls of the chip, as Figure 7j shown. The insulating dielectric material used in the insulating isolation structure can be SiO2 etc., and can be formed by means such as ALD, PECVD, etc., and are not limited thereto;

[0143] S8. Use processes such as photolithography and etching to pattern the metal layer 206' to form the second electrode 206, as Figure 7k shown. Preferably, the second electrode 206 has the characteristic of reflecting light.

[0144] In this embodiment, the vertical chip structures of each micro light-emitting diode can also be separated by mechanical, laser scribing and other means to form discrete light-emitting units.

[0145] Embodiment 6: A vertical chip structure of a micro light-emitting diode provided in this embodiment is basically the same as that in Embodiment 5, the difference being: Please refer to Figure 8 shown, wherein the top height of the first electrode 210' is higher than the top height of the first semiconductor layer 205', thereby forming an optical barrier structure surrounding the first semiconductor layer. Preferably, the inner ring surface of the optical barrier structure can be set as a mirror structure. In this way, not only can the problem of light efficiency loss caused by the first electrode occupying the effective light-emitting surface on the front of the micro light-emitting diode be eliminated, but also the first electrode can be used to play a role in light reflection, thereby further improving the light extraction efficiency and brightness of the vertical chip structure of the micro light-emitting diode, increasing forward light emission, and at the same time better reducing and even eliminating the light crosstalk between the vertical chip structures of each micro light-emitting diode. When applied to display, color coordinate shift can be avoided and display color purity can be improved.

[0146] The preparation process of the vertical chip structure of the micro light-emitting diode in this embodiment is also basically the same as that in Embodiment 5, the difference being that it further includes:

[0147] S9. Use processes such as photolithography, dry or wet etching, etc. to process the first semiconductor layer to make it thinner (i.e., reduce its top height) until a certain height difference is formed between the top of the first electrode and the top of the first semiconductor layer, so that the first electrode forms the optical barrier structure.

[0148] Embodiment 7: A vertical chip structure of a micro light-emitting diode provided in this embodiment is basically the same as that in Embodiment 6 and is a deep ultraviolet light chip, the difference being: Please refer to Figure 9 shown, and a quantum dot light conversion material layer 215 is further provided on the first semiconductor layer. In particular, red, green, and blue quantum dot light conversion material layers can be provided at intervals on the first semiconductor layers of adjacent vertical chip structures of micro light-emitting diodes, thereby realizing full-color display. The advantages of this embodiment are at least: There is no need for massive chip transfer, and compared with the full-color display technology of red, green, and blue micro light-emitting diodes, cost can be saved.

[0149] Correspondingly, the preparation process of the micro light-emitting diode vertical chip structure in this embodiment is also basically the same as that in Embodiment 2, except that it further includes:

[0150] S10. Coating a red, green or blue quantum dot light conversion material layer on the first semiconductor layer by means of photolithography, inkjet printing, spin coating or the like.

[0151] The micro light-emitting diode vertical chip structures provided in the above Embodiments 1-7 can also be used as light-emitting units and assembled with corresponding driving modules to form an optical module. The optical module can be applied to display devices, optical communication devices, etc., and is not limited thereto. The driving module can be selected from various types of driving modules known in the art, such as a CMOS driving module, etc., and is not limited thereto.

[0152] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements expressly listed, but also includes other elements not expressly listed or inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0153] The above are only specific embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A vertical chip structure of a micro light-emitting diode, comprising an epitaxial structure, the epitaxial structure including a first semiconductor layer, an active region, and a second semiconductor layer sequentially arranged in a set direction, the first semiconductor layer and the second semiconductor layer being respectively matched with a first electrode and a second electrode, and the surface of the first semiconductor layer being a light-emitting surface. Characterized in that: The first electrode is disposed on the active region, the first electrode surrounds the first semiconductor layer to form an optical barrier structure, and forms an electrical contact with the sidewall of the first semiconductor layer.

2. The vertical chip structure of a micro light-emitting diode according to claim 1, Characterized in that: The first electrode forms an ohmic contact with the sidewall of the first semiconductor layer.

3. The vertical chip structure of a micro light-emitting diode according to claim 1, Characterized in that: A heavily doped region is formed at the sidewall of the first semiconductor layer and is continuously and circumferentially arranged, and the heavily doped region forms an ohmic contact with the first electrode.

4. The vertical chip structure of a micro light-emitting diode according to claim 1, Characterized in that: A carrier blocking layer is further disposed between the first semiconductor layer and the active region, and the first electrode is disposed on the carrier blocking layer.

5. The vertical chip structure of a micro light-emitting diode according to claim 1, Characterized in that: Either the first semiconductor layer or the second semiconductor layer is p-type, and the other is n-type.

6. The vertical chip structure of a micro light-emitting diode according to claim 5, Characterized in that: The first semiconductor layer and the second semiconductor layer are respectively a p-type layer and an n-type layer, a conductive substrate is distributed between the second semiconductor layer and the second electrode, or the second electrode is disposed on the second semiconductor layer and forms an ohmic contact with the second semiconductor layer.

7. The vertical chip structure of a micro light-emitting diode according to claim 5, Characterized in that: The first semiconductor layer is an n-type layer, and the first electrode is disposed on the active layer.

8. The vertical chip structure of a micro light-emitting diode according to claim 5, Characterized in that: The first semiconductor layer and the second semiconductor layer are respectively an n-type layer and a p-type layer, and the second electrode is disposed on the second semiconductor layer and forms an ohmic contact with the second semiconductor layer.

9. The vertical chip structure of a micro light-emitting diode according to claim 1, Characterized in that: The active region includes a multi-quantum well active region.

10. The vertical chip structure of a micro light-emitting diode according to claim 1, Characterized in that: The vertical chip structure of the micro light-emitting diode further includes a light conversion structure and / or an insulation isolation structure, the light conversion structure is disposed on the first semiconductor layer, and the insulation isolation structure at least surrounds the first semiconductor layer and the active region.

11. The vertical chip structure of a micro light-emitting diode according to claim 10, Characterized in that: The light conversion structure includes a quantum dot light conversion material layer coated on the first semiconductor layer.

12. A method for preparing the vertical chip structure of a micro light-emitting diode according to any one of claims 1-11, Comprising: Steps for providing an epitaxial structure for manufacturing an LED chip, the epitaxial structure including a first semiconductor layer, an active region, and a second semiconductor layer stacked in sequence along a set direction; Steps for manufacturing a first electrode and a second electrode that cooperate with the epitaxial structure; It is characterized in that the step of manufacturing the first electrode includes: Etching a pattern channel in a selected area of the first semiconductor layer; At least disposing a first metal layer in the pattern channel, and forming a first electrode on the sidewall of the first semiconductor layer by using the first metal layer.

13. According to the manufacturing method described in claim 12, It is characterized in that, The step of manufacturing the first electrode further includes: disposing a mask corresponding to the pattern channel on the first semiconductor layer, exposing the selected area of the first semiconductor layer from the mask, then performing a heavy doping process on the selected area, and then etching the pattern channel in the selected area, and making the pattern channel surround the remaining heavily doped area.

14. According to the manufacturing method described in claim 13, It is characterized in that, It further includes: Etching the first semiconductor layer and the active region at the pattern channel until the bottom of the formed etching trench reaches or enters the second semiconductor layer, thereby forming an insulating isolation structure.

15. According to the manufacturing method described in claim 14, It is characterized in that It further includes: Filling an insulating medium in the etching trench, thereby forming the insulating isolation structure.

16. According to the manufacturing method described in claim 12, It is characterized in that, The step of manufacturing the first electrode further includes: manufacturing and forming the first electrode by using a lift-off process.

17. According to the manufacturing method described in claim 12, It is characterized in that, It includes: After forming the first electrode, thinning the first semiconductor layer until the top height of the first semiconductor layer is lower than the top height of the first electrode, thereby making the first electrode form an optical barrier structure surrounding the first semiconductor layer.

18. According to the manufacturing method described in claim 12, It is characterized in that, It includes: Disposing a light conversion structure on the first semiconductor layer.

19. According to the manufacturing method described in claim 12, It is characterized in that, The second semiconductor layer is grown on a substrate, and the step of manufacturing the second electrode includes: Separating the substrate from the second semiconductor layer, and then manufacturing a second electrode on the second semiconductor layer; Or, manufacturing a second electrode on the substrate, the substrate being a conductive substrate and having the same conductivity type as the second semiconductor layer.

20. A light-emitting component, It is characterized in that: The light-emitting component includes a plurality of light-emitting units, and at least one light-emitting unit has the vertical chip structure of a micro light-emitting diode described in any one of claims 1-11.

21. According to the light-emitting component described in claim 20, It is characterized in that: The radial dimension of the light-emitting unit is below 5 μm.

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