A resource-constrained device

Abstract

The application discloses a simplified instruction set of micro-operation system bytecode and a resource-restricted device, and the simplified instruction set comprises: a first instruction, the first instruction is composed of an operation code, and parameter information of the first instruction is implied in the operation code; a second instruction, the second instruction is a high-frequency instruction with multiple instruction formats; a third instruction, the third instruction comprises instructions with different instruction formats based on different parameter numbers; a fourth instruction, the fourth instruction comprises instructions of common data types and instructions of uncommon data types, the instructions of common data types have multiple instruction formats, and the instructions of uncommon data types have one instruction format; a fifth instruction, the fifth instruction is an instruction with a single-byte constant pool index; and a sixth instruction, the sixth instruction is a macro instruction. The instruction set of the application can reduce the size of bytecode as much as possible, can not only reduce the demand of persistent storage of a chip, but also can improve the execution efficiency of code.

Description

Technical Field

[0001] This invention relates to the field of virtual machine instruction set technology, specifically to a micro-operating system bytecode reduced instruction set and resource-constrained device. Background Technology

[0002] The Java programming language is object-oriented. A "class" describes a collection of data (described by fields) and various methods for manipulating that data. The fields and methods of a class describe the state and behavior of an object. Due to resource constraints, smart SE (Secure Element) and MCU (Micro Controller Unit) security chips currently mostly use the Java Card Virtual Machine, which can run applications written in Java. Java applications need to be compiled into Class files by a Java compiler, then converted into CAP files using the conversion tool provided by Java Card, downloaded to the chip, and executed by the Java Card Virtual Machine. The Java Card instruction set is based on an operand stack, which results in poorer execution performance compared to register-based bytecode instruction sets. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide a micro-operating system bytecode reduced instruction set and resource-constrained device for resource-constrained devices such as intelligent SE and secure MCU chips. This allows for the minimization of bytecode size for various object-oriented and architecture-neutral programs, thereby reducing the chip's persistent storage requirements and improving code execution efficiency.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] A reduced instruction set for micro-operating system bytecode, the reduced instruction set comprising:

[0006] The first instruction consists of an opcode, and the opcode implicitly contains the parameter information of the first instruction.

[0007] The second instruction is a high-frequency instruction with multiple instruction formats;

[0008] The third instruction includes instructions with different instruction formats based on different numbers of parameters;

[0009] The fourth instruction includes instructions for commonly used data types and instructions for less commonly used data types. The instructions for commonly used data types have multiple instruction formats, while the instructions for less commonly used data types have one instruction format.

[0010] The fifth instruction is an instruction with a single-byte constant pool index;

[0011] The sixth instruction is a macro instruction.

[0012] Furthermore, in the simplified instruction set described above, the first instruction includes:

[0013] Instructions that implicitly include operand and register numbers in their opcodes;

[0014] Instructions that embed register numbers into their opcodes;

[0015] Instructions that implicitly include constant operands in the opcode;

[0016] Array member access instructions that implicitly include the member type of array members in the opcode;

[0017] Instructions that implicitly specify the type and parameters of a method call within the opcode.

[0018] Furthermore, in the simplified instruction set described above, the second instruction includes:

[0019] Commonly used arithmetic operation commands with multiple operation formats;

[0020] Array member access instructions using 4-bit register format;

[0021] An array creation instruction that implicitly includes the member type of array members in the opcode;

[0022] Branch instructions with multiple instruction formats are based on the results of equality and inequality comparisons.

[0023] Furthermore, in the simplified instruction set described above, the third instruction includes:

[0024] Static method call instructions with different instruction formats exist based on the number of parameters.

[0025] Virtual method call instructions have different instruction formats depending on the number of parameters;

[0026] Private instance method invocation instructions have different instruction formats depending on the number of parameters.

[0027] Furthermore, in the simplified instruction set described above, the fourth instruction includes:

[0028] Commands for commonly used data types include those for the short data type;

[0029] Instructions for less commonly used data types include those for the int data type.

[0030] Furthermore, in the simplified instruction set described above, the fifth instruction includes:

[0031] A static method call instruction with a single-byte constant pool index;

[0032] Virtual method invocation instructions with a single-byte constant pool index;

[0033] Static field access instructions with a single-byte constant pool index;

[0034] Instance field access instructions with a single-byte constant pool index.

[0035] Furthermore, in the simplified instruction set described above, the sixth instruction includes:

[0036] Macro instructions generated based on static method call instruction replacement;

[0037] Macro instructions are formed by merging multiple adjacent instructions.

[0038] A resource-constrained device, wherein a virtual machine runs on the resource-constrained device, the virtual machine being used to execute the reduced instruction set described in any of the preceding claims.

[0039] The beneficial effects of this invention are as follows: This invention designs a register-based virtual machine instruction set for resource-constrained devices such as intelligent SE and secure MCU chips, and for various object-oriented and architecture-neutral programs, minimizing the size of bytecode. This not only reduces the chip's persistent storage requirements but also improves code execution efficiency. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a simplified instruction set of micro-operating system bytecode provided in an embodiment of the present invention. Detailed Implementation

[0041] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0042] An instruction consists of a one-byte opcode specifying the operation to be performed, followed by zero or more operands representing the values ​​to be manipulated. Each unit in the instruction format description represents one byte. Registers in the instruction are 16 bits and can represent boolean, byte, short, reference types, and return addresses. The int type requires two consecutively numbered register pairs. A null reference has a value of short type 0, i.e., (object)null == (short)0. The last few registers in the stack frame of a method call are used to pass method parameters. This invention proposes a register-based TGoMOS virtual machine instruction set (hereinafter referred to as the reduced instruction set). This instruction set is used for resource-constrained devices such as smart SEs and security MCU chips, and various object-oriented, architecture-neutral programs. It is specifically designed for virtual machines in resource-constrained devices such as smart SEs and security MCU chips, minimizing bytecode size, which not only reduces the chip's persistent storage requirements but also improves code execution efficiency.

[0043] like Figure 1 As shown, this embodiment of the invention provides a reduced instruction set for micro-operating system bytecode, the reduced instruction set including: a first instruction, a second instruction, a third instruction, a fourth instruction, a fifth instruction, and a sixth instruction.

[0044] The first instruction consists of an opcode, which implicitly contains the parameter information for the first instruction. The first instruction includes:

[0045] a. Instructions that implicitly include operand and register numbers in the opcode, such as the constant assignment instructions in Table 1 below.

[0046] Table 1

[0047]

[0048] As shown in Table 1, constant assignment is a very frequent operation, and the above encoding can significantly reduce the length of the method's bytecode.

[0049] b. Instructions that imply register numbers in the opcode, such as constant assignment instructions in Table 2, static field access instructions in Table 3, instructions that return non-object results of method calls in Table 4, instructions that return object reference results of method calls in Table 5, and array member access instructions in Table 6.

[0050] Table 2

[0051]

[0052] Table 3

[0053]

[0054] Table 4

[0055]

[0056] Table 5

[0057]

[0058] Table 6

[0059]

[0060] c. Instructions that implicitly include constant operands in the opcode;

[0061] d. Array member access instructions that implicitly embed the member type of array members into the opcode;

[0062] e. Instructions that imply the type and parameters of a method call in the opcode.

[0063] The simplified instruction set of this invention also includes a second instruction, which is a high-frequency instruction with multiple instruction formats. The second instruction includes:

[0064] a. Commonly used arithmetic operation instructions with multiple operation formats, such as the addition operation instructions in Table 7 and the AND operation instructions in Table 8.

[0065] Table 7

[0066]

[0067] Since addition operations are frequently used, providing multiple operation formats can reduce the bytecode size. Compared to the 4-byte instruction length of addrAA rBB rCC / iadd rAA rBB rCC, using other instructions can reduce the size by 1 or 2 bytes.

[0068] Table 8

[0069]

[0070] Because the operations are frequently used, providing multiple operation formats can reduce the bytecode size. Compared to the 4-byte instruction length of `andrAA rBB rCC` / `iand rAA rBB rCC`, using other instructions can reduce the length by 1 or 2 bytes. For example, the third line instruction `s2b2s rA rB` implicitly includes the operand 0xFF in the opcode, reducing the instruction length.

[0071] b. Array member access instructions using 4-bit register format, as shown in Table 9.

[0072] Table 9

[0073]

[0074] As shown in Table 9, instructions using 4-bit register format are one byte shorter than instructions using 8-bit register. For frequently occurring instructions (such as getarray-o), using 4-bit register can significantly reduce the length of the bytecode.

[0075] c. Array creation instructions that implicitly embed the member type of array members into the opcode, as shown in Table 10.

[0076] Table 10

[0077]

[0078] As shown in Table 10, the first instruction, newarray-b rA rB, is more commonly used. It implies the member type (bytes) of the array members in the opcode, which can reduce the number of bytes by 1 or 2 compared to the other two instructions.

[0079] d. Branch instructions with various instruction formats based on the results of equality and inequality comparisons, including branch instructions that compare with a value of 0, as shown in Table 11, and branch instructions that compare two operands, as shown in Table 12.

[0080] Table 11

[0081]

[0082] Table 12

[0083]

[0084] In Table 12 above, instructions using an 8-bit offset can reduce the length by one byte.

[0085] The simplified instruction set of this invention also includes third instructions, which include instructions with different instruction formats based on different numbers of parameters. The third instructions include:

[0086] a. Static method call instructions with different instruction formats based on different numbers of parameters, as shown in Table 13.

[0087] b. Virtual method call instructions with different instruction formats based on different numbers of parameters, as shown in Table 14.

[0088] c. Private instance method call instructions with different instruction formats based on different numbers of parameters.

[0089] Table 13

[0090]

[0091] Table 14

[0092]

[0093] As shown in Table 13-14, for method calls with no parameters or few parameters, the above encoding instructions are shorter, especially since such calls are frequently used, which can significantly reduce the bytecode size of the method.

[0094] The simplified instruction set of this invention also includes a fourth instruction, which includes instructions for commonly used data types and instructions for less commonly used data types. Instructions for commonly used data types have multiple instruction formats, while instructions for less commonly used data types have one instruction format. Instructions for commonly used data types include instructions for the short data type, and instructions for less commonly used data types include instructions for the int data type.

[0095] The simplified instruction set of this invention also includes a fifth instruction, which is an instruction with a single-byte constant pool index. The fifth instruction includes:

[0096] a. Static method call instructions with single-byte constant pool indexes, as shown in Table 15.

[0097] b. Virtual method call instructions with single-byte constant pool indexes, as shown in Table 16.

[0098] c. Static field access instructions with single-byte constant pool indexes, as shown in Table 17.

[0099] d. Instance field access instructions with single-byte constant pool indexes, as shown in Table 18.

[0100] Table 15

[0101]

[0102] Table 16

[0103]

[0104] Table 17

[0105]

[0106] Table 18

[0107]

[0108] As shown in Tables 15-18, if a single-byte constant pool index can be used, the length of the bytecode can be significantly reduced.

[0109] The simplified instruction set of this invention also includes a sixth instruction, which is a macro instruction. The sixth instruction includes macro instructions formed by static method call instruction substitution and macro instructions formed by merging multiple adjacent instructions, as shown in Table 19.

[0110]

[0111]

[0112]

[0113] As shown in Table 19, macro instructions that replace static methods do not require a constant pool index. Since such static methods are called frequently, replacing them with corresponding macro instructions can significantly reduce the size of the bytecode.

[0114] The TGoMOS virtual machine instruction set of this invention (the simplified instruction set of this invention) is shown in Table 20 below as a general table of bytecode instruction sets.

[0115] Table 20

[0116]

[0117]

[0118]

[0119] This invention also provides a resource-constrained device on which a virtual machine runs, the virtual machine being used to execute the aforementioned reduced instruction set.

[0120] The register-based virtual machine instruction set designed in this invention is used in resource-constrained devices such as intelligent SE and secure MCU chips. It enables various object-oriented and architecture-neutral programs to minimize the size of bytecode, thereby reducing the chip's persistent storage requirements and improving code execution efficiency.

[0121] To verify the aforementioned beneficial effects of the simplified instruction set of this invention, we compared the Java Card instruction set and the TGoMOS instruction set (the simplified instruction set of this invention). In virtual machine systems implemented on the same chip, except for the bytecode interpreter code, the other code was essentially identical. Time-consuming cryptographic algorithms and Flash write operations in the commands were disabled. The average time of 10 executions was compared to obtain the comparison results. Table 21 shows the comparison results of the bytecode sizes converted from the Java Card instruction set and the TGoMOS instruction set. Table 22 shows the performance comparison results of the EDEP e-wallet application on the Java Card and TGoMOS platforms.

[0122] Table 21

[0123]

[0124] Table 22

[0125]

[0126] As shown in Table 21, the bytecode size of the TGoMOS instruction set (the simplified instruction set of this invention) is close to that of the Java Card instruction set. As shown in Table 22, the performance of running the EDEP e-wallet on the TGoMOS virtual machine instruction set platform is better.

[0127] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention is also intended to include these modifications and variations.

Claims

1. A resource-constrained device, characterized in that, The resource-constrained device runs a virtual machine, which executes a reduced instruction set (RISC) that is a register-based virtual machine instruction set. The RISC includes: The first instruction consists of an opcode, the opcode implicitly containing parameter information of the first instruction, the parameter information including register number and / or constant operand; The second instruction is a high-frequency instruction with multiple instruction formats, including register addressing formats with different bit widths, in order to reduce the bytecode size by shortening the bit width of the register number. The third instruction includes instructions with different instruction formats based on different numbers of parameters; The fourth instruction includes instructions for commonly used data types and instructions for less commonly used data types. The instructions for commonly used data types have multiple instruction formats, while the instructions for less commonly used data types have one instruction format. The fifth instruction is an instruction with a single-byte constant pool index; The sixth instruction is a macro instruction.

2. The resource-constrained device according to claim 1, characterized in that, The first instruction includes: Instructions that implicitly include operand and register numbers in their opcodes; Instructions that embed register numbers into their opcodes; Instructions that implicitly include constant operands in the opcode; Array member access instructions that implicitly include the member type of array members in the opcode; Instructions that implicitly specify the type and parameters of a method call within the opcode.

3. The resource-constrained device according to claim 1, characterized in that, The second instruction includes: Commonly used arithmetic operation commands with multiple operation formats; Array member access instructions using 4-bit register format; An array creation instruction that implicitly includes the member type of array members in the opcode; Branch instructions with multiple instruction formats are based on the results of equality and inequality comparisons.

4. The resource-constrained device according to claim 1, characterized in that, The third instruction includes: Static method call instructions with different instruction formats exist based on the number of parameters. Virtual method call instructions have different instruction formats depending on the number of parameters; Private instance method invocation instructions have different instruction formats depending on the number of parameters.

5. The resource-constrained device according to claim 1, characterized in that, The fourth instruction includes: Commands for commonly used data types include those for the short data type; Instructions for less commonly used data types include those for the int data type.

6. The resource-constrained device according to claim 1, characterized in that, The fifth instruction includes: A static method call instruction with a single-byte constant pool index; Virtual method invocation instructions with a single-byte constant pool index; Static field access instructions with a single-byte constant pool index; Instance field access instructions with a single-byte constant pool index.

7. The resource-constrained device according to claim 1, characterized in that, The sixth instruction includes: Macro instructions generated based on static method call instruction replacement; Macro instructions are formed by merging multiple adjacent instructions.

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