A diode and a method for manufacturing the same

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a diode and a method for making the same, wherein the diode comprises an N substrate, an active region P+ layer and a plurality of MOS structures, wherein an active region P+ layer is formed on the N substrate, a plurality of MOS structures are arranged in the active region P+ layer, an anode metal is arranged on the active region P+ layer, and the MOS structure comprises a groove, a gate oxide layer and polysilicon are formed in the groove, an N+ layer electrically connected to the anode metal is arranged outside the groove, an insulating dielectric layer is arranged on the groove to separate the polysilicon and the anode metal, and when the reverse voltage applied to the diode increases, the polysilicon applies a turn-on voltage, a conductive channel is formed outside the groove, the conductive channel is connected to the space charge region in the diode, and a reverse current is formed in the diode. The present invention provides a diode that can have a specific reverse current capability within a certain reverse voltage range, and the avalanche withstand capability of the diode far exceeds that of an ordinary diode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a diode and a manufacturing method thereof. Background Art

[0002] In electronic circuits, diodes are widely used, and choosing the right diode is very important for the entire electronic circuit system. Diodes often encounter situations where the peak voltage exceeds the breakdown voltage of the diode, causing the diode to avalanche breakdown, the current suddenly increases, and the avalanche current can increase to infinity. In addition, ordinary diode avalanches generally occur in local areas of the terminal. Due to the large avalanche current flowing through, the temperature of the local area rises, which sometimes causes thermal damage to the diode.

[0003] Therefore, choosing a suitable diode requires that the diode can withstand the current in the circuit and meet a certain avalanche tolerance. Avalanche tolerance means that when a large reverse decay bias is applied to the junction of the semiconductor, the flow of the electric field decay current will cause avalanche decay. At this time, the energy that the diode element can absorb is called avalanche tolerance, which indicates the ability to resist breakdown when voltage is applied. However, current diodes directly undergo avalanche breakdown when the reverse voltage is large, and their avalanche tolerance is weak, resulting in failure to meet the use requirements in many circuits. Summary of the invention

[0004] The present invention solves the technical problem of weak avalanche withstand capability of diodes in the prior art and proposes a diode and a manufacturing method thereof. The diode can have a specific reverse current capability within a certain reverse voltage range and the avalanche withstand capability of the diode far exceeds that of ordinary diodes.

[0005] The technical solution of the present invention:

[0006] A diode, comprising:

[0007] An N substrate, on which an active region P+ layer is formed;

[0008] An active region P+ layer, wherein a plurality of MOS structures are arranged in the active region P+ layer, and an anode metal is arranged on the active region P+ layer;

[0009] A plurality of MOS structures are provided, wherein the MOS structure comprises a groove, a gate oxide layer and polysilicon are formed in the groove, an N+ layer electrically connected to an anode metal is provided outside the sidewall of the groove, an insulating dielectric layer is provided on the groove to separate the polysilicon from the anode metal, when the reverse voltage applied to the diode increases, a turn-on voltage is applied to the polysilicon, a conductive channel is formed outside the groove, the conductive channel is connected to a space charge region in the diode, and a reverse current is formed in the diode.

[0010] Optionally, the diode further includes a P+ field ring, the polysilicon extends out of the trench and is electrically connected to the P+ field ring, and field oxygen is provided between the extended portion of the polysilicon and the N substrate and the active region P+ layer.

[0011] Furthermore, there are multiple P+ field rings, and the polysilicon is electrically connected to one or more of the P+ field rings.

[0012] Optionally, the polysilicon extends out of the trench, a metal layer is provided on the extended portion of the polysilicon to be electrically connected to an external circuit, and field oxygen is provided between the extended portion of the polysilicon and the N substrate and the active area P+ layer.

[0013] Furthermore, a first end of the extension part of the polysilicon is provided with the insulating dielectric layer to be separated from the anode metal, and a second end of the extension part of the polysilicon is provided with a protective layer to wrap the extension part of the polysilicon.

[0014] Optionally, the diode further includes an internal P+ ring junction, the polysilicon extension is electrically connected to the internal P+ ring junction, and field oxygen is provided between the extended portion of the polysilicon and the N substrate and the active region P+ layer.

[0015] Furthermore, there are multiple P+ layers in the active area, and the polysilicon in multiple MOS structures in the multiple P+ layers in the active area are all extended to be electrically connected to the internal P+ ring junction.

[0016] Another aspect of the present invention provides a method for manufacturing a diode, firstly growing a layer of field oxide on an N substrate and etching an active area, and further comprising the following steps:

[0017] Using photolithography and etching processes, photolithography defines the groove area, and etching is performed to form the groove;

[0018] Using a thermal oxidation process, a layer of oxide layer is grown on the surface of the groove by thermal oxidation to form a gate oxide layer;

[0019] A deposition process is adopted to deposit a layer of polysilicon on the gate oxide layer to fill the groove, and an extension of the polysilicon is deposited on the field oxide, and the extension of the polysilicon is connected to a P+ field ring or a metal layer electrically connected to an external circuit or an internal P+ ring junction.

[0020] Furthermore, the method for manufacturing the diode further comprises the following steps:

[0021] Using photolithography and etching processes, different polysilicon areas are defined by photolithography, and unnecessary polysilicon is etched away;

[0022] Photolithography, ion implantation and annealing processes are used to define the active area P+ layer area to be implanted, and boron ions are implanted and annealed to form the active area P+ layer;

[0023] Photolithography, ion implantation and annealing processes are used to define the N+ area to be implanted, and arsenic or phosphorus ions are implanted and annealed to form an N+ layer.

[0024] Using a deposition process, a layer of insulating dielectric layer is deposited on the surface of the polysilicon to serve as electrical isolation between the polysilicon and the anode metal;

[0025] Using photolithography and etching processes, the contact hole layer is defined by photolithography, and the unnecessary insulating dielectric layer is etched away;

[0026] Using a deposition process, a layer of metal is deposited on the insulating dielectric layer and the active area P+ layer;

[0027] Photolithography and etching processes are used to define the anode metal layer domain by photolithography, and then etching is performed to form the anode metal electrode of the device.

[0028] Preferably, the method for manufacturing the diode further comprises the following steps:

[0029] Using an epitaxial process, an N-epitaxial layer of a desired thickness is grown on the surface of the N substrate to form an N matrix;

[0030] Using a thermal oxidation process, an oxide layer is grown on the surface of the N-epitaxial layer by thermal oxidation to form field oxide;

[0031] The photolithography and etching processes are used to define the active area by photolithography, and then field oxygen etching is performed to form the active area.

[0032] After adopting the above technical scheme, the present invention has the following beneficial effects compared with the prior art: the present invention adds multiple MOS structures to the active area P+ layer of the diode, and grows a gate oxide layer and polysilicon in the groove of the MOS structure. The polysilicon is connected to the terminal or the high-voltage area through the surface, so that an inversion layer electronic conductive channel is formed between the gate oxide layer and the active area P+ layer in the groove. When the reverse voltage increases, the space charge layer of the active area P+ layer will gradually expand toward the groove. When the space charge layer expands to the vicinity of the groove, the electrons in the inversion layer at the groove will flow to the cathode of the diode under the action of the electric field to form a reverse current. This diode can have a specific reverse current capability within a certain reverse voltage range, and its reverse current capability far exceeds the avalanche current capability of ordinary diodes. The avalanche tolerance capability of this diode far exceeds that of ordinary diodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the structure of a diode in the prior art;

[0034] Figure 2 It is a schematic diagram of the structure of the diode in Embodiment 1 and Embodiment 3;

[0035] Figure 3 The diode in the first embodiment Figure 2 Schematic diagram of the structure cut along the YY direction;

[0036] Figure 4 A schematic diagram showing the relationship between the reverse voltage and current of the diode of the present invention;

[0037] Figure 5 The diode edge in the third embodiment Figure 2 Schematic diagram of the structure cut along the YY direction;

[0038] Figure 6 It is a partial structural schematic diagram of the diode in the fourth embodiment;

[0039] Figure 7 This is a schematic diagram of the connection of polysilicon in the fourth embodiment;

[0040] Figure 8 The diode edge in the fourth embodiment Figure 6 Schematic diagram of the structure cut along the YY direction.

[0041] in,

[0042] N base 1, N substrate 11, N- epitaxial layer 12, active area P+ layer 2, mos structure 21, trench 211, gate oxide layer 212, polysilicon 213, extension part 2131, N+ layer 214, insulating dielectric layer 3, protective layer 31, anode metal 4, P+ field ring 5, metal layer 6, internal P+ ring junction 7, field oxygen 8. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0045] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0046] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0047] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0048] The purpose of the present invention is to provide a diode with high reverse current tolerance, in which grooves and N+ layers are added to the active region P+ layer, and a gate oxide layer and polysilicon are grown in the groove. The polysilicon is connected to the terminal or high voltage region through the surface, so that an inversion layer electron conductive channel is formed between the gate oxide layer in the groove and the active region P+ layer. When the reverse voltage increases, the space charge layer of the active region P+ layer will gradually expand toward the groove. When the space charge layer expands to the vicinity of the groove, the electrons in the inversion layer at the groove will flow to the cathode of the diode under the action of the electric field to form a reverse current. This diode can have a specific reverse current capability within a certain reverse voltage range, and its reverse current capability can far exceed the avalanche current capability of ordinary diodes. The structure of the diode and its manufacturing method are described in detail below through specific embodiments.

[0049] Embodiment 1:

[0050] like Figure 1 As shown, the diode in the prior art includes an N substrate 1 and an active region P+ layer 2 formed on the N substrate 1, an anode metal 4 is formed on the active region P+ layer 2, and when a small reverse voltage is applied, the reverse current is small and almost zero. When the reverse voltage increases to the reverse breakdown voltage, the current increases sharply and an avalanche breakdown occurs.

[0051] like Figure 2 As shown, the diode of this embodiment includes an N substrate 1 and an active region P+ layer 2 formed on the N substrate 1, and an anode metal 4 is provided on the active region P+ layer 2. Here, the N substrate 1 includes an N substrate 11 and an N- epitaxial layer 12 formed epitaxially on the N substrate 11, and the whole is formed into a PiN diode structure. Further, a plurality of mos structures 21 are provided in the active region P+ layer 2, and each mos structure 21 includes a groove 211, a gate oxide layer 212, polysilicon 213 and an N+ layer 214. Specifically, the bottom of the groove 211 is higher than the bottom of the active region P+ layer 2, a gate oxide layer 212 is formed in the groove 211, and polysilicon 213 is filled in the gate oxide layer 212. N+ layers 214 electrically connected to the anode metal 4 are provided on both sides of the sidewalls of the groove 211, and an insulating dielectric layer 3 is provided on the groove 211 to separate the polysilicon 213 and the anode metal 4.

[0052] Furthermore, the diode of this embodiment further includes a P+ field ring 5, such as Figure 3 As shown, the polysilicon 213 first extends upward along the side wall of the trench 211, and then extends outside the trench 211 to be electrically connected to the terminal P+ field ring 5. The extended portion 2131 of the polysilicon 213 is separated from the N substrate 1 and the active area P+ layer 2 by the field oxide 8.

[0053] In this way, when the reverse voltage applied to the diode gradually increases, the space charge region gradually expands. When the space charge region expands to the P+ field ring 5, the P+ field ring 5 forms a high potential. Since the P+ field ring 5 is connected to the polysilicon 213 in the groove 211, it is equivalent to applying a turn-on voltage to the polysilicon 213, so that a circle of inversion layer, i.e., a conductive channel, is formed outside the groove 211. When the reverse voltage applied to the diode continues to increase, the space charge region continues to expand toward the groove 211. When the space charge region is connected to the inversion layer, the electrons in the inversion layer will flow to the cathode of the diode under the action of the electric field, forming a reverse current.

[0054] Figure 4 The figure shows the relationship between the reverse voltage and the current of the diode of the present embodiment, wherein the horizontal axis is the magnitude of the reverse voltage, the vertical axis is the magnitude of the reverse current, and curves A, B, C, and D are curves at different depths of the groove 211, respectively. Taking curve A as an example, when the reverse voltage is small, such as less than 190V, since the space charge region is also small and does not contact the inversion layer outside the groove 211, the reverse current is very small and almost zero at this time, which can ensure the unidirectional conductivity of the diode; when the reverse voltage increases to 190V, the space charge region begins to contact the inversion layer outside the groove 211, and a reverse current gradually begins to form at this time. When the reverse voltage is in the range of 190V-760V, the diode has a stable reverse current, while the diode in the prior art has a current of almost zero in this voltage range, and is prone to avalanche breakdown under high electric field strength. Obviously, the diode of the present embodiment has a larger reverse current tolerance than the ordinary diode in the prior art, and has a certain reverse current capability within a certain reverse voltage range. The avalanche tolerance capability of this diode far exceeds that of the ordinary diode.

[0055] like Figure 4 As shown, the depth of the groove 211 corresponding to the curves A, B, C, and D gradually decreases, that is, the deeper the depth of the groove 211, the smaller the reverse voltage required to be applied for the diode to form a specific reverse current. In this way, the voltage range for forming a specific reverse current can be adjusted by adjusting the depth of the groove 211 to meet different circuit requirements.

[0056] Furthermore, the magnitude of the specific reverse current is related to the density of the MOS structure 21 in the diode and the potential of the polysilicon 213. The density of the MOS structure 21 in the active region P+ layer 2 and the potential of the polysilicon 213 can be designed according to the reverse current requirement. Among them, multiple MOS structures 21 can be evenly distributed in the active region P+ layer 2 of the diode, and the potential of the polysilicon 213 can connect it with different P+ field rings 5 ​​in the diode. Specifically, there are generally multiple P+ field rings 5 ​​in the diode, and the P+ field rings 5 ​​at different positions have different potentials when the reverse voltage of the diode increases. Therefore, the potential of the polysilicon 213 can be changed by electrically connecting the polysilicon 213 to one or more P+ field rings 5 ​​at different positions.

[0057] In addition, it should be noted that the present embodiment can be implemented in a silicon-based PiN diode device, and can also be implemented in a silicon-based Schottky diode device with an active region P+ layer. Similarly, the present embodiment can be implemented in a silicon carbide-based PiN diode device, and can also be implemented in a silicon carbide-based Schottky diode device with an active region P+ layer. In other words, the structure of the diode of the present embodiment is applicable to any diode device with an active region P+ layer.

[0058] It can be seen from the above content that the diode provided in this embodiment can have a specific reverse current capability within a certain reverse voltage range, and the avalanche withstand capability of the diode far exceeds that of ordinary diodes.

[0059] Embodiment 2:

[0060] This embodiment provides a method for manufacturing the diode of Embodiment 1, which specifically includes the following steps:

[0061] S1: using an epitaxial process, epitaxially growing an N-epitaxial layer 12 of a desired thickness on the surface of the N substrate 11 to form an N matrix 1;

[0062] S2: using a thermal oxidation process, a layer of oxide is grown on the surface of the N-epitaxial layer 12 by thermal oxidation to form a field oxide 8;

[0063] S3: using photolithography and etching processes, photolithography defines the active area, and performs field oxide 8 etching to form the active area;

[0064] S4: using photolithography and etching processes, photolithography defines the groove 211 region, and etching is performed to form the groove 211;

[0065] S5: using a thermal oxidation process to grow an oxide layer on the surface of the trench 211 by thermal oxidation to form a gate oxide layer 212;

[0066] S6: using a deposition process, depositing a layer of polysilicon 213 on the gate oxide layer 212 to fill the trench 211, and depositing an extension portion 2131 of the polysilicon 213 on the field oxide 8, and connecting the extension portion 2131 of the polysilicon 213 to the P+ field ring 5;

[0067] S7: using photolithography and etching processes, photolithography defines different polysilicon 213 regions, and etches away unnecessary polysilicon 213;

[0068] S8: using photolithography, ion implantation and annealing processes, photolithography defines the active region P+ layer 2 region to be implanted, implants boron ions and performs annealing to form the active region P+ layer 2;

[0069] S9: using photolithography, ion implantation and annealing processes, photolithography defines the N+ region to be implanted, implants arsenic ions or phosphorus ions and performs annealing to form an N+ layer 214;

[0070] S10: using a deposition process, depositing an insulating dielectric layer 3 on the surface of the polysilicon 213 to serve as electrical isolation between the polysilicon 213 and the anode metal 4;

[0071] S11: using photolithography and etching processes, photolithography defines a contact hole layer, and etches away unnecessary insulating dielectric layer 3;

[0072] S12: using a deposition process, depositing a layer of metal on the insulating dielectric layer 3 and the active region P+ layer 2;

[0073] S13: Photolithography and etching processes are used to photolithographically define the anode metal 4 layer domain, and etching is performed to form the anode metal 4 electrode of the device.

[0074] Embodiment three:

[0075] The difference between the diode of this embodiment and the first embodiment is that the polysilicon 213 of this embodiment is connected to an external circuit and obtains a turn-on voltage through the external circuit. Specifically, Figure 5 As shown, the polysilicon 213 extends out of the trench 211 , and a metal layer 6 is disposed on the extended portion 2131 of the polysilicon 213 to be electrically connected to an external circuit, and the extended portion 2131 of the polysilicon 213 is separated from the N substrate 1 and the active region P+ layer 2 by a field oxide 8 .

[0076] Furthermore, the first end of the extension portion 2131 of the polysilicon 213 is provided with an insulating dielectric layer 3 to separate it from the anode metal 4 , and the second end of the extension portion 2131 of the polysilicon 213 is provided with an insulating protective layer 31 to wrap the polysilicon 213 , and the polysilicon 213 is protected by the protective layer 31 .

[0077] Furthermore, the manufacturing method of the diode of this embodiment is different from that of the second embodiment in that in the manufacturing step S6 of the diode of this embodiment, a deposition process is adopted to deposit a layer of polysilicon 213 on the gate oxide layer 212 to fill the groove 211, and an extension portion 2131 of the polysilicon 213 is deposited on the field oxide 8, and the extension portion 2131 of the polysilicon 213 is connected to the metal layer 6 electrically connected to the external circuit.

[0078] Embodiment 4:

[0079] The difference between the diode of this embodiment and the first embodiment is that the polysilicon 213 of this embodiment is connected to the internal P+ ring junction 7 of the diode. Specifically, Figure 6-8 As shown, the diode of this embodiment also includes an internal P+ ring junction 7, the polysilicon 213 is extended and electrically connected to the internal P+ ring junction 7, and a field oxide 8 is provided between the extended portion 2131 of the polysilicon 213 and the N substrate 1 and the active area P+ layer 2. When the reverse voltage applied to the diode increases, the internal P+ ring junction 7 reaches a high level, thereby forming an inversion layer outside the groove 211.

[0080] Furthermore, if Figure 6-7 As shown, in the diode of this embodiment, there are multiple active region P+ layers 2, and multiple MOS structures 21 are arranged in each active region P+ layer 2. The polysilicon 213 in these MOS structures 21 is arranged in Figure 7 The cross-sectional structure shown extends to be electrically connected to the internal P+ ring junction 7, Figure 7 The cross section shown is Figure 6 The cross section in the figure is parallel, so that after the reverse voltage of the polysilicon 213 in each mos structure 21 increases, the internal P+ ring junction 7 is at a high level, and the polysilicon 213 of each mos structure 21 is also at a high level, thereby forming an inversion layer outside the trench 211 of each mos structure 21. And, as Figure 8 As shown, an N+ layer 214 may also be disposed on the outer sidewall of the trench 211 where the polysilicon 213 is located, thereby increasing the width of the conductive channel.

[0081] Furthermore, the difference between the method for manufacturing the diode of this embodiment and that of the second embodiment is that in this embodiment, in step S6, a deposition process is used to deposit a layer of polysilicon 213 on the gate oxide layer 212 to fill the groove 211, and an extension portion 2131 of the polysilicon 213 is deposited on the field oxide 8, and each extension portion 2131 of the polysilicon 213 is connected to the internal P+ ring junction 7.

[0082] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A diode, characterized in that: include: An N substrate (1), wherein an active region P+ layer (2) is formed on the N substrate (1); A plurality of MOS structures (21) are provided in the active region P+ layer (2), and an anode metal (4) is provided on the active region P+ layer (2); The MOS structure (21) comprises a groove (211), a gate oxide layer (212) and polysilicon (213) are formed in the groove (211), an N+ layer (214) electrically connected to an anode metal (4) is provided outside the side wall of the groove (211), an insulating dielectric layer (3) is provided on the groove (211) to separate the polysilicon (213) and the anode metal (4), the polysilicon (213) extends outside the groove (211) to be electrically connected to a P+ field ring (5), and a field oxygen (8) is provided between an extended portion (2131) of the polysilicon (213), the N substrate (1) and the active region P+ layer (2); Alternatively, the polysilicon (213) extends outward from the groove (211), a metal layer (6) is provided on the extended portion (2131) of the polysilicon (213) to be electrically connected to an external circuit, and a field oxide (8) is provided between the extended portion (2131) of the polysilicon (213) and the N substrate (1) and the active region P+ layer (2); Or, the diode further comprises an internal P+ ring junction (7), the polysilicon (213) is extended and electrically connected to the internal P+ ring junction (7), and a field oxygen (8) is provided between the extended portion (2131) of the polysilicon (213), the N substrate (1) and the active region P+ layer (2); When the reverse voltage applied to the diode increases, the polysilicon (213) applies a turn-on voltage, a conductive channel is formed outside the groove (211), the conductive channel is connected to the space charge region in the diode, and a reverse current is formed in the diode.

2. The diode according to claim 1, characterized in that There are a plurality of P+ field rings (5), and the polysilicon (213) is electrically connected to one or more of the P+ field rings (5).

3. The diode according to claim 1, characterized in that The first end of the extension part (2131) of the polycrystalline silicon (213) is provided with the insulating dielectric layer (3) to separate it from the anode metal (4), and the second end of the extension part (2131) of the polycrystalline silicon (213) is provided with a protective layer (31) to wrap the extension part (2131) of the polycrystalline silicon (213).

4. The diode according to claim 1, characterized in that There are multiple active region P+ layers (2), and the polysilicon (213) in multiple MOS structures (21) in the multiple active region P+ layers (2) are all extended to be electrically connected to the internal P+ ring junction (7).

5. A method for manufacturing a diode according to any one of claims 1 to 4, wherein a layer of field oxide (8) is grown on an N substrate (1), and an active region is etched out, characterized in that: The following steps are involved: Using photolithography and etching processes, photolithography defines the groove (211) area, and etching is performed to form the groove (211); Using a thermal oxidation process, a layer of oxide is grown on the surface of the groove (211) by thermal oxidation to form a gate oxide layer (212); Using a deposition process, a layer of polysilicon (213) is deposited on the gate oxide layer (212) to fill the trench (211), and an extension portion (2131) of the polysilicon (213) is deposited on the field oxide (8), and the extension portion (2131) of the polysilicon (213) is connected to a P+ field ring (5) or a metal layer (6) electrically connected to an external circuit or an internal P+ ring junction (7); The following steps are also included: Using photolithography and etching processes, photolithography defines different polysilicon (213) regions, and etches away unnecessary polysilicon (213); Using photolithography, ion implantation and annealing processes, photolithography defines the active region P+ layer (2) region to be implanted, implants boron ions and performs annealing to form the active region P+ layer (2); Using photolithography, ion implantation and annealing processes, photolithography defines the N+ region to be implanted, implants arsenic ions or phosphorus ions and performs annealing to form an N+ layer (214); Using a deposition process, a layer of insulating dielectric layer (3) is deposited on the surface of the polysilicon (213) to serve as electrical isolation between the polysilicon (213) and the anode metal (4); Using photolithography and etching processes, the contact hole layer is defined by photolithography, and the unnecessary insulating dielectric layer is etched away (3); Using a deposition process, a layer of metal is deposited on the insulating dielectric layer (3) and the active region P+ layer (2); Photolithography and etching processes are used to photolithographically define the anode metal (4) layer domain, and etching is performed to form the anode metal (4) electrode of the device.

6. The method for manufacturing a diode according to claim 5, characterized in that: The following steps are also included: Using an epitaxial process, an N-epitaxial layer (12) of a desired thickness is epitaxially grown on the surface of an N substrate (11) to form an N matrix (1); Using a thermal oxidation process, an oxide layer is grown on the surface of the N-epitaxial layer (12) by thermal oxidation to form a field oxide (8); The photolithography and etching process is adopted to define the active area by photolithography, and then the field oxide (8) is etched to form the active area.

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