Image sensor equipment

Abstract

An image sensor device includes: a first digital pixel, including a first photodetector and a first storage unit, the first storage unit is used to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel, including a second photodetector and a second storage unit, the second storage unit is used to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel is adjacent to one side of the first digital pixel, the first storage unit and the second storage unit are connected to a plurality of bit lines, the first storage unit is connected to a first word line and a third word line, the second storage unit is connected to a second word line and a fourth word line, the second word line is between the first word line and the third word line, and the third word line is between the second word line and the fourth word line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0117504 filed in the Korean Intellectual Property Office on September 24, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to semiconductor devices, and more particularly, to image sensor devices. Background Art

[0004] An image sensor is a sensor that detects and transmits information to form an image. It does this by converting light signals into electrical signals. With the development of the computer and communications industries, there is a growing demand for high-performance image sensors in various electronic devices such as digital cameras, camcorders, smartphones, tablet personal computers (PCs), laptops, game consoles, security cameras, and medical miniature cameras.

[0005] Conventional image sensors include analog pixels. The analog pixels output light signals as analog signals, and the analog signals are converted into digital signals. However, analog signals are easily affected by noise or coupling, and may not be able to process high-resolution image signals well. Summary of the invention

[0006] According to an exemplary embodiment of the present invention, an image sensor device includes: a first digital pixel, including a first photodetector and a first storage unit, the first storage unit being configured to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel, including a second photodetector and a second storage unit, the second storage unit being configured to store a second digital signal corresponding to a second output from the second photodetector, wherein the second digital pixel is adjacent to a side of the first digital pixel along a first direction, wherein the first storage unit and the second storage unit are connected to a plurality of bit lines, wherein the first storage unit is connected to a first word line and a third word line, wherein the second storage unit is connected to a second word line and a fourth word line, wherein the second word line is between the first word line and the third word line, and wherein the third word line is between the second word line and the fourth word line.

[0007] According to an exemplary embodiment of the inventive concept, an image sensor device includes: a first digital pixel including a first photodetector and a first storage unit, the first storage unit being configured to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and a second storage unit, the second storage unit being configured to store a second digital signal corresponding to a second output from the second photodetector, wherein the second digital pixel is adjacent to a first side of the first digital pixel along a first direction, wherein the first storage unit and the second storage unit are formed on a first semiconductor wafer, wherein the first semiconductor wafer includes: a first region including the first storage unit; a second region including the second storage unit, wherein the second region is adjacent to the first region along the first direction; a first shared dummy pattern region between a first side of the first region and a first side of the second region; a first dummy pattern region adjacent to a second side of the first region opposite to the first side of the first region; and a second dummy pattern region adjacent to a second side of the second region opposite to the first side of the second region, and wherein a first width of the first shared dummy pattern region in the first direction is less than twice a second width of the first dummy pattern region in the first direction or twice a third width of the second dummy pattern region in the second direction.

[0008] According to an exemplary embodiment of the present invention, an image sensor device includes: a first digital pixel, including a first photodetector and a first storage unit, the first storage unit being configured to store a first digital signal corresponding to a first detection signal from the first photodetector; and a second digital pixel, including a second photodetector and a second storage unit, the second storage unit being configured to store a second digital signal corresponding to a second detection signal from the second photodetector, the second digital pixel being adjacent to the first digital pixel along a first direction, and the first storage unit and the second storage unit being included in a single storage cell array.

[0009] According to an exemplary embodiment of the present invention, an image sensor device includes: a first digital pixel, including a first photodetector and a first storage unit, the first storage unit being configured to store a first digital signal corresponding to a first detection signal from the first photodetector; and a second digital pixel, including a second photodetector and a second storage unit, the second storage unit being configured to store a second digital signal corresponding to a second detection signal from the second photodetector, wherein the second digital pixel is adjacent to the first digital pixel along a first direction, wherein a dummy storage unit is arranged between the first storage unit and the second storage unit, and wherein the dummy storage unit, the first storage unit and the second storage unit are included in a single storage cell array. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present inventive concept will become apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0011] Figure 1 is a block diagram illustrating an image sensor device according to an exemplary embodiment of the inventive concept.

[0012] Figure 2A It shows Figure 1 Block diagram of a pixel driver.

[0013] Figure 2B It shows Figure 1 Block diagram of a digital logic circuit.

[0014] Figure 3A , Figure 3B , Figure 3C and Figure 3D Is used to describe Figure 1 Schematic diagram of a digital pixel.

[0015] Figure 4A and Figure 4B It shows Figure 1 Schematic diagram of the configuration of the pixel array.

[0016] Figure 5A , Figure 5B and Figure 5C It shows that the Figure 4A FIG. 1 is a plan view of a schematic layout of an upper wafer and a lower wafer in a pixel array.

[0017] Figure 6 It shows Figure 4A A plan view of the layout of the upper and lower wafers of the pixel array is shown.

[0018] Fig. 7A It shows Figure 6A plan view of the layout of the memory cell area is shown.

[0019] Figure 7B It shows that the application Fig. 7A A plan view of the lower wafer of the memory cell area.

[0020] Figure 8 It shows Figure 6 A floor plan of the layout of the storage unit area.

[0021] Fig. 9 It shows that the Figure 1 Schematic diagram of the structure of a digital pixel shared comparator in a pixel array.

[0022] Fig. 10A and Fig. 10B It shows Figure 4A A plan view of the layout of the lower wafer and memory cell area.

[0023] Fig.11A and Fig. 11B It shows Figure 4A A plan view of the layout of the lower wafer and memory cell area.

[0024] Fig.12 is a plan view illustrating a memory cell region according to an exemplary embodiment of the inventive concept.

[0025] Fig.13 is a plan view illustrating a memory cell region according to an exemplary embodiment of the inventive concept.

[0026] Fig.14A and Fig. 14B is a plan view illustrating a layout of a lower wafer and a memory cell region according to an exemplary embodiment of the inventive concept.

[0027] Fig.15A and Fig. 15B is a plan view illustrating a layout of an upper wafer and a lower wafer of an image sensor device according to an exemplary embodiment of the inventive concept.

[0028] Fig.16A It shows Figure 1 A perspective view of an image sensor device.

[0029] Fig. 16B It shows Figure 1 A plan view of an image sensor device.

[0030] Fig.17 is a block diagram illustrating an electronic device to which an image sensor device according to an exemplary embodiment of the inventive concept is applied. DETAILED DESCRIPTION

[0031] Exemplary embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram illustrating an image sensor device according to an exemplary embodiment of the inventive concept. Figure 1 , the image sensor device 100 may include a pixel array 110, a pixel driver 120, and a digital logic circuit 130. In an exemplary embodiment of the present inventive concept, the image sensor device 100 may be a camera module included in various electronic devices such as a closed-circuit television (CCTV), a black box, a digital camera, a smart phone, a tablet personal computer (PC), and a notebook computer.

[0033] In a conventional CMOS image sensor (CIS), image pixels output analog signals based on light signals. The analog signals from CIS-based image pixels are converted into digital signals in columns at separate analog-to-digital converters. In this case, when the analog signals output by the CIS-based image pixels are sent to the analog-to-digital converters, noise or coupling may occur, thereby reducing the quality of the final image.

[0034] The pixel array 110 according to an exemplary embodiment of the inventive concept may include a plurality of digital pixels DP. Each of the digital pixels DP may be configured to sense a light signal from the outside and output a digital signal DOUT corresponding to the sensed light signal.

[0035] For example, the digital pixel DP may include a photodetector PDT, an analog-to-digital converter ADC, and a storage circuit MCT. The photodetector PDT may be configured to convert an optical signal sensed from the outside into an electrical signal, in other words, into an analog signal. The analog-to-digital converter ADC may be configured to convert an analog signal output from the photodetector PDT into a digital signal. The storage circuit MCT may be configured to store a digital signal DOUT converted by the analog-to-digital converter ADC and output the stored digital signal DOUT. Unlike conventional CIS-based image pixels, the digital pixel DP according to an exemplary embodiment of the present invention can output a digital signal DOUT at the pixel level.

[0036] The pixel driver 120 may output various control signals CTRL (e.g., a photodetector control signal, a memory control signal, a ramp signal, and count information) to control the plurality of digital pixels DP included in the pixel array 110. Based on the control signal CTRL from the pixel driver 120, each of the plurality of digital pixels DP may perform a series of pixel operations or image detection operations, such as an operation of detecting a light signal to generate an analog signal, an operation of converting the analog signal into a digital signal, an operation of storing a digital signal, and an operation of outputting the stored digital signal.

[0037] The digital logic circuit 130 may perform digital signal processing on the digital signal DOUT received from the pixel array 110, and may provide a final image signal to an external device (e.g., an image signal processor (ISP) or an application processor (AP)). In an exemplary embodiment of the present inventive concept, the digital logic circuit 130 may provide a driving signal to the pixel driver 120 under the control of the external device. The pixel driver 120 may operate in response to the driving signal.

[0038] As described above, unlike conventional CIS devices, each of the plurality of digital pixels DP can generate and output a digital signal DOUT at the pixel level. This makes it possible to reduce the modification of the digital signal DOUT output from the plurality of digital pixels DP and process the image signal at high speed. In other words, the digital signal DOUT output from the plurality of digital pixels DP is not easily affected by noise or coupling.

[0039] Figure 2A It shows Figure 1 Block diagram of a pixel driver. Figure 1 and Figure 2A , the pixel driver 120 may include a counter 121 , a row driver 122 , a ramp generator 123 , and a voltage generator 124 .

[0040] The counter 121 may sequentially increase or sequentially decrease the value of the code "CODE" in response to a clock (eg, an operation clock or a system clock) during a given time. In other words, the value of the code "CODE" may sequentially change over time.

[0041] The row driver 122 may generate a control signal for controlling each of the plurality of digital pixels DP. For example, the row driver 122 may generate a photodetector control signal CS-PD for controlling a photodetector PDT of each of the plurality of digital pixels DP. The row driver 122 may generate a memory control signal CS-MC for controlling a memory circuit MCT of each of the plurality of digital pixels DP.

[0042] The ramp generator 123 may output a ramp signal VRAMP. The ramp signal VRAMP may be used as a reference signal to compare with an analog signal at a digital pixel DP. In an exemplary embodiment of the inventive concept, the ramp signal VRAMP may be a uniformly increasing or decreasing signal (eg, a signal increasing / decreasing with a single slope).

[0043] The voltage generator 124 may be configured to generate various voltages (eg, a power supply voltage VDDA and a bias voltage VB) used by the image sensor device 100 for operation.

[0044] The photodetector control signal CS-PD, the memory control signal CS-MC, the code “CODE”, and the ramp signal VRAMP may be included in the reference Figure 1 In an exemplary embodiment of the inventive concept, each of the plurality of digital pixels DP included in the pixel array 110 may be based on a control signal CTRL as described by reference. Figure 2A The pixel driver 120 described above operates based on various signals CODE, CS-PD, CS-MC, VRAMP, VDDA, and VB generated therefrom.

[0045] Figure 2B It shows Figure 1 A block diagram of a digital logic circuit. Figure 1 and Figure 2B The digital logic circuit 130 includes a sensor controller 131 , a digital signal processing unit 132 , and an input / output interface 133 .

[0046] The sensor controller 131 may be configured to control the overall operation of the image sensor device 100. For example, the sensor controller 131 may control the overall operation of the image sensor device 100 based on control information CI provided by an external device (e.g., an ISP or AP) through the input / output interface 133. The sensor controller 131 may be a timing controller for controlling the operation timing of the pixel driver 120. In an exemplary embodiment of the inventive concept, the pixel driver 120 may generate the above-mentioned various signals based on the timing signal from the sensor controller 131.

[0047] The digital signal processing unit 132 may receive the digital signal DOUT from the pixel array 110 and may perform digital signal processing on the received digital signal DOUT.

[0048] In an exemplary embodiment of the inventive concept, the digital signal DOUT output from one digital pixel DP may include a reset sampling value and a signal sampling value. The digital signal processing unit 132 may determine a final digital value corresponding to a light signal sensed by one digital pixel DP by performing an arithmetic operation on the reset sampling value and the signal sampling value.

[0049] The final image data IMG may be generated by combining the final digital signals respectively determined by the plurality of digital pixels DP. In other words, a correlated double sampling (CDS) operation may be implemented by the digital signal DOUT, wherein the digital signal DOUT is generated by the operation of the comparator or analog-to-digital converter ADC included in the digital pixel DP and the digital signal processing operation of the digital signal processing unit 132 included in the digital logic circuit 130.

[0050] The input / output interface 133 may be configured to receive control information CI from an external device (e.g., an ISP or AP) or output final image data IMG. In an exemplary embodiment of the present invention, the input / output interface 133 may exchange the above information with the external device according to a protocol. In an exemplary embodiment of the present invention, the input / output interface 133 may include a physical layer for supporting the protocol.

[0051] FIG. 3A to FIG. 3D Is used to describe Figure 1 Schematic diagram of a digital pixel of . For the sake of brevity of explanation and convenience of description, one digital pixel DP is described, but the inventive concept is not limited thereto. In addition, in order to easily describe an exemplary embodiment of the inventive concept, the structure or operation of the digital pixel DP will be described with reference to an exemplary circuit diagram or block diagram, but the inventive concept is not limited thereto. For example, the digital pixel DP may be modified in various forms.

[0052] refer to Figure 1 , Figure 2A , Figure 2B as well as FIG. 3A to FIG. 3D , the digital pixel DP may include a photo detector PDT, a comparator COMP, and a storage circuit MCT.

[0053] The photo detector PDT may be configured to output a detection signal DET in response to a photo detector control signal CS-PD from the pixel driver 120. For example, Figure 3BAs shown, the photodetector PDT may include a photodiode PD, a transfer transistor TX, and a reset transistor RX. The photodiode PD may be connected between a ground node and the transfer transistor TX, and may be configured to accumulate photocharges in response to the size of light incident from the outside. The transfer transistor TX may be connected between the floating diffusion node FD and the photodiode PD, and may operate in response to a transfer signal TG. For example, the transfer transistor TX may be configured to transfer the charge accumulated at the photodiode PD to the floating diffusion node FD in response to the transfer signal TG. The reset transistor RX may be connected between the power supply voltage VDDA and the floating diffusion node FD, and may operate in response to a reset signal RG. For example, the reset transistor RX may reset the voltage level of the floating diffusion node FD in response to a reset signal RS. In an exemplary embodiment of the present invention, the photodetector control signal CS-PD may include the transfer signal TG and the reset signal RG described above. In an exemplary embodiment of the present invention, the voltage (e.g., VFD) of the floating diffusion node FD may change depending on the operation of the photodetector PDT, and the change may be output as a detection signal DET.

[0054] The comparator COMP may compare the detection signal DET from the photo detector PDT (or the voltage VFD of the floating diffusion node FD) with the ramp signal VRAMP, and may output a comparison signal COMP-OUT based on the comparison result.

[0055] In an exemplary embodiment of the inventive concept, the comparator COMP may be a low power comparator. Figure 3BAs shown, the comparator COMP may include a first p-type metal oxide semiconductor (PMOS) transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3, and a first n-type metal oxide semiconductor (NMOS) transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. The first PMOS transistor MP1, the first NMOS transistor MN1, and the third NMOS transistor MN3 may be connected in series between a power supply voltage VDDA and a ground voltage GND. The gate of the first PMOS transistor MP1 may be connected to a node between the first PMOS transistor MP1 and the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 may be connected to a floating diffusion node FD and may be configured to receive a detection signal DET. The gate of the third NMOS transistor MN3 may be configured to receive a bias voltage VB. The second PMOS transistor MP2 and the second NMOS transistor MN2 may be connected in series between the power supply voltage VDDA and the ground voltage GND. The gate of the second PMOS transistor MP2 may be connected to the gate of the first PMOS transistor MP1. The gate of the second NMOS transistor MN2 may be configured to receive a ramp signal VRAMP. The third PMOS transistor MP3 and the fourth NMOS transistor MN4 may be connected in series between the power supply voltage VDDA and the ground voltage GND. The gate of the third PMOS transistor MP3 may be connected to a node between the second PMOS transistor MP2 and the second NMOS transistor MN2. The gate of the fourth NMOS transistor MN4 may be configured to receive a bias voltage VB.

[0056] exist Figure 3B In the illustrated comparator COMP, when the detection signal DET is lower than the ramp signal VRAMP, the comparison signal COMP-OUT may have a logic high level; and when the detection signal DET is higher than the ramp signal VRAMP, the comparison signal COMP-OUT may have a logic low level.

[0057] In an exemplary embodiment of the present inventive concept, Figure 3B The structure of the comparator COMP is exemplary, and the inventive concept is not limited thereto. For example, the comparator COMP may have a structure of various comparators or differential amplifiers configured to compare the detection signal DET with the ramp signal VRAMP and output a comparison signal COMP-OUT based on the comparison result.

[0058] The storage circuit MCT may be configured to store a code “CODE” in response to the comparison signal COMP_OUT and the memory control signal CS-MC, or to output the stored code “CODE” as a digital signal DOUT in response to the comparison signal COMP_OUT and the memory control signal CS-MC. Figure 3B As shown, the memory circuit MCT may include a first selection circuit SEL1 and a second selection circuit SEL2 and a plurality of memory cells MC1 and MC2.

[0059] Each of the plurality of memory cells MC1 and MC2 may be one of various forms of data storage components such as a dynamic random access memory (DRAM) cell, a synchronous dynamic random access memory (SDRAM) cell, and a latch, which are configured to store a code "CODE" at a specific timing. The plurality of memory cells MC1 and MC2 may be connected to a first word line WL1 and a second word line WL2 and a bit line BL. Depending on the levels of the first word line WL1 and the second word line WL2, the plurality of memory cells MC1 and MC2 may store a code "CODE" provided through the bit line BL, or may output the stored code "CODE" as a digital signal DOUT through the bit line BL.

[0060] In an exemplary embodiment of the present inventive concept, the number of first storage cells MC1 among the plurality of storage cells MC1 and MC2 may be "N" (N is a natural number 2 or greater), and the number of second storage cells MC2 among the plurality of storage cells MC1 and MC2 may be "M" (M is a natural number). In an exemplary embodiment of the present inventive concept, the number "N" of the first storage cells MC1 may be the same as or different from the number "M" of the second storage cells MC2.

[0061] In an exemplary embodiment of the inventive concept, the first memory cell MC1 may be configured to store a reset sampling value "R", and the second memory cell MC2 may be configured to store a signal sampling value "S". The first memory cell MC1 may be connected to the first word line WL1 and the bit line BL, and the second memory cell MC2 may be connected to the second word line WL2 and the bit line BL.

[0062] The first selection circuit SEL1 may be configured to control the first word line WL1 and the second word line WL2 in response to the comparison signal COMP-OUT and the memory control signal CS-MC. Figure 3CAs shown, the first selection circuit SEL1 may include a first switch SW1. Each of the first switches SW1 may be configured to provide a first voltage V1 to one of the first word line WL1 and the second word line WL2 in response to a comparison signal COMP-OUT and a memory control signal CS-MC. In an exemplary embodiment of the inventive concept, the first voltage V1 may be a voltage high enough to activate each of the plurality of memory cells MC1 and MC2 (e.g., a high voltage for activating a selection transistor in the case where the memory cell is a DRAM cell).

[0063] For example, the memory control signal CS-MC may include a first sampling signal SMP1 and a second sampling signal SMP2 and a first read signal RD1 and a second read signal RD2. The first sampling signal SMP1 may be a signal for storing a reset sampling value "R" in the first storage unit MC1, and the second sampling signal SMP2 may be a signal for storing a signal sampling value "S" in the second storage unit MC2. The first read signal RD1 may be a signal for outputting the reset sampling value "R" stored in the first storage unit MC1 as a digital signal DOUT, and the second read signal RD2 may be a signal for outputting the signal sampling value "S" stored in the second storage unit MC2 as a digital signal DOUT. However, the inventive concept is not limited thereto. For example, the memory control signal CS-MC for controlling the storage circuit MCT may be changed or modified differently.

[0064] In the case where the first sampling signal SMP1 or the first read signal RD1 is activated, the first switch SW1 may provide the first voltage V1 to the first word line WL1 in response to the falling edge (or rising edge) of the comparison signal COMP-OUT. In this way, the first memory cell MC1 connected to the first word line WL1 may be activated. In this case, the value of the code "CODE" may be stored in the first memory cell MC1, or the value stored in the activated first memory cell MC1 (e.g., the reset sampling value "R") may be output.

[0065] In the case where the second sampling signal SMP2 or the second read signal RD2 is activated, the first switch SW1 can provide the second voltage V2 to the second word line WL2 in response to the falling edge (or rising edge) of the comparison signal COMP-OUT. In this way, the second storage cell MC2 connected to the second word line WL2 can be activated. In this case, the value of the code "CODE" can be stored in the second storage cell MC2, or the value stored in the activated second storage cell MC2 (for example, the signal sampling value "S") can be output.

[0066] As described above, the first selection circuit SEL1 may select at least one of a group of first memory cells MC1 and a group of second memory cells MC2 in response to the comparison signal COMP-OUT and the memory control signal CS-MC.

[0067] In response to the memory control signal CS-MC, the second selection circuit SEL2 may be configured to provide a code “CODE” to the bit line BL or output a digital signal DOUT from the bit line BL. Figure 3C As shown, the second selection circuit SEL2 may include a second switch SW2. In response to the memory control signal CS-MC, the second switch SW2 may be configured to connect the bit line BL to one of a group of lines receiving the code "CODE" and a group of lines outputting the digital signal DOUT.

[0068] For example, when the first sampling signal SMP1 or the second sampling signal SMP2 is activated, the second switch SW2 can connect the bit line BL to the line receiving the code "CODE". In this case, the code "CODE" provided from the counter 121 can be provided to the first storage cell MC1 or the second storage cell MC2 through the bit line BL. When the first read signal RD1 or the second read signal RD2 is activated, the second switch SW2 can connect the bit line BL to the line receiving the digital signal DOUT. In this case, the value stored in the first storage cell MC1 or the second storage cell MC2 (for example, the reset sampling value "R" or the signal sampling value "S") can be output as the digital signal DOUT.

[0069] In an exemplary embodiment of the present inventive concept, Figure 3C The first selection circuit SEL1 and the second selection circuit SEL2 shown are exemplary, and the inventive concept is not limited thereto. For example, each of the first selection circuit SEL1 and the second selection circuit SEL2 may be changed or modified differently to store or read information corresponding to a storage unit associated with the digital pixel DP (e.g., a reset sampling value "R" or a signal sampling value "S"). In an exemplary embodiment of the inventive concept, each of the first selection circuit SEL1 and the second selection circuit SEL2 may be modified differently according to the number of word lines, the number of bit lines, the way the word lines are wired, and the way the bit lines are wired. An exemplary embodiment of the inventive concept is shown as the first selection circuit SEL1 and the second selection circuit SEL2 being included in one digital pixel DP, but the inventive concept is not limited thereto. For example, the first selection circuit SEL1 and the second selection circuit SEL2 may be set in units of a pixel group including a plurality of digital pixels DP.

[0070] As described above, the digital pixel DP according to an exemplary embodiment of the inventive concept may be configured to generate an analog signal corresponding to light received from the outside, convert the generated analog signal into a digital signal, and output the digital signal. Figure 3D A schematic operation of the digital pixel DP is described.

[0071] like Figure 3D As shown, the first sampling signal SMP1 may be activated from the first time T1 to the third time T3. In other words, during the period from the first time T1 to the third time T3, a sampling operation may be performed on the reset level of the photo detector PDT.

[0072] For example, during the activation of the first sampling signal SMP1, the ramp generator 123 may output a ramp signal VRAMP that decreases uniformly (e.g., decreases at a single slope), and the counter 121 may sequentially output a code "CODE" that increases or decreases at a given interval. At the second time T2, the level of the ramp signal VRAMP may become less than the level of the floating diffusion node FD (e.g., VFD). In this case, the output signal COMP-OUT of the comparator COMP may transition from a high level to a low level. In other words, when the ramp signal VRAMP intersects a predetermined threshold, the output signal COMP-OUT transitions.

[0073] Because the first sampling signal SMP1 is active at the falling edge of the output signal COMP-OUT of the comparator COMP (e.g., the second time T2), the code "CODE" can be provided to the bit line BL by the second selection circuit SEL2. In addition, the first storage cell MC1 can be activated by the first selection circuit SEL1. In other words, the value of the code "CODE" can be stored in the first storage cell MC1 as the reset sampling value "R" at the second time T2.

[0074] Thereafter, the transfer transistor TX of the photodetector PDT may be turned on in response to the transfer signal TG activated at the fourth time T4, and thus the charge accumulated by the photodiode PD may be transferred to the floating diffusion node FD. Thus, at time T4, the level (e.g., VFD) of the floating diffusion node FD (or the level of the detection signal DET) may be reduced by as much as the level corresponding to the amount of charge transferred.

[0075] Thereafter, the second sampling signal SMP2 may be activated from the fifth time T5 to the seventh time T7. In other words, during the period from the fifth time T5 to the seventh time T7, a signal sampling operation may be performed on the detection signal DET from the photo detector PDT.

[0076] As in the above description, for example, during the activation of the second sampling signal SMP2, the ramp generator 123 may output the ramp signal VRAMP, and the counter 121 may output the code "CODE". At the sixth time T6, the detection signal DET may become lower than the ramp signal VRAMP. In this case, the output signal COMP-OUT of the comparator COMP may transition from a high level to a low level. In other words, when the ramp signal VRAMP intersects another predetermined threshold, the output signal COMP-OUT transitions.

[0077] Because the second sampling signal SMP2 is active at the falling edge of the output signal COMP-OUT of the comparator COMP (e.g., the sixth time T6), the code "CODE" can be provided to the bit line BL by the second selection circuit SEL2. In addition, the second storage cell MC2 can be activated by the second selection circuit SEL2. In other words, the value "S" of the code "CODE" can be stored in the second storage cell MC2 at the sixth time T6.

[0078] Afterwards, during the activation period of the first read signal RD1, the first memory cell MC1 may be activated by the first selection circuit SEL1, and the bit line BL may be connected to the output signal line (e.g., the line outputting the digital signal DOUT) through the second selection circuit SEL2. In this case, the value stored in the first memory cell MC1 (e.g., the reset sampling value "R") may be output as the digital signal DOUT. For example, the reset sampling voltage "R" stored in the first memory cell MC1 may be output as the digital signal DOUT between the seventh time T7 and the eighth time T8.

[0079] Afterwards, during the activation period of the second read signal RD2, the second storage cell MC2 can be activated by the second selection circuit SEL2, and the bit line BL can be connected to the output signal line through the second selection circuit SEL2. In this case, the value stored in the second storage cell MC2 (e.g., the signal sampling value "S") can be output as a digital signal DOUT. For example, the signal sampling voltage "S" stored in the second storage cell MC2 can be output as a digital signal DOUT between the seventh time T7 and the eighth time T8.

[0080] Thereafter, at an eighth time T8 , the reset transistor RX may be turned on in response to activation of the reset signal RG, and thus the level VFD of the floating diffusion node FD may be reset.

[0081] In an exemplary embodiment of the inventive concept, the digital signal DOUT (or the reset sampling value "R" and the signal sampling value "S") output from the storage circuit MCT may be provided to the digital logic circuit 130 through the sense amplifier SA. In an exemplary embodiment of the inventive concept, the sense amplifier SA may be provided in units of columns of a plurality of pixels included in the pixel array 110.

[0082] refer to FIG. 3A to FIG. 3D The described structure or operation of the digital pixel DP is exemplary, and the inventive concept is not limited thereto. For example, the structure or operation of the digital pixel DP may be variously changed according to a way of implementing the digital pixel DP.

[0083] Figure 4A and Figure 4B It shows Figure 1 Schematic diagram of the configuration of the pixel array 110. Figure 1 , Figure 4A and Figure 4B , the pixel array 110 may include an upper wafer WF-u and a lower wafer WF-d. The upper wafer WF-u may be stacked on the lower wafer WF-d (eg, along a third direction DR3).

[0084] Each of the upper wafer WF-u and the lower wafer WF-d may include a semiconductor pattern formed on a semiconductor substrate. The upper wafer WF-u may include a plurality of first pixel circuits PXC1, and the lower wafer WF-d may include a plurality of second pixel circuits PXC2.

[0085] In an exemplary embodiment of the inventive concept, each of the plurality of first pixel circuits PXC1 may be formed in a corresponding one of the first pixel circuit regions of the upper wafer WF-u, and each of the plurality of second pixel circuits PXC2 may be formed in a corresponding one of the second pixel circuit regions of the lower wafer WF-d. Below, for ease of description, the term "pixel circuit" is used, but the term "pixel circuit" may indicate a related component according to an exemplary embodiment of the inventive concept or a disclosed context, or may indicate a region where a related component is formed.

[0086] One of the plurality of first pixel circuits PXC1 and one of the plurality of second pixel circuits PXC2 may constitute a digital pixel DP. For example, the first pixel circuit PXC1 included in the upper wafer WF-u may include a reference FIG. 3A to FIG. 3D Some components of a digital pixel DP described above, and a second pixel circuit PXC2 included in the lower wafer WF-d may include reference FIG. 3A to FIG. 3DThe remaining components of the digital pixel DP described herein. In an exemplary embodiment of the present inventive concept, one digital pixel DP may be implemented by electrically connecting a first pixel circuit PXC1 of an upper wafer WF-u and a second pixel circuit PXC2 of a lower wafer WF-d. In an exemplary embodiment of the present inventive concept, the first pixel circuit PXC1 and the second pixel circuit PXC2 may be electrically connected through a connection structure (e.g., through silicon vias (TSVs) or Cu to Cu bonding) between the upper wafer WF-u and the lower wafer WF-d.

[0087] In an exemplary embodiment of the inventive concept, the first pixel circuit PXC1 and the second pixel circuit PXC2 constituting one digital pixel DP may be arranged on a plane formed by the first direction DR1 and the second direction DR2 to overlap and align with each other. Figure 4B As shown, the first pixel circuit PXC1 of the upper wafer WF-u may include Figure 3B The photodetector PDT and the comparator COMP are part of the Figure 4B As shown, a photodiode PD may be formed at a first substrate SUB1, and a color filter CF and a lens LS may be formed on the photodiode PD.

[0088] The first pixel circuit layer PXC-LAY1 may be formed under the first substrate SUB1. The transfer transistor TX and the reset transistor RX of the photodetector PDT and a portion of the comparator COMP may be formed at the first pixel circuit layer PXC-LAY1. In an exemplary embodiment of the inventive concept, this portion of the comparator COMP may include at least one of various transistors included in the comparator COMP.

[0089] The first metal layer ML-LAY1 may be formed under the first pixel circuit layer PXC-LAY1. Metal lines (or wires) for connecting various components included in the upper wafer WF-u may be formed at the first metal layer ML-LAY1.

[0090] The lower wafer WF-d may be formed at the second substrate SUB2. For example, the second pixel circuit PXC2 included in the lower wafer WF-d may include the rest of the comparator COMP and the storage circuit MCT. The rest of the comparator COMP and the storage circuit MCT may be formed at the second pixel circuit layer PXC-LAY2 on the second substrate SUB2.

[0091] The second metal layer ML-LAY2 may be formed on the second pixel circuit layer PXC-LAY2. The second metal layer ML-LAY2 may include metal lines (or wires) for connecting components.

[0092] In an exemplary embodiment of the inventive concept, the memory circuit MCI of the digital pixel DP may be included in the second pixel circuit PXC2 of the lower wafer WF-d. In this case, the memory cell MC included in the memory circuit MCT may be formed in a memory cell area MCA disposed at the second pixel circuit layer PXC-LAY2, and the remaining components of the second pixel circuit PXC2 may be formed at the peripheral area PRA.

[0093] As described above, the pixel array 110 or the plurality of digital pixels DP of the image sensor device 100 according to an exemplary embodiment of the inventive concept may be implemented by stacking the upper wafer WF-u and the lower wafer WF-d to be electrically connected to each other.

[0094] FIG. 5A to FIG. 5C is a plan view showing a schematic layout of an upper chip and a lower chip included in a pixel array. For simplicity of explanation and convenience of description, a layout associated with four digital pixels DP is shown in the following figures, but the inventive concept is not limited thereto. For example, other digital pixels DP can be expanded to be similar to the above example.

[0095] Ginseng Figure 5A , the upper chip WF-u may include four first pixel circuits pxc11, pxc21, pxc31 and pxc41, and the first pixel circuits pxc11 to pxc41 may be arranged in a 2×2 matrix. The lower chip WF-d may include four second pixel circuits pxc12, pxc22, pxc32 and pxc42, and the second pixel circuits pxc12 to pxc42 may be arranged in a 2×2 matrix. Four digital pixels DP may be formed by electrically connecting the first pixel circuits pxc11 to pxc41 with the second pixel circuits pxc12 to pxc42, respectively. For example, one digital pixel DP may be formed by electrically connecting the first pixel circuit pxc11 and the second pixel circuit pxc12.

[0096] In this case, the size, length or pitch of a first pixel circuit (e.g., pxc11) belonging to the upper chip WF-u may be equal to the size, length or pitch of a second pixel circuit (e.g., pxc12) belonging to the lower chip WF-d. In other words, the first pixel circuits pxc11 to pxc41 may be arranged to overlap with the second pixel circuits pxc12 to pxc42 on a plane formed by the first direction DR1 and the second direction DR2.

[0097] As described above, each of the first pixel circuits pxc11 to pxc41 may include a photodetector PDT and a portion of a comparator COMP, and each of the second pixel circuits pxc12 to pxc42 may include the remaining portion of the comparator COMP and a storage circuit MCT. The second pixel circuits pxc12 to pxc42 may be formed in the peripheral regions pra1 to pra4 and the storage cell regions mca1 to mca4 of the lower wafer WF-D, respectively.

[0098] For example, the second pixel circuit pxc12 corresponding to the first pixel circuit pxc11 can be formed in the first peripheral area pra1 and the first storage unit area mca1, the second pixel circuit pxc22 corresponding to the first pixel circuit pxc21 can be formed in the second peripheral area pra2 and the second storage unit area mca2, the second pixel circuit pxc32 corresponding to the first pixel circuit pxc31 can be formed in the third peripheral area pra3 and the third storage unit area mca3, and the second pixel circuit pxc42 corresponding to the first pixel circuit pxc41 can be formed in the fourth peripheral area pra4 and the fourth storage unit area mca4.

[0099] The memory cells of the memory circuit MCT included in the second pixel circuit (e.g., pxc12) may be formed in the first memory cell region mca1, and the remaining components of the second pixel circuit (e.g., pxc12) may be formed in the first peripheral region pra1. In this case, the memory cells of the memory circuit MCT may be formed in the first memory cell region mca1 in the shape of an array.

[0100] For example, Figure 5B As shown, a plurality of memory cells may be formed in the first memory cell region mca1. Some of the plurality of memory cells may be real memory cells RMC for storing real data or actual data (e.g., reset sampling value "R" or signal sampling value "S"), and the remaining memory cells may be dummy cells DC for ensuring the reliability of data stored in the real memory cells RMC. The dummy cells DC may be formed on the dummy pattern area DPA of the first memory cell region mca1.

[0101] For example, the real memory cell RMC may be connected to the first word line WL1 and the second word line WL2 and the bit line BL. FIG. 3A to FIG. 3D As described, the real memory cell RMC connected to the first word line WL1 can be used to store the reset sampling value "R", and the real memory cell RMC connected to the second word line WL2 can be used to store the signal sampling value "S". Figure 5BAs shown, the dummy cell DC can be formed in the first direction DR1, the direction opposite to the first direction DR1, the second direction DR2, and the direction opposite to the second direction DR2 relative to the region in which the real memory cell RMC is formed in the first memory cell region mca1. In other words, the memory cell placed in the edge region of the first memory cell region mca1 can be used as the dummy cell DC.

[0102] For simplicity of explanation, the real memory cell RMC and the dummy cell DC are shown as being connected to the bit line BL and the first word line WL1 and the second word line WL2, but the inventive concept is not limited thereto. The real memory cell RMC may be electrically connected to the first word line WL1 and the second word line WL2 and the bit line BL, and may be configured to store the digital signal DOUT. In contrast, the structure of the dummy cell DC may be similar to that of the real memory cell RMC, but the dummy cell DC may not be electrically connected to an external wire (e.g., a metal wire).

[0103] Figure 5B The configuration of the memory cells shown is exemplary, and the inventive concept is not limited thereto. For example, in the first memory cell region mca1, the total number of memory cells, the number of real memory cells, the number of dummy cells, the number of word lines, or the number of bit lines may be variously changed or modified.

[0104] In an exemplary embodiment of the present inventive concept, the remaining memory cell regions (e.g., mca2, mca3, and mca4) may be similar in shape to the first memory cell region mca1. In this case, in the second pixel circuits pxc12 to pxc42, the pattern of the memory cell region may be similar to that of the reference Figure 5C The pattern described is the same.

[0105] In this case, the size of the second pixel circuit (e.g., pxc12) may be "L1×L2", and the size of one storage area (e.g., mca1) may be "L3×L4". In this case, the size of the peripheral area (e.g., pra1) of the second pixel circuit (e.g., pxc12) may be "(L1×L2)-(L3×L4)".

[0106] In an exemplary embodiment of the present inventive concept, Figure 5BThe first memory cell region mca1 shown may have a third length L3 in the first direction DR1, and may have a fourth length L4 in the second direction DR2. In the first memory cell region mca1, the region where the real memory cells RMC are placed may have a sixth length L6 in the first direction DR1, and may have an eighth length L8 in the second direction DR2. The dummy pattern region DPA may have a fifth length L5 in the first direction DR1 and in a direction opposite to the first direction DR1 relative to the region where the real memory cells RMC are placed, and may have a seventh length L7 in the second direction DR2 and in a direction opposite to the second direction DR2 relative to the region where the real memory cells RMC are placed.

[0107] In other words, the total size of the first storage cell area mca1 may be "L3×L4", the size of the area in the first storage cell area mca1 where the real storage cell RMC is placed may be "L6×L8", and the size of the dummy pattern area DPA may be "(L3×L4)-(L6×L8)".

[0108] As described above, due to the size of the dummy pattern area DPA of the storage cell area formed in each unit digital pixel DP, the total size of the peripheral areas pra1, pra2, pra3 and pra4 may be limited. In this case, due to the limited size of the peripheral areas pra1 to pra4, the reliability of the components formed in the peripheral areas pra1 to pra4 may be reduced. According to an exemplary embodiment of the present invention, in the storage cell area formed for each digital pixel DP, the dummy area can be reduced by sharing the storage cell areas and / or dummy areas adjacent to each other. The memory layout of an exemplary embodiment of the present invention will be described more fully with reference to the accompanying drawings.

[0109] Figure 6 It shows Figure 4A A plan view of the layout of the upper and lower wafers of the pixel array is shown. Figure 4A and Figure 6 , the upper wafer WF-u may include four first pixel circuits PXC11, PXC21, PXC31, and PXC41, and the first pixel circuits PXC11 to PXC41 may be arranged in a 2×2 matrix. The first pixel circuits PXC11 to PXC41 may be similar to the above-described pixel circuits, and thus additional description will be omitted to avoid redundancy.

[0110] The lower wafer WF-d may include four second pixel circuits PXC12, PXC22, PXC32, and PXC42, and the second pixel circuits PXC12 to PXC42 may be arranged in a 2×2 matrix. As described above, each of the first pixel circuits PXC11 to PXC41 and the second pixel circuits PXC12 to PXC42 may have a size of "L1×L2", and the first pixel circuits PXC11 to PXC41 and the second pixel circuits PXC12 to PXC42 may be electrically connected to form four digital pixels DP. For example, the first pixel circuit PXC11 may be electrically connected to the second pixel circuit PXC12 to form a single digital pixel DP.

[0111] and Figure 5A The second pixel circuits pxc12 to pxc42 of the lower wafer WF-d are different, Figure 6 The second pixel circuits PXC12 to PXC42 of the lower wafer WF-d can share a memory cell area MCA. For example, Figure 5A The second pixel circuits PXC12 to PXC42 include different memory cell regions mca1 to mca4, respectively. Figure 6 In the lower wafer WF-d, memory cells may be formed in one memory cell area MCA, and the second pixel circuits PXC12 to PXC42 may share one memory cell area MCA.

[0112] For example, the memory cell area MCA may be divided into a first sub-memory cell area sMCA1, a second sub-memory cell area sMCA2, a third sub-memory cell area sMCA3, and a fourth sub-memory cell area sMCA4 (hereinafter referred to as "sub-areas"). In an exemplary embodiment, the first sub-memory cell area sMCA1 may be located in the first peripheral area PRA1, the second sub-memory cell area sMCA2 may be located in the second peripheral area PRA2, the third sub-memory cell area sMCA3 may be located in the third peripheral area PRA3, and the fourth sub-memory cell area sMCA4 may be located in the fourth peripheral area PRA4. Each of the first sub-area sMCA1 to the fourth sub-area sMCA4 may include a real memory cell RMC. The real memory cell RMC included in the first sub-area sMCA1 may store a digital signal of a digital pixel DP formed by the pixel circuits PXC11 and PXC12. The real memory cell RMC included in the second sub-area sMCA2 may store a digital signal of a digital pixel DP formed by the pixel circuits PXC21 and PXC22. The real memory cell RMC included in the third sub-region sMCA3 may store digital signals of digital pixels DP formed by pixel circuits PXC31 and PXC32. The real memory cell RMC included in the fourth sub-region sMCA4 may store digital signals of digital pixels DP formed by pixel circuits PXC41 and PXC42.

[0113] In an exemplary embodiment of the inventive concept, a shared dummy pattern area sDPA may exist between the first to fourth sub-areas sMCA1 to sMCA4. The shared dummy pattern area sDPA may be a dummy pattern area shared by the first to fourth sub-areas sMCA1 to sMCA4. Figure 5B To ensure the reliability of the real memory cells RMC in the first memory cell area mca1, the dummy pattern area DPA exists in the edge area of ​​the first memory cell area mca1. In other words, the dummy pattern area DPA surrounds the real memory cells RMC. On the contrary, in order to ensure the reliability of the real memory cells RMC in each of the first to fourth sub-areas sMCA1 to sMCA4, Figure 6 The memory cell area MCA of the embodiment may include a shared dummy pattern area sDPA disposed between the real memory cells RMC of the first to fourth sub-areas sMCA1 to sMCA4. In other words, the first to fourth sub-areas sMCA1 to sMCA4 may share a dummy pattern area (e.g., a shared dummy pattern area sDPA) disposed in a specific area. In this case, FIG. 5A to FIG. 5CCompared to the embodiment of the present invention, since the dummy pattern area DPA for forming four digital pixels DP (for example, the dummy pattern area for the real memory cell RMC) is reduced, the size of the peripheral areas PRA1 to PRA4 can be increased. As the size of the peripheral areas PRA1 to PRA4 increases, the reliability of the components formed in the peripheral areas PRA1 to PRA4 can be increased, or a component for another function can be additionally implemented.

[0114] Fig. 7A It shows Figure 6 A plan view of the layout of the memory cell area is shown. Figure 7B It shows that the application Fig. 7A In an exemplary embodiment of the present invention, Fig. 7A and Figure 7B The layout of the memory cell area MCA shown is exemplary, and the inventive concept is not limited thereto. For example, in the memory cell area MCA, the total number of memory cells, the number of real memory cells RMC, the number of dummy cells DC, or the number of shared dummy cells sDC may be changed or modified differently.

[0115] refer to Figure 6 and Fig. 7A , the memory cell area MCA may include a plurality of memory cells. A plurality of memory cells may be arranged along a row direction (e.g., a first direction DR1) and a column direction (e.g., a second direction DR2) on the memory cell area MCA. Each of the plurality of memory cells may be connected to a bit line or a word line. Hereinafter, for ease of description, additional descriptions associated with word lines or bit lines for the remaining memory cells (e.g., dummy cells DC and shared dummy cells sDC) other than the real memory cells RMC are omitted to avoid redundancy. However, the inventive concept is not limited thereto. For example, on the memory cell area MCA, word lines or bit lines corresponding to the remaining cells (e.g., dummy cells DC and shared dummy cells sDC) may be formed, but word lines or bit lines corresponding to the remaining cells (e.g., dummy cells DC and shared dummy cells sDC) may not be electrically connected to any other circuit (e.g., components of the peripheral area).

[0116] The plurality of storage cells may include a real storage cell RMC, a dummy cell DC, and a shared dummy cell sDC. The real storage cell RMC may store a corresponding digital signal (e.g., a reset sampling value "R" or a signal sampling value "S"). The dummy cell DC and the shared dummy cell sDC may be cells or patterns for ensuring the reliability of the real storage cell RMC.

[0117] In an exemplary embodiment of the present inventive concept, one memory cell region MCA may form one memory cell array or a single memory cell array. One memory cell array may indicate a structure in which adjacent memory cells or a pattern of memory cells are repeatedly formed in a specific area. For example, Figure 5C An embodiment is an embodiment in which a storage unit array is implemented in units of one digital pixel DP, and Figure 6 An embodiment is an embodiment of implementing a memory cell array in units of a plurality of digital pixels DP. In an exemplary embodiment of the present invention, a single memory cell array may indicate a set or structure of memory cells surrounded by a dummy pattern area. In an exemplary embodiment of the present invention, only a repeated pattern such as a memory cell or a dummy cell may be included in a single memory cell array, and other additional components may be formed in a peripheral area outside a single memory cell.

[0118] The memory cell area MCA is divided into first to fourth sub-areas sMCA1 to sMCA4. Each of the first to fourth sub-areas sMCA1 to sMCA4 may include real memory cells RMC, dummy cells DC, and shared dummy cells sDC.

[0119] For example, the first sub-region sMCA1 may include real memory cells RMC in the first region RA1, a first portion of dummy cells DC in the dummy pattern region DPA, and a first portion of shared dummy cells sDC in the shared dummy pattern region sDPA. The real memory cells RMC in the first region RA1 may be connected to the word lines WL11 and WL12 and the bit lines BL11 and BL12, and may be configured to store the corresponding digital signal DOUT as described above. The first portion of the dummy cells DC in the dummy pattern region DPA of the first sub-region sMCA1 may include dummy cells DC on the side of the word line WL11 facing away from the second direction DR2 or on the side of the bit line BL11 facing away from the first direction DR1. The first portion of the shared dummy cells sDC in the shared dummy pattern region sDPA of the first sub-region sMCA1 may include shared dummy cells sDC on the side of the word line WL31 facing away from the second direction DR2 or on the side of the bit line BL21 facing away from the first direction DR1.

[0120] The second sub-region sMCA2 may include a real memory cell RMC in the second region RA2, a second portion of a dummy cell DC in the dummy pattern region DPA, and a second portion of a shared dummy cell sDC in the shared dummy pattern region sDPA. The real memory cell RMC in the second region RA2 may be connected to the word lines WL21 and WL22 and the bit lines BL21 and BL22, and may be configured to store the corresponding digital signal DOUT as described above. The second portion of the dummy cell DC in the dummy pattern region DPA of the second sub-region sMCA2 may include a dummy cell DC on the side of the word line WL21 facing away from the second direction DR2 or on the side of the bit line BL22 facing away from the first direction DR1. The second portion of the shared dummy cell sDC in the shared dummy pattern region sDPA of the second sub-region sMCA2 may include a shared dummy cell sDC on the side of the word line WL41 facing away from the second direction DR2 or on the side of the bit line BL12 facing the first direction DR1.

[0121] The third sub-region sMCA3 may include a real memory cell RMC in the third region RA3, a third portion of a dummy cell DC in the dummy pattern region DPA, and a third portion of a shared dummy cell sDC in the shared dummy pattern region sDPA. The real memory cell RMC in the third region RA3 may be connected to the word lines WL31 and WL32 and the bit lines BL11 and BL12, and may be configured to store the corresponding digital signal DOUT as described above. The third portion of the dummy cell DC in the dummy pattern region DPA of the third sub-region sMCA3 may include a dummy cell DC on the side of the word line WL32 facing the second direction DR2 or on the side of the bit line BL11 facing away from the first direction DR1. The third portion of the shared dummy cell sDC in the shared dummy pattern region sDPA of the third sub-region sMCA3 may include a shared dummy cell sDC on the side of the word line WL12 facing the second direction DR2 or on the side of the bit line BL21 facing away from the first direction DR1.

[0122] The fourth sub-region sMCA4 may include a real memory cell RMC in the fourth region RA4, a fourth portion of a dummy cell DC in the dummy pattern region DPA, and a fourth portion of a shared dummy cell sDC in the shared dummy pattern region sDPA. The real memory cell RMC in the fourth region RA4 may be connected to the word lines WL41 and WL42 and the bit lines BL21 and BL22, and may be configured to store the corresponding digital signal DOUT as described above. The fourth portion of the dummy cell DC in the dummy pattern region DPA of the fourth sub-region sMCA4 may include a dummy cell DC on the side of the word line WL42 facing the second direction DR2 or on the side of the bit line BL22 facing the first direction DR1. The fourth portion of the shared dummy cell sDC in the shared dummy pattern region sDPA of the fourth sub-region sMCA4 may include a shared dummy cell sDC on the side of the word line WL22 facing the second direction DR2 or on the side of the bit line BL12 facing the first direction DR1.

[0123] As described above, the first to fourth sub-regions sMCA1 to sMCA4 may share the shared dummy cells sDC in the shared dummy pattern area sDPA. Figure 5B and Figure 5C In an embodiment, two dummy pattern areas DPA may exist between real memory cells RMC of the first memory cell area mca1 and the second memory cell area mca2. In other words, in a case where the length (e.g., the length in the first direction DR1) of one dummy pattern area DPA is "L5", the real memory cells RMC of the first memory cell area mca1 and the real memory cells RMC of the second memory cell area mca2 may be spaced apart from each other by at least twice the length "L5", and a dummy pattern area DPA having a length of "2×L5" may exist between the real memory cells RMC of the first memory cell area mca1 and the real memory cells RMC of the second memory cell area mca2.

[0124] On the contrary, Fig. 7A In the memory cell area MCA, only the shared dummy pattern area sDPA may exist between the first area RA1 to the fourth area RA4 where the real memory cells RMC are placed. For example, the first area RA1 and the second area RA2 may be spaced apart from each other as large as the shared dummy pattern area sDPA. In this case, the shared dummy pattern area sDPA may have a length "L9" in the first direction DR1. In an exemplary embodiment of the present inventive concept, the length "L9" may be equal to "L5" which is the length of a dummy pattern area DPA in the first direction DR1, or may be less than twice the length "L5". In other words, Figure 5B or Figure 5C Compared with the embodiment of Fig. 7A In the embodiment, the pseudo pattern area DPA between adjacent real memory cells RMC can be reduced.

[0125] In an exemplary embodiment of the inventive concept, a portion of the dummy pattern area DPA corresponding to the reduced size may be used as a peripheral area. Figure 7B , the lower wafer WF-d may include four second pixel circuits PXC12 to PXC42. As described above, the second pixel circuits PXC12 to PXC42 may share one memory cell area MCA, and thus the size of the dummy pattern area DPA used in the memory cell area MCA may be reduced. For example, assuming that the size of the area of ​​the real memory cell RMC required for each of the second pixel circuits PXC12 to PXC42 is "L6×L6" (reference Figure 5B ), and the length of the dummy pattern area DPA relative to the area of ​​the real memory cell is "L5" in the first direction DR1 and the second direction DR2, respectively.

[0126] according to Figure 5B and Figure 5C In the embodiment, the total size of the real memory cells RMC belonging to the four digital pixels DP may be “4×(L6×L6)”, and the total size of the dummy pattern area DPA may be “4×{(L5+L6+L5)×(L5+L6+L5)-(L6×L6)}”. In other words, the total size of the memory cell area MCA including the four digital pixels DP may be “4×(L3×L3)” (=4×(L6×L6)+4×{(L5+L6+L5)×(L5+L6+L5)-(L6×L6)}).

[0127] On the contrary, according to Fig. 7A and Figure 7B In an embodiment, the total size of the area for the real storage cells RMC belonging to the four digital pixels DP may be “4×(L6×L6)”, and the total size of the dummy pattern area DPA may be “4×{(L5+L6+L9+L6+L9)2-4×(L6×L6)}”. In other words, the total size of the storage cell area MCA including the four digital pixels DP may be “L10×L10” (=4×(L6×L6)+4×{(L5+L6+L9+L6+L9)2-4×(L6×L6)})”. In this case, “L10” may be less than twice the length “L3”.

[0128] As a result, according to an exemplary embodiment of the inventive concept, since a plurality of digital pixels share one storage unit region or the storage unit regions of a plurality of digital pixels share different dummy pattern regions, the total size of the storage unit region can be reduced, a portion of the storage unit region corresponding to the reduced size can be utilized, and thus the reliability of components formed in the peripheral region can be increased, or any other components for additional functions can be added.

[0129] In an exemplary embodiment of the present inventive concept, Fig. 7A and Figure 7B As shown, the word line connected to the real memory cell RMC can be connected to the metal line (reference Figure 4B )connect.

[0130] For example, the word lines WL11 and WL12 connected to the real memory cells RMC of the first area RA1 may be connected to the metal lines through the word line contacts formed in the first peripheral area PRA1. The word lines WL21 and WL22 connected to the real memory cells RMC of the second area RA2 may be connected to the metal lines through the word line contacts formed in the second peripheral area PRA2. The word lines WL31 and WL32 connected to the real memory cells RMC of the third area RA3 may be connected to the metal lines through the word line contacts formed in the third peripheral area PRA3. The word lines WL41 and WL42 connected to the real memory cells RMC of the fourth area RA4 may be connected to the metal lines through the word line contacts formed in the fourth peripheral area PRA4. In an exemplary embodiment of the present inventive concept, the metal lines connected to the plurality of word lines WL11 to WL42 may be connected to other components (e.g., comparator COMP or first selection circuit SEL1) formed in the corresponding peripheral areas PRA1 to PRA4, and may be operated according to the above-described operation method.

[0131] In an exemplary embodiment of the inventive concept, the bit lines BL11, BL12, BL21, and BL22 may be connected to a metal line through a contact formed in at least one of the peripheral regions PRA1 to PRA4. The metal line connected to the bit lines BL11, BL12, BL21, and BL22 may be connected to other components (e.g., a counter, a sense amplifier, and a second selection circuit) formed in at least one of the peripheral regions PRA1 to PRA4.

[0132] As described above, according to an exemplary embodiment of the inventive concept, a plurality of digital pixels adjacent to each other may share a memory cell region (or memory cell array), or may share a dummy pattern region. In this way, the size of the dummy pattern region for ensuring the reliability of the real memory cells used in the plurality of digital pixels may be reduced. Because the portion of the dummy pattern region corresponding to the reduced size is used as a peripheral region for forming other components, the reliability of the components formed in the peripheral region may be increased, or components for adding any other functions of the digital pixels may also be formed. Therefore, an image sensor device having reduced cost, improved reliability, and improved performance is provided.

[0133] Figure 8 It shows Figure 6 For ease of description, additional descriptions associated with the above components will be omitted to avoid redundancy. In addition, for the sake of brevity of description, some of the above components may be omitted, or some reference symbols used to describe the above components may be omitted. However, the present invention is not limited thereto, and all of the above embodiments and Figure 8 The present invention is understood by referring to the embodiments.

[0134] refer to Figure 6 and Figure 8 , as in the above description, the memory cell area MCA-a may be divided into a first sub-area sMCA1 to a fourth sub-area sMCA4. The real memory cells RMC included in the first sub-area sMCA1 may be connected to the word lines WL11 and WL12 and the bit lines BL11 and BL12. The real memory cells RMC included in the second sub-area sMCA2 may be connected to the word lines WL21 and WL22 and the bit lines BL21 and BL22. The real memory cells RMC included in the third sub-area sMCA3 may be connected to the word lines WL31 and WL32 and the bit lines BL11 and BL12. The real memory cells RMC included in the fourth sub-area sMCA4 may be connected to the word lines WL41 and WL42 and the bit lines BL21 and BL22.

[0135] The memory cell area MCA-a may include a plurality of memory cells. The plurality of memory cells may include a real memory cell RMC, a dummy cell DC, and a shared dummy cell sDC. Figure 8 The memory cell array MCA-a may further include a shared dummy cell sDC-iso (hereinafter referred to as “isolation unit”) for isolation.

[0136] The isolation unit sDC-iso may be a dummy unit for separating the word lines of the real memory cells RMC placed in the same row. For example, the first digital pixel DP and the second digital pixel DP placed in the same row and adjacent to each other may operate independently of each other. In other words, the first digital pixel DP and the second digital pixel DP may store data at different timings, respectively, according to the light incident thereon. To this end, the memory cells corresponding to the first digital pixel DP and the second digital pixel DP may be controlled by separate signal lines (e.g., word lines).

[0137] exist Figure 8 In the embodiment of , it is assumed that the real memory cell RMC included in the first sub-region sMCA1 corresponds to the first digital pixel, and the real memory cell RMC included in the second sub-region sMCA2 corresponds to the second digital pixel, which is adjacent to the first digital pixel and belongs to the same row as the first digital pixel. In this case, in order to realize independent operation of the first digital pixel and the second digital pixel, the real memory cell RMC included in the first sub-region sMCA1 can be connected to the word lines WL11 and WL12, and the real memory cell RMC included in the second sub-region sMCA2 can be connected to the word lines WL21 and WL22.

[0138] In this case, the real memory cell RMC included in the first sub-region sMCA1 and the real memory cell RMC included in the second sub-region sMCA2 can be placed in the same row at the memory cell array level. Because the memory cells are formed in a repeated pattern, the real memory cell RMC included in the first sub-region sMCA1 and the real memory cell RMC included in the second sub-region sMCA2 can be connected to the same word line. In order to prevent the real memory cells RMC of different sub-regions sMCA from being connected to the same word line, an isolation unit sDC-iso can be added between the real memory cell RMC included in the first sub-region sMCA1 and the real memory cell RMC included in the second sub-region sMCA2. The isolation unit sDC-iso can be some of the shared dummy cells sDC placed between the real memory cells RMC included in the first sub-region sMCA1 and the second sub-region sMCA2. The isolation unit sDC-iso may not be electrically connected to other cells (e.g., shared dummy cells sDC) in the same row. For example, a word line pattern for the isolation unit sDC-iso may not be formed. In other words, the isolation unit sDC-iso may not be connected to the word line. In this case, the real memory cells RMC included in the first sub-region sMCA1 and the real memory cells RMC included in the second sub-region sMCA2 may be connected to different word lines, and thus independent operations of the first digital pixel and the second digital pixel may be ensured.

[0139] Figure 8 The memory cell area MCA-a may further include an additional isolation unit. The additional isolation unit may be placed between the real memory cells RMC of the first sub-area sMCA1 and the real memory cells RMC of the third sub-area sMCA3, or may be placed between the real memory cells RMC of the second sub-area sMCA2 and the real memory cells RMC of the fourth sub-area sMCA4, so that the bit lines of the respective sub-areas may be separated from each other.

[0140] Fig. 9 It shows that the Figure 1 Schematic diagram of the structure of the digital pixel shared comparator in the pixel array. Figure 1 and Fig. 9 , the four digital pixels DP1 to DP4 can share one comparator sCOMP (hereinafter referred to as “shared comparator”).

[0141] For example, the first to fourth digital pixels DP1 to DP4 may include first to fourth photodetectors PDT1 to PDT4, one shared comparator sCOMP, and a storage circuit MCT. Each of the first to fourth photodetectors PDT1 to PDT4 is connected to a reference FIG. 3A to FIG. 3D The described photodetectors PDT are similar, and thus additional description will be omitted to avoid redundancy. An output (eg, a detection signal DET) of each of the first to fourth photodetectors PDT1 to PDT4 may be provided to a shared comparator sCOMP.

[0142] The shared comparator sCOMP may compare the output of each of the first to fourth photodetectors PDT1 to PDT4 with the ramp signal VRAMP and may output a comparison signal. In an exemplary embodiment of the inventive concept, the outputs of the first to fourth photodetectors PDT1 to PDT4 may be output at different timings, and thus the shared comparator sCOMP may output comparison signals corresponding to the first to fourth photodetectors PDT1 to PDT4, respectively, at different timings.

[0143] The storage circuit MCT may store a code “CODE” corresponding to each of the first to fourth photodetectors PDT1 to PDT4 based on a comparison signal from the shared comparator sCOMP. For example, the storage circuit MCT may include a first selection circuit SEL1, a second selection circuit SEL2, a first storage cell MC1, a second storage cell MC2, a third storage cell MC3, and a fourth storage cell MC4.

[0144] When a comparison signal corresponding to the first photo detector PDT1 is output from the shared comparator sCOMP, the first selection circuit SEL1 may select a word line corresponding to the first memory cell MC1. When a comparison signal corresponding to the second photo detector PDT2 is output from the shared comparator sCOMP, the first selection circuit SEL1 may select a word line corresponding to the second memory cell MC2. When a comparison signal corresponding to the third photo detector PDT3 is output from the shared comparator sCOMP, the first selection circuit SEL1 may select a word line corresponding to the third memory cell MC3. When a comparison signal corresponding to the fourth photo detector PDT4 is output from the shared comparator sCOMP, the first selection circuit SEL1 may select a word line corresponding to the fourth memory cell MC4.

[0145] In other words, the first storage cell MC1 may be configured to store a digital signal corresponding to the light signal detected by the first photodetector PDT1, the second storage cell MC2 may be configured to store a digital signal corresponding to the light signal detected by the second photodetector PDT2, the third storage cell MC3 may be configured to store a digital signal corresponding to the light signal detected by the third photodetector PDT3, and the fourth storage cell MC4 may be configured to store a digital signal corresponding to the light signal detected by the fourth photodetector PDT4. As a result, the first photodetector PDT1, the shared comparator sCOMP, and the first storage cell MC1 may be operated as a first digital pixel DP1; the second photodetector PDT2, the shared comparator sCOMP, and the second storage cell MC2 may be operated as a second digital pixel DP2; the third photodetector PDT3, the shared comparator sCOMP, and the third storage cell MC3 may be operated as a third digital pixel DP3; and the fourth photodetector PDT4, the shared comparator sCOMP, and the fourth storage cell MC4 may be operated as a fourth digital pixel DP4. In addition to the comparators being shared, each digital pixel is connected to a reference pixel DP1. FIG. 3A to FIG. 3D The described digital pixels are similar, so additional description will be omitted to avoid redundancy.

[0146] In an exemplary embodiment of the inventive concept, operation timings of the first to fourth photo detectors PDT1 to PDT4 and the memory circuit MCT may be controlled by a control signal CTRL (eg, CS-PD or CS-MC) from the pixel driver 120 .

[0147] In an exemplary embodiment of the present inventive concept, the first to fourth photodetectors PDT1 to PDT4 may be respectively included in the reference Figure 6In the first pixel circuits PXC11 to PXC41 of the upper wafer WF-u described above, the first to fourth memory cells MC1 to MC4 may be formed on the reference Figures 6 to 8 In the first to fourth sub-regions sMCA1 to sMCA4 of the memory cell region MCA or MCA-a of the lower wafer WF-d described.

[0148] In an exemplary embodiment of the inventive concept, the shared comparator sCOMP, the first selection circuit SEL1 and the second selection circuit SEL2 may include a reference circuit. Figures 6 to 8 In other words, one comparator may be formed at the upper wafer WF-u or the lower wafer WF-d in units of four digital pixels.

[0149] In exemplary embodiments of the inventive concept, one memory cell area MCA (or memory cell array) may be provided in units of a pixel group including a plurality of digital pixels, or may be provided in units of a single comparator.

[0150] Fig. 10A and Fig. 10B It shows Figure 4A For the sake of brevity and ease of description, the description given with reference to the above components or reference symbols associated with the above components may be omitted to avoid redundancy. However, the present invention is not limited thereto and may be understood in consideration of all the above embodiments or all embodiments described later. Fig. 10A and Fig. 10B Embodiment of the invention.

[0151] refer to Fig. 10A and Fig. 10B , the lower wafer WF-db may include a plurality of second pixel circuits PXC12 to PXCn2. The plurality of second pixel circuits PXC12 to PXCn2 may be arranged in pairs along the second direction DR2. For example, PXC12 and PXC22, PXC32 and PXC42, PXC52 and PXC62, PXC72 and PXC82 ... PXCn-12 and PXCn2 may be placed in the same row, respectively, PXC12, PXC32, PXC52, PXC72 ... PXCn-12 may be placed in the same column, and PXC22, PXC42, PXC62, PXC82 ... PXCn2 may be placed in the same column.

[0152] The second pixel circuits PXC12, PXC32, PXC52, PXC72...PXCn-12 in the same column (e.g., the first column) and the second pixel circuits PXC22, PXC42, PXC62, PXC82...PXCn2 in the same column (e.g., the second column adjacent to the first column) may share a storage unit area MCA-b.

[0153] For example, Fig. 10B As shown, the memory cell area MCA-b may include a plurality of memory cells, and the plurality of memory cells may include real memory cells RMC, dummy cells DC, and shared dummy cells sDC.

[0154] In this case, the real storage cells RMC corresponding to the second pixel circuits PXC12, PXC32, PXC52, PXC72 ... PXCn-12 in the same column (e.g., the first column) can be connected to the corresponding word lines WL11 and WL12, WL31 and WL32, WL51 and WL52, WL71 and WL72 ... WLn-11 and WLn-12, respectively. The word lines can be connected to the metal lines through word line contacts. The real storage cells RMC corresponding to the second pixel circuits PXC22, PXC42, PXC62, PXC82 ... PXCn2 in the same column (e.g., the second column adjacent to the first column) can be connected to the corresponding word lines WL21 and WL22, WL41 and WL42, WL61 and WL62, WL81 and WL82 ... WLn1 and WLn2, respectively. The word lines may be connected to metal lines through word line contacts.

[0155] The shared dummy storage cell sDC may be inserted between the real storage cell RMC corresponding to the second pixel circuit PXC12, PXC32, PXC52, PXC72 ... PXCn-12 in the same column (e.g., the first column) and the real storage cell RMC corresponding to the second pixel circuit PXC22, PXC42, PXC62, PXC82 ... PXCn2 in the same column (e.g., the second column). This configuration is similar to that of the above-described shared dummy cell sDC, and therefore additional description will be omitted to avoid redundancy.

[0156] and Figures 6 to 8 The embodiments are different. Fig. 10BIn the memory cell area MCA-b, the dummy cell DC or the dummy pattern area DPA between the real memory cells RMC adjacent along the second direction DR2 can be omitted. For example, the dummy cell DC, the dummy pattern area DPA, the shared dummy cell sDC and the shared dummy pattern area sDPA between the real memory cells RMC corresponding to the pixel circuit PXC32 (for example, the real memory cells associated with the word lines WL31 and WL32) and the real memory cells RMC corresponding to the pixel circuit PXC52 (for example, the real memory cells associated with the word lines WL51 and WL52) can be omitted. In this case, the above-mentioned two groups of real memory cells can be formed physically adjacent to each other. In other words, since the dummy pattern area DPA between the real memory cells RMC adjacent along the second direction DR2 is removed, the total size of the dummy pattern area can be reduced, and thus the size of the peripheral area can be increased.

[0157] In an exemplary embodiment of the present inventive concept, with respect to the real memory cells RMC corresponding to the second pixel circuits (e.g., PXC12, PXC22, PXCn-12, and PXCn2) disposed in the edge region of the pixel array 110, there may be dummy cells DC or dummy pattern areas DPA along the second direction DR2. For example, the dummy cells DC may be formed on one side of the real memory cells RMC corresponding to PXC12 (e.g., the real memory cells connected to the word lines WL11 and WL12). For example, in Fig. 10B , the dummy cell DC of the second pixel circuit PXC12 is disposed on the left side of the real storage cell RMC of the second pixel circuit PXC12. In addition, as in the above description, the dummy cell may be formed in the remaining edge region, and thus additional description will be omitted to avoid redundancy. Fig. 10B In the embodiment, the dummy cell DC of the second pixel circuit PXC12 is disposed above the real storage cell RMC of the second pixel circuit PXC12 (eg, facing away from the second direction DR2 ).

[0158] Fig.11A and Fig. 11B It shows Figure 4A 1. A plan view of the layout of the lower wafer and the memory cell area. For simplicity of explanation and ease of description, the description given with reference to the above components or reference symbols associated with the above components may be omitted to avoid redundancy. However, the inventive concept is not limited thereto.

[0159] refer to Fig.11A and Fig. 11B , the lower wafer WF-dc may include four second pixel circuits PXC12 to PXC42. The second pixel circuits PXC12 to PXC42 may share the memory cell area MCA-c.

[0160] The memory cell area MCA-c may include a plurality of memory cells. The plurality of memory cells may include real memory cells RMC and dummy cells DC. The memory cell area MCA-c is divided into first to fourth sub-areas sMCA1 to sMCA4.

[0161] In the above-mentioned embodiment, the real memory cell RMC included in each of the first to fourth sub-regions sMCA1 to sMCA4 is configured to store the digital signal of the corresponding digital pixel. Fig. 11B The real memory cell RMC included in each of the first to fourth sub-regions sMCA1 to sMCA4 may be configured to store a digital signal of a corresponding digital pixel or to store a digital signal of an adjacent digital pixel.

[0162] For example, the real memory cell RMC included in the first sub-region sMCA1 may be connected to the first to fourth word lines WL1 to WL4, and may be connected to the first bit line BL1 and the second bit line BL2. The real memory cell RMC included in the second sub-region sMCA2 may be connected to the first to fourth word lines WL1 to WL4, and may be connected to the third bit line BL3 and the fourth bit line BL4. The real memory cell RMC included in the third sub-region sMCA3 may be connected to the fifth to eighth word lines WL5 to WL8, and may be connected to the first bit line BL1 and the second bit line BL2. The real memory cell RMC included in the fourth sub-region sMCA4 may be connected to the fifth to eighth word lines WL5 to WL8, and may be connected to the third bit line BL3 and the fourth bit line BL4.

[0163] In this case, the real memory cell RMC connected to the first word line WL1 and the third word line WL3 may be configured to store a digital signal corresponding to the first digital pixel. The real memory cell RMC connected to the second word line WL2 and the fourth word line WL4 may be configured to store a digital signal corresponding to the second digital pixel. In this case, the first digital pixel may be a digital pixel including a second pixel circuit in which the first sub-region sMCA1 is placed, and the second digital pixel may be a digital pixel including a second pixel circuit in which the second sub-region sMCA2 is placed. In other words, the memory cells included in adjacent digital pixels may be configured to share the same bit line. In other words, according to Fig.11A and Fig. 11B In an embodiment of the present invention, actual storage units of digital pixels may have a structure of sharing bit lines.

[0164] According to the above embodiment, the memory cell corresponding to the first digital pixel is connected to the first word line WL1 and the third word line WL3, and the memory cell corresponding to the second digital pixel is connected to the second word line WL2 and the fourth word line WL4. In other words, the real memory cell storing the digital signal corresponding to the digital pixel disposed on the side of the memory cell region facing away from the first direction DR1 may be connected to the odd word line, and the real memory cell storing the digital signal corresponding to the digital pixel disposed on the side of the memory cell region facing the first direction DR1 may be connected to the even word line.

[0165] The first word line WL1 and the third word line WL3 may be connected to the metal line through the word line contact disposed in the first peripheral region PRA1, and the second word line WL2 and the fourth word line WL4 may be connected to the metal line through the word line contact disposed in the second peripheral region PRA2. In this case, the distance between the word line contacts formed in the same peripheral region (e.g., the word line pitch WLpt) may be increased compared to the above-mentioned embodiment. For example, in reference FIG. 5A to FIG. 10B In the described embodiment, word line contacts connected to adjacent word lines are continuously formed in the same peripheral region. Fig.11A In the embodiment of FIG. 1 , word line contacts connected to word lines (eg, WL1 and WL3 ) that are not physically adjacent to each other are formed in the same peripheral region (eg, PRA1 ).

[0166] In other words, because the distance between word line contacts formed in one peripheral region along the second direction DR2 (eg, a word line pitch) increases, complexity of a process for forming the word line contacts or complexity of wires may be reduced.

[0167] According to the above embodiment, the memory cell area MCA-c included in the image sensor device 100 may include a plurality of memory cells. The plurality of memory cells may include a plurality of real memory cells connected to a plurality of bit lines. A real memory cell RMC for storing a digital signal of a first digital pixel among the plurality of real memory cells may be connected to a first word line WL1 and a third word line WL3. A real memory cell RMC for storing a digital signal of a second digital pixel physically adjacent to the first digital pixel may be connected to a second word line WL2 and a fourth word line WL4. In this case, the second word line WL2 may be inserted between the first word line WL1 and the third word line WL3, and the third word line WL3 may be inserted between the second word line WL2 and the fourth word line WL4. In this case, a word line contact associated with the first word line WL1 and the third word line WL3 may be formed in the first peripheral area PRA1, and a word line contact associated with the second word line WL2 and the fourth word line WL4 may be formed in the second peripheral area PRA2. Therefore, the distance between the word line contacts may be increased, and thus the complexity of the process for forming the word line contacts may be reduced.

[0168] In addition, as mentioned above, according to Fig.11A and Fig. 11B In the embodiment, since there is no dummy cell or dummy pattern area DPA between the real memory cells RMC, the total size of the memory cell area MCA-c can be reduced. The portion of the memory cell area MCA-c corresponding to the reduced size can be used to form the peripheral areas PRA1 to PRA4. Therefore, an image sensor device with reduced cost, improved reliability and improved performance is provided.

[0169] Fig.12 2 is a plan view illustrating a memory cell region according to an exemplary embodiment of the inventive concept. For convenience of description, additional descriptions associated with the above-described components may be omitted to avoid redundancy.

[0170] refer to Fig.12 , the memory cell area MCA-d may include a plurality of memory cells, and the plurality of memory cells may include a real memory cell RMC, a dummy cell DC, and a shared dummy cell sDC. The memory cell area MCA-d is divided into a first sub-area sMCA1 to a fourth sub-area sMCA4. As in the above description, the memory cell area MCA-d may be a memory cell area shared by four digital pixels, and the configuration of the real memory cell RMC used by the four digital pixels may be the same as that of the reference numeral sDC. Fig.11A and Fig. 11BThe configuration described is similar. In other words, the real memory cell RMC of the memory cell area MCA-d may have a structure that shares the bit lines BL1 to BL4. In other words, the real memory cell RMC connected to the first word line WL1 and the third word line WL3 and the first bit line BL1 to the fourth bit line BL4 may store a digital signal corresponding to the first digital pixel, and the real memory cell RMC connected to the second word line WL2 and the fourth word line WL4 and the first bit line BL1 to the fourth bit line BL4 may store a digital signal corresponding to the second digital pixel. In this case, the first digital pixel and the second digital pixel may be digital pixels that are placed in the same row at the pixel array level and are adjacent to each other.

[0171] and Fig.11A and Fig. 11B The storage unit area MCA-c is different. Fig.12 In the memory cell area MCA-d, the shared dummy cell sDC or the shared dummy pattern area sDPA may exist between the real memory cells RMC arranged along the second direction DR2. For example, the shared dummy cell sDC or the shared dummy pattern area sDPA may exist between the real memory cells RMC in the first sub-area sMCA1 and the second sub-area sMCA2 and the real memory cells RMC in the third sub-area sMCA3 and the fourth sub-area sMCA4.

[0172] Fig.13 2 is a plan view illustrating a memory cell region according to an exemplary embodiment of the inventive concept. For convenience of description, additional descriptions associated with the above-described components may be omitted to avoid redundancy.

[0173] refer to Fig.13 , the memory cell area MCA-e may include a plurality of memory cells, and the plurality of memory cells may include real memory cells RMC, dummy cells DC, and shared dummy cells sDC. The memory cell area MCA-e is divided into first to fourth sub-areas sMCA1 to sMCA4.

[0174] In this case, the real memory cell RMC connected to the first word line WL1 and the third word line WL3 and the first bit line BL1 and the second bit line BL2 can store a digital signal corresponding to the first digital pixel, and the real memory cell RMC connected to the second word line WL2 and the fourth word line WL4 and the third bit line BL3 and the fourth bit line BL4 can store a digital signal corresponding to the second digital pixel. In this case, the first digital pixel and the second digital pixel can be digital pixels that are placed in the same row and adjacent to each other at the pixel array level. In other words, as described above, in the memory cell area MCA-e (or memory cell array), the real memory cells used at one digital pixel can be connected to word lines that are not adjacent to each other and can be included in a sub-area corresponding to one digital pixel.

[0175] In addition, as mentioned above Fig. 7A or Figure 8 As described above, the shared dummy cell sDC or the shared dummy pattern area sDPA may exist between the first to fourth sub-areas sMCA1 to sMCA4 of the memory cell area MCA-e.

[0176] Fig.14A and Fig. 14B is a plan view illustrating a layout of a lower wafer and a memory cell region according to an exemplary embodiment of the inventive concept. For convenience of description, additional descriptions associated with the above-mentioned components may be omitted to avoid redundancy.

[0177] refer to Fig.14A and Fig. 14B , the lower wafer WF-df may include a plurality of second pixel circuits PXC12, PXC22, PXC32, PXC42, PXC52, and PXC62. The plurality of second pixel circuits PXC12 to PXC62 may share one memory cell area MCA-f.

[0178] The memory cell area MCA-f may include a plurality of memory cells, and the plurality of memory cells may include real memory cells RMC and dummy cells DC. As described above, the memory cell area MCA-f may be divided into a plurality of sub-arrays sMCA1 to sMCA6. The real memory cells RMC of the memory cell area MCA-f may be connected to a plurality of word lines WL1 to WL12 and a plurality of bit lines BL1 to BL4. The correspondence between the real memory cells RMC and the first digital pixel or the second digital pixel may be the same as the reference pixel. Fig.11A and Fig. 11B The corresponding relationship described is similar. In other words, the real memory cells RMC of the memory cell area MCA-f may have a structure of sharing a bit line. This is described above, so additional description will be omitted to avoid redundancy.

[0179] Different from the description given above, in Fig.14A and Fig. 14B In the memory cell area MCA-f, the dummy cell DC or the shared dummy cell sDC may not exist between the real memory cells RMC arranged along the second direction DR2. Fig. 10A and Fig. 10B A configuration in which the dummy cell DC or the shared dummy cell sDC does not exist between the real memory cells RMC arranged in the second direction DR2 is described, and thus additional description will be omitted to avoid redundancy.

[0180] In addition, as in reference Fig. 10A and Fig. 10B As in the above description given, the sub-region associated with the second pixel circuit disposed in the edge region of the lower wafer WF-df may include a dummy cell DC disposed on one side of the memory cell region facing the second direction DR2 or facing away from the second direction DR2. Fig. 10A and Fig. 10B A description thereof will be given, and thus additional description will be omitted to avoid redundancy.

[0181] Fig.15A and Fig. 15B is a plan view showing the layout of an upper wafer and a lower wafer of an image sensor device according to an exemplary embodiment of the inventive concept. For the convenience of description, additional descriptions associated with the above components may be omitted to avoid redundancy. Fig.15A and Fig. 15B , the upper wafer WF-u1 may include a plurality of first sub-pixel circuits sPD11, sPD21, sPD31, and sPD41. Each of the plurality of first sub-pixel circuits sPD11 to sPD41 ​​may include a photodetector or a photodiode configured to detect light incident from the outside. For example, each of the plurality of first sub-pixel circuits sPD11 to sPD41 ​​may include a reference FIG. 3A to FIG. 3D The photodetector PDT or the photodiode PD described above may be a plurality of first sub-pixel circuits sPD11 to sPD41 ​​that may be arranged in a row direction (eg, a first direction DR1 ) and a column direction (eg, a second direction DR2 ).

[0182] In an exemplary embodiment of the present invention, the photodetectors or photodiodes included in the same pixel group may be configured to detect light of the same color. For example, a plurality of first sub-pixel circuits sPD11 included in the first pixel group PXG1 may be configured to detect light of a first color (e.g., green (G)), a plurality of second sub-pixel circuits sPD21 included in the second pixel group PXG2 may be configured to detect light of a second color (e.g., red (R)), a plurality of third sub-pixel circuits sPD31 included in the third pixel group PXG3 may be configured to detect light of a third color (e.g., blue (B)), and a plurality of fourth sub-pixel circuits sPD41 ​​included in the fourth pixel group PXG4 may be configured to detect light of a first color (e.g., green (G)). However, the present invention is not limited thereto. For various detection patterns, various patterns of a color filter array may be formed on a plurality of sub-pixel circuits.

[0183] The lower chip WF-d1 may include a plurality of second pixel circuits sPD12, sPD22, sPD32, and sPD42. The plurality of second pixel circuits sPD12, sPD22, sPD32, and sPD42 may be arranged to overlap with the plurality of first sub-pixel circuits sPD11 to sPD41 ​​of the upper chip WF-u1. For example, the first sub-pixel circuit (e.g., sPD11) may be arranged to overlap with the second sub-pixel circuit (e.g., sPD12), respectively. The remaining second sub-pixel circuits sPD22 to sPD42 are arranged similar to those described above, and thus additional descriptions will be omitted to avoid redundancy.

[0184] The plurality of first sub-pixel circuits sPD11 to sPD41 ​​and the plurality of second sub-pixel circuits sPD12 to sPD42 may be classified into a plurality of pixel groups PXG1 to PXG4. For example, four first sub-pixel circuits sPD11 and four second sub-pixel circuits sPD12 may form a first pixel group PXG1. The first pixel group PXG1 may be used as a reference. FIG. 3A to FIG. 3D In other words, the detection signals or light signals from the four photodetectors PDT or the four photodiodes PD may be combined into one signal, and one comparison signal corresponding to the four first sub-pixel circuits sPD11 may be output through one comparator COMP. In this case, the set of digital signals corresponding to the four first sub-pixel circuits sPD11 may be stored in the storage circuit MCT. The remaining sub-pixel circuits sPD21 to sPD41 ​​and the remaining pixel groups PXG2 to PXG4 are also similar to those described above, so additional description will be omitted to avoid redundancy.

[0185] exist Fig.15A and Fig. 15B, the size or pitch of each of the first sub-pixel circuit (e.g., sPD11) and the second sub-pixel circuit (e.g., sPD12) may be "L11". The size or pitch of one pixel group (e.g., PXG1) may be "L12". As described above, since four sub-pixel circuits constitute one pixel group and one comparator is used for each pixel group, the size or pitch of one comparator may be equal to "L12" which is the size or pitch of one pixel group.

[0186] In other words, a plurality of photodetectors or a plurality of photodiodes may be included in a pixel group operating as a digital pixel, and a pixel group may include a comparator and a storage circuit. A comparator may be formed at a second sub-pixel circuit (e.g., four sub-pixel circuits sPD12) of the lower wafer WF-d1. Alternatively, a portion of a comparator may be formed in a region of a first sub-pixel circuit (e.g., four sub-pixel circuits sPD11) of the upper wafer WF-u1, and the remainder of the comparator may be formed at a second sub-pixel circuit (e.g., four sub-pixel circuits sPD12) of the lower wafer WF-d1.

[0187] In an exemplary embodiment of the present inventive concept, the four pixel groups PXG1 to PXG4 may share the memory cell area MCA. For example, because each of the four pixel groups PXG1 to PXG4 operates as a digital pixel, each of the four pixel groups PXG1 to PXG4 may use a real memory cell RMC set. In this case, as shown in FIG. Figures 1 to 14B As described, four real memory cells RMC sets may be included in one memory cell area MCA-1, and four pixel groups PXG1 to PXG4 may share one memory cell area MCA-1. Fig. 15B FIG. 1 shows a portion of the memory cell area MCA-1 (the structure of this “portion” is similar to that of Fig. 7A The memory cell region MCA-1 may be implemented in the shape of each memory cell region having the above-described various structures or layouts or in a combination thereof.

[0188] As described above, according to an exemplary embodiment of the present invention, an image sensor device may include a plurality of digital pixels. Each of the plurality of digital pixels may use a storage unit for storing digital signals. In this case, according to an exemplary embodiment of the present invention, at least two adjacent digital pixels may share a storage unit region. In this way, the size of the dummy pattern region formed in the storage unit region may be reduced, and a portion of the dummy pattern region corresponding to the reduced size may be used as a peripheral region for forming any other component. In other words, the reliability of the component formed in the peripheral region may be increased, or a component for any other additional function may also be added. Therefore, an image sensor device with reduced cost, increased reliability, and improved performance is provided.

[0189] Fig.16A It shows Figure 1 A perspective view of an image sensor device, Fig. 16B It shows Figure 1 A plan view of an image sensor device. Fig.16A and Fig. 16B An example of the image sensor device 100 according to an exemplary embodiment of the inventive concept is described in terms of a physical structure. In other words, in the following description, the inventive concept will be described with reference to a semiconductor wafer included in the image sensor device 100. In order to easily describe the inventive concept, unlike an actually implemented semiconductor wafer, semiconductor chip, semiconductor die, or semiconductor package, Fig.16A and Fig. 16B The components shown are shown schematically.

[0190] refer to Figure 1 , Fig.16A and Fig. 16B , the image sensor device 100 may include a first semiconductor wafer WF1, a second semiconductor wafer WF2, and a third semiconductor wafer WF3. The first to third semiconductor wafers WF1 to WF3 may be manufactured by different semiconductor processes or using different semiconductor wafers.

[0191] The first semiconductor wafer WF1 may be stacked on the second semiconductor wafer WF2 and may be electrically connected to the second semiconductor wafer WF2. The second semiconductor wafer WF2 may be stacked on the third semiconductor wafer WF3 and may be electrically connected to the third semiconductor wafer WF3. In other words, the second semiconductor wafer WF2 may be inserted between the first semiconductor wafer WF1 and the third semiconductor wafer WF3.

[0192] The first semiconductor wafer WF1 may include a first pixel circuit area PXCA1 and a first pad area PA1. The first pixel circuit area PXCA1 and the first pad area PA1 may be physically separated from each other or may be spaced apart from each other by a given distance.

[0193] The first pixel circuit region PXCA1 may be a region for forming a portion of the plurality of digital pixels DP. For example, as described above, the first pixel circuit region PXCA1 may include a first pixel circuit (eg, a portion of a photodetector or comparator) of each of the plurality of digital pixels DP.

[0194] The first pad area PA1 may be an area for forming a plurality of pads connected to the second pad area PA2 of the second semiconductor wafer WF2. The first pad area PA1 may be connected to components of the first pixel circuit area PXCA1 through a metal layer formed in the first semiconductor wafer WF1.

[0195] The second semiconductor wafer WF2 may include a second pixel circuit area PXCA2, a second pad area PA2, a pixel driver area PDA, and a third pad area PA3. The second pixel circuit area PXCA2 may include a second pixel circuit (e.g., a portion of a comparator or the remaining components of a pixel) of each of the plurality of digital pixels DP. In an exemplary embodiment of the inventive concept, the second pixel circuit area PXCA2 may include a reference Figures 1 to 15B Describe the memory cell area and the peripheral area.

[0196] In an exemplary embodiment of the present inventive concept, a first portion of a comparator formed in a first pixel circuit region PXCA1 of a first semiconductor wafer WF1 and a second portion of a comparator formed in a second pixel circuit region PXCA2 of a second semiconductor wafer WF2 may be bonded by a connection structure formed on a plane corresponding to the first pixel circuit region PXCA1 or the second pixel circuit region PXCA2. In an exemplary embodiment of the present inventive concept, the connection structure may be a component configured to bond a semiconductor wafer (e.g., Cu to Cu bonding, TSV, or BVS), or a material for bonding a semiconductor wafer.

[0197] The pixel driver area PDA may be an area for forming the above-described pixel driver 120. Some analog circuits such as a counter 121, a row driver 122, a ramp generator 123, and a voltage generator 124 may be formed in the pixel driver area PDA.

[0198] The second pad area PA2 may be an area for forming a plurality of pads connected to the first pad area PA1. The plurality of pads of the second pad area PA2 may be connected to the plurality of pads of the first pad area PA1, respectively, through a connection structure. In an exemplary embodiment of the present inventive concept, the connection structure may be a component configured to bond a semiconductor wafer (e.g., Cu to Cu bonding, TSV, or BVS), or a material for bonding a semiconductor wafer.

[0199] The third pad area PA3 may be an area for forming a plurality of pads connected to the third semiconductor wafer WF3.

[0200] In an exemplary embodiment of the inventive concept, various components included in the second pixel circuit area PXCA2 , the second pad area PA2 , the pixel driver area PDA, and the third pad area PA3 may be connected to each other through a metal layer of the second semiconductor wafer WF2 .

[0201] The third semiconductor wafer WF3 may include a digital logic circuit area DLA and a fourth pad area PA4. The digital logic circuit area DLA may be an area for forming the above-mentioned digital logic circuit 130. The fourth pad area PA4 may be an area for forming a plurality of pads. The plurality of pads of the fourth pad area PA4 may be connected to the plurality of pads of the third pad area PA3 respectively by a connection structure. In an exemplary embodiment of the present inventive concept, the connection structure may be a component configured to bond a semiconductor wafer (e.g., Cu to Cu bonding, TSV or BVS), or a material for bonding a semiconductor wafer.

[0202] In an exemplary embodiment of the inventive concept, the first pixel circuit area PXCA1 of the first semiconductor wafer WF1 and the second pixel circuit area PXCA2 of the second semiconductor wafer WF2 may overlap each other in the same plane area and may be areas for forming a plurality of digital pixels, for example, pixel core areas.

[0203] As the peripheral region (or peripheral circuit region), the remaining regions of the first semiconductor wafer WF1 and the second semiconductor wafer WF2, except for the first pixel circuit region PXCA1 and the second pixel circuit region PXCA2, may be regions for forming a connection structure between semiconductor wafers, or a driver circuit, an analog circuit, etc. In an exemplary embodiment of the inventive concept, a circuit or a physical component operating based on a digital signal in the image sensor device 100 may be formed in the third semiconductor wafer WF3.

[0204] As described above, in the image sensor device 100 according to the exemplary embodiment of the inventive concept, since a plurality of pixels share one memory cell region, the size of the memory cell region can be reduced. Since a portion of the memory cell region corresponding to the reduced size is used as a peripheral region, the reliability of components included in the peripheral region can be increased, and additional components for any other functions of the image sensor device 100 can also be added. Therefore, an image sensor device with reduced cost, increased reliability, and improved performance is provided.

[0205] Fig.17 is a block diagram illustrating an electronic device to which an image sensor device according to an exemplary embodiment of the inventive concept is applied. Fig.17 , the electronic device 1000 may include a touch panel 1100, a touch driver integration (TDI) circuit 1102, a display panel 1200, a display driver integration (DDI) circuit 1202, a system memory 1400, a storage device 1500, an image processor 1600, a communication block 1700, an audio processor 1800, and a main processor 1900. In an exemplary embodiment according to the inventive concept, the electronic device 1000 may be, for example, one of the following various electronic devices: a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smart phone, a tablet computer, a laptop computer, and a wearable device.

[0206] The touch driver integrated circuit 1102 may be configured to control the touch panel 1100. The touch panel 1100 may be configured to sense a touch input from a user under the control of the touch driver integrated circuit 1102. The display driver integrated circuit 1202 may be configured to control the display panel 1200. The display panel 1200 may be configured to display image information under the control of the display driver integrated circuit 1202.

[0207] The system memory 1400 may store data for operation of the electronic device 1000. For example, the system memory 1400 may temporarily store data processed or to be processed by the main processor 1900. In an exemplary embodiment of the inventive concept, output data provided from the image signal processor 1630 may be stored in the system memory 1400.

[0208] The storage device 1500 can store data regardless of whether power is supplied. For example, the storage device 1500 may include at least one of the following non-volatile memories: flash memory, phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), and ferroelectric RAM (FRAM). For example, the storage device 1500 may include an embedded memory and / or a removable memory of the electronic device 1000.

[0209] The image processor 1600 may receive light through the lens 1610. The image device 1620 and the image signal processor 1630 included in the image processor 1600 may generate image information related to an external object based on the received light. In an exemplary embodiment of the present inventive concept, the image signal processor 1630 may be a reference Figures 1 to 16B The image sensor device described herein may be based on reference Figures 1 to 16B The described method operates.

[0210] The communication block 1700 may exchange signals with an external device / system through an antenna 1710. A transceiver 1720 and a modem (eg, modulator / demodulator) 1730 of the communication block 1700 may process signals exchanged with an external device / system according to one or more of various wired / wireless communication protocols.

[0211] The audio processor 1800 may process an audio signal using an audio signal processor 1810. The audio processor 1800 may receive an audio input through a microphone 1820, or may provide an audio output through a speaker 1830.

[0212] The main processor 1900 may control the overall operation of the electronic device 1000. The main processor 1900 may control / manage the operations of the components of the electronic device 1000. The main processor 1900 may process various operations in order to operate the electronic device 1000. In an exemplary embodiment of the inventive concept, Fig.17 A portion of the components may be implemented in the form of a system on chip and may be provided as an application processor (AP) of the electronic device 1000 .

[0213] According to an exemplary embodiment of the present invention, digital pixels included in an image sensor device share a memory cell area or a memory cell array. In this way, the size of a dummy pattern area or a dummy cell necessary to maintain the reliability of the memory cell can be reduced, and a portion of the dummy pattern area corresponding to the reduced size can be used as a peripheral area in which other components can be set. As the size of the peripheral area increases, the reliability of the components formed in the peripheral area can be increased. In addition, other types of components for realizing additional functions of digital pixels can also be added to the peripheral area. Therefore, an image sensor device with reduced cost, increased reliability and improved performance is provided.

[0214] While the inventive concepts have been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the inventive concepts as set forth in the appended claims.

Claims

1. An image sensor device, comprising: a first digital pixel comprising a first photodetector and a first storage unit, the first storage unit being configured to store a first digital signal corresponding to a first output from the first photodetector; as well as a second digital pixel comprising a second photodetector and a second storage unit, the second storage unit being configured to store a second digital signal corresponding to a second output from the second photodetector, The second digital pixel is adjacent to one side of the first digital pixel along a first direction, The first storage unit and the second storage unit are connected to a plurality of bit lines. Wherein, the first storage unit is connected to the first word line and the third word line, The second storage unit is connected to the second word line and the fourth word line. The second word line is between the first word line and the third word line. The third word line is between the second word line and the fourth word line, and The first memory cell and the second memory cell are included in a single memory cell array.

2. The image sensor device according to claim 1, wherein: The first word line is electrically connected to a first word line contact, and the third word line is electrically connected to a third word line contact, wherein the first word line contact and the third word line contact are on one side of the first memory cell, and The second word line is electrically connected to a second word line contact, and the fourth word line is electrically connected to a fourth word line contact, wherein the second word line contact and the fourth word line contact are on a side of the second memory cell opposite to the side of the first memory cell.

3. The image sensor device according to claim 2, wherein: Each of a first distance between the first word line contact and the third word line contact and a second distance between the second word line contact and the fourth word line contact is greater than each of a distance between the first word line and the second word line, a distance between the second word line and the third word line, and a distance between the third word line and the fourth word line.

4. The image sensor device according to claim 1, further comprising: a third digital pixel, comprising a third photodetector and a third storage unit, the third storage unit being configured to store a third digital signal corresponding to a third output from the third photodetector, the third digital pixel being adjacent to one side of the first digital pixel along the second direction; as well as a fourth digital pixel, comprising a fourth photodetector and a fourth storage unit, the fourth storage unit being configured to store a fourth digital signal corresponding to a fourth output from the fourth photodetector, the fourth digital pixel being adjacent to one side of the second digital pixel along the second direction, The third storage unit and the fourth storage unit are connected to the plurality of bit lines. The third storage unit is connected to the fifth word line and the seventh word line, and the fourth storage unit is connected to the sixth word line and the eighth word line, and The fifth word line is between the fourth word line and the sixth word line, the seventh word line is between the sixth word line and the eighth word line, and the sixth word line is between the fifth word line and the seventh word line.

5. The image sensor device according to claim 4, wherein: The fifth word line is electrically connected to a fifth word line contact, and the seventh word line is electrically connected to a seventh word line contact, wherein the fifth word line contact and the seventh word line contact are on one side of the third memory cell, and The sixth word line is electrically connected to a sixth word line contact, and the eighth word line is electrically connected to an eighth word line contact, wherein the sixth word line contact and the eighth word line contact are on one side of the fourth memory cell.

6. The image sensor device according to claim 4, wherein: The first memory cell, the second memory cell, the third memory cell, and the fourth memory cell are included in a single memory cell array, and Wherein, the single storage cell array further comprises: a first dummy pattern region on one side of the first word line, wherein the first dummy pattern region extends along the first direction; a second dummy pattern region on one side of the eighth word line, wherein the second dummy pattern region extends along the first direction; a third dummy pattern region on one side of the first to fourth storage units, wherein the third dummy pattern region extends along the second direction; and A fourth dummy pattern region is on one side of the first to fourth storage cells, wherein the fourth dummy pattern extends along the second direction, and the fourth dummy pattern region and the third dummy pattern region are opposite to each other.

7. The image sensor device according to claim 6, wherein: The single memory cell array further comprises: A shared dummy pattern region is between the fourth word line and the fifth word line.

8. The image sensor device according to claim 1, further comprising: a counter configured to provide a digital code to the plurality of bit lines; a row driver configured to output first and second photodetector control signals for controlling the first and second photodetectors and first and second memory control signals for controlling the first and second memory cells; as well as A ramp generator is configured to generate a ramp signal, wherein the first photodetector is configured to output the first output in response to the first photodetector control signal, and Wherein, the second photodetector is configured to output the second output in response to the second photodetector control signal.

9. The image sensor device according to claim 8, wherein: The first digital pixel further includes: a first comparator configured to compare the first output from the first photodetector with the ramp signal and output a first comparison signal, and The second digital pixel further includes: a second comparator configured to compare the second output from the second photodetector with the ramp signal and output a second comparison signal.

10. The image sensor device according to claim 9, wherein: The first storage unit is configured to store the digital code provided through the plurality of bit lines as the first digital signal in response to the first memory control signal and the first comparison signal, and The second storage unit is configured to store the digital code provided through the plurality of bit lines as the second digital signal in response to the second memory control signal and the second comparison signal.

11. The image sensor device according to claim 8, further comprising: Shared comparator, configured as: comparing the first output from the first photodetector with the ramp signal to output a first comparison signal; as well as The second output from the second photodetector is compared with the ramp signal to output a second comparison signal.

12. The image sensor device according to claim 1, wherein: The first photodetector includes: a plurality of first photodiodes configured to detect light of a first color incident from outside the image sensor device, and The second photodetector includes: a plurality of second photodiodes configured to detect light of a second color incident from the outside.

13. An image sensor device, comprising: a first digital pixel comprising a first photodetector and a first storage unit, the first storage unit being configured to store a first digital signal corresponding to a first output from the first photodetector; as well as a second digital pixel comprising a second photodetector and a second storage unit, the second storage unit being configured to store a second digital signal corresponding to a second output from the second photodetector, The second digital pixel is adjacent to a first side of the first digital pixel along a first direction, wherein the first memory cell and the second memory cell are included in a single memory cell array and formed on a first semiconductor wafer, Wherein, the first semiconductor wafer comprises: A first region including the first storage unit; a second region, comprising the second storage unit, wherein the second region is adjacent to the first region along the first direction; a first shared dummy pattern region between a first side of the first region and a second side of the second region; a first dummy pattern region adjacent to a second side of the first region opposite to the first side of the first region; and a second dummy pattern region adjacent to a first side of the second region opposite to the second side of the second region, and The first width of the first shared dummy pattern region in the first direction is less than twice the second width of the first dummy pattern region in the first direction or twice the third width of the second dummy pattern region in the first direction.

14. The image sensor device according to claim 13, wherein: The first memory cell is connected to a first bit line and a first word line, and the second memory cell is connected to a second bit line and a second word line.

15. The image sensor device according to claim 14, wherein: At least one of the first memory cells and at least one of the second memory cells are in the same row, and Wherein, the first shared dummy pattern area includes: at least one isolated dummy unit, the at least one isolated dummy unit is in the same row as the at least one first storage unit in the first storage unit and the at least one second storage unit in the second storage unit, and is not connected to the first word line and the second word line.

16. The image sensor device according to claim 13, further comprising: a third digital pixel, comprising a third photodetector and a third storage unit, the third storage unit being configured to store a third digital signal corresponding to a third output from the third photodetector, the third digital pixel being adjacent to a second side of the first digital pixel along a second direction; as well as a fourth digital pixel, comprising a fourth photodetector and a fourth storage unit, the fourth storage unit being configured to store a fourth digital signal corresponding to a fourth output from the fourth photodetector, the fourth digital pixel being adjacent to a second side of the second digital pixel along the second direction, The third storage unit and the fourth storage unit are formed on the first semiconductor wafer. Wherein, the first semiconductor wafer further comprises: a third region including the third storage unit and adjacent to the first region along the second direction; a fourth region, including the fourth storage unit and adjacent to the third region along the first direction; a second shared dummy pattern region between the first side of the third region and the first side of the fourth region; a third dummy pattern region adjacent to a second side of the third region opposite to the first side of the third region; and a fourth dummy pattern region adjacent to a second side of the fourth region opposite to the first side of the fourth region, and The fourth width of the second shared dummy pattern region in the first direction is less than twice the fifth width of the third dummy pattern region in the first direction or twice the sixth width of the fourth dummy pattern region in the first direction.

17. The image sensor device according to claim 16, wherein: The first semiconductor wafer further comprises: a fifth dummy pattern region on one side of the first region and the second region; a sixth dummy pattern region on one side of the third region and the fourth region, wherein the fifth dummy pattern region and the sixth dummy pattern region are opposite to each other; and a third shared dummy pattern region between the first region and the second region and the third region and the fourth region, and The seventh width of the third shared dummy pattern region in the second direction is less than twice the eighth width of the fifth dummy pattern region in the second direction or twice the ninth width of the sixth dummy pattern region in the second direction.

18. The image sensor device according to claim 16, wherein: The first photodetector, the second photodetector, the third photodetector, and the fourth photodetector are formed on a second semiconductor wafer, and wherein the first semiconductor chip is stacked on the second semiconductor chip such that an area where the first photodetector is formed overlaps with the first area, an area where the second photodetector is formed overlaps with the second area, an area where the third photodetector is formed overlaps with the third area, and an area where the fourth photodetector is formed overlaps with the fourth area.

19. An image sensor device comprising: a first digital pixel comprising a first photodetector and a first storage unit, wherein the first storage unit is configured to store a first digital signal corresponding to a first detection signal from the first photodetector; as well as a second digital pixel comprising a second photodetector and a second storage unit, wherein the second storage unit is configured to store a second digital signal corresponding to a second detection signal from the second photodetector, The second digital pixel is adjacent to the first digital pixel along a first direction, and The first memory cell and the second memory cell are included in a single memory cell array.

20. The image sensor device according to claim 19, wherein: The first memory cell is connected to a first word line and a plurality of bit lines, and The second storage unit is connected to the second word line and the plurality of bit lines.

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