Semiconductor memory device employing in-memory processing and method of operation thereof

Abstract

Disclosed are a semiconductor memory device employing in-memory processing and an operating method thereof. The semiconductor memory device includes a plurality of banks including a first bank group including a computing circuit and a second bank group having no computing circuit, and a control circuit configured to control a PIM operation by the first bank group to be performed together with processing of a memory request to the plurality of banks, in a case where a maximum power consumption condition of the semiconductor memory device is satisfied.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-012568, filed on October 10, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] The following description relates to a semiconductor memory device employing processing in memory (PIM) and a method of operating the semiconductor memory device. Background Technology

[0003] Existing semiconductor memory devices have functions completely separated from the processor that performs arithmetic operations. Therefore, in systems implementing applications such as neural networks, big data, and the Internet of Things (IoT) (where massive amounts of data need to be processed), large amounts of data are sent or received between the semiconductor memory device and the processor, frequently leading to bottlenecks. To address this issue, research is underway on processing in memory (PIM), which combines the functions of the processor for performing arithmetic operations with the functions of memory, functioning as a semiconductor memory device. Summary of the Invention

[0004] This summary is provided to introduce, in a simplified form, the selection of concepts that will be further described in the detailed embodiments below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0005] In one general aspect, a semiconductor memory device employing processing in memory (PIM) includes: a plurality of memory banks, including a first group of memory banks containing computing circuitry and a second group of memory banks not having computing circuitry; and control circuitry configured to: control the PIM operations performed by the first group of memory banks to be executed together with the processing of memory requests to the plurality of memory banks, provided that a maximum power consumption condition of the semiconductor memory device is met.

[0006] The control circuit can adjust and / or pause the PIM operation performed by the first memory bank group to ensure that the sum of the power consumed by the processing of memory requests and the power consumed by the PIM operation meets the maximum power consumption condition.

[0007] The control circuit may include a request counter that counts memory requests for each of the plurality of memory banks according to a predetermined time period, and the control circuit may schedule the processing of memory requests and PIM operations based on the number counted by the request counter.

[0008] When the number of requests counted by the request counter that corresponds to the second memory bank is equal to or greater than a preset threshold, the control circuit may slow down the PIM operation performed by the first memory bank in order to process the memory request for the second memory bank.

[0009] When the first memory bank group includes a first memory bank and a second memory bank, and the number of the number counted by the request counter that corresponds to the first memory bank is equal to or greater than a preset threshold, the control circuit can pause the PIM operation performed by the first memory bank and slow down the PIM operation performed by the second memory bank in order to process the memory request for the first memory bank.

[0010] The control circuit can broadcast commands to the first memory group to indicate the adjustment or suspension of PIM operations performed by the first memory group according to a preset timing.

[0011] The number of memory cells included in the first memory cell group among the plurality of memory cells can be configured such that when all memory cells included in the first memory cell group perform a read operation for PIM calculation, the power consumed by the semiconductor memory device satisfies the maximum power consumption condition.

[0012] Each of the plurality of memory banks may include one or more dynamic random access memory (DRAM) arrays, and the memory request may be a DRAM request including at least one of read, write, copy, and erase.

[0013] The computing circuitry included in the first memory bank can perform calculations using data read from the corresponding memory bank, and rewrite the results of the calculations to the corresponding memory bank or output the results to the outside.

[0014] The computing circuit may include hardware that performs at least one of arithmetic operations, logical operations, and shift operations.

[0015] In another general aspect, a method of operating a semiconductor memory device employing processing in memory (PIM) includes: processing memory requests for a plurality of memory banks, the plurality of memory banks including a first group of memory banks containing computing circuitry and a second group of memory banks not having computing circuitry; and controlling the PIM operations performed by the first group of memory banks to be executed together with the processing of the memory requests, provided that a maximum power consumption condition of the semiconductor memory device is met.

[0016] In another general aspect, a non-transitory computer-readable recording medium having one or more programs, including instructions, recorded thereon performs the method described above.

[0017] In another general aspect, a semiconductor memory device includes: a first memory bank including computing circuitry configured to perform in-memory processing (PIM) operations; a second memory bank that processes one or more memory requests concurrently with the PIM operations; and control circuitry that controls the PIM operations such that the sum of the power consumed in processing the one or more memory requests and the power consumed in the PIM operations does not exceed a maximum threshold.

[0018] A first memory bank may be included in a first memory bank group having two or more memory banks, and each memory bank in the first memory bank group may include computing circuitry. A second memory bank may be included in a second memory bank group having two or more memory banks, and all memory banks in the second memory bank group may not include computing circuitry.

[0019] A first memory cell may be included in a first memory cell group having two or more memory cells, and the two or more memory cells in the first memory cell group may include a third memory cell that does not contain computing circuitry. A second memory cell may not contain computing circuitry, and a second memory cell may be included in a second memory cell group having two or more memory cells, and the two or more memory cells in the second memory cell group may include a fourth memory cell that contains computing circuitry.

[0020] Other features and aspects will become clear from the following detailed description, drawings, and claims. Attached Figure Description

[0021] Figure 1 It is a block diagram of a semiconductor memory device based on an example.

[0022] Figure 2 This is a block diagram of an example semiconductor memory device.

[0023] Figure 3 This is a diagram illustrating an example of a memory bank that includes computing circuitry.

[0024] Figure 4 This is a diagram illustrating an example of the specific circuit structure of a Processing In-Memory (PIM) arithmetic unit.

[0025] Figure 5 It is a diagram used to describe the scheduling process based on the example.

[0026] Figure 6 This is a table showing examples of commands used in scheduling processes.

[0027] Figure 7 This is a timing diagram corresponding to an example of scheduling processing.

[0028] Figure 8 It is a block diagram of the electronic system based on the example.

[0029] Figure 9 This is a flowchart illustrating a method for operating a semiconductor memory device according to an example.

[0030] Throughout the accompanying drawings and detailed embodiments, unless otherwise described or provided, the same reference numerals will be understood to denote the same elements, features, and structures. The drawings may not be to scale, and for clarity, illustration, and convenience, the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated. Detailed Implementation

[0031] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those set forth herein, but may be varied as will become clear upon understanding this disclosure, except for operations that must occur in a specific order. Furthermore, for clarity and brevity, descriptions of features known upon understanding this disclosure may be omitted.

[0032] The features described herein may be implemented in different forms and are not to be construed as limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many feasible ways of implementing the methods, apparatus, and / or systems described herein that will be clear upon understanding the disclosure of this application.

[0033] Throughout this specification, when a component is described as "connected to" or "bonded to" another component, the component may be directly "connected to" or "bonded to" the other component, or there may be one or more other components in between. Conversely, when an element is described as "directly connected to" or "directly bonded to" another element, there may be no other elements in between. Similarly, similar expressions (e.g., "between" and "immediately between," and "adjacent to" and "right next to") will be interpreted in the same manner. As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more.

[0034] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts should not be limited by these terms. Rather, these terms are used only to distinguish one component, assembly, region, layer, or part from another. Thus, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part referred to as a second component, second assembly, second region, second layer, or second part may also be referred to as a second component, second assembly, second region, second layer, or second part.

[0035] The terminology used herein is for the purpose of describing various examples only and is not intended to limit disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. The terms “comprising,” “including,” and “having” indicate the presence of the features, quantities, operations, components, elements, and / or combinations thereof stated therein, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and as commonly understood based on an understanding of the disclosure of this application. Unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant art and in the disclosure of this application, and shall not be interpreted ideally or overly formally. The use of the term "may" (e.g., regarding what an example or embodiment may include or implement) with respect to examples or embodiments indicates that there exists at least one example or embodiment that includes or implements such a feature, and that all examples are not limited thereto.

[0037] Figure 1 This is a block diagram based on the example semiconductor memory device 10.

[0038] Reference Figure 1 The semiconductor memory device 10, which employs processing in memory (PIM) as a memory device, may include multiple memory banks and control circuitry 130. Figure 1 Only some components are shown in the semiconductor memory device 10. The semiconductor memory device 10 may also include, in addition to Figure 1 Other general components besides those shown. For example, the semiconductor memory device 10 may also include an internal memory bus. The internal memory bus may represent a data transfer path configured to send and receive data between components in the semiconductor memory device 10.

[0039] Multiple memory banks may include a first memory bank group 110 and a second memory bank group 120. The first memory bank group 110 may include one or more memory banks containing computing circuitry. For example, the first memory bank group 110 may include a memory bank 110a containing computing circuitry 115a and a memory bank 110b containing computing circuitry 115b. Each of memory banks 110a and 110b includes either computing circuitry 115a or computing circuitry 115b, thus enabling memory banks 110a and 110b to perform PIM operations and process normal memory requests.

[0040] A memory request may represent an inherent memory operation including at least one of reading, writing, copying, and erasing. A PIM operation may represent a computational operation including at least one of arithmetic operations (such as addition, multiplication, and accumulation) and logical operations (such as AND, OR, and XOR). In one example, when the semiconductor memory device 10 is used to implement a recurrent neural network (RNN), the PIM operation may be a matrix-vector multiplication operation, but is not necessarily limited to this.

[0041] Each of the computing circuits 115a and 115b may represent hardware performing computational operations within memory banks 110a and 110b. For example, each of the computing circuits 115a and 115b may include an arithmetic logic unit (ALU) as hardware performing at least one of arithmetic operations, logical operations, and shift operations, and the computational operations may include, but are not limited to, function operations such as addition, subtraction, integration, and accumulation. Each of the computing circuits 115a and 115b may be implemented as an array of multiple logic gates, or as a combination of an array of logic gates and a buffer for temporary data storage. Each of the computing circuits 115a and 115b may perform operations using data read from memory bank 110a corresponding to computing circuit 115a or memory bank 110b corresponding to computing circuit 115b, and write the result of the operation back to the corresponding memory bank 110a or 110b.

[0042] The second memory bank group 120 may include one or more memory banks that do not contain computing circuitry. For example, the second memory bank group 120 may include memory bank 120a and memory bank 120b. Memory bank 120a and memory bank 120b do not contain computing circuitry, therefore memory bank 120a and memory bank 120b cannot perform PIM operations and can only process memory requests.

[0043] As described above, the semiconductor memory device 10 according to the example includes both a first memory bank group 110 containing computing circuitry and a second memory bank group 120 not containing computing circuitry, thereby performing PIM operations simultaneously with memory request processing. Therefore, the semiconductor memory device 10 can operate as a memory and simultaneously as an accelerator for driving neural networks, thus making it suitable for systems requiring simultaneous processing of memory requests, critical latency, or operation on large amounts of data.

[0044] Furthermore, semiconductor memory devices can be determined during manufacturing to have maximum power consumption conditions for normal operation. However, the problem is that conventional semiconductor memory devices employing PIM do not consider maximum power consumption conditions, and therefore are either not practically implemented or only implemented under ideal conditions. In contrast, the semiconductor memory device 10 according to the example is configured to simultaneously perform memory request processing and PIM operations while satisfying the maximum power consumption conditions.

[0045] For example, the control circuit 130 can control the PIM operation performed by the first memory bank group 110 to be performed together with the processing of memory requests for multiple memory banks while satisfying the maximum power consumption condition of the semiconductor memory device 10. The control circuit 130 can control the sum of the power consumed by processing memory requests and the power consumed by the PIM operation to be within the maximum power consumption condition by adjusting and / or pausing the PIM operation performed by the first memory bank group 110. Furthermore, the number of memory banks included in the first memory bank group 110 can be determined such that when all memory banks included in the first memory bank group 110 perform read operations for the PIM operation, the power consumed by the semiconductor memory device 10 is within the maximum power consumption condition. Hereinafter, a method for operating the semiconductor memory device 10 according to the example while considering the maximum power consumption condition will be described in detail with reference to the accompanying drawings.

[0046] exist Figure 1 In this example, the first memory group 110 includes two memory banks (i.e., memory banks 110a and 110b), and the second memory group 120 also includes two memory banks (i.e., memory banks 120a and 120b), but this is only an example. Each of the first memory group 110 and the second memory group 120 may include only one memory bank or may include more than two memory banks.

[0047] Figure 2 This is a block diagram of an example of a semiconductor memory device 20 according to some embodiments.

[0048] Reference Figure 2 Semiconductor memory device 20 is shown as Figure 1An example of a semiconductor memory device 10. The semiconductor memory device 20 may include two memory channels: Channel 0 and Channel 1. Each of the memory channels Channel 0 and Channel 1 may include multiple memory banks and control circuitry. For example, memory channel Channel 0 may include multiple memory banks Bank 0 through Bank 7 and may include control circuitry 0. Memory channel Channel 1 may include multiple memory banks Bank 8 through Bank 15 and may include control circuitry 1.

[0049] like Figure 2 As shown, among the memory banks Bank 0 to Bank 7 included in memory channel 0, memory banks Bank 2 to Bank 5 may include computing circuitry, while memory banks Bank 0, Bank 1, Bank 6, and Bank 7 may not include computing circuitry. Among the memory banks Bank 8 to Bank 15 included in memory channel 1, memory banks Bank 10 to Bank 13 may include computing circuitry, while memory banks Bank 8, Bank 9, Bank 14, and Bank 15 may not include computing circuitry. Figure 2 The black blocks in the memory can be represented as... Figure 1 The computing circuit shown.

[0050] Storage banks 2 to 5 and 10 to 13 can correspond to Figure 1 The first storage group 110, storage banks Bank 0, Bank 1, Bank 6 to Bank 9, Bank 14 and Bank 15 can correspond to Figure 1 The second memory bank 120, and control circuits 0 and 1 may correspond to Figure 1 The control circuit 130. Memory channels Channel 0 and Channel 1 can be configured in the same way and can operate in parallel with each other. Figure 2 The example only shows two memory channels, but this is only for the sake of description. Figure 1 Semiconductor memory device 10 or Figure 2 The semiconductor memory device 20 may include a single memory channel or may include a greater number of memory channels that operate in parallel with each other. Furthermore, in Figure 2 In the example, eight memory banks are included in a single memory channel, but this is only for the sake of description. The memory banks included in a single memory channel are not limited to this example.

[0051] Of the sixteen memory banks included in memory channels Channel 0 and Channel 1, only eight banks may include computing circuitry. PIM operations can consume more power than typical memory request processing; therefore, the maximum power consumption condition of the semiconductor memory device 20 will not be met when all sixteen memory banks include computing circuitry and perform PIM operations. Therefore, the semiconductor memory device 20 according to the example can perform PIM operations by arranging computing circuitry only in some memory banks to achieve maximum performance while minimizing area overhead within the available design space.

[0052] For example, assuming all memory banks including the computing circuitry simultaneously perform read operations for PIM calculations, the number of memory banks including the computing circuitry is limited to eight, such that the power consumed by driving the semiconductor memory device 20 does not exceed the maximum power consumption condition. The number eight is merely an example, and the examples are not limited thereto. The number of memory banks including the computing circuitry can be determined based on the maximum power consumption condition of the semiconductor memory device 20.

[0053] Figure 3 This is a diagram showing an example of a memory bank 30 that includes computing circuitry.

[0054] Reference Figure 3 In an example where the semiconductor memory device 20 is dynamic random access memory (DRAM), a memory bank 30 including computing circuitry is shown. The memory bank 30 may correspond to... Figure 1 Storage units 110a and 110b, or Figure 2 The storage bank 30 may include each of Banks 2 to 5 and Banks 10 to 13. The storage bank 30 may include a DRAM cell array 310 configured as one or more DRAM arrays. In this case, a memory request to the storage bank 30 may correspond to a DRAM request including at least one of read, write, copy, and delete.

[0055] Row decoder 320 and column decoder 330 can be configured to select specific memory cells included in the DRAM cell array 310 of memory bank 30. When row decoder 320 selects a row direction word line based on a received row address, and column decoder 330 selects a column direction bit line based on a received column address, the memory cells corresponding to the selected row direction word line and column direction bit line can be selected. Row decoder 320 and column decoder 330 include Figure 3 The storage bank 30 is used, but this is only an example. Depending on the method of defining the storage bank 30, the row decoder 320 and the column decoder 330 may be located outside the storage bank 30.

[0056] The Global Input / Output Sensing Amplifier (GIO SA) 340 can be used as a buffer to temporarily store data read from the DRAM cell array 310. The GIO SA 340 can transfer the data read from the DRAM cell array 310 to the Multiply-Accumulate Unit (MAC) 350. The MAC 350 can correspond to... Figure 1 Each of the calculation circuits 115a and 115b. The MAC 350 can use data sent from the GIO SA 340 to perform calculations and output the results of the calculations. In the following text, for ease of description, the GIO SA 340 and the MAC 350 are referred to as the PIM arithmetic unit 40.

[0057] Figure 4 This is a diagram illustrating an example of the specific circuit structure of the PIM arithmetic unit 40.

[0058] Reference Figure 4 The diagram illustrates the specific circuit structure of a PIM arithmetic unit 40 in an example of a semiconductor memory device performing matrix-vector multiplication. According to one example, a DRAM array can be configured to store 256 bits of data corresponding to at least one row of a matrix, and a GIO SA 41 can receive 256-bit read data (256-bit RD data) from the DRAM array. The DRAM array can include multiple DRAM cells, and each of the multiple DRAM cells can store one bit of data. One or more DRAM cells can collectively represent one data entry. For example, 16-bit data can include 16 DRAM cells. The 16-bit data corresponding to the 16 DRAM cells can correspond to each element of the matrix and can be transferred to the corresponding MAC 42 and used as an operand. Input vector data, as another operand for the operation, can be input via data input / output path data I / O. The input vector data can be stored in input vector static random access memory (SRAM) 43 and then transferred to each MAC 42. Each MAC 42 can perform operations on the matrix data transferred from the DRAM array and the input vector data transferred from the input vector SRAM 43, and output the operation result. The results of operations output from each MAC 42 can be summed via the adder tree 44, and the output vector data corresponding to the final operation result can be stored in the output vector SRAM 45. The output vector data stored in the output vector SRAM 45 can be output to the outside via the data input / output path data I / O 46, and can be used again for operations via the input vector SRAM 43. The PIM arithmetic unit 40 may include a command generator unit 47, which receives commands from the control circuit (e.g., Figure 2The control circuit 0 or control circuit 1 sends the DRAM command and address, and then converts the command into a more detailed subcommand.

[0059] As described above, the memory bank 30, including the PIM operation unit 40, can be used to perform the operations required for neural network implementation, but it can also be used to handle general memory requests. However, after data for PIM operations is read from one DRAM array, in order to read data for memory request processing from another DRAM array, the data for PIM operations needs to be precharged (PRE) and then the data for memory request processing needs to be activated (ACT). The time required for reactivation after precharging is quite long, so it is desirable to minimize the number of times switching between PIM operations and memory request processing.

[0060] When prioritizing PIM operations to minimize the number of switches between PIM operations and memory request processing, memory request processing may become unavailable, and the efficiency of PIM operations may be excessively degraded when prioritizing memory request processing. Therefore, a technique may be needed that enables simultaneous execution of memory request processing while performing PIM operations as efficiently as possible. According to example semiconductor memory devices (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 The semiconductor memory device 20) can be scheduled to process memory requests simultaneously while performing PIM operations as efficiently as possible. In the following text, reference will be made to... Figure 5 Detailed description of a semiconductor memory device according to an example (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 Scheduling of the semiconductor memory device 20).

[0061] Figure 5 It is a diagram used to describe the scheduling process based on the example.

[0062] Reference Figure 5 It shows that it includes Figure 2 The example of memory channel 0 in semiconductor memory device 20 performing simultaneous processing of memory requests by scheduling PIM operations as efficiently as possible. (See reference...) Figure 5 Only memory channel 0 is described, but the same content can be applied equivalently to other memory channels (e.g., memory channel 1) that may be included in the semiconductor memory device 20.

[0063] Figure 5The first graph 510 illustrates the state of the memory bank over time. In the first graph 510, "normal memory bank" represents a memory bank that does not include computing circuitry and can only perform memory request processing; "MV-mul" represents a memory bank that includes computing circuitry and is capable of performing PIM operations, performing matrix-vector multiplication operations such as PIM operations. Furthermore, "slow down" indicates a memory bank that includes computing circuitry and is capable of performing PIM operations slowing down its PIM operations; and "pause" indicates a memory bank that includes computing circuitry and is capable of performing PIM operations pausing its PIM operations. Figure 2 As shown, only storage banks Bank 2 to Bank 5 include computing circuitry. Figure 5 In the diagram, storage banks Bank 0 to Bank 7 are abbreviated as B0 to B7, respectively.

[0064] The second chart 520 shows the status of the memory request queues for the memory bank in chronological order and indicates the memory requests that need to be processed within a specific interval IV. In the request queues on the second chart 520, higher requests represent older memory requests, and lower requests represent newer memory requests.

[0065] The third figure, 530, shows the number of accumulated requests for each memory bank. The number of accumulated requests for each memory bank can be counted by a request counter. When the number counted by the request counter is equal to or greater than a preset threshold, processing of the memory request for the memory bank corresponding to that number can be performed. The preset threshold can be determined to be a value set to prevent excessive delay in memory request processing while giving priority to PIM operations. Figure 5 In this context, "MViD" indicates a memory bank that includes computing circuitry, while "No MViD" indicates a memory bank that does not include computing circuitry.

[0066] Referenced in chronological order Figure 5 In the first chart 510, the second chart 520, and the third chart 530, memory request processing requests for storage banks Bank 2, Bank 3, Bank 0, and Bank 7 are accumulated on a request queue, and the number counted by the request counter is updated in the first interval 1IV. The number of accumulated requests for storage banks Bank 0 and Bank 7 (excluding computing circuitry) is 2, and the number of accumulated requests for each of storage banks Bank 2 and Bank 3 is 1. Figure 5 In the example, when the threshold is 4, there are no storage banks in the first interval 1IV with an accumulated number of requests equal to or greater than the threshold. Therefore, in the first interval 1IV, PIM operations performed by storage banks Bank 2 to Bank 5 can be executed consecutively.

[0067] Between the first interval 1IV and the second interval 2IV, new memory request processing requests for memory bank Bank 3 are accumulated in the request queue, and the number counted by the request counter is updated in the second interval 2IV. The number of accumulated requests for memory banks Bank 0 and Bank 7 is equal to or greater than a threshold of 4. Therefore, in the second interval 2IV, memory request processing for memory banks Bank 0 and Bank 7, which do not include computing circuitry, can be performed.

[0068] When PIM operations from Bank 2 to Bank 5 are performed in the same manner, and memory requests from Bank 0 and Bank 7 are added, the maximum power consumption condition may no longer be met. Therefore, in order to meet the maximum power consumption condition while simultaneously processing memory requests from Bank 0 and Bank 7 and continuously performing PIM operations from Bank 2 to Bank 5, the PIM operations from Bank 2 to Bank 5 can be slowed down. The power reduction achieved by slowing down the PIM operations from Bank 2 to Bank 5 may correspond to, but is not necessarily limited to, the power consumption required to process memory requests from Bank 0 and Bank 7.

[0069] In the third interval 3IV, since memory requests for banks 0 and 7 are processed, only memory requests for banks 2 and 3 are retained in the request queue, and the count by the request counter is updated. The number of accumulated requests for bank 3 is equal to or greater than a threshold of 5. Therefore, memory request processing for bank 3 can be performed in the third interval 3IV. Because bank 3 is an MViD, PIM operations performed on bank 3 must be paused to process memory requests for bank 3. Furthermore, in order to meet the maximum power consumption condition while simultaneously performing memory request processing and PIM operations on bank 3, PIM operations performed on banks 2, 4, and 5 can be slowed down.

[0070] As mentioned above, including Figure 1 Semiconductor memory device 10 or Figure 2 The control circuit in the semiconductor memory device 20 (e.g., Figure 1 Control circuit 130 or Figure 2Each of the control circuits (Control circuit 0 and Control circuit 1) may also include a request counter that counts memory requests for each of the plurality of memory banks according to a predetermined time period, and schedules the processing of memory requests and PIM operations based on the number counted by the request counter.

[0071] When the number counted by the request counter is among the group of memory banks that do not include the calculation circuitry (e.g., Figure 1 Second memory group 120 or Figure 2 When the number of memory banks (Bank0, Bank1, Bank6 to Bank9, Bank14 and Bank15) is equal to or greater than a preset threshold, in order to process memory requests for the group of memory banks that do not include computing circuitry, the control circuit (e.g., Figure 1 Control circuit 130 or Figure 2 Each of Control circuit 0 and Control circuit 1 can slow down the group of memory containing computing circuitry (e.g., Figure 1 First memory group 110 or Figure 2 The PIM operation is performed on the storage banks Bank 2 to Bank 5 and Bank 10 to Bank 13.

[0072] When a group of memory cells includes computing circuitry (e.g., Figure 1 First memory group 110 or Figure 2 The memory banks Bank2 to Bank5 and Bank10 to Bank13 include a third memory bank and a fourth memory bank. When the number of requests corresponding to the third memory bank, counted by the request counter, is equal to or greater than a preset threshold, in order to process the memory request for the third memory bank, the control circuit (e.g., ...) Figure 1 Control circuit 130 or Figure 2 Each of the control circuits (Control circuit 0 and Control circuit 1) can pause the PIM operation performed by the third memory bank and slow down the PIM operation performed by the fourth memory bank. When the PIM operation is paused, the memory bank can store the operation result up to the current time, precharge the currently active DRAM row, and then activate the DRAM row corresponding to the memory request to process the memory request.

[0073] As described above, according to the example semiconductor memory device (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 The semiconductor memory device 20) can perform PIM operations and memory request processing simultaneously as efficiently as possible through scheduling. Figure 5It is only used to describe semiconductor memory devices (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 This is an example of scheduling processing performed by a semiconductor memory device 20, but it is not limited to this, and scheduling can be performed in other scenarios in a similar manner to that described above.

[0074] Figure 6 Table 610 shows examples of commands used in scheduling processes, based on examples.

[0075] In order to enable the semiconductor memory device according to the example (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 The semiconductor memory device 20) performs the above scheduling, and in addition to the commands commonly used in existing DRAM (e.g., PRE command for precharging data, ACT command for activating data, RD command for reading data, etc.), it must add or change sub-commands. Figure 6 Table 610 shows examples of commands that need to be added or modified to execute the scheduling. In Table 610, the memory controller (MC) may represent commands included in a semiconductor memory device (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 The memory controller, command control unit (CCU), is located in the main processor outside the semiconductor memory device 20. It may be included in the control circuitry (e.g., Figure 1 Control circuit 130 or Figure 2 The logic in the control circuits Control circuit 0 and Control circuit 1).

[0076] The CCU receives commands from the MC of the main processor and transmits them to the Command Generator Unit (CGU) in each memory bank. The CGU receives DRAM commands as well as commands and addresses regarding PIM operations and translates the commands and addresses into more detailed subcommands.

[0077] The command "MV-mul" can be issued from the memory controller and can indicate the command used to begin a matrix-vector multiplication operation. In this example, because the PIM operation is a matrix-vector multiplication operation, although the command used to begin the operation in memory is called "MV-mul," in another example, the command could be represented differently depending on the type of operation performed in memory. The command "SD" is issued from the CCU and can indicate the command used to slow down the PIM operation performed by all MV-banks (i.e., the memory bank including the computing circuitry). The command "P" is issued from the CCU and can indicate the command used to pause the PIM operation performed by the target MV-bank.

[0078] The command "p-PRE" is issued by the memory controller and can indicate a pause along with precharge to notify the PIM operation being performed by the target memory. The timing for executing the corresponding operation after issuing the command "p-PRE" needs to be at least tRC. In this example, as an example to maximize the guarantee of PIM operation execution, the timing of "p-PRE" is set to tRC + tRP. tRC is the row cycle time representing the minimum time interval between consecutive ACTIVE commands for the same memory, and tRP is the row precharge time, which is the number of clock cycles spent between issuing the precharge PRE command and issuing the ACTIVE command. In "p-PRE", p can represent a pause.

[0079] The command "s-PRE" is issued by the memory controller and can indicate the end of the slowdown in PIM operations along with a precharge command. The timing for executing the corresponding operation after issuing the command "s-PRE" can be tRP+1tCK. 1tCK is the time corresponding to one clock cycle and can be the time required for command decoding. In "s-PRE", 's' can represent slowdown.

[0080] The command "r-PRE" is issued by the memory controller and can indicate the end of the pause in PIM operation along with a precharge command. The timing for executing the corresponding operation after issuing the command "r-PRE" can be tRP+1tCK. In "r-PRE", 'r' can represent a restart.

[0081] The command "WR-input" is issued by the memory controller and instructs the operation to write the input vector into the SRAM of the MV-bank. The timing for executing the corresponding operation after issuing the "WR-input" command can be 375 ns. The command "RD-output" is issued by the memory controller and instructs the operation to read the output vector from the SRAM of the MV-bank. The timing for executing the corresponding operation after issuing the "RD-output" command can be 187.5 ns. However, the timing of executing the corresponding operations of "WR-input" and "RD-output" can vary depending on the amount of data read from and written to the SRAM.

[0082] The command "All commands" is issued from the memory controller (e.g., all commands commonly used in existing DRAM, such as the read RD command, write WR command, activate ACT command, precharge PRE command, etc.) and may indicate the command used to notify the start of a slowdown in PIM operations. The timing for executing the corresponding operation after issuing the command "All commands" can be 3tCK. 3tCK may correspond to the sum of the time 1tCK required for command decoding and the time 2tCK spent broadcasting the command "SD". When any MV-bank is not in a slowdown or pause state, a timing change corresponding to the command "All commands" may be necessary.

[0083] exist Figure 6 The commands shown in Table 610 that need to be added or modified to execute the schedule are merely examples. The entity issuing each command can be changed to either the MC or the CCU, and the terminology related to each command can also be changed appropriately. Furthermore, the timing of executing the corresponding operation after each command is issued can also be changed appropriately. The example is not limited to the configuration above.

[0084] Figure 7 It is a timing diagram based on the example and the example of scheduling processing.

[0085] Reference Figure 7 ,based on Figure 6 The commands shown in Table 610 illustrate the timing of the scheduled processing according to the example above. Specifically, Figure 7 The timing diagram illustrates the execution of SD and P commands to process memory requests and PIM operations in parallel.

[0086] In one example, while Bank2, which is a memory bank containing computing circuitry and an MV-bank, is performing a PIM operation (e.g., MV-mul), a memory request for Bank0, a general memory bank without computing circuitry, can be requested via the external command CA bus. When the Activate ACT command is sent to Bank0 via the external command CA bus, the SD command can first be broadcast to all MV-banks, and the actual Activate ACT command can be transmitted to Bank0 via the internal DRAM command CA bus after 3tCK. 3tCK corresponds to the sum of 1tCK required for processing command decoding and 2tCK required for broadcasting the SD command, where tRCD represents the row address to column address delay.

[0087] In another example, while Bank 2 is performing a PIM operation (e.g., MV-mul), a memory request for Bank 2 can be requested via the external command CA bus. When the p-PRE command is sent to Bank 2 via the external command CA bus, the P command is first transmitted to the target Bank 2 via the internal DRAM command CA bus, and the actual PRE command can be transmitted to Bank 2 after tRC. Therefore, Bank 2 can pause the PIM operation, store the result up to the current operation, precharge the currently active DRAM row, and then activate the DRAM row corresponding to the memory request after tRP, where tRP is the time used to ensure precharging in order to process the memory request.

[0088] As described above, in order to perform PIM operations and memory request processing simultaneously as efficiently as possible through scheduling, according to the example semiconductor memory device (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 The semiconductor memory device 20) can broadcast instructions at a preset time to adjust and / or pause the group of memory cells including computing circuitry (e.g., Figure 1 First memory group 110 or Figure 2 Commands for PIM operations performed on the storage banks (Bank 2 to Bank 5 and Bank 10 to Bank 13).

[0089] When adding or changing commands, because the timing of executing the corresponding operation after issuing the command is adjusted, the command does not need to be processed separately in all memory banks, and scheduling can be done in the control circuitry (e.g., Figure 1 Control circuit 130 or Figure 2 It executes appropriately under the control of Control circuit 0 and Control circuit 1. Furthermore, the amount of command CA bus used for commands can be reduced.

[0090] Figure 8 It is a block diagram based on the example electronic system 800.

[0091] Reference Figure 8The electronic system 800 can analyze input data in real time based on a neural network to extract useful information, determine the situation based on the extracted information, or control the configuration of electronic devices equipped with the electronic system 800. For example, the electronic system 800 can be applied to robotic devices (such as drones, advanced driver assistance systems (ADAS), etc.), smart TVs, smartphones, medical devices, mobile devices, image display devices, measuring devices, IoT devices, etc., and can be installed on at least one of various electronic devices. For example, the electronic system 800 can be a server.

[0092] The electronic system 800 may include a processor 810, a semiconductor memory device 820, a neural network device 830, a system memory 840, a sensor module 850, and a communication module 860. The electronic system 800 may also include an input / output module, a security module, a power control device, etc. Some of the hardware components of the electronic system 800 may be mounted on at least one semiconductor chip.

[0093] Processor 810 controls the overall operation of electronic system 800. Processor 810 may include one processor core (single-core) or multiple processor cores (multi-core). Processor 810 can process or execute programs and / or data stored in system memory 840. In some examples, processor 810 can control the functions of semiconductor memory device 820 or neural network device 830 by executing programs stored in system memory 840. Processor 810 may be implemented as a central processing unit (CPU), graphics processing unit (GPU), application processor (AP), etc. Processor 810 may include a memory controller for controlling semiconductor memory device 820 or system memory 840.

[0094] Semiconductor memory device 820 can temporarily store programs, data, or instructions. For example, programs and / or data stored in system memory 840 can be temporarily stored in semiconductor memory device 820 according to the control or boot code of processor 810. Semiconductor memory device 820 can be implemented as a memory such as DRAM. Semiconductor memory device 820 may correspond to reference Figures 1 to 7 The semiconductor memory device described (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 (Semiconductor memory device 20). Semiconductor memory device 820 corresponds to PIM including computing circuitry, thereby performing not only the memory function of storing data but also the processor function of performing computational operations.

[0095] Because the computing circuitry included in the semiconductor memory device 820 is located inside the semiconductor memory device 820, the computing circuitry can be referred to as an internal processor, and because the processor 810 is located outside the semiconductor memory device 820, the processor 810 can be referred to as a main processor or an external processor. Because the internal processor and memory are implemented on-chip, the PIM architecture enables low-latency, fast memory access. Furthermore, when the PIM architecture utilizes the parallelism of memory bank units or memory bank groups, it can utilize several to tens of times more memory bandwidth compared to general memory access. The semiconductor memory device 820 including the PIM architecture can also be referred to by terms such as intelligent random access memory (RAM), computational RAM, or intelligent memory.

[0096] The semiconductor memory device 820 can perform neural network operations using computing circuitry based on internally stored data, and generate information signals based on the results of the operations. The information signals may include one of various types of recognition signals (such as speech recognition signals, object recognition signals, image recognition signals, biometric recognition signals, etc.). In one example, the neural network implemented by the semiconductor memory device 820 may be an RNN, but is not limited to this. The neural network implemented by the semiconductor memory device 820 may include convolutional neural networks (CNNs), feedforward neural networks (FNNs), deep belief networks, restricted Boltzmann machines, etc. The semiconductor memory device 820 can be used in various applications such as image recognition, time series prediction, rhythm learning, and natural language processing (NLP) applications (such as speech recognition, machine translation, language modeling, language prediction, etc.).

[0097] In addition to the semiconductor memory device 820, the electronic system 800 may also include a separate neural network device 830 to implement a neural network. In this case, the semiconductor memory device 820 can operate as a general-purpose memory to provide the necessary data to the neural network device 830.

[0098] The neural network device 830 can perform neural network operations based on received input data and generate information signals based on the results of the operations. The neural network may include, but is not limited to, CNN, RNN, FNN, deep belief networks, restricted Boltzmann machines, etc. The neural network device 830 can drive a neural network separate from the semiconductor memory device 820, and can also drive a neural network collaboratively with the semiconductor memory device 820.

[0099] System memory 840 is a storage location for storing data and can store the operating system (OS), various programs, and various types of data. In one example, system memory 840 may store intermediate results generated during processing that performs operations on semiconductor memory device 820 or neural network device 830.

[0100] System memory 840 may include at least one of volatile memory and non-volatile memory. Non-volatile memory includes ROM, PROM, EPROM, EEPROM, flash memory, PRAM, MRAM, RRAM, FRAM, etc. Volatile memory includes DRAM, SRAM, SDRAM, etc. In one example, system memory 840 may include at least one of HDD, SSD, CF, SD, micro SD, mini SD, xD, and Memory Stick.

[0101] Sensor module 850 can collect information about the vicinity of an electronic device on which electronic system 800 is mounted. Sensor module 850 can sense or receive signals (e.g., image signals, sound signals, magnetic signals, biosignals, touch signals, etc.) from outside the electronic device and convert the sensed or received signals into data. For this purpose, sensor module 850 may include at least one of various types of sensing devices (such as microphones, imaging devices, image sensors, light detection and ranging (LIDAR) sensors, ultrasonic sensors, infrared sensors, biosensors, touch sensors, etc.).

[0102] Sensor module 850 can provide the converted data as input data to semiconductor memory device 820 or neural network device 830. For example, sensor module 850 may include an image sensor that captures the external environment of the electronic device to generate a video stream, and sequentially provides consecutive data frames of the video stream as input data to semiconductor memory device 820 or neural network device 830. However, the configuration of sensor module 850 is not limited to this, and sensor module 850 may provide various types of data to semiconductor memory device 820 or neural network device 830.

[0103] The communication module 860 may have various wired or wireless interfaces for communicating with external devices. For example, the communication module 860 may include communication interfaces that can connect to wireless local area networks (WLANs) (such as local area networks (LANs)), Wi-Fi, wireless personal area networks (WPANs) (such as Bluetooth), mobile cellular networks (such as wireless USB), Zigbee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), or third-generation (3G), fourth-generation (4G), long-term evolution (LTE), etc.

[0104] Figure 9 This is a flowchart illustrating a method for operating a semiconductor memory device according to an example.

[0105] Reference Figure 9 The method of operating a semiconductor memory device may include using a reference Figures 1 to 7 The semiconductor memory device described (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 The semiconductor memory device 20) operates in a time-series manner. Therefore, even if the following is omitted, the above regarding... Figures 1 to 7 Semiconductor memory devices (e.g., Figure 1 Semiconductor memory device 10 or Figure 2 The description provided for the semiconductor memory device 20) can also be applied to Figure 9 Methods for operating semiconductor memory devices.

[0106] In operation 910, the semiconductor memory device can process memory requests for a plurality of memory banks, including a first group of memory banks containing computing circuitry and a second group of memory banks not containing computing circuitry. In one example, the semiconductor memory device may be DRAM. In this case, each of the plurality of memory banks may include one or more DRAM arrays, and the memory request may correspond to a DRAM request including at least one of read, write, copy, and delete. The computing circuitry included in each memory bank in the first group of memory banks can perform operations using data read from the corresponding memory bank and rewrite the results of the operations to the corresponding memory bank or output the results to an external device. The operations performed by the computing circuitry included in each memory bank in the first group of memory banks may be referred to as PIM operations.

[0107] In operation 920, the semiconductor memory device can control the PIM operation performed by the first memory bank group to be executed together with the memory request processing, while meeting the maximum power consumption conditions of the semiconductor memory device. For example, the semiconductor memory device can control the sum of the power consumed by the memory request processing and the power consumed by the PIM operation to be within the maximum power consumption conditions by adjusting and / or pausing the PIM operation performed by the first memory bank group.

[0108] The semiconductor memory device can schedule the processing of memory requests and PIM operations based on the number counted by a request counter, which counts memory requests for each of a plurality of memory banks according to a predetermined time period. In one example, when the number of counts by the request counter corresponding to the second memory bank group is equal to or greater than a preset threshold, the semiconductor memory device can slow down the PIM operations performed on the first memory bank group in order to process memory requests for the second memory bank group.

[0109] In another example, when the first memory bank group includes a third memory bank and a fourth memory bank, and the number of the number counted by the request counter that corresponds to the third memory bank is equal to or greater than a preset threshold, in order to process the memory request for the third memory bank, the semiconductor memory device may suspend the PIM operation performed by the third memory bank and slow down the PIM operation performed by the fourth memory bank.

[0110] The semiconductor memory device can broadcast commands to the first memory bank group, indicating adjustments and / or pausing of PIM operations performed by the first memory bank group, according to a preset timing. As described above, the semiconductor memory device can simultaneously process memory requests while performing PIM operations as efficiently as possible through scheduling.

[0111] Semiconductor memory devices can perform PIM operations by arranging computing circuitry only in some memory banks, thereby achieving maximum performance while minimizing area overhead within the available design space. For example, the number of memory banks included in a first memory bank group can be determined such that the power consumed by the semiconductor memory device is within maximum power consumption conditions when all memory banks included in the first memory bank group perform read operations for PIM operations.

[0112] Methods of operating a semiconductor memory device can be recorded in a computer-readable recording medium having recorded one or more programs including instructions for performing the methods. Examples of computer-readable recording media include magnetic media (such as hard disks, floppy disks, and magnetic tapes), optical media (such as CD-ROMs and DVDs), magneto-optical media (such as floppy disks), and hardware devices specifically configured to store and execute program instructions (e.g., ROM, RAM, and flash memory). Examples of program instructions include machine language code (such as machine language code generated by a compiler) and high-level language code that can be executed by a computer using an interpreter or the like.

[0113] Although this disclosure includes specific examples, it will be clear upon understanding this disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered only in a descriptive sense and not for limiting purposes. The description of features or aspects in each example will be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if the components in the described system, architecture, apparatus, or circuit are combined in a different manner, and / or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is not limited by the specific embodiments but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents will be construed as included in the disclosure.

Claims

1. A semiconductor memory device employing in-memory processing of PIM, the semiconductor memory device comprising: Multiple memory banks, including a first memory bank group containing computing circuitry and a second memory bank group not containing computing circuitry; as well as The control circuit is configured to, while satisfying the maximum power consumption condition of the semiconductor memory device, control the PIM operation performed by the first bank group to be executed together with the processing of memory requests to the plurality of banks. The control circuit includes a request counter configured to count memory requests for each of the plurality of memory banks according to a predetermined time period. The control circuitry is configured to schedule the processing of memory requests and PIM operations based on the number of requests counted by the request counter. The control circuit is configured to slow down the PIM operation performed by the first memory bank when the number of the number counted by the request counter that corresponds to the second memory bank is equal to or greater than a preset threshold, so as to process the memory request for the second memory bank.

2. The semiconductor memory device according to claim 1, wherein, The control circuit is configured to control the sum of the power consumed by the processing of memory requests and the power consumed by the PIM operation performed by the first memory bank group to meet the maximum power consumption condition by adjusting and / or pausing the PIM operation.

3. The semiconductor memory device according to claim 1, wherein, When the first memory bank group includes a first memory bank and a second memory bank, and the number of the number counted by the request counter that corresponds to the first memory bank is equal to or greater than a preset threshold, the control circuit is configured to: suspend the PIM operation performed by the first memory bank and slow down the PIM operation performed by the second memory bank in order to process the memory request for the first memory bank.

4. The semiconductor memory device according to claim 1, wherein, The control circuit is configured to broadcast commands to the first memory bank for indicating adjustment and / or pausing of PIM operations performed by the first memory bank according to a preset timing.

5. The semiconductor memory device according to claim 1, wherein, The number of memory cells included in the first memory cell group among the plurality of memory cells is configured such that when all memory cells included in the first memory cell group perform a read operation for PIM calculation, the power consumed by the semiconductor memory device satisfies the maximum power consumption condition.

6. The semiconductor memory device according to claim 1, wherein, Each of the plurality of memory banks includes one or more dynamic random access memory arrays, and The memory request is a dynamic random access memory request that includes at least one of reading, writing, copying, and erasing.

7. The semiconductor memory device according to claim 1, wherein, The computing circuitry included in the first memory bank group is configured to perform calculations using data read from the corresponding memory bank, and to rewrite the results of the calculations to the corresponding memory bank or output the results to an external device.

8. The semiconductor memory device according to claim 1, wherein, A computing circuit includes hardware that performs at least one of arithmetic operations, logical operations, and shift operations.

9. A method of operating a semiconductor memory device employing a memory for processing PIM, the method comprising: Processing memory requests for multiple memory banks, the multiple memory banks including a first memory bank group containing computing circuitry and a second memory bank group not containing computing circuitry; as well as While meeting the maximum power consumption conditions of the semiconductor memory device, the PIM operation performed by the first memory bank group is executed together with the processing of the memory request. The control steps include: scheduling the processing of memory requests and PIM operations based on the number counted by a request counter, wherein the request counter is configured to count memory requests for each of the plurality of memory banks according to a predetermined time period. The scheduling steps include: when the number of requests counted by the request counter that corresponds to the second memory bank is equal to or greater than a preset threshold, slowing down the PIM operation performed by the first memory bank to process memory requests to the second memory bank.

10. The method according to claim 9, wherein, The control steps include: By adjusting and / or pausing the PIM operation performed by the first memory bank group, the power consumed by the processing of the memory request and the power consumed by the PIM operation are controlled to meet the maximum power consumption condition.

11. The method according to claim 9, wherein, The steps for performing the scheduling include: When the first memory bank group includes a first memory bank and a second memory bank, and the number of the number of requests counted by the request counter that corresponds to the first memory bank is equal to or greater than a preset threshold, the PIM operation performed by the first memory bank is paused and the PIM operation performed by the second memory bank is slowed down in order to process the memory request for the first memory bank.

12. The method according to claim 9, further comprising: According to a preset timer, commands for instructing adjustment and / or pausing PIM operations performed by the first memory group are broadcast to the first memory group.

13. The method according to claim 9, wherein, The number of memory cells included in the first memory cell group among the plurality of memory cells is configured such that when all memory cells included in the first memory cell group perform a read operation for PIM calculation, the power consumed by the semiconductor memory device satisfies the maximum power consumption condition.

14. The method according to claim 9, in, Each of the plurality of memory banks includes one or more dynamic random access memory arrays, and The memory request corresponds to a dynamic random access memory request that includes at least one of reading, writing, copying, and erasing.

15. The method according to claim 9, wherein, The computing circuitry included in the first memory bank group is configured to perform calculations using data read from the corresponding memory bank, and to rewrite the results of the calculations to the corresponding memory bank or output the results to an external device.

16. A non-transitory computer-readable recording medium having recorded thereon one or more programs including instructions for performing the method of claim 9.

17. A semiconductor memory device, comprising: The first storage unit includes computing circuitry configured to perform PIM operations in the memory; The second storage unit is configured to process one or more memory requests simultaneously with the PIM operation; as well as The control circuit is configured to control the PIM operation such that the sum of the power consumed by processing the one or more memory requests and the power consumed by the PIM operation does not exceed a maximum threshold. The control circuit includes a request counter configured to count memory requests for each of the first and second memory banks according to a predetermined time period. The control circuitry is configured to schedule the processing of memory requests and PIM operations based on the number of requests counted by the request counter. The control circuit is configured to slow down the PIM operation performed by the first memory bank when the number of the number counted by the request counter that corresponds to the second memory bank is equal to or greater than a preset threshold, so as to process the memory request for the second memory bank.

18. The semiconductor memory device according to claim 17, wherein, The first memory bank is included in a first memory bank group comprising two or more memory banks, and each memory bank in the first memory bank group includes computing circuitry. The second memory bank is included in a second memory bank group comprising two or more memory banks, and none of the memory banks in the second memory bank group include computing circuitry.

19. The semiconductor memory device according to claim 17, wherein, The first memory bank is included in a first memory bank group comprising two or more memory banks, wherein the two or more memory banks in the first memory bank group include a third memory bank that does not contain computing circuitry. The second memory bank does not include computing circuitry, and The second memory bank is included in a second memory bank group comprising two or more memory banks, wherein the two or more memory banks in the second memory bank group include a fourth memory bank containing computing circuitry.

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