Semiconductor memory, semiconductor structure and manufacturing method thereof

Abstract

This disclosure relates to the field of memory technology, specifically to a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor memory. The semiconductor structure includes: a substrate, an isolation structure, word line trenches, and word lines. The isolation structure is formed in the substrate and defines a plurality of active regions within the substrate. The word line trenches are formed on the substrate and the isolation structure. Word lines are disposed in the word line trenches and pass through the active regions and the isolation structure. In the depth direction of the word line trenches, the height of the word lines located on the active regions is greater than the height of the word lines at least partially located on the isolation structure. The semiconductor structure provided by this disclosure can reduce the impact of word lines in the active isolation region on the electrical properties of memory transistors in adjacent active regions during operation, thereby reducing leakage current.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor memory. Background Art

[0002] As electronic products are increasingly moving towards being lighter, thinner, shorter and smaller, the design of dynamic random access memory (DRAM) components must also meet the requirements of high integration and high density and move towards miniaturization. In order to increase the integration of dynamic random access memory to speed up the operation speed of components and meet consumers' demand for miniaturized electronic devices, buried gate word line dynamic random access memory has been developed in recent years to meet the above-mentioned various needs.

[0003] However, as the array of dynamic random access memory continues to shrink and as the device size decreases, the word line resistance will gradually increase, which increases the access time of the device. The low resistance of the word line is usually achieved by increasing the height of the word line, while the larger gate-induced drain leakage current will greatly reduce the reliability of the memory device, increase the refresh frequency of the memory device, and increase the power consumption of the memory device.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a semiconductor structure, a method for manufacturing the semiconductor structure and a semiconductor memory that can reduce the influence of the word line of the active isolation region on the electrical properties of the storage transistor in the adjacent active region during operation and reduce leakage current.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor structure, the semiconductor structure comprising:

[0007] substrate;

[0008] an isolation structure formed in the substrate and defining a plurality of active regions in the substrate;

[0009] word line trenches formed on the substrate and the isolation structure; and

[0010] A word line is disposed in the word line trench, and the word line passes through the active area and the isolation structure; wherein,

[0011] In a depth direction of the word line trench, a height of the word line located on the active region is greater than a height of the word line located at least partially on the isolation structure.

[0012] In an exemplary embodiment of the present disclosure, a depth of the word line trench located on the active area is greater than a depth of the word line trench at least partially located on the isolation structure.

[0013] In an exemplary embodiment of the present disclosure, the height of a region where the depth of the word line trench on the isolation structure is less than the depth of the word line trench on the active region is 28 nm to 32 nm.

[0014] In an exemplary embodiment of the present disclosure, in a width direction of the word line trench, the width of the word line located on the isolation structure is greater than the width of the word line located on the active region.

[0015] In an exemplary embodiment of the present disclosure, in the width direction of the word line trench, the width of the word line located on the isolation structure is 20 nm to 35 nm.

[0016] In an exemplary embodiment of the present disclosure, at least one of the active regions is provided with two word lines passing therethrough.

[0017] According to another aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0018] providing a substrate;

[0019] forming an isolation structure in the substrate, the isolation structure defining a plurality of active regions in the substrate;

[0020] forming word line trenches on the substrate and the isolation structure;

[0021] A word line passing through the active area and the isolation structure is formed in the word line groove, and in the depth direction of the word line groove, the height of the word line located on the active area is greater than the height of the word line at least partially located on the isolation structure.

[0022] In an exemplary embodiment of the present disclosure, forming a word line trench on the substrate and the isolation structure includes:

[0023] Etching the active area to form a first trench with a first preset depth;

[0024] The isolation structure is etched to form a second trench of a second preset depth in at least a partial area, the first trench is connected to the second trench to form the word line trench, and the first preset depth is greater than the second preset depth.

[0025] In an exemplary embodiment of the present disclosure, etching the isolation structure includes:

[0026] Etching the isolation structure by isotropic etching;

[0027] The isolation structure is etched to the second preset depth by anisotropic etching to form the second trench.

[0028] In an exemplary embodiment of the present disclosure, forming a word line passing through the active area and the isolation structure in the word line trench includes:

[0029] forming a gate oxide layer on the inner wall of the word line trench;

[0030] The word line is formed on the gate insulating layer.

[0031] According to another aspect of the present disclosure, a semiconductor memory is provided, which includes the semiconductor structure described in any one of the above items.

[0032] In the semiconductor structure provided by the present disclosure, in the depth direction of the word line groove, the height of the word line located on the active area is greater than the height of the word line located at least partially on the isolation structure, so that the overlapping area between the word line located on the isolation structure and the word line located on the active area on adjacent word lines can be reduced, thereby reducing the influence of the word line on the isolation structure on the electrical properties of the storage transistor in the adjacent active area during the working state, reducing the leakage current, improving the device refresh time, and increasing the reliability of the semiconductor device.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0035] Figure 1 A top view of a semiconductor structure provided for one embodiment of the present disclosure;

[0036] Figure 2 A flowchart of a method for manufacturing a semiconductor structure provided for one embodiment of the present disclosure;

[0037] Figure 3-Figure 8 For Figure 1 A process diagram of a method for manufacturing a semiconductor structure with a cross-section along plane AA;

[0038] Figure 9-14 For Figure 1 A process diagram of a method for manufacturing a semiconductor structure showing a cross section taken along plane BB. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0040] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0041] The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0042] In this exemplary embodiment, a semiconductor structure is first provided. Figure 1 , Figure 8 and Fig.14As shown, the semiconductor structure includes: a substrate 10, an isolation structure 20, a word line groove 40 and a word line 30, wherein the isolation structure 20 is formed in the substrate 10 and defines a plurality of active areas 101 in the substrate 10; the word line groove 40 is formed on the substrate 10 and the isolation structure 20; the word line 30 is arranged in the word line groove 40, and the word line 30 passes through the active area 101 and the isolation structure 20; wherein, in the depth direction of the word line groove 40, the height of the word line 30 located on the active area 101 is greater than the height of the word line 30 located on the isolation structure 20.

[0043] In the semiconductor structure provided by the present disclosure, in the depth direction of the word line groove 40, the height of the word line 30 located on the active area 101 is greater than the height of the word line 30 located at least partially on the isolation structure 20, so that the overlapping area between the word line 30 located on the isolation structure 20 and the word line 30 located on the active area 101 on adjacent word lines 30 can be reduced, thereby reducing the influence of the word line 30 on the isolation structure on the electrical properties of the storage transistor in the adjacent active area 101 domain during the working state, reducing the leakage current, improving the device refresh time, and increasing the reliability of the semiconductor device.

[0044] Wherein, the substrate 10 is a semiconductor substrate, and the forming material of the substrate 10 includes but is not limited to a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. In addition, when the semiconductor substrate is a single crystal substrate or a polycrystalline substrate, it can also be an intrinsic silicon substrate or a slightly doped silicon substrate, and further, it can be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. The isolation structure 20 is an insulating material, and the forming material of the isolation structure 20 can include silicon nitride or silicon oxide, etc., and the filling medium can be silicon nitride or silicon oxide, etc. The word line 30 is a conductive material, and the conductive material forming the word line can include one of tungsten, titanium, nickel, aluminum, titanium oxide, and titanium nitride, or a combination thereof.

[0045] Specifically, in the width direction of the word line trench 40, the width of the word line 30 located on the isolation structure 20 is greater than the width of the word line 30 located on the active area 101. Figure 8 The height direction of the cross-sectional view is shown, and the width direction of the word line trench 40 is Figure 8 By relatively increasing the width of the word line 30, the cross-sectional area of ​​the word line 30 can be increased, thereby reducing the resistance of the word line 30 on the isolation structure 20, thereby avoiding the problem of increasing the resistance of the word line 30 due to the reduction in the height of the word line 30 on the isolation structure 20, ensuring that the overlapping area of ​​the word line 30 on the isolation structure 20 and the word line 30 on the active area of ​​adjacent word lines 30 is reduced while the resistance of the word line 30 does not increase relatively, which is beneficial to the turn-on speed of the transistor.

[0046] Among them, in the width direction of the word line groove 40, the width of the word line 30 located on the isolation structure 20 is 20nm to 35nm. For example, the width of the word line 30 located on the isolation structure 20 can be 20nm, 22nm, 25nm, 27nm, 29nm, 30nm, 32nm, 35nm, etc., which are not listed here one by one. It can be seen that the width of the word line 30 on the isolation structure 20 provided by the present disclosure can reach 30nm, so that the width of the word line 30 is relatively greatly increased, and the area of ​​the cross section of the word line 30 can be greatly increased, thereby ensuring that the resistance of the word line 30 on the isolation structure 20 is within a preset range.

[0047] Specifically, the depth of the word line trench 40 located on the active region 101 is greater than the depth of the word line trench 40 located at least partially on the isolation structure 20. Fig.14 As shown, the depth of the word line groove 40 on the isolation structure 20 near the active area 101 is greater than the depth of the word line groove on the active area 101. By making the depth of the word line groove 40 on the active area 101 greater than the depth of the word line groove 40 at least partially located on the isolation structure 20, when the word line 30 is formed in the groove by deposition or other processes, the height of the word line 30 deposited on the active area 101 can be greater than the height of the word line 30 deposited on the isolation structure 20, so that the overlapping area of ​​the word line 30 located on the isolation structure 20 and the word line 30 located on the active area 101 on adjacent word lines 30 can be reduced, thereby reducing the influence of the word line 30 on the isolation structure 20 on the electrical properties of the storage transistor in the adjacent active area 101 domain in the working state, and reducing the leakage current.

[0048] Furthermore, if Fig.14 As shown, the side of the word line 30 facing the opening of the word line groove 40 is a plane. By making the side of the word line 30 facing the opening of the word line groove 40 a plane, the height of the overlapping area between the word line 30 on the isolation structure 20 and the word line 30 on the active area 101 on the adjacent word line 30 can be made the same as the height of the word line 30 on the isolation structure 20, thereby achieving control of the height of the overlapping area between the word line 30 on the isolation structure 20 and the word line 30 on the active area 101 on the adjacent word line 30, further ensuring that the overlapping area is reduced, and reducing the influence of the word line 30 on the isolation structure on the electrical properties of the storage transistor in the adjacent active area 101 in the working state.

[0049] The depth of the word line trench on the isolation structure 20 is less than the depth of the word line trench on the active area 101, and the height is 28nm to 32nm. By setting the height of the isolation structure 20 under the word line trench 40 to 28nm to 32nm, the height of the isolation structure 20 under the word line trench 40 is increased, and the depth of the word line trench 40 on the isolation structure 20 is relatively reduced, so that the overlapping area of ​​the word line 30 on the isolation structure 20 and the word line 30 on the active area 101 on the adjacent word line 30 is reduced.

[0050] like Figure 1 As shown, at least one active region 101 is provided with two word lines 30 passing through, and the isolation structure 20 may be a shallow trench isolation (STI).

[0051] This exemplary embodiment also provides a method for manufacturing a semiconductor structure, such as Figure 2 As shown, the method for manufacturing the semiconductor structure includes:

[0052] Step S100, providing a substrate;

[0053] Step S200, forming an isolation structure in a substrate, wherein the isolation structure defines a plurality of active regions in the substrate;

[0054] Step S300, forming word line trenches on the substrate and the isolation structure;

[0055] Step S400, forming a word line passing through the active area and the isolation structure in the word line trench, and making the height of the word line located on the active area greater than the height of the word line located at least partially on the isolation structure in the depth direction of the word line trench.

[0056] The manufacturing method of the semiconductor memory provided by the present disclosure makes the height of the word line located on the active area greater than the height of the word line located at least partially on the isolation structure in the depth direction of the word line groove, which can reduce the overlapping area between the word line located on the isolation structure and the word line located on the active area on adjacent word lines, reduce the influence of the word line on the isolation structure on the electrical properties of the storage transistor in the adjacent active area in the working state, reduce the leakage current, improve the device refresh time, and increase the reliability of the semiconductor device.

[0057] Next, each step of the method for manufacturing the semiconductor structure in this exemplary embodiment will be further described.

[0058] In step S100 , a substrate is provided.

[0059] Specifically, Figure 3As shown, a semiconductor substrate 10 is provided, and the material of the substrate includes but is not limited to a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. In addition, when the semiconductor substrate is a single crystal substrate or a polycrystalline substrate, it can also be an intrinsic silicon substrate or a lightly doped silicon substrate. Further, it can be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

[0060] In step S200 , an isolation structure is formed in a substrate, wherein the isolation structure defines a plurality of active regions in the substrate.

[0061] Specifically, Figure 3 and Fig. 9 As shown, the semiconductor substrate is isolated by shallow trench isolation (STI) technology, and a shallow trench isolation trench is formed on the semiconductor substrate. The depth of the shallow trench isolation trench can be 28nm to 32nm. Then, chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition techniques are used to form an isolation structure 20 in the etched shallow trench isolation trench. The multiple active regions 101 isolated by the isolation structure 20 can be, but are not limited to, Figure 1 The isolation structure 20 may be made of insulating materials such as silicon nitride or silicon oxide. As an example, a MOS device (not shown) is formed in the active region 101. The MOS device includes a gate, a source and a drain. The source and the drain are located on opposite sides of the gate.

[0062] In step S300 , word line trenches are formed on the substrate and the isolation structure.

[0063] Specifically, it includes step S310 and step S320:

[0064] In step S310, the active area is etched to form a first trench with a first preset depth.

[0065] Specifically, Figure 4 and Fig.10 As shown, a photoresist layer is formed on the upper surface of the substrate 10 and the isolation structure 20, and then a word line pattern 70 is formed on the photoresist layer by exposure, and then the active area 101 is etched through the patterned photoresist layer, and an etching solution corresponding to the material of the active area 101 is selected to avoid etching the isolation structure 20. Alternatively, the active area 101 is etched by an anisotropic dry etching process to form a first trench on the active area 101.

[0066] In step S320, the isolation structure is etched to form a second trench of a second preset depth in at least a partial area, the first trench is connected to the second trench to form a word line trench, and the first preset depth is greater than the second preset depth.

[0067] Specifically, Figure 5 and Fig.11 As shown, the isolation structure 20 is etched through the patterned photoresist layer, and firstly, the isolation structure 20 is etched by isotropic etching to form an opening with a relatively large width on the isolation structure 20. The isolation structure 20 can be etched down by about 10 nm by isotropic etching to form an opening with a width of 20 nm to 35 nm on the isolation structure 20.

[0068] Then, if Figure 6 , Fig.12 and Fig.14 As shown, the isolation structure 20 is further etched downward from the opening by anisotropic etching. The isolation structure 20 can be etched downward by about 90 nm by anisotropic etching to form a second trench of a second preset depth in at least a portion of the region, as shown in FIG. Fig.14 As shown, the depth of the word line trench on the isolation structure 20 near the active area 101 is greater than the depth of the word line trench on the active area 101. After the second trench is formed in the isolation structure 20, the second trench is connected with the first trench to form the word line trench 40, and the first preset depth is greater than the second preset depth, that is, the depth of the first trench is greater than 100nm.

[0069] Those skilled in the art should understand that the width of the isolation structure 20 should be greater than 32 nm to ensure that after the second trench is formed on the isolation structure, there is still isolation structure material between the inner wall of the second trench and the active area 101 to form insulation between the second trench and the active area 101.

[0070] In step S400, a word line passing through the active area and the isolation structure is formed in the word line trench, and in the depth direction of the word line trench, the height of the word line located on the active area is greater than the height of the word line located at least partially on the isolation structure.

[0071] Specifically, it includes step S410 and step S420:

[0072] In step S410 , a gate oxide layer is formed on the inner wall of the word line trench.

[0073] Specifically, Figure 7 and Fig.13 As shown, a gate oxide layer 50 may be formed on the inner wall of the word line trench 40 by chemical vapor deposition, physical vapor deposition or other deposition techniques, wherein the gate oxide layer 50 is U-shaped at the bottom of the word line trench 40, and the thickness of the gate oxide layer 50 may be 5nm to 6nm. Alternatively, a thermal oxidation process may be used to oxidize a portion of the inner surface of the word line trench 40 to form a gate oxide layer 50 on the inner surface of the word line trench 40. The gate oxide layer 50 may be made of an excellent material such as silicon dioxide.

[0074] In step S420 , a word line is formed in the word line trench.

[0075] Specifically, Figure 8 and Fig.14 As shown, a metal word line 30 can be formed on the gate oxide layer 50 on the inner surface of the word line groove 40 by chemical vapor deposition, physical vapor deposition or other methods. The conductive material forming the word line 30 includes one of tungsten, titanium, nickel, aluminum, titanium oxide, titanium nitride or a combination thereof. Those skilled in the art may also select other conductive materials, which are not limited by the present disclosure. Since the second trench is connected to the first trench to form the word line trench 40, and the first preset depth is greater than the second preset depth, the height of the word line 30 located on the active area 101 is greater than the height of the word line 30 located at least partially on the isolation structure 20, which can reduce the overlapping area of ​​the word line 30 located on the isolation structure 20 and the word line 30 located on the active area 101 on the adjacent word line 30, reduce the influence of the word line 30 on the isolation structure on the electrical properties of the storage transistor in the adjacent active area 101 domain in the working state, reduce the leakage current, improve the device refresh time, and increase the reliability of the semiconductor device.

[0076] In addition, the method for manufacturing the semiconductor structure further includes: forming a top protection layer.

[0077] Specifically, Figure 8 and Fig.14 As shown, after the word line 30 is formed, a top protective layer 60 is formed by chemical vapor deposition, physical vapor deposition or other deposition techniques, and the top protective layer 60 completely covers the active area 101 of the substrate 10, the isolation structure 20 and the word line 30. The top protective layer 60 is an insulating oxide, such as silicon oxide or silicon carbide, which is not limited in the present application.

[0078] It should be noted that although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0079] The semiconductor structure with buried gate lines provided in the present disclosure can be applied to, for example, metal oxide semiconductor field effect transistors (MOSFET), insulated gate bipolar transistors (IGBT) or junction field effect transistors (JFET), etc. By reducing the overlapping area between the word lines located on the isolation structure and the word lines located on the active area on the adjacent word lines, the influence of the word lines on the isolation structure on the electrical properties of the storage transistors in the adjacent active area in the working state is reduced, the leakage current is reduced, the device refresh time is improved, and the reliability of the semiconductor device is increased.

[0080] The present disclosure also provides a semiconductor memory, including the above-mentioned semiconductor structure. The semiconductor memory can be a computing memory (e.g., DRAM, SRAM, DDR3SDRAM, DDR2SDRAM, DDRSDRAM, etc.), a consumer memory (e.g., DDR3SDRAM, DDR2SDRAM, DDRSDRAM, SDRSDRAM, etc.), a graphics memory (e.g., DDR3SDRAM, GDDR3SDMRA, GDDR4SDRAM, GDDR5SDRAM, etc.), a mobile memory, etc. The beneficial effects thereof can be referred to the above description of the semiconductor structure, which will not be repeated here.

[0081] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; an isolation structure formed in the substrate and defining a plurality of active regions in the substrate; A word line trench formed on the substrate and the isolation structure; as well as A word line is disposed in the word line trench, and the word line passes through the active area and the isolation structure; wherein, In the depth direction of the word line trench, the height of the word line located on the active area is greater than the height of the word line at least partially located on the isolation structure; The height of the word line refers to the length of the word line in a direction perpendicular to the substrate.

2. The semiconductor structure according to claim 1, characterized in that: The depth of the word line trench located on the active area is greater than the depth of the word line trench at least partially located on the isolation structure.

3. The semiconductor structure according to claim 2, characterized in that: The height of a region where the depth of the word line trench on the isolation structure is less than the depth of the word line trench on the active region is 28 nm to 32 nm.

4. The semiconductor structure according to claim 1, characterized in that: In a width direction of the word line trench, a width of the word line located on the isolation structure is greater than a width of the word line located on the active region.

5. The semiconductor structure according to claim 4, characterized in that: In the width direction of the word line trench, the width of the word line located on the isolation structure is 20 nm to 35 nm.

6. The semiconductor structure according to claim 1, characterized in that At least one of the active regions is provided with two word lines passing therethrough.

7. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming an isolation structure in the substrate, the isolation structure defining a plurality of active regions in the substrate; forming word line trenches on the substrate and the isolation structure; forming a word line passing through the active area and the isolation structure in the word line trench, so that in the depth direction of the word line trench, the height of the word line located on the active area is greater than the height of the word line at least partially located on the isolation structure; The height of the word line refers to the length of the word line in a direction perpendicular to the substrate.

8. The manufacturing method according to claim 7, characterized in that: Forming word line trenches on the substrate and the isolation structure, comprising: Etching the active area to form a first trench with a first preset depth; The isolation structure is etched to form a second trench of a second preset depth in at least a partial area, the first trench is connected to the second trench to form the word line trench, and the first preset depth is greater than the second preset depth.

9. The manufacturing method according to claim 8, characterized in that: Etching the isolation structure includes: Etching the isolation structure by isotropic etching; The isolation structure is etched to the second preset depth by anisotropic etching to form the second trench.

10. The manufacturing method according to claim 7, characterized in that: Forming a word line passing through the active area and the isolation structure in the word line trench, comprising: forming a gate oxide layer on the inner wall of the word line trench; The word line is formed in the word line trench.

11. A semiconductor memory, characterized in that: A semiconductor structure comprising any one of claims 1 to 6.

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