Display device and method of manufacturing a display device

Abstract

The present invention relates to a display device and a method of manufacturing a display device. The display device includes a substrate, a first active layer of a first transistor and a second active layer of a second transistor over the substrate, a first gate insulating layer over the first active layer, a first gate electrode over the first gate insulating layer, a second gate insulating layer over the second active layer, and a second gate electrode over the second gate insulating layer, wherein a hydrogen concentration of the first gate insulating layer is lower than a hydrogen concentration of the second gate insulating layer.

Description

Technical Field

[0001] Some aspects of exemplary embodiments of this disclosure relate to display devices and methods of manufacturing display devices. Background Technology

[0002] With the development of the information society, display devices are used more frequently to display images and information. Therefore, recent display devices include liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting diode displays (OLEDs), and micro-light-emitting diode displays.

[0003] The pixels of an organic light-emitting display device or a micro light-emitting diode display device may include a light-emitting diode, a first transistor for adjusting the amount of drive current supplied from a first supply voltage line to the light-emitting element according to the voltage of the gate electrode, and a scan transistor for applying a data voltage from a data line to the gate electrode of the first transistor in response to a scan signal from a scan line.

[0004] The driving voltage of the first transistor refers to the voltage applied to the gate electrode of the first transistor to allow the driving current to flow. The driving voltage range of the first transistor refers to the voltage range from a first voltage that allows the minimum driving current (e.g., a set or predetermined minimum driving current) to a second voltage that allows the maximum driving current (e.g., a predetermined maximum driving current) to flow.

[0005] The driving voltage range of the first transistor can be expanded by increasing the channel length. However, increasing the channel length of the first transistor may also increase its size, potentially leading to a larger pixel size. As the pixel size increases, it may become difficult to achieve high-resolution display devices and high pixels per inch (PPI) display devices.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0007] Some aspects of exemplary embodiments of this disclosure relate to display devices capable of increasing the driving voltage range of a first transistor in each pixel.

[0008] Some exemplary embodiments of this disclosure also relate to a method of manufacturing a display device capable of increasing the driving voltage range of a first transistor in each pixel.

[0009] However, the exemplary embodiments of this disclosure are not limited to those set forth herein. The above and other aspects of some exemplary embodiments of this disclosure will become more apparent to those skilled in the art to which this disclosure pertains from the following detailed description of the disclosure.

[0010] According to some example embodiments of this disclosure, the display device includes: a substrate; a first active layer of a first transistor and a second active layer of a second transistor on the substrate; a first gate insulating layer on the first active layer; a first gate electrode on the first gate insulating layer; a second gate insulating layer on the second active layer; and a second gate electrode on the second gate insulating layer. The hydrogen concentration of the first gate insulating layer is lower than the hydrogen concentration of the second gate insulating layer.

[0011] According to some example embodiments of this disclosure, a display device is provided, including: a plurality of pixels connected to scan lines and data lines intersecting the scan lines. Each pixel includes: a light-emitting element; a first transistor for controlling a drive current flowing to the light-emitting element according to a data voltage applied to the gate electrode of the first transistor; and a second transistor for being turned on by a scan signal from the scan lines to apply a data voltage from the data lines to the gate electrode of the first transistor. The drive voltage range of the first transistor is wider than the drive voltage range of the second transistor.

[0012] According to some exemplary embodiments of this disclosure, in a method of manufacturing a display device, the method includes: forming a first active layer of a first transistor and a second active layer of a second transistor on a substrate; forming a first gate insulating layer on a first channel region of the first active layer and forming a first gate electrode of the first transistor on the first gate insulating layer, the first gate electrode overlapping the first channel region in a first direction that is the thickness direction of the substrate; and forming a second gate insulating layer on a second channel region of the second active layer and forming a second gate electrode of the second transistor on the second gate insulating layer, the second gate electrode overlapping the second channel region in the first direction. The hydrogen concentration of the first gate insulating layer is lower than the hydrogen concentration of the second gate insulating layer.

[0013] According to the foregoing and other exemplary embodiments of this disclosure, the hydrogen concentration in the first gate insulating layer between the first active layer and the first gate electrode of the first transistor can be lower than the hydrogen concentration in the second gate insulating layer between the second active layer and the second gate electrode of the second transistor. The lower the hydrogen concentration in the first gate insulating layer, the more electron traps can be generated due to the oxygen interstitial atoms in the first gate insulating layer. As a result, the driving voltage range of the first transistor can be expanded.

[0014] Furthermore, the minimum thickness of the first gate insulating layer can be greater than the minimum thickness of the second gate insulating layer. As a result, the distance between the first gate electrode and the first active layer increases, and thus the driving voltage range of the first transistor can be expanded.

[0015] Other aspects and features of some of the exemplary embodiments will become more apparent from the following detailed description, drawings and claims. Attached Figure Description

[0016] The above and other aspects of some exemplary embodiments of this disclosure will become more apparent from a more detailed description of such exemplary embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 This is a perspective view of a display device according to some example embodiments of the present disclosure.

[0018] Figure 2 This is a plan view illustrating an example display panel according to some exemplary embodiments of the present disclosure.

[0019] Figure 3 It is shown Figure 2 A circuit diagram of an example of one of the sub-pixels.

[0020] Figure 4 It is shown Figure 3 A cross-sectional view of an example of the first and second transistors.

[0021] Figure 5 It is a graph showing the drive current curves of a first transistor with different hydrogen concentrations in the first gate insulating layer.

[0022] Figure 6 This is a table showing the drive current flowing at the on-voltage, the drive current flowing at the off-voltage, the electron mobility, the drive voltage range, and the threshold voltage for each of the first and second transistors.

[0023] Figure 7 It is shown Figure 3 A cross-sectional view of an example of the first and second transistors.

[0024] Figure 8 This is a table showing the drive current flowing under the on-voltage, the drive current flowing under the off-voltage, the electron mobility, the drive voltage range, and the threshold voltage of the first transistor.

[0025] Figure 9 This is a flowchart illustrating a method for manufacturing a display device according to some example embodiments of the present disclosure.

[0026] Figures 10 to 21 This is a cross-sectional view of a first transistor and a second transistor used to illustrate a method of manufacturing a display device according to some example embodiments of the present disclosure.

[0027] Figure 22 This is a flowchart illustrating a method for manufacturing a display device according to some example embodiments of the present disclosure.

[0028] Figures 23 to 25 Is Figure 22 Cross-sectional views of the first and second transistors in steps S201, S204 and S205. Detailed Implementation

[0029] Further details of some exemplary embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments of the present disclosure are illustrated. However, embodiments according to the present disclosure may be embodied in different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be more thorough and complete, and will more fully convey to those skilled in the art the scope of embodiments according to the present disclosure. Throughout the specification, the same reference numerals denote the same parts. In the drawings, the thickness of layers and regions is exaggerated for clarity.

[0030] In the following description, some exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0031] Figure 1 This is a perspective view of a display device according to some example embodiments of the present disclosure. Figure 2 This is a plan view illustrating an example display panel according to some exemplary embodiments of the present disclosure.

[0032] As used herein, the terms “above,” “top,” and “upper surface” refer to the upper side of the display panel 100, i.e., the side indicated by the arrow in the z-axis direction, while the terms “below,” “bottom,” and “lower surface” refer to the lower side of the display panel 100, i.e., the opposite side in the z-axis direction. As used herein, the terms “left,” “right,” “upper,” and “lower” indicate the relative position when the display panel 100 is viewed from above. For example, “left side” refers to the opposite direction indicated by the arrow in the x-axis direction, “right side” refers to the direction indicated by the arrow in the x-axis direction, “upper side” refers to the direction indicated by the arrow in the y-axis direction, and “lower side” refers to the opposite direction indicated by the arrow in the y-axis direction.

[0033] Display device 10 is used to display moving or still images. Display device 10 can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablets, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile computers (UMPCs), as well as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things.

[0034] Display device 10 may be one of the following: organic light-emitting display device, liquid crystal display device, plasma display device, field emission display device, electrophoretic display device, electrowetting display device, quantum dot light-emitting display device, and micro-LED display device. In the following description, organic light-emitting display device is described as an example of display device 10. However, it should be understood that the embodiments according to this disclosure are not limited thereto.

[0035] refer to Figure 1 and Figure 2 According to some example embodiments, the display device 10 includes a display panel 100, a display driver 200, and a circuit board 300.

[0036] The display panel 100 can be formed as a rectangular plane having a shorter side in the x-axis direction and a longer side in the y-axis direction intersecting the x-axis direction. Each of the corners where the shorter side in the x-axis direction meets the longer side in the y-axis direction can be rounded with a curvature (e.g., a set or predetermined curvature) or can be a right angle.

[0037] The shape of the display panel 100 when viewed from above is not limited to a quadrilateral shape, but can be formed into different polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 can be, but is not limited to, being formed as a flat surface. For example, the display panel 100 may include curved portions formed at its left and right ends and having constant or varying curvature. In addition, the display panel 100 can be formed as flexible, so that it can be bent, folded, or rolled up.

[0038] The display panel 100 may include a display area DA with sub-pixels PX for displaying images and a non-display area NDA surrounding the display area DA. When the display panel 100 includes a curved portion, the display area DA may be disposed on the curved portion. In such a case, the image of the display panel 100 may also be seen on the curved portion.

[0039] In the display area DA, in addition to the sub-pixel PX, scan lines SL, emitter lines EL, data lines DL, and a first supply voltage line VDDL can be provided connected to the sub-pixel PX. Scan lines SL and EL can be provided in the x-axis direction, while data line DL can be provided in the y-axis direction, which intersects the x-axis direction. The first supply voltage line VDDL can be provided parallel to each other in the y-axis direction within the display area DA. The first supply voltage lines VDDL, which are parallel to each other in the y-axis direction within the display area DA, can be connected to each other in the non-display area NDA.

[0040] Each sub-pixel PX can be connected to at least one scan line SL, at least one data line DL, at least one emitter line EL, and at least one first supply voltage line VDDL. Figure 2In the example shown, for ease of illustration, each of the sub-pixels PX is connected to two scan lines SL, one data line DL, one emitter line EL, and one first supply voltage line VDDL. However, it should be understood that embodiments according to this disclosure are not limited thereto. For example, each of the sub-pixels PX may be connected to three scan lines SL instead of two scan lines SL.

[0041] Each sub-pixel (PX) may include a driving transistor, a light-emitting element, a capacitor, and at least one switching transistor. When a data voltage is applied to the gate electrode, the driving transistor can supply a driving current to the light-emitting element, allowing light to be emitted. The driving transistor and the at least one switching transistor may be thin-film transistors. The light-emitting element can emit light according to the driving current from the driving transistor. The light-emitting element may be an organic light-emitting diode (OLED) including a first electrode, an organic emitting layer, and a second electrode. The capacitor can maintain a constant data voltage applied to the gate electrode of the driving transistor.

[0042] The non-display area NDA can be defined as the area extending from the outer edge of the display area DA to the edge of the display panel 100. Within the non-display area NDA, a scan driver 410 for applying scan signals to the scan line SL and a pad DP connected to the data line DL can be provided. Since the circuit board 300 is attached to the pad DP, the pad DP can be located on one edge of the display panel 100 (e.g., the lower edge of the display panel 100).

[0043] The scan driver 410 can be connected to the display driver 200 via multiple first scan control lines SCL1. The scan driver 410 receives scan control signals from the pad DP via the multiple first scan control lines SCL1. The scan driver 410 can generate scan signals according to the scan control signals and can sequentially output the scan signals to the scan lines SL. The scan signals from the scan driver 410 select the sub-pixel PX to which data voltage is supplied, and the data voltage is supplied to the selected sub-pixel PX.

[0044] The transmit control driver 420 can be connected to the display driver 200 via multiple second scan control lines SCL2. The transmit control driver 420 can receive transmit control signals from pad DP via multiple second scan control lines SCL2. The transmit control driver 420 can generate transmit signals according to the transmit control signals and can sequentially output the transmit signals to the transmit line EL.

[0045] Despite Figure 2In the example shown, the scan driver 410 is disposed outside the display area DA, and the transmit control driver 420 is disposed on the opposite side of the display area DA, but the embodiments according to this disclosure are not limited thereto. The scan driver 410 and the transmit control driver 420 may both be disposed outside one of the display areas DA, or they may both be disposed outside each of the display areas DA.

[0046] The display driver 200 receives digital video data and timing signals from an external device. The display driver 200 converts the digital video data into analog positive / negative data voltages and supplies them to the data line DL. The display driver 200 generates scan control signals to control the operating timing of the scan driver 410 and supplies these signals via the first scan control line SCL1. The display driver 200 generates transmit control signals to control the operating timing of the transmit control driver 420 and supplies these signals via the second scan control line SCL2. The display driver 200 can supply a first supply voltage to the first supply voltage line VDDL.

[0047] The display driver 200 can be implemented as an integrated circuit (IC) and attached to the circuit board 300 via chip-on-film (COF) technology. Alternatively, the display driver 200 can be attached to the display panel 100 via any suitable mounting technology such as chip-on-glass (COG), chip-on-plastic (COP), or ultrasonic bonding.

[0048] An anisotropic conductive film can be used to attach the circuit board 300 to the pad DP. In this way, the leads of the circuit board 300 can be electrically connected to the pad DP. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0049] Figure 3 It is shown Figure 2 A circuit diagram of an example of one of the sub-pixels.

[0050] exist Figure 3 In the example shown, subpixel PX is connected to scan line Sk-1 (k-1), scan line Sk (k), and data line Dj (j).

[0051] exist Figure 3 In the example shown, sub-pixel PX may overlap with scan line Sk-1 (k-1), scan line Sk (k), and data line Dj (j). Additionally, sub-pixel PX may be connected to a first supply voltage line VDDL (applied with a first supply voltage), an initialization voltage line VIL (applied with an initialization voltage), and a second supply voltage line VSSL (applied with a second supply voltage lower than the first supply voltage).

[0052] Sub-pixel PX includes a driving transistor, a light-emitting element LE, a switching element, and a first capacitor C1. Sub-pixel PX may include a first transistor T1 as the driving transistor and second to seventh transistors T2, T3, T4, T5, T6, and T7 as switching elements. However, the sub-pixel PX according to embodiments of this disclosure is not subject to... Figure 3 The sub-pixel limit is shown in the figure.

[0053] The first transistor T1 may include a first gate electrode, a first source electrode, and a first drain electrode. The drain-source current Ids (hereinafter referred to as the "drive current") of the first transistor T1 is controlled according to the data voltage applied to the first gate electrode. The drive current Ids flowing through the channel of the first transistor T1 is proportional to the square of the difference between the gate-source voltage Vgs (the voltage between the gate electrode and the first source electrode of the first transistor T1) and the threshold voltage, as shown in Equation 1 below:

[0054] [Formula 1]

[0055] Ids = k' × (Vgs - Vth) 2

[0056] Where k' represents the scaling factor determined by the structure and physical characteristics of the first transistor T1, Vgs represents the gate-source voltage of the first transistor T1, and Vth represents the threshold voltage of the first transistor T1.

[0057] A light-emitting element (LE) emits light as a driving current (Ids) flows through it. The amount of light emitted from the LE is proportional to the driving current (Ids). The LE can be an organic light-emitting diode (OLED) comprising a first electrode, a second electrode, and an organic emitting layer located between the first and second electrodes.

[0058] Alternatively, the light-emitting element LE can be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode. Alternatively, the light-emitting element LE can be a quantum dot light-emitting element comprising a first electrode, a second electrode, and a quantum dot emitting layer located between the first electrode and the second electrode. Alternatively, the light-emitting element LE can be a micro light-emitting diode.

[0059] The first electrode of the light-emitting element LE can be connected to the second electrode of the fifth transistor T5, and the second electrode of the light-emitting element LE can be connected to the second supply voltage line VSSL. A parasitic capacitance Cel can be formed between the anode and cathode electrodes of the light-emitting element LE.

[0060] The second transistor T2 is turned on by the scan signal of the k-th scan line Sk to connect the first source electrode of the first transistor T1 to the j-th data line Dj. The second transistor T2 may include a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode may be connected to the k-th scan line Sk, the second source electrode may be connected to the first source electrode of the first transistor T1, and the second drain electrode may be connected to the j-th data line Dj.

[0061] The third transistor T3 can be implemented as a dual transistor comprising a 3-1 transistor T3-1 and a 3-2 transistor T3-2 connected in series between the gate electrode of the first transistor T1 and the node between the first transistor T1 and the fifth transistor T5. The 3-1 transistor T3-1 and the 3-2 transistor T3-2 are turned on by a scan signal from the k-th scan line Sk to connect the first gate electrode and the first drain electrode of the first transistor T1. That is, when the 3-1 transistor T3-1 and the 3-2 transistor T3-2 are turned on, the first gate electrode and the first drain electrode of the first transistor T1 are connected to each other, and therefore, the first transistor T1 operates as a diode (e.g., is diode-connected). The 3-1 transistor T3-1 may include a 3-1 gate electrode, a 3-1 source electrode, and a 3-1 drain electrode.

[0062] The 3-1 gate electrode can be connected to the k-th scan line Sk, the 3-1 source electrode can be connected to the first drain electrode of the first transistor T1, and the 3-1 drain electrode can be connected to the 3-2 source electrode of the 3-2 transistor T3-2. The 3-2 transistor T3-2 may include a 3-2 gate electrode, a 3-2 source electrode, and a 3-2 drain electrode. The 3-2 gate electrode can be connected to the k-th scan line Sk, the 3-2 source electrode can be connected to the 3-1 drain electrode of the 3-1 transistor T3-1, and the 3-2 drain electrode can be connected to the first gate electrode of the first transistor T1.

[0063] The fourth transistor T4 can be implemented as a dual transistor comprising a 4-1 transistor T4-1 and a 4-2 transistor T4-2 connected in series between the third transistor T3 and the initialization voltage line VIL. The 4-1 transistor T4-1 and the 4-2 transistor T4-2 are turned on by a scan signal from the (k-1)th scan line Sk-1 to connect the first gate electrode of the first transistor T1 to the initialization voltage line VIL.

[0064] Therefore, the first gate electrode of the first transistor T1 can be discharged to the initialization voltage of the initialization voltage line VIL. The 4-1 transistor T4-1 may include a 4-1 gate electrode, a 4-1 source electrode, and a 4-1 drain electrode. The 4-1 gate electrode can be connected to the (k-1)th scan line Sk-1, the 4-1 source electrode can be connected to the first gate electrode of the first transistor T1, and the 4-1 drain electrode can be connected to the 4-2 source electrode of the 4-2 transistor T4-2. The 4-2 transistor T4-2 may include a 4-2 gate electrode, a 4-2 source electrode, and a 4-2 drain electrode. The 4-2 gate electrode can be connected to the (k-1)th scan line Sk-1, the 4-2 source electrode can be connected to the 4-1 drain electrode of the 4-1 transistor T4-1, and the 4-2 drain electrode can be connected to the initialization voltage line VIL.

[0065] A fifth transistor T5 is connected between the first drain electrode of the first transistor T1 and the anode electrode of the light-emitting element LE. The fifth transistor T5 is turned on by the emission signal from the k-th emission line Ek to connect the first drain electrode of the first transistor T1 to the anode electrode of the light-emitting element LE. The fifth transistor T5 may include a fifth gate electrode, a fifth source electrode, and a fifth drain electrode. The fifth gate electrode is connected to the k-th emission line Ek, the fifth source electrode is connected to the first drain electrode of the first transistor T1, and the fifth drain electrode is connected to the anode electrode of the light-emitting element LE.

[0066] The sixth transistor T6 is turned on by the emission signal of the k-th emitter line Ek to connect the first source electrode of the first transistor T1 to the first supply voltage line VDDL. The sixth transistor T6 may include a sixth gate electrode, a sixth source electrode, and a sixth drain electrode. The sixth gate electrode is connected to the k-th emitter line Ek, the sixth source electrode is connected to the first supply voltage line VDDL, and the sixth drain electrode is connected to the first source electrode of the first transistor T1. When both the fifth transistor T5 and the sixth transistor T6 are turned on, a drive current Ids can be supplied to the light-emitting element LE.

[0067] The seventh transistor T7 is turned on by the scan signal of the k-th scan line Sk to connect the anode of the light-emitting element LE to the initialization voltage line VIL. The anode of the light-emitting element LE can be discharged to the initialization voltage. The seventh transistor T7 may include a seventh gate electrode, a seventh source electrode, and a seventh drain electrode. The seventh gate electrode is connected to the k-th scan line Sk, the seventh source electrode is connected to the anode of the light-emitting element LE, and the seventh drain electrode is connected to the initialization voltage line VIL.

[0068] A first capacitor C1 is formed between the first gate electrode of the first transistor T1 and the first supply voltage line VDDL. One electrode of the first capacitor C1 can be connected to the first gate electrode of the first transistor T1, while the other electrode of the first capacitor C1 can be connected to the first supply voltage line VDDL.

[0069] The active layer of each of the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 can be made of an oxide semiconductor including indium (In), gallium (Ga) and oxygen (O).

[0070] Although transistors T1, T2, T3, T4, T5, T6, and T7 are p-type metal-oxide-semiconductor field-effect transistors (MOSFETs), this is merely an example. They could also be n-type MOSFETs.

[0071] Figure 4 It is shown Figure 3 A cross-sectional view of an example of the first and second transistors.

[0072] refer to Figure 4 The substrate SUB can be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. The substrate SUB can be made of insulating materials such as glass, quartz, and polymer resin.

[0073] A buffer layer BF can be formed on the substrate SUB. The buffer layer BF is formed on the substrate SUB to protect the thin-film transistor and emitter layer 172, which are susceptible to moisture penetration, from moisture penetrating through the substrate SUB. The buffer layer BF can be composed of multiple layers, wherein one or more inorganic layers selected from silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, and aluminum oxide are stacked alternately. For example, the buffer layer BF can be composed of multiple layers of silicon nitride and silicon oxide. In such a case, the silicon oxide layer can be thicker than the silicon nitride layer. The buffer layer BF can be removed.

[0074] The first transistor T1 and the second transistor T2 can be formed on the buffer layer BF. The first transistor T1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The second transistor T2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

[0075] The first active layer ACT1 and the second active layer ACT2 can be formed on the buffer layer BF. The first active layer ACT1 and the second active layer ACT2 can be made of an oxide semiconductor including indium (In), gallium (Ga), and oxygen (O). For example, each of the first active layer ACT1 and the second active layer ACT2 can be made of IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0076] The first gate insulating layer 131 may be formed on the first active layer ACT1. The first gate insulating layer 131 may be located on a portion of the first active layer ACT1. The first gate insulating layer 131 may be made of an inorganic layer (e.g., a silicon oxide layer).

[0077] The first gate electrode G1 can be formed on the first gate insulating layer 131. The portion of the first active layer ACT1 that overlaps with the first gate electrode G1 in the first direction DR1 can be defined as the first channel region CP1. The first source region SP1 can be located on one side of the first channel region CP1 in the second direction DR2 that intersects the first direction DR1, and the first drain region DP1 can be located on the other side of the first channel region CP1. The first direction DR1 can be the thickness direction of the substrate SUB, and the second direction DR2 can be a direction perpendicular to the first direction DR1. The first gate electrode G1 can be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0078] The second gate insulating layer 132 may be formed on the second active layer ACT2 and the first gate electrode G1. The second gate insulating layer 132 may be located on a portion of the second active layer ACT2. The second gate insulating layer 132 may be located on the upper surface and side surface of the first gate electrode G1. The second gate insulating layer 132 may be located on the side surface of the first gate insulating layer 131. The second gate insulating layer 132 may be located on a portion of the first source region SP1 and a portion of the first drain region DP1. This portion of the first source region SP1 and this portion of the first drain region DP1 may be adjacent to the first channel region CP1. The second gate insulating layer 132 may be made of an inorganic layer (e.g., a silicon oxide layer).

[0079] The second gate electrode G2 and the capacitor electrode CE can be formed on the second gate insulating layer 132. The second gate electrode G2 and the capacitor electrode CE can be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof.

[0080] The portion of the second active layer ACT2 that overlaps with the second gate electrode G2 in the first direction DR1 can be defined as the second channel region CP2. The second source region SP2 can be located on one side of the second channel region CP2, and the second drain region DP2 can be located on the other side of the second channel region CP2.

[0081] The capacitor electrode CE may overlap with the first gate electrode G1 in the first direction DR1. The capacitor electrode CE may be an electrode of the first capacitor C1 connected to the first supply voltage line VDDL. The capacitor electrode CE may be located on the upper surface of the second gate insulating layer 132, which is located on the upper surface of the first gate electrode G1. The capacitor electrode CE may be located on the side surface of the second gate insulating layer 132, which is located on the side surface of the first gate electrode G1. The capacitor electrode CE may overlap with the upper surface of the first gate electrode G1 in the first direction DR1. The capacitor electrode CE may overlap with the side surface of the first gate electrode G1 in the second direction DR2.

[0082] Incidentally, the first transistor T1 is a driving transistor, and it is desirable that the driving voltage range of the first transistor T1 is wide. The driving voltage range of the first transistor T1 ranges from a first voltage that allows a first driving current (e.g., a set or predetermined driving current) to a second voltage that allows a second driving current (e.g., a set or predetermined driving current) to flow. The first driving current may be 1 nA, and the second driving current may be 500 nA.

[0083] The oxygen interstitial atoms in the first gate insulating layer 131 can be used as traps for electrons in the first channel region CP1. Since hydrogen in the first gate insulating layer 131 binds to the oxygen interstitial atoms, the lower the hydrogen concentration in the first gate insulating layer 131, the more electron traps may be caused by oxygen interstitial atoms in the first channel region CP1. Conversely, the higher the hydrogen concentration in the first gate insulating layer 131, the fewer electron traps will be caused by oxygen interstitial atoms in the first channel region CP1.

[0084] When the hydrogen concentration of the first gate insulating layer 131 is at the first hydrogen concentration, the increase in electron trapping caused by oxygen interstitial atoms allows the slope of the drive current curve of the first transistor T1 to be gentler, such as... Figure 5 As indicated in (a) in the diagram. Therefore, the driving voltage range of the first transistor T1 can be expanded.

[0085] Conversely, when the hydrogen concentration of the first gate insulating layer 131 is a second hydrogen concentration higher than the first hydrogen concentration, the reduction in electron traps caused by oxygen interstitial atoms allows for a steeper slope in the drive current curve of the first transistor T1, such as... Figure 5 As indicated in (b) above. Therefore, the driving voltage range of the first transistor T1 can be narrowed.

[0086] Since the first transistor T1 is a driving transistor, it is desirable that the driving voltage range of the first transistor T1 be wide. Therefore, the hydrogen concentration of the first gate insulating layer 131 can be less than 5 × 1,020 atoms / cm³.

[0087] Conversely, the second transistor T2 is a switching transistor, and therefore the driving voltage range of the second transistor T2 does not need to be wide. Therefore, the hydrogen concentration of the second gate insulating layer 132 can be 5 × 1,020 atoms / cm³ or greater. That is, the hydrogen concentration of the first gate insulating layer 131 can be lower than the hydrogen concentration of the second gate insulating layer 132.

[0088] Furthermore, as the distance between the first gate electrode G1 and the first active layer ACT1 increases, the driving voltage range of the first transistor T1 can be widened. Conversely, the second transistor T2 is a switching transistor, and therefore the driving voltage range of the second transistor T2 does not need to be wide. Additionally, the minimum thickness d1 of the first gate insulating layer 131 can be greater than the minimum thickness d2 of the second gate insulating layer 132.

[0089] An interlayer dielectric layer 140 can be formed on the second gate electrode G2 and the capacitor electrode CE. The interlayer dielectric layer 140 can be disposed on a portion of the first source region SP1 excluding the portion covered by the second gate insulating layer 132 and a portion of the first drain region DP1 excluding the portion covered by the second gate insulating layer 132. The interlayer dielectric layer 140 can be disposed on the second source region SP2 and the second drain region DP2 of the second active layer ACT2. The interlayer dielectric layer 140 can be disposed on a buffer layer BF not covered by the first active layer ACT1 and the second active layer ACT2. The interlayer dielectric layer 140 can be made of an inorganic layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, or an aluminum oxide layer.

[0090] The first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the first supply voltage line VDDL can be formed on the interlayer dielectric layer 140. The first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the first supply voltage line VDDL can be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and their alloys.

[0091] The first contact hole CT1 may be a hole that penetrates the interlayer dielectric layer 140 to expose the first source region SP1 of the first active layer ACT1. The first source electrode S1 can be connected to the first source region SP1 through the first contact hole CT1.

[0092] The second contact hole CT2 may be a hole that penetrates the interlayer dielectric layer 140 to expose the first drain region DP1 of the first active layer ACT1. The first drain electrode D1 can be connected to the first drain region DP1 through the second contact hole CT2.

[0093] The third contact hole CT3 may be a hole penetrating the interlayer dielectric layer 140 to expose the capacitor electrode CE. The first supply voltage line VDDL can be connected to the capacitor electrode CE through the third contact hole CT3.

[0094] The fourth contact hole CT4 may be a hole penetrating the interlayer dielectric layer 140 to expose the second source region SP2 of the second active layer ACT2. The second source electrode S2 can be connected to the second source region SP2 through the fourth contact hole CT4.

[0095] The fifth contact hole CT5 may be a hole that penetrates the interlayer dielectric layer 140 to expose the second drain region DP2 of the second active layer ACT2. The second drain electrode D2 can be connected to the second drain region DP2 through the fifth contact hole CT5.

[0096] The passivation layer 150 can be formed on the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the first supply voltage line VDDL. The passivation layer 150 can be made of an inorganic layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, or an aluminum oxide layer.

[0097] A planarization layer 160 may be formed on the passivation layer 150 to provide a flat surface over the first transistor T1 and the second transistor T2. The planarization layer 160 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0098] Despite Figure 4 In the example shown, the first transistor T1 and the second transistor T2 are implemented as top-gate transistors, but it will be understood that this disclosure is not limited thereto. That is, the first transistor T1 and the second transistor T2 can be implemented as bottom-gate transistors with their gate electrodes located below the active layer, or as dual-gate transistors with their gate electrodes located above and below the active layer.

[0099] The first electrode 171 and the dam layer 180 of the light-emitting element LE are formed on the planarization layer 160.

[0100] A sixth contact hole can be formed through the planarization layer 160 to expose the fifth drain electrode of the fifth transistor T5. The first electrode 171 can be connected to the fifth drain electrode of the fifth transistor T5 through the sixth contact hole. In a top-emission structure where light is emitted from the emitting layer 172 toward the second electrode 173, the first electrode 171 can be made of a metallic material with high reflectivity. For example, the first electrode 171 can be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu). Alternatively, the first electrode 171 can be composed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al).

[0101] A dam layer 180 may be formed on the planarization layer 160 to separate the first electrode 171, thereby defining the emission region of each of the sub-pixels PX. For this purpose, the dam layer 180 may be formed to cover the edge of the first electrode 171. In the emission region of each of the sub-pixels PX, the first electrode 171, the emission layer 172, and the second electrode 173 are stacked on top of each other in this order, such that holes from the first electrode 171 and electrons from the second electrode 173 combine with each other in the emission layer 172 to emit light. The dam layer 180 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0102] An emitting layer 172 is formed on the first electrode 171 and the dam layer 180. The emitting layer 172 may include organic materials and emit light of a specific color. For example, the emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer.

[0103] A second electrode 173 is formed on the emitter layer 172. The second electrode 173 may be formed to cover the emitter layer 172. The second electrode 173 may be a common layer formed across sub-pixels PX. A capping layer may be formed on the second electrode 173.

[0104] In a top-emitting organic light-emitting diode, the second electrode 173 can be formed of a transparent conductive material (TCP) such as ITO and IZO that transmits light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 173 is formed of a semi-transmissive conductive material, the light extraction efficiency can be improved by using a microcavity.

[0105] An encapsulation layer 190 may be formed on the second electrode 173. The encapsulation layer 190 may include at least one inorganic layer to prevent or reduce the penetration of oxygen, moisture, or other contaminants into the emitter layer 172 and the second electrode 173. In addition, the encapsulation layer 190 may include at least one organic layer to protect the emitter layer 172 from foreign matter such as dust.

[0106] Alternatively, another substrate may be disposed on the second electrode 173 instead of the encapsulation layer 190, such that the space between the second electrode 173 and the other substrate can be empty in a vacuum state, or a filling film may be located in that space. The filling film may be an epoxy filling film or a silicon filling film.

[0107] according to Figure 4 In the illustrated embodiment, the hydrogen concentration of the first gate insulating layer 131 between the first active layer ACT1 and the first gate electrode G1 of the first transistor T1 is lower than the hydrogen concentration of the second gate insulating layer 132 between the second active layer ACT2 and the second gate electrode G2 of the second transistor T2. As the hydrogen concentration of the first gate insulating layer 131 decreases, electron trapping caused by oxygen interstitial atoms in the first gate insulating layer 131 can increase. Therefore, the driving voltage range of the first transistor T1 can be expanded.

[0108] In addition, according to Figure 4 In the example embodiment shown, the minimum thickness d1 of the first gate insulating layer 131 can be greater than the minimum thickness d2 of the second gate insulating layer 132. As a result, the distance between the first gate electrode G1 and the first active layer ACT1 is increased, and thus the driving voltage range of the first transistor T1 can be expanded.

[0109] Figure 3 The transistors shown, namely 3-1 transistor T3-1, 3-2 transistor T3-2, 4-1 transistor T4-1, 4-2 transistor T4-2, fifth transistor T5, sixth transistor T6, and seventh transistor T7, can be referenced above. Figure 4 The description of the second transistor T2 is essentially the same, and therefore redundant descriptions will be omitted.

[0110] Figure 6 This is a table showing the drive current flowing at the on-voltage, the drive current flowing at the off-voltage, the electron mobility, the drive voltage range, and the threshold voltage for each of the first and second transistors.

[0111] exist Figure 6 In this configuration, the on-state voltage applied to the gate electrodes of the first transistor T1 and the second transistor T2 can be 15V, and the off-state voltage applied to the gate electrodes can be 0V. Figure 6 In this context, DR can refer to the driving voltage range of each of the first transistor T1 and the second transistor T2. Figure 6 In this context, the threshold voltage Vth can refer to the gate voltage applied to the gate electrode of either transistor T1 or transistor T2 when a drive current of 10nA flows through it. Figure 6 In the first transistor T1, the channel length of the first channel region CP1 and the second channel region CP2 of the second transistor T2 can be 3.5 μm.

[0112] refer to Figure 6 When the turn-on voltage is applied to the first gate electrode G1 of the first transistor T1, the drive current ION is 7.58 × 10⁻⁶. -6 A. When the cutoff voltage is applied to the first gate electrode G1 of the first transistor T1, the drive current IOFF is 4.61 × 10⁻⁶. -11 A. Additionally, the electron mobility of the first transistor T1 can be 4.04 cm⁻¹. 2 / V·s, and the driving voltage range DR can be 3.12V. The threshold voltage Vth of the first transistor T1 can be 0.54V.

[0113] When the on-state voltage is applied to the second gate electrode G2 of the second transistor T2, the drive current ION is 1.78 × 10⁻⁶. - 5 A. When the cutoff voltage is applied to the second gate electrode G2 of the second transistor T2, the drive current IOFF is 5.75 × 10⁻⁶. -11 A. The electron mobility of the second transistor T2 can be 12.49 cm⁻¹. 2 The voltage range is 1.88V / s, and the driving voltage range DR can be 1.88V. The threshold voltage Vth of the second transistor T2 can be 0.30V.

[0114] Because the hydrogen concentration in the first gate insulating layer 131 is lower than that in the second gate insulating layer 132, there may be more electron traps caused by oxygen interstitial atoms in the first channel region CP1 of the first transistor T1 than in the second channel region CP2 of the second transistor T2. Therefore, the electron mobility of the first transistor T1 can be lower than that of the second transistor T2. Furthermore, the slope of the drive current curve of the first transistor T1 can be gentler than that of the drive current curve of the second transistor T2, and thus the drive voltage range DR of the first transistor T1 can be wider than that of the second transistor T2.

[0115] Figure 7 It is shown Figure 3 A cross-sectional view of an example of the first and second transistors.

[0116] Figure 7 The example embodiments shown are similar to Figure 4The difference in the example embodiment is that the light-shielding layer BML is formed on the substrate SUB, and the first source electrode S1 of the first transistor T1 is connected to the light-shielding layer BML.

[0117] refer to Figure 7 A light-shielding layer BML can be formed on the substrate SUB. The light-shielding layer BML can overlap with the first channel region CP1 of the first active layer ACT1 in the first direction DR1. With the light-shielding layer BML, it is possible to prevent or reduce light entering from the substrate SUB from incident on the first channel region CP1 of the first active layer ACT1. In this way, it is possible to prevent or reduce leakage current flowing in the first channel region CP1 of the first active layer ACT1 due to light in other situations. The light-shielding layer BML can be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. A buffer layer BF can be formed on the light-shielding layer BML.

[0118] The seventh contact hole CT7 can be a hole that penetrates the interlayer dielectric layer 140 and the buffer layer BF to expose the light-shielding layer BML. The first source electrode S1 can be connected to the light-shielding layer BML through the seventh contact hole CT7.

[0119] When the first source electrode S1 is connected to the light-shielding layer BML through the seventh contact hole CT7, the light-shielding layer BML and the first source electrode S1 have the same voltage. When the light-shielding layer BML and the first source electrode S1 have the same potential, the first active layer ACT1 adjacent to the light-shielding layer BML in the first direction DR1 may not be activated like the first active layer ACT1 adjacent to the first gate electrode G1. That is, the electron mobility of the first channel region CP1 of the first active layer ACT1 can be reduced, and the slope of the drive current curve of the first transistor T1 can be reduced. Therefore, as shown in the figure... Figure 4 Compared to the driving voltage range DR of the first transistor T1 excluding the light-shielding layer BML shown, when... Figure 7 When the first source electrode S1 shown is connected to the light-shielding layer BML through the seventh contact hole CT7, the driving voltage range DR of the first transistor T1 can be expanded.

[0120] Figure 8 This is a table showing the drive current flowing under the on-voltage, the drive current flowing under the off-voltage, the electron mobility, the drive voltage range, and the threshold voltage of the first transistor.

[0121] exist Figure 8 In this configuration, the on-state voltage applied to the gate electrode of the first transistor T1 can be 15V, and the off-state voltage applied to the gate electrode can be 0V. Figure 8In this context, DR can refer to the driving voltage range of the first transistor T1. Figure 8 In this context, the threshold voltage Vth can refer to the gate voltage when a drive current of 10nA flows. Figure 8 In the first transistor T1, the channel length of the first channel region CP1 and the second channel region CP2 of the second transistor T2 can be 3.5 μm.

[0122] refer to Figure 8 When the turn-on voltage is applied to the first gate electrode G1 of the first transistor T1, the drive current ION is 6.33 × 10⁻⁶. -6 A. When the cutoff voltage is applied to the first gate electrode G1 of the first transistor T1, the drive current IOFF is 2.54 × 10⁻⁶. -13 A. Additionally, the electron mobility of the first transistor T1 can be 3.20 cm⁻¹. 2 / V·s, and the driving voltage range DR can be 3.54V. The threshold voltage Vth of the first transistor T1 can be 1.07V.

[0123] By connecting the light-shielding layer BML located below the first channel region CP1 of the first active layer ACT1 to the first source electrode S1, the electron mobility of the first channel region CP1 of the first active layer ACT1 can be reduced, thereby reducing the slope of the drive current curve of the first transistor T1. Therefore, compared with the drive voltage range DR of the first transistor T1 without the light-shielding layer BML, the drive voltage range DR of the first transistor T1 can be expanded when the first source electrode S1 is connected to the light-shielding layer BML.

[0124] Figure 9 This is a flowchart illustrating a method for manufacturing a display device according to some example embodiments of the present disclosure. Figures 10 to 21 This is a cross-sectional view of a first transistor and a second transistor used to illustrate a method of manufacturing a display device according to some example embodiments of the present disclosure.

[0125] In the following text, reference will be made to Figures 9 to 21 A method for manufacturing a display device 10 according to some example embodiments will be described in more detail.

[0126] First, such as Figure 10 As shown, a buffer layer BF is formed on a substrate SUB, and a first active layer ACT1 of the first transistor T1 and a second active layer ACT2 of the second transistor T2 are formed on the buffer layer BF. Figure 9 Step S101 in the process.

[0127] For example, the buffer layer BF can be formed using plasma-enhanced chemical vapor deposition (PECVD) technology.

[0128] Subsequently, an active material layer can be formed on the buffer layer (BF), and a photoresist pattern can be formed on the active material layer. The active material layer can be an oxide semiconductor comprising indium (In), gallium (Ga), and oxygen (O). For example, the active material layer can be made of IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)). The active material layer can be formed using sputtering or metal-organic chemical vapor deposition (MOCVD) techniques.

[0129] Subsequently, the active material layer not covered by the photoresist pattern is etched to form the first active layer ACT1 and the second active layer ACT2. The photoresist pattern can then be removed via a stripping process.

[0130] Second, such as Figures 11 to 13 As shown, a first gate insulating layer 131 is formed on a portion of the first active layer ACT1 of the first transistor T1, and a first gate electrode G1 is formed on the first gate insulating layer 131. Figure 9 Step S102 in the process.

[0131] For example, such as Figure 11 As shown, the first gate insulating material layer 131' can be formed on the first active layer ACT1 and the second active layer ACT2. Alternatively, the first gate insulating material layer 131' can be formed on the portion of the buffer layer BF not covered by the first active layer ACT1 and the second active layer ACT2. The first gate insulating material layer 131' can be formed as an inorganic layer, such as a silicon oxide layer. The first gate insulating material layer 131' can be formed using PECVD technology.

[0132] Subsequently, a first gate metal layer GM1 can be formed on the first gate insulating material layer 131'. The first gate metal layer GM1 can be composed of a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). The first gate metal layer GM1 can be formed using sputtering or MOCVD technology.

[0133] Subsequently, a photoresist pattern PR1 can be formed on the first gate metal layer GM1. The photoresist pattern PR1 can overlap with a portion of the first active layer ACT1 in the first direction DR1.

[0134] Subsequently, as Figure 12As shown, the first gate electrode G1 can be formed by wet etching or dry etching of the first gate metal layer GM1 using a photoresist pattern PR1 as a mask. Subsequently, the first gate insulating layer 131 can be formed by dry etching of the first gate insulating material layer 131' using the first gate electrode G1 as a mask. In doing so, a portion of the first active layer ACT1 not covered by the first gate insulating layer 131 can be exposed to plasma during the dry etching process and can become a conductive first source region SP1. In addition, another portion of the first active layer ACT1 not covered by the first gate insulating layer 131 can be exposed to plasma during the dry etching process and can become a conductive first drain region DP1.

[0135] Subsequently, as Figure 13 As shown, the photoresist pattern PR1 can be removed by a stripping process.

[0136] Third, such as Figures 14 to 18 As shown, the second gate insulating layer 132 and the second gate electrode G2 are formed on a portion of the second active layer ACT2 of the second transistor T2, and the second gate insulating layer 132 and the capacitor electrode CE are formed on the first gate electrode G1 of the first transistor T1. Figure 9 Step S103)

[0137] For example, such as Figure 14 As shown, the second gate insulating material layer 132' can be formed on the first gate electrode G1. Additionally, the second gate insulating material layer 132' can be formed on the side surface of the first gate insulating layer 131. Furthermore, the second gate insulating material layer 132' can be formed on the first active layer ACT1, which is not covered by the first gate insulating layer 131. Additionally, the second gate insulating material layer 132' can be formed on the second active layer ACT2. Furthermore, the second gate insulating material layer 132' can be formed on the portion of the buffer layer BF that is not covered by the first active layer ACT1 and the second active layer ACT2. The second gate insulating material layer 132' can be formed as an inorganic layer, for example, a silicon oxide layer. The second gate insulating material layer 132' can be formed using PECVD technology.

[0138] Subsequently, as Figure 14 As shown, an oxygen supply layer 133 can be formed on the second gate insulating material layer 132'. Oxygen is supplied to the second gate insulating material layer 132' via oxygen plasma during the process of depositing the oxygen supply layer 133, and oxygen can be supplied to the second active layer ACT2 via a thermal processing process after the deposition of the oxygen supply layer 133. In doing so, the second active layer ACT2, which has already been exposed to plasma to become a conductor during the dry etching process used to form the first gate insulating layer 131, can again become a semiconductor layer.

[0139] The oxygen supply layer 133 can be made of the same material as the second active layer ACT2. The oxygen supply layer 133 can be an oxide semiconductor comprising indium (In), gallium (Ga), and oxygen (O). For example, the oxygen supply layer 133 can be made of IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)). The oxygen supply layer 133 can be formed using sputtering or metal-organic chemical vapor deposition (MOCVD) techniques.

[0140] Subsequently, the oxygen supply layer 133 was wet-etched and removed, as shown. Figure 15 As shown in the image.

[0141] Subsequently, as Figure 16 As shown, the second gate metal layer GM2 can be formed on the second gate insulating material layer 132'. The second gate metal layer GM2 can be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof. The second gate metal layer GM2 can be formed using sputtering or MOCVD technology.

[0142] Subsequently, a photoresist pattern PR2 can be formed on the second gate metal layer GM2. The photoresist pattern PR2 can overlap with a portion of the second active layer ACT2 in the first direction DR1. The photoresist pattern PR2 can also overlap with the first gate electrode G1 in the first direction DR1.

[0143] Subsequently, as Figure 17 As shown, the second gate metal layer GM2, not covered by the photoresist pattern PR2, can be wet-etched or dry-etched to form the second gate electrode G2 and the capacitor electrode CE. Subsequently, the second gate insulating material layer 132' can be dry-etched using the second gate electrode G2 and the capacitor electrode CE as a mask to form the second gate insulating layer 132'. In doing so, a portion of the second active layer ACT2 not covered by the second gate insulating layer 132 can be exposed to plasma during the dry etching process and can become a conductive second source region SP2. Additionally, another portion of the second active layer ACT2 not covered by the second gate insulating layer 132 can be exposed to plasma during the dry etching process and can become a conductive second drain region DP2.

[0144] Subsequently, as Figure 18 As shown, the photoresist pattern PR2 can be removed (e.g., by any suitable stripping process).

[0145] Fourth, such as Figure 19As shown, an interlayer dielectric layer 140 is formed on the second gate electrode G2 and the capacitor electrode CE of the second transistor T2, and contact holes CT1, CT2, CT3, CT4 and CT5 are formed in the interlayer dielectric layer 140. Figure 9 Step S104 in the process.

[0146] For example, such as Figure 19 As shown, an interlayer dielectric layer 140 is formed on the second gate electrode G2 and the capacitor electrode CE of the second transistor T2. Additionally, the interlayer dielectric layer 140 is formed on the side surface of the second gate insulating layer 132. Furthermore, the interlayer dielectric layer 140 is formed on the first active layer ACT1 and the second active layer ACT2, which are not covered by the second gate insulating layer 132. Alternatively, the interlayer dielectric layer 140 can be formed on a buffer layer BF, which is not covered by the first active layer ACT1 and the second active layer ACT2. The interlayer dielectric layer 140 can be formed as an inorganic layer, such as a silicon oxide layer. The interlayer dielectric layer 140 can be formed using PECVD technology.

[0147] Subsequently, a photoresist pattern can be formed on the interlayer dielectric layer 140. The interlayer dielectric layer 140 can then be etched to form contact holes CT1, CT2, CT3, CT4, and CT5, and the photoresist pattern can be removed by a stripping process.

[0148] The first contact hole CT1 may be a hole that penetrates the interlayer dielectric layer 140 to expose the first source region SP1 of the first active layer ACT1. The second contact hole CT2 may be a hole that penetrates the interlayer dielectric layer 140 to expose the first drain region DP1 of the first active layer ACT1. The third contact hole CT3 may be a hole that penetrates the interlayer dielectric layer 140 to expose the capacitor electrode CE. The fourth contact hole CT4 may be a hole that penetrates the interlayer dielectric layer 140 to expose the second source region SP2 of the second active layer ACT2. The fifth contact hole CT5 may be a hole that penetrates the interlayer dielectric layer 140 to expose the second drain region DP2 of the second active layer ACT2.

[0149] Fifth, such as Figure 20 As shown, the first source electrode S1 and the first drain electrode D1 of the first transistor T1, the second source electrode S2 and the second drain electrode D2 of the second transistor T2, and the first supply voltage line VDDL can be formed on the interlayer dielectric layer 140. Figure 9 Step S105).

[0150] For example, a source-drain metal layer is formed on the interlayer dielectric layer 140. The source-drain metal layer may consist of a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). The source-drain metal layer can be formed using sputtering or MOCVD techniques.

[0151] Subsequently, a photoresist pattern can be formed on the source-drain metal layer. The source-drain metal layer not covered by the photoresist pattern is etched to form a first source electrode S1, a first drain electrode D1, a second source electrode S2, a second drain electrode D2, and a first supply voltage line VDDL, and the photoresist pattern can be removed by a stripping process. The first source electrode S1 can be connected to the first source region SP1 through a first contact hole CT1. The first drain electrode D1 can be connected to the first drain region DP1 through a second contact hole CT2. The first supply voltage line VDDL can be connected to the capacitor electrode CE through a third contact hole CT3. The second source electrode S2 can be connected to the second source region SP2 through a fourth contact hole CT4. The second drain electrode D2 can be connected to the second drain region DP2 through a fifth contact hole CT5.

[0152] Sixth, such as Figure 21 As shown, a passivation layer 150 and a planarization layer 160 are formed, a first electrode 171, a dam layer 180, an emitter layer 172, and a second electrode 173 are formed on the planarization layer 160, and an encapsulation layer 190 is formed on the second electrode 173. Figure 9 Step S106 in the process.

[0153] For example, such as Figure 21 As shown, the passivation layer 150 can be formed on the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the first supply voltage line VDDL. Alternatively, the passivation layer 150 can be formed on the portion of the interlayer dielectric layer 140 not covered by the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the first supply voltage line VDDL. The passivation layer 150 can be formed using PECVD technology.

[0154] Subsequently, a planarization layer 160 is formed on the passivation layer 150, and a sixth contact hole is formed through the planarization layer 160 and the passivation layer 150 to expose the fifth drain electrode.

[0155] Subsequently, a first metal layer is formed on the planarization layer 160. In the top-emission structure, the first metal layer can be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO). Alternatively, the first metal layer can consist of a monolayer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al). The first metal layer can be formed using sputtering or MOCVD techniques.

[0156] Subsequently, a photoresist pattern can be formed on the first metal layer. The first electrode 171 can be formed by etching the first metal layer not covered by the photoresist pattern. The first electrode 171 can be connected to the fifth drain electrode of the fifth transistor T5 through the sixth contact hole.

[0157] Subsequently, the embankment 180 can be formed to cover the edge of the first electrode 171.

[0158] Subsequently, an emitter layer 172 may be formed on the first electrode 171 and the dam layer 180, which are not covered by the dam layer 180. The emitter layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer.

[0159] Subsequently, a second electrode 173 can be formed on the emitter layer 172.

[0160] Subsequently, an encapsulation layer 190 may be formed on the second electrode 173. The encapsulation layer 190 may include at least one inorganic layer to prevent or reduce the penetration of oxygen, moisture, or other contaminants into the emitter layer 172 and the second electrode 173. In addition, the encapsulation layer 190 may include at least one organic layer to protect the emitter layer 172 from foreign matter such as dust.

[0161] Alternatively, another substrate may be located on the second electrode 173 instead of the encapsulation layer 190, such that the space between the second electrode 173 and the other substrate can be empty in a vacuum state, or a filling film may be disposed in the space. The filling film may be an epoxy filling film or a silicon filling film.

[0162] Figure 22 This is a flowchart illustrating a method for manufacturing a display device according to some example embodiments of the present disclosure. Figures 23 to 25 Is Figure 22 Cross-sectional views of the first and second transistors in steps S201, S204 and S205.

[0163] In the following text, reference will be made to Figures 22 to 25 A method for manufacturing a display device 10 according to some example embodiments will be described in more detail.

[0164] First, such as Figure 23 As shown, a light-shielding layer BML is formed on a substrate SUB, a buffer layer BF is formed on the light-shielding layer BML, and the first active layer ACT1 of the first transistor T1 and the second active layer ACT2 of the second transistor T2 are formed on the buffer layer BF. Figure 22 Step S201 in the process.

[0165] For example, a light-shielding material layer can be formed on a substrate SUB. The light-shielding material layer can consist of a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). The light-shielding material layer can be formed using sputtering or MOCVD techniques.

[0166] Subsequently, a photoresist pattern can be formed on the light-shielding material layer, and the light-shielding material layer not covered by the photoresist pattern can be etched to form the light-shielding layer BML.

[0167] Subsequently, a buffer layer BF can be formed on the light-shielding layer BML. The buffer layer BF can also be formed on the substrate SUB that is not covered by the light-shielding layer BML.

[0168] exist Figure 22 In step S201, the process of forming the first active layer ACT1 of the first transistor T1 and the second active layer ACT2 of the second transistor T2 on the buffer layer BF is similar to... Figure 9 Step S101 is essentially the same, and therefore redundant descriptions will be omitted.

[0169] in addition, Figure 22 Steps S202 and S203 are the same as Figure 9 Steps S202 and S203 are basically the same, and therefore some redundant descriptions can be omitted.

[0170] Fourth, such as Figure 24 As shown, an interlayer dielectric layer 140 is formed on the second gate electrode G2 and the capacitor electrode CE of the second transistor T2, and contact holes CT1, CT2, CT3, CT4, CT5 and CT7 are formed in the interlayer dielectric layer 140. Figure 22 Step S204 in the process.

[0171] Figure 22 Step S204 and Figure 9 The steps S104 are basically the same, except for the seventh contact hole CT7.

[0172] The seventh contact hole CT7 can be a hole that penetrates the interlayer dielectric layer 140 and the buffer layer BF to expose the light-shielding layer BML.

[0173] Fifth, such as Figure 25 As shown, the first source electrode S1 and the first drain electrode D1 of the first transistor T1, the second source electrode S2 and the second drain electrode D2 of the second transistor T2, and the first supply voltage line VDDL can be formed on the interlayer dielectric layer 140. Figure 22 Step S205).

[0174] Figure 22 Step S205 and Figure 9 Step S105 is essentially the same, and therefore some redundant descriptions will be omitted.

[0175] in addition, Figure 22 Step S206 and Figure 9 Step S106 is essentially the same, and therefore some redundant descriptions will be omitted.

[0176] Although some exemplary embodiments of this disclosure have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: substrate; The first active layer of the first transistor and the second active layer of the second transistor on the substrate; The first gate insulating layer on the first active layer; The first gate electrode on the first gate insulating layer; The second gate insulating layer on the second active layer; and The second gate electrode on the second gate insulating layer Wherein the hydrogen concentration of the first gate insulating layer is lower than that of the second gate insulating layer, and The second gate insulating layer is located on the first gate electrode.

2. The display device according to claim 1, wherein, The minimum thickness of the first gate insulating layer is greater than the minimum thickness of the second gate insulating layer.

3. The display device according to claim 1, wherein, The second gate insulating layer is on the upper surface and side surface of the first gate electrode.

4. The display device according to claim 1, wherein, The second gate insulating layer is on the side surface of the first gate insulating layer.

5. The display device according to claim 1, further comprising: A capacitor electrode that overlaps with the first gate electrode on the second gate insulating layer and in a first direction that is the thickness direction of the substrate.

6. The display device according to claim 5, wherein, The capacitor electrodes are on the upper surface of the second gate insulating layer and on a portion of each of the side surfaces of the second gate insulating layer.

7. The display device according to claim 6, wherein, The capacitor electrode overlaps with the first gate electrode in a second direction that intersects the first direction.

8. The display device according to claim 5, wherein, The first active layer includes a first channel region, a first source region on a first side of the first channel region, and a first drain region on a second side of the first channel region.

9. The display device according to claim 8, wherein, The first gate insulating layer is on the first channel region, and the second gate insulating layer is on a portion of the first source region and a portion of the first drain region.

10. The display device according to claim 9, further comprising: Interlayer dielectric layer on the capacitor electrodes; A first source electrode is located on the interlayer dielectric layer and connected to the portion of the first source region other than the aforementioned portion via a first contact hole penetrating the interlayer dielectric layer; as well as A first drain electrode is connected to the portion of the first drain region other than the stated portion, on the interlayer dielectric layer and through a second contact hole penetrating the interlayer dielectric layer.

11. The display device according to claim 10, further comprising: A light-shielding layer on the substrate and overlapping the first channel region in the first direction; as well as A buffer layer between the light-shielding layer and the first active layer. The first source electrode is connected to the light-shielding layer through a contact hole that penetrates the interlayer dielectric layer and the buffer layer.

12. The display device according to claim 10, further comprising: The supply voltage line is connected to the capacitor electrode on the interlayer dielectric layer and through a third contact hole penetrating the interlayer dielectric layer.

13. The display device according to claim 8, wherein, The second active layer includes a second channel region, a second source region on one side of the second channel region, and a second drain region on the opposite side of the second channel region.

14. The display device according to claim 13, wherein, The second gate insulating layer is on the second channel region.

15. The display device according to claim 13, further comprising: Interlayer dielectric layer on the second gate electrode; A second source electrode is connected to the second source region on the interlayer dielectric layer and through a fourth contact hole penetrating the interlayer dielectric layer; as well as The second drain electrode is connected to the second drain region on the interlayer dielectric layer and through a fifth contact hole penetrating the interlayer dielectric layer.

16. The display device according to claim 1, wherein, The first gate insulating layer and the second gate insulating layer comprise silicon oxide layers.

17. The display device according to claim 1, wherein, The first active layer and the second active layer are formed of an oxide semiconductor comprising indium, gallium and oxygen.

18. A method of manufacturing a display device, the method comprising: A first active layer of the first transistor and a second active layer of the second transistor are formed on the substrate; A first gate insulating layer is formed on the first channel region of the first active layer, and a first gate electrode of the first transistor is formed on the first gate insulating layer. The first gate electrode overlaps with the first channel region in a first direction that is the thickness direction of the substrate. as well as A second gate insulating layer is formed on the second channel region of the second active layer, and a second gate electrode of the second transistor is formed on the second gate insulating layer, the second gate electrode overlapping the second channel region in the first direction. Wherein the hydrogen concentration of the first gate insulating layer is lower than that of the second gate insulating layer, and The second gate insulating layer is located on the first gate electrode.

19. The method according to claim 18, wherein, The minimum thickness of the first gate insulating layer is greater than the minimum thickness of the second gate insulating layer.

20. The method according to claim 18, wherein, The second gate electrode forming the second transistor on the second gate insulating layer includes: A capacitor electrode is formed on the second gate insulating layer such that the capacitor electrode overlaps with the first gate electrode in the first direction.

21. The method according to claim 20, wherein, The capacitor electrode overlaps with the first gate electrode in a second direction that intersects the first direction.

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