Display substrate, method of manufacturing the same, and display device including the same

Abstract

The present application relates to a display substrate, a method of manufacturing the same, and a display device including the same. The display substrate includes a substrate; a first gate electrode on the substrate; a first gate insulating layer on the first gate electrode; an active layer on the first gate insulating layer; a second gate insulating layer on the active layer; a second gate electrode on the second gate insulating layer; an interlayer insulating layer on the second gate electrode; a first electrode on the interlayer insulating layer to contact a top surface, sidewalls, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer; and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

Description

Technical Field

[0001] One or more embodiments relate to a display substrate. More particularly, one or more embodiments relate to a display substrate, a method of manufacturing a display substrate, and a display device including the display substrate. Background Technology

[0002] A display device is an apparatus configured to display images for providing visual information to a user. The display device may include light-emitting elements configured to generate light for displaying images. The display device may also include a display substrate comprising transistors configured to provide current and voltage, etc., for driving the light-emitting elements.

[0003] In the manufacturing process of a display substrate, optical processes can be performed to form conductive patterns or contact holes in an insulating layer. Because optical masks are used in these optical processes, and manufacturing time and cost are related to the formation of the optical mask, the manufacturing time and cost of the display substrate can increase with the additional optical processes performed (e.g., optical processes performed in addition to other optical processes). Summary of the Invention

[0004] One or more aspects of the embodiments relate to a display substrate in which the contact resistance between a first electrode and an active layer is reduced, and a display device including the display substrate.

[0005] One or more aspects of the embodiments relate to a method for manufacturing a display substrate for forming a first contact hole and a second contact hole without additional photolithography processes.

[0006] The display substrate according to the embodiments may include: a substrate; a first gate electrode on the substrate; a first gate insulating layer on the substrate covering the first gate electrode; an active layer on the first gate insulating layer; a second gate insulating layer on the first gate insulating layer covering the active layer; a second gate electrode on the second gate insulating layer; an interlayer insulating layer on the second gate insulating layer covering the second gate electrode; a first electrode on the interlayer insulating layer, which contacts the top surface, sidewall, and bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer; and a second electrode on the interlayer insulating layer, which contacts the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

[0007] In one embodiment, the second electrode may contact the top surface of the first gate electrode via a second contact hole.

[0008] In one embodiment, the first contact hole may include: a first portion formed to expose the top surface of the active layer through the second gate insulating layer; a second portion formed to expose the sidewalls of the active layer through the active layer; and a third portion formed to expose the bottom surface of the active layer through the portion of the first gate insulating layer.

[0009] In one implementation, the width of the first portion may be greater than the width of the second portion.

[0010] In one implementation, the width of the third portion may be greater than the width of the second portion.

[0011] In one embodiment, the first gate insulating layer may include a first sub-insulating layer on the substrate to cover the first gate electrode and a second sub-insulating layer on the first sub-insulating layer.

[0012] In one embodiment, this portion of the first gate insulating layer may include a second sub-insulating layer.

[0013] In one embodiment, the first sub-insulating layer may include silicon nitride.

[0014] In one embodiment, the second sub-insulating layer may include silicon oxide.

[0015] In one implementation, the active layer may include polysilicon.

[0016] In one embodiment, the second gate insulating layer may include silicon oxide.

[0017] In one embodiment, the first gate electrode may overlap with the second gate electrode, with the active layer inserted between them.

[0018] In one embodiment, the interlayer insulation layer may include a first interlayer insulation layer on the second gate insulation layer to cover the second gate electrode and a second interlayer insulation layer on the first interlayer insulation layer.

[0019] In one embodiment, the first interlayer insulating layer may include silicon nitride.

[0020] In one embodiment, the display substrate may further include a capacitor electrode between the first interlayer insulating layer and the second interlayer insulating layer and overlapping with the second gate electrode.

[0021] A method for manufacturing a display substrate according to an embodiment may include: forming a first gate electrode on the substrate; forming a first gate insulating layer on the substrate to cover the first gate electrode; forming an active layer on the first gate insulating layer; forming a second gate insulating layer on the first gate insulating layer to cover the active layer; forming a second gate electrode on the second gate insulating layer; forming an interlayer insulating layer on the second gate insulating layer to cover the second gate electrode; forming a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer to expose the top surface, sidewalls, and bottom surface of the active layer; forming a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer to expose the first gate electrode; and forming a first electrode on the interlayer insulating layer to fill the first contact hole and forming a second electrode to fill the second contact hole. The first contact hole and the second contact hole may be formed substantially simultaneously (e.g., synchronously).

[0022] In one embodiment, the first contact hole and the second contact hole can be formed using a dry etching process with an etching gas (e.g., only one etching gas).

[0023] In one embodiment, the first contact hole and the second contact hole can be formed by an etching gas obtained by mixing a first gas comprising at least one of CHF3, C4F8, C2HF5, CH2F2 and CF4 with a second gas comprising at least one of SF6 and NF3.

[0024] In one embodiment, the first contact hole and the second contact hole can be formed by using at least two different etching materials.

[0025] In one embodiment, forming the first contact hole may include: forming a first portion of the first contact hole exposing the top surface of the active layer by etching the second gate insulating layer; forming a second portion of the first contact hole exposing the sidewalls of the active layer by etching the active layer; and forming a third portion of the first contact hole exposing the bottom surface of the active layer by etching the portion of the first gate insulating layer. The first etching material used to form the first portion may be different from the second etching material used to form the second portion.

[0026] In one embodiment, the first etching material may include an etching gas or an etchant comprising a buffered oxide etchant (BOE), which is obtained by mixing a first gas comprising at least one of CHF3, C4F8, C2HF5, CH2F2 and CF4 with a second gas comprising at least one of SF6 and NF3.

[0027] In one embodiment, the second etching material may include an etching gas obtained by mixing a first gas comprising at least one of CHF3, C4F8, C2HF5, CH2F2, and CF4 with a second gas comprising at least one of SF6 and NF3.

[0028] In one embodiment, the third etch material used to form the third portion may be different from the second etch material.

[0029] In one embodiment, the third etching material may be the same as the first etching material.

[0030] A display device according to an embodiment may include: a substrate; a first gate electrode on the substrate; a first gate insulating layer on the substrate covering the first gate electrode; an active layer on the first gate insulating layer; a second gate insulating layer on the first gate insulating layer covering the active layer; a second gate electrode on the second gate insulating layer; an interlayer insulating layer on the second gate insulating layer covering the second gate electrode; a first electrode on the interlayer insulating layer, contacting a top surface, sidewall, and bottom surface of the active layer via a first contact hole passing through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer; a second electrode on the interlayer insulating layer, contacting the first gate electrode via a second contact hole passing through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer; a planarization layer on the interlayer insulating layer covering the first and second electrodes; a pixel electrode on the planarization layer; a counter electrode overlapping the pixel electrode; and a light-emitting layer between the pixel electrode and the counter electrode.

[0031] In the display substrate and display device according to the embodiments, the first electrode can contact the top surface, sidewall and bottom surface of the active layer exposed by the first contact hole through the first contact hole of the active layer, so that the contact resistance between the first electrode and the active layer can be reduced.

[0032] In the method of manufacturing a display substrate according to an embodiment, a first contact hole that exposes the top surface, sidewalls and bottom surface of the active layer through the active layer and a second contact hole that exposes the first gate electrode can be formed substantially simultaneously (e.g., substantially synchronously) so that the first contact hole and the second contact hole can be formed without additional photolithography processes. Attached Figure Description

[0033] Illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0034] Figure 1 This is a cross-sectional view showing a display substrate according to one or more embodiments of the present disclosure.

[0035] Figure 2 To display Figure 1A cross-sectional view of region A.

[0036] Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 A cross-sectional view showing a method of manufacturing a display substrate according to one or more embodiments of the present disclosure.

[0037] Figure 8 , Figure 9 and Figure 10 A cross-sectional view showing a method for manufacturing a display substrate according to another embodiment of the present disclosure.

[0038] Figure 11 A plan view of a display device according to one or more embodiments of the present disclosure.

[0039] Figure 12 To display Figure 11 A circuit diagram of an example pixel.

[0040] Figure 13 For along Figure 11 The cross-sectional view taken by line B-B'. Detailed Implementation

[0041] The following will explain in more detail the display substrate, the method of manufacturing the display substrate, and the display device according to the embodiments, with reference to the accompanying drawings.

[0042] The following text will refer to Figure 1 and Figure 2 A display substrate according to one or more embodiments of the present disclosure is described.

[0043] Figure 1 This is a cross-sectional view showing a display substrate according to one or more embodiments of the present disclosure. Figure 2 To display Figure 1 A cross-sectional view of region A.

[0044] refer to Figure 1 and Figure 2 A display substrate according to one or more embodiments of the present disclosure may include a transistor TR, a capacitor CAP, a first electrode 191, and a second electrode 192 disposed on a substrate 100 (e.g., disposed on a substrate 100 having one or more intermediate layers or components). The transistor TR may include a first gate electrode 110, an active layer 130, and a second gate electrode 150. The capacitor CAP may include a second gate electrode 150 and a capacitor electrode 170. In one or more embodiments, the transistor TR and the capacitor CAP include the same second gate electrode 150 (e.g., the second gate electrode 150 serves as the lower electrode of the capacitor CAP and the upper gate electrode of the transistor TR).

[0045] The substrate 100 may be a transparent insulating substrate including glass, quartz, and / or plastic. In one or more embodiments, the substrate 100 may include a first plastic layer, a first barrier layer disposed on the first plastic layer, a second plastic layer disposed on the first barrier layer, and / or a second barrier layer disposed on the second plastic layer. The first plastic layer and / or the second plastic layer may include an organic insulating material, such as polyimide (PI). The first barrier layer and / or the second barrier layer may include an inorganic insulating material, such as silicon oxide, silicon nitride, and / or amorphous silicon. For example, the first barrier layer may have a multilayer structure including an amorphous silicon layer and a silicon oxide layer disposed on the amorphous silicon layer, and the second barrier layer may have a single-layer structure including a silicon oxide layer.

[0046] A first gate electrode 110 may be disposed on the substrate 100. The first gate electrode 110 may block external light and / or impurities from being introduced into the active layer 130 through the substrate 100. In one or more embodiments, the first gate electrode 110 may be located between the active layer 130 and the substrate 100. Additionally, when a voltage is applied to the first gate electrode 110, the first gate electrode 110 may function as the lower gate electrode of the transistor TR. For example, a DC voltage may be applied to the first gate electrode 110. In this case, the threshold voltage of the transistor TR can be adjusted. Accordingly, the hysteresis characteristics of the transistor TR can be improved. The first gate electrode 110 may comprise a conductive material, such as molybdenum (Mo) and / or copper (Cu).

[0047] A first gate insulating layer 120 may be disposed on the substrate 100 to cover the first gate electrode 110. The first gate insulating layer 120 may prevent impurities from being introduced through the substrate 100 and may provide a flat surface on the substrate 100. In addition, the first gate insulating layer 120 may insulate the active layer 130 from the first gate electrode 110. The first gate insulating layer 120 may include silicon nitride and / or silicon oxide, etc.

[0048] In one or more embodiments, the first gate insulating layer 120 may include a first sub-insulating layer 121 and a second sub-insulating layer 122. The first sub-insulating layer 121 may be disposed on the substrate 100 to cover the first gate electrode 110. The second sub-insulating layer 122 may be disposed on the first sub-insulating layer 121.

[0049] In one or more embodiments, the first sub-insulating layer 121 may include silicon nitride, and the second sub-insulating layer 122 may include silicon oxide. The thickness of the second sub-insulating layer 122 may be greater than the thickness of the first sub-insulating layer 121. For example, the thickness of the second sub-insulating layer 122 may be approximately [missing information]. Furthermore, the thickness of the first sub-insulating layer 121 can be approximately [missing information].

[0050] An active layer 130 may be disposed on the first gate insulating layer 120. The active layer 130 may overlap with the first gate electrode 110 (e.g., in the thickness direction). In one or more embodiments, the active layer 130 may comprise polysilicon. The active layer 130 may comprise a source region, a drain region, and a channel region disposed between the source and drain regions. Each of the source and drain regions may be doped with a P-type impurity or dopant or an N-type impurity or dopant.

[0051] A second gate insulating layer 140 may be disposed on the first gate insulating layer 120 to cover the active layer 130. The second gate insulating layer 140 may insulate the second gate electrode 150 from the active layer 130. In one or more embodiments, the second gate insulating layer 140 may comprise silicon oxide (e.g., SiO2). The thickness of the second gate insulating layer 140 may be approximately [missing information].

[0052] The second gate electrode 150 may be disposed on the second gate insulating layer 140. The second gate electrode 150 may overlap with the channel region of the active layer 130 (e.g., in the thickness direction). The first gate electrode 110 may overlap with the second gate electrode 150, wherein the active layer 130 is inserted between them. The second gate electrode 150 may serve as the upper gate electrode of the transistor TR. Accordingly, the transistor TR may be formed as a transistor with a dual-gate structure, the dual-gate structure including a first gate electrode 110 as the lower gate electrode and a second gate electrode 150 as the upper gate electrode. In addition, the second gate electrode 150 may serve as the lower electrode of the capacitor CAP. The second gate electrode 150 may include a conductive material, such as molybdenum (Mo) and / or copper (Cu).

[0053] A first interlayer insulating layer 160 may be disposed on the second gate insulating layer 140 to cover the second gate electrode 150. The first interlayer insulating layer 160 may insulate the capacitor electrode 170 from the second gate electrode 150. In one or more embodiments, the first interlayer insulating layer 160 may comprise silicon nitride. The thickness of the first interlayer insulating layer 160 may be approximately [missing information - likely a number].

[0054] Capacitor electrode 170 may be disposed on the first interlayer insulating layer 160. Capacitor electrode 170 may overlap with the second gate electrode 150 (e.g., in the thickness direction). Capacitor electrode 170 may function as the upper electrode of capacitor CAP. Accordingly, capacitor CAP may be formed as a capacitor including the second gate electrode 150 as the lower electrode and capacitor electrode 170 as the upper electrode. Capacitor electrode 170 may comprise a conductive material, such as molybdenum (Mo) and / or copper (Cu).

[0055] A second interlayer insulating layer 180 may be disposed on the first interlayer insulating layer 160 to cover the capacitor electrode 170. The second interlayer insulating layer 180 may insulate the first electrode 191 and the second electrode 192 from the capacitor electrode 170. The second interlayer insulating layer 180 may include silicon nitride and / or silicon oxide, etc. The first interlayer insulating layer 160 and the second interlayer insulating layer 180 may be configured (or formed) as interlayer insulating layers.

[0056] A first electrode 191 and a second electrode 192 may be disposed on a second interlayer insulating layer 180. The first electrode 191 may be connected (e.g., electrically connected) to an active layer 130, and the second electrode 192 may be connected (e.g., electrically connected) to a first gate electrode 110. For example, the first electrode 191 may be connected (e.g., electrically connected) to a source or drain region of the active layer 130. Each of the first electrode 191 and the second electrode 192 may comprise a conductive material, such as aluminum (Al), titanium (Ti), and / or copper (Cu).

[0057] The first electrode 191 can contact the active layer 130 through a first contact hole CH1, which is formed through a portion of the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, the active layer 130, and the first gate insulating layer 120. More specifically, the first electrode 191 can contact the top surface 130U, the sidewall 130S, and the bottom surface 130L of the active layer 130 exposed by the first contact hole CH1.

[0058] In one or more embodiments, the first contact hole CH1 may be formed as a second sub-insulating layer 122 passing through the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, the active layer 130, and the first gate insulating layer 120. In other words, the portion of the first gate insulating layer 120 through which the first contact hole CH1 is formed may be the second sub-insulating layer 122. In one or more embodiments, the first contact hole CH1 does not extend through the first sub-insulating layer 121.

[0059] The first contact hole CH1 may include a first portion P1 formed to pass through the second gate insulating layer 140, a second portion P2 formed to pass through the active layer 130, and a third portion P3 formed to pass through that portion of the first gate insulating layer 120 (i.e., the second sub-insulating layer 122). The first portion P1 may expose the top surface 130U of the active layer 130, the second portion P2 may expose the sidewalls 130S of the active layer 130, and the third portion P3 may expose the bottom surface 130L of the active layer 130. In one or more embodiments, the first portion P1 may be a region between opposite ends of the second gate insulating layer 140, the second portion P2 may be a region between opposite ends of the active layer 130, and the third portion P3 may be a region between opposite ends of the second sub-insulating layer 122. In one or more embodiments, the second portion P2 may be between the first portion P1 and the third portion P3. The second portion P2 may be adjacent to the first portion P1 and the third portion P3.

[0060] In one or more embodiments, the width W1 of the first portion P1 may be greater than the width W2 of the second portion P2, and the width W3 of the third portion P3 may be greater than the width W2 of the second portion P2. In other words, the width W2 of the second portion P2 may be smaller or less than the width W1 of the first portion P1, and the width W2 of the second portion P2 may be less or less than the width W3 of the third portion P3. In the process of forming the first contact hole CH1, the second gate insulating layer 140 and the second sub-insulating layer 122 of the first gate insulating layer 120 (the second gate insulating layer 140 and the second sub-insulating layer 122 of the first gate insulating layer 120 include silicon oxide) are etched isotropically, and the active layer 130 including polysilicon is etched anisotropically, so that the width W1 of the first portion P1 and the width W3 of the third portion P3 may be greater than the width W2 of the second portion P2. Accordingly, a portion of the top surface 130U and a portion of the bottom surface 130L of the active layer 130, as well as the sidewall 130S, may be exposed, and the first electrode 191 may contact the top surface 130U, sidewall 130S, and bottom surface 130L of the active layer 130 exposed by the first contact hole CH1.

[0061] The second electrode 192 can contact the first gate electrode 110 through the second contact hole CH2, which is formed through the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, and the first gate insulating layer 120. More specifically, the second electrode 192 can contact the top surface 110U of the first gate electrode 110 exposed by the second contact hole CH2.

[0062] In a display substrate according to a comparative example in the relevant art, the first contact hole may expose only the sidewall of the active layer, and the first electrode may contact the sidewall of the active layer exposed by the first contact hole. In this case, because the first electrode only contacts the sidewall of the active layer, the contact resistance between the first electrode and the active layer may increase. However, in a display substrate according to one or more embodiments of the present disclosure, the top surface 130U and bottom surface 130L of the active layer 130 and the sidewall 130S of the active layer 130 may be exposed by the first contact hole CH1, and the first electrode 191 may contact the top surface 130U, sidewall 130S, and bottom surface 130L of the active layer 130 exposed by the first contact hole CH1. Because the first electrode 191 contacts the top surface 130U and bottom surface 130L of the active layer 130 and the sidewall 130S of the active layer 130, the contact resistance between the first electrode 191 and the active layer 130 may decrease.

[0063] The following text will refer to Figure 1 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 A method for manufacturing a display substrate according to one or more embodiments of the present disclosure is described.

[0064] Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 A cross-sectional view showing a method of manufacturing a display substrate according to one or more embodiments of the present disclosure.

[0065] refer to Figure 3 The first gate electrode 110 may be formed on the substrate 100, and the first gate insulating layer 120 may be formed on the substrate 100 to cover the first gate electrode 110.

[0066] In one or more embodiments, the first gate electrode 110 may be formed on the substrate 100. For example, a conductive layer may be formed on the substrate 100 by depositing a conductive material (such as molybdenum (Mo) and / or copper (Cu)) using physical vapor deposition (such as sputtering), and the conductive layer may be etched to form the first gate electrode 110.

[0067] Next, a first gate insulating layer 120 (including a first sub-insulating layer 121 and a second sub-insulating layer 122) may be formed on the first gate electrode 110. For example, the first sub-insulating layer 121 may be formed by depositing silicon nitride on the first gate electrode 110 using chemical vapor deposition (such as plasma-enhanced chemical vapor deposition (PECVD)), and the second sub-insulating layer 122 may be formed by depositing silicon oxide on the first sub-insulating layer 121 using chemical vapor deposition (such as PECVD).

[0068] refer to Figure 4 The active layer 130 may be formed on the first gate insulating layer 120 (e.g., on the second sub-insulating layer 122), and the second gate insulating layer 140 may be formed on the first gate insulating layer 120 (e.g., on the second sub-insulating layer 122) to cover the active layer 130.

[0069] In one or more embodiments, the active layer 130 may be formed on the first gate insulating layer 120. For example, an amorphous silicon layer may be formed by depositing amorphous silicon on the first gate insulating layer 120 using chemical vapor deposition (e.g., PECVD), and the amorphous silicon layer may be crystallized using an excimer laser or the like to form a polycrystalline silicon layer. Alternatively, the polycrystalline silicon layer may be etched to form the active layer 130.

[0070] Next, a second gate insulating layer 140 may be formed on the active layer 130. For example, the second gate insulating layer 140 may be formed by depositing silicon oxide on the active layer 130 using chemical vapor deposition (e.g., PECVD). In one or more embodiments, the second gate insulating layer 140 is formed on the active layer 130 in response to the formation of the active layer 130.

[0071] refer to Figure 5 The second gate electrode 150 may be formed on the second gate insulating layer 140, and the first interlayer insulating layer 160 may be formed on the second gate insulating layer 140 to cover the second gate electrode 150. In one or more embodiments, the first interlayer insulating layer 160 is formed on the second gate insulating layer 140 in response to the formation of the second gate electrode 150.

[0072] In one or more embodiments, the second gate electrode 150 may be formed on the second gate insulating layer 140. For example, a conductive layer may be formed by depositing a conductive material (such as molybdenum (Mo) and / or copper (Cu)) on the second gate insulating layer 140 using physical vapor deposition (e.g., sputtering), and the conductive layer may be etched to form the second gate electrode 150. After the second gate electrode 150 is formed, P-type impurities or dopants or N-type impurities or dopants may be implanted into the active layer 130 by using the second gate electrode 150 as a mask.

[0073] Next, a first interlayer insulating layer 160 may be formed on the second gate electrode 150. For example, the first interlayer insulating layer 160 may be formed by depositing silicon nitride on the second gate electrode 150 using chemical vapor deposition (e.g., PECVD). In one or more embodiments, the first interlayer insulating layer 160 is formed on the second gate electrode 150 in response to implanting impurities into or doping the active layer 130.

[0074] refer to Figure 6 The capacitor electrode 170 may be formed on the first interlayer insulating layer 160, and the second interlayer insulating layer 180 may be formed on the first interlayer insulating layer 160 to cover the capacitor electrode 170.

[0075] In one or more embodiments, capacitor electrode 170 may be formed on first interlayer insulating layer 160. For example, a conductive layer may be formed by depositing a conductive material (such as molybdenum (Mo) and / or copper (Cu)) on first interlayer insulating layer 160 using physical vapor deposition (such as sputtering), and the conductive layer may be etched to form capacitor electrode 170.

[0076] Next, a second interlayer insulating layer 180 may be formed on the capacitor electrode 170. For example, the second interlayer insulating layer 180 may be formed by depositing silicon nitride or silicon oxide on the capacitor electrode 170 using chemical vapor deposition (e.g., PECVD). In one or more embodiments, the second interlayer insulating layer 180 is formed on the capacitor electrode 170 in response to the formation of the capacitor electrode 170.

[0077] refer to Figure 7 The first contact hole CH1 and the second contact hole CH2 may be formed in the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140 and the first gate insulating layer 120.

[0078] The first contact hole CH1 can expose the active layer 130 through this portion of the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, the active layer 130, and the first gate insulating layer 120. More specifically, the first contact hole CH1 can expose the top surface, sidewalls, and bottom surface of the active layer 130. In one or more embodiments, this portion of the first gate insulating layer 120 can be a second sub-insulating layer 122. In one or more embodiments, the first contact hole CH1 can extend through this portion of the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, the active layer 130, and the first gate insulating layer 120 (e.g., the second sub-insulating layer 122). In one or more embodiments, the first contact hole CH1 can expose the bottom surface of the first interlayer insulating layer 160 that defines the gap between the bottom surface of the first interlayer insulating layer 160 and the top surface of the active layer 130. In one or more embodiments, the first contact hole CH1 may expose the top surface of the first gate insulating layer 120 (e.g., the first sub-insulating layer 121) that defines the gap between the top surface of the first gate insulating layer 120 (e.g., the first sub-insulating layer 121) and the bottom surface of the active layer 130.

[0079] The second contact hole CH2 can expose the first gate electrode 110 through the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, and the first gate insulating layer 120. More specifically, the second contact hole CH2 can expose the top surface of the first gate electrode 110. In one or more embodiments, the second contact hole CH2 extends through the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, and extends into a portion of the first gate insulating layer 120 (e.g., through the second sub-insulating layer 122 and into a portion of the first sub-insulating layer 121). In one or more embodiments, the second contact hole CH2 extends a greater distance in the thickness direction than the first contact hole CH1.

[0080] The first contact hole CH1 and the second contact hole CH2 can be formed simultaneously or substantially at the same time. For example, the first contact hole CH1 and the second contact hole CH2 can be formed substantially at the same time based on an optical process using a mask having light-transmitting portions corresponding to the first contact hole CH1 and the second contact hole CH2, respectively.

[0081] In one or more embodiments, the first contact hole CH1 and the second contact hole CH2 can be formed using an etching scheme (e.g., a dry etching scheme) with an etching gas (e.g., only one etching gas). In other words, by using an etching gas, the first contact hole CH1 can be formed by etching this portion of the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, the active layer 130, and the first gate insulating layer 120, and the second contact hole CH2 can be formed by etching the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, and the first gate insulating layer 120.

[0082] In one or more embodiments, the first contact hole CH1 and the second contact hole CH2 can be formed using an etching gas obtained by mixing a first gas comprising at least one of CHF3, C4F8, C2HF5, CH2F2, and CF4 with a second gas comprising at least one of SF6 and NF3. The first gas can be used to etch polysilicon. The etching rate of the second gas on silicon oxide can be greater than the etching rate of the second gas on silicon nitride.

[0083] In the process of forming the first contact hole CH1, the etching rate of the second gas on silicon oxide is greater than the etching rate of the second gas on silicon nitride, so that the second gate insulating layer 140 and the second sub-insulating layer 122 of the first gate insulating layer 120 (which includes silicon oxide) can be etched isotropically. Accordingly, each of the first portion P1 of the first contact hole CH1 formed by etching the second gate insulating layer 140 and the third portion P3 of the first contact hole CH1 formed by etching the second sub-insulating layer 122 of the first gate insulating layer 120 can have a relatively large width (e.g., a width greater than or larger than the width of the second portion P2 of the first contact hole CH1), and the first portion P1 and the third portion P3 of the first contact hole CH1 can expose the top and bottom surfaces of the active layer 130, respectively.

[0084] Additionally, the first gas can etch the polysilicon during the process of forming the first contact hole CH1, so that the active layer 130 including the polysilicon can be anisotropically etched. Accordingly, the second portion P2 of the first contact hole CH1 formed by etching the active layer 130 can expose the sidewalls of the active layer 130.

[0085] refer to Figure 1A first electrode 191 may fill (e.g., be configured to fill) a first contact hole CH1, and a second electrode 192 may fill (e.g., be configured to fill) a second contact hole CH2. The first electrode 191 and the second electrode 192 may be formed on a second interlayer insulating layer 180. For example, a conductive layer configured to fill the first contact hole CH1 and the second contact hole CH2 may be formed by depositing a conductive material (e.g., aluminum (Al), titanium (Ti), and / or copper (Cu)) on the second interlayer insulating layer 180 using physical vapor deposition (e.g., sputtering), and the conductive layer may be etched to form the first electrode 191 and the second electrode 192. The first electrode 191 may fill the first contact hole CH1 to contact the top surface, sidewalls, and bottom surface of the active layer 130 exposed by the first contact hole CH1. The second electrode 192 may fill the second contact hole CH2 to contact the top surface of the first gate electrode 110 exposed by the second contact hole CH2.

[0086] In a method for manufacturing a display substrate according to a comparative example, two optical processes can be used to form a first contact hole exposing the top surface of the active layer and a second contact hole exposing the top surface of the first gate electrode. In this case, additional optical processes can be used to form the second contact hole, thereby increasing the manufacturing time and cost of the display substrate. However, in a method for manufacturing a display substrate according to one or more embodiments of the present disclosure, one optical process can be used to form a first contact hole CH1 exposing the top surface, sidewalls, and bottom surface of the active layer 130 and a second contact hole CH2 exposing the top surface of the first gate electrode 110. Because the second contact hole CH2 is formed together with the first contact hole CH1 without additional optical processes, the manufacturing time and cost of the display substrate can be reduced (e.g., reduced compared to the comparative example).

[0087] The following text will refer to Figure 8 , Figure 9 and Figure 10 A method for manufacturing a display substrate according to another embodiment of the present disclosure is described.

[0088] Figure 8 , Figure 9 and Figure 10 A cross-sectional view showing a method for manufacturing a display substrate according to another embodiment of the present disclosure. (Refer to...) Figure 8 , Figure 9 and Figure 10 The method for manufacturing the display substrate described herein is consistent with the reference. Figure 1 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7The methods for manufacturing the display substrate described are essentially the same or similar, differing only in the formation of the first contact hole CH1 and the second contact hole CH2. Accordingly, in the reference... Figure 8 , Figure 9 and Figure 10 In the described method for manufacturing a display substrate, the reference... Figure 1 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 Descriptions of components that are substantially the same as or similar to those used in the method of manufacturing the display substrate will not be provided.

[0089] refer to Figure 8 , Figure 9 and Figure 10 The first contact hole CH1 and the second contact hole CH2 may be formed in the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140 and the first gate insulating layer 120.

[0090] In one or more embodiments, the first contact hole CH1 and the second contact hole CH2 can be formed using two or more different etching materials. In other words, by using two or more different etching materials, the first contact hole CH1 can be formed by etching this portion of the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, the active layer 130, and the first gate insulating layer 120, and the second contact hole CH2 can be formed by etching the second interlayer insulating layer 180, the first interlayer insulating layer 160, the second gate insulating layer 140, and the first gate insulating layer 120.

[0091] In one or more embodiments, such as Figure 8 As shown, a first portion P1 of the first contact hole CH1, exposing the top surface of the active layer 130, can be formed by etching the second interlayer insulating layer 180, the first interlayer insulating layer 160, and the second gate insulating layer 140. In one or more embodiments, the bottom surface of the first interlayer insulating layer 160 is exposed by the first contact hole CH1. A first etching material can be used to form the first portion P1 of the first contact hole CH1. Simultaneously with forming the first portion P1 of the first contact hole CH1, a second contact hole CH2 can be partially formed by etching the second interlayer insulating layer 180, the first interlayer insulating layer 160, and the second gate insulating layer 140.

[0092] In one or more embodiments, the first etching material may include an etching gas or an etchant comprising a buffered oxide etchant (BOE), which is obtained by mixing a first gas comprising at least one of CHF3, C4F8, C2HF5, CH2F2, and CF4 with a second gas comprising at least one of SF6 and NF3. The etching rate of the first etching material on silicon oxide may be greater than the etching rate of the first etching material on silicon nitride. Because the etching rate of the first etching material on silicon oxide is greater than the etching rate of the first etching material on silicon nitride, the second gate insulating layer 140 comprising silicon oxide can be etched isotropically. Accordingly, the first portion P1 of the first contact hole CH1 formed by etching the second gate insulating layer 140 may have a relatively large width (e.g., more than or greater than the second portion P2 of the first contact hole CH1 (see...)). Figure 9 (width of the width).

[0093] Next, as Figure 9 As shown, a second portion P2 of the first contact hole CH1, exposing the sidewalls of the active layer 130, can be formed by etching the active layer 130. A second etching material can be used to form the second portion P2 of the first contact hole CH1. Simultaneously with forming the second portion P2 of the first contact hole CH1, the second contact hole CH2 can be partially formed by etching this portion of the first gate insulating layer 120 (e.g., the second sub-insulating layer 122).

[0094] In one or more embodiments, the second etching material may include an etching gas obtained by mixing a first gas comprising at least one of CHF3, C4F8, C2HF5, CH2F2, and CF4 with a second gas comprising at least one of SF6 and NF3, and the second etching material may differ from the first etching material. The second etching material can be used to etch polysilicon. Because the second etching material can etch polysilicon, the active layer 130 comprising polysilicon can be anisotropically etched. Accordingly, the second portion P2 of the first contact hole CH1 formed by etching the active layer 130 may be exposed having a relatively small width (e.g., less than or smaller than the first portion P1 of the first contact hole CH1 and / or the third portion P3 of the first contact hole CH1 (see [link to relevant documentation]). Figure 10 The active layer 130 has a sidewall of width CH1 and the first portion P1 of the first contact hole CH1 can expose the top surface of the active layer 130.

[0095] Next, as Figure 10As shown, a third portion P3 of the first contact hole CH1 exposing the bottom surface of the active layer 130 can be formed by etching this portion of the first gate insulating layer 120 (e.g., the second sub-insulating layer 122). A third etching material can be used to form the third portion P3 of the first contact hole CH1. Simultaneously with forming the third portion P3 of the first contact hole CH1, a second contact hole CH2 can be formed by etching a portion of the first gate insulating layer 120 (e.g., the first sub-insulating layer 121).

[0096] In one or more embodiments, the third etch material may be different from the second etch material. In one or more embodiments, the third etch material may be substantially the same as the first etch material. The etch rate of the third etch material on silicon oxide may be greater than the etch rate of the third etch material on silicon nitride. Because the etch rate of the third etch material on silicon oxide is greater than the etch rate of the third etch material on silicon nitride, the second sub-insulator layer 122 of the first gate insulating layer 120, which includes silicon oxide, can be etched isotropically. Accordingly, the third portion P3 of the first contact hole CH1 formed by etching the second sub-insulator layer 122 of the first gate insulating layer 120 can expose the bottom surface of the active layer 130 with a relatively large width (e.g., more than or greater than the width of the second portion P2 of the first contact hole CH1).

[0097] The following text will refer to Figure 11 , Figure 12 and Figure 13 This describes a display device according to one or more embodiments of the present disclosure.

[0098] Figure 11 A plan view of a display device according to one or more embodiments of the present disclosure.

[0099] refer to Figure 11 A display device according to one or more embodiments may include a plurality of pixels PX. Each of the pixels PX may emit light, and the display device may display an image formed by using the light emitted from each of the pixels PX. The pixels PX may be arranged substantially in a matrix form along the row and column directions.

[0100] Figure 12 To display Figure 11 A circuit diagram of an example pixel PX.

[0101] refer to Figure 12 A pixel PX may include a pixel circuit PC and a light-emitting element EL connected to the pixel circuit PC. The pixel circuit PC may provide a drive current to the light-emitting element EL. The light-emitting element EL may emit light based on the drive current provided from the pixel circuit PC. The pixel circuit PC may include at least one transistor and at least one capacitor to generate the drive current.

[0102] In one or more embodiments, the pixel circuit PC may include a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, a seventh transistor TR7, and a capacitor CAP, but this disclosure is not limited thereto. In another embodiment, the pixel circuit PC may include two to six or eight or more transistors, and / or two or more capacitors.

[0103] The gate electrode of the first transistor TR1 can be connected to a first node N1. The source electrode of the first transistor TR1 can be connected to a second node N2, and the drain electrode of the first transistor TR1 can be connected to a third node N3. The first transistor TR1 can generate a drive current based on the voltage between the gate electrode and the source electrode.

[0104] A first scan signal SS1 can be applied to the gate electrode of the second transistor TR2. A data signal DS can be applied to the source electrode of the second transistor TR2, and the drain electrode of the second transistor TR2 can be connected to the second node N2. The second transistor TR2 can transmit the data signal DS to the second node N2 based on the first scan signal SS1.

[0105] A first scan signal SS1 can be applied to the gate electrode of a third transistor TR3. The source electrode of the third transistor TR3 can be connected to a first node N1, and the drain electrode of the third transistor TR3 can be connected to a third node N3. The third transistor TR3 can compensate for the threshold voltage of the first transistor TR1 by connecting the gate and drain electrodes of the first transistor TR1 based on the first scan signal SS1.

[0106] The second scan signal SS2 can be applied to the gate electrode of the fourth transistor TR4. In one or more embodiments, when pixel PX is included in the Nth pixel row, the second scan signal SS2 can be a first scan signal applied to the (N-1)th pixel row. The initialization voltage VINT can be applied to the source electrode of the fourth transistor TR4, and the drain electrode of the fourth transistor TR4 can be connected to the first node N1. The fourth transistor TR4 can initialize the gate electrode of the first transistor TR1 by transmitting the initialization voltage VINT to the first node N1 based on the second scan signal SS2.

[0107] The light emission control signal EM can be applied to the gate electrode of the fifth transistor TR5. The first power supply voltage VDD can be applied to the source electrode of the fifth transistor TR5, and the drain electrode of the fifth transistor TR5 can be connected to the second node N2.

[0108] The light emission control signal EM can be applied to the gate electrode of the sixth transistor TR6. The source electrode of the sixth transistor TR6 can be connected to the third node N3, and the drain electrode of the sixth transistor TR6 can be connected to the light-emitting element EL. The fifth transistor TR5 and the sixth transistor TR6 can transmit the drive current generated by the first transistor TR1 to the light-emitting element EL based on the light emission control signal EM.

[0109] The third scan signal SS3 may be applied to the gate electrode of the seventh transistor TR7. In one or more embodiments, when pixel PX is included in the Nth pixel row, the third scan signal SS3 may be a first scan signal applied to the (N+1)th pixel row. The initialization voltage VINT may be applied to the source electrode of the seventh transistor TR7, and the drain electrode of the seventh transistor TR7 may be connected to the light-emitting element EL. The seventh transistor TR7 can initialize the light-emitting element EL by transmitting the initialization voltage VINT to the light-emitting element EL based on the third scan signal SS3.

[0110] A first power supply voltage VDD can be applied to the first electrode of capacitor CAP, and the second electrode of capacitor CAP can be connected to the first node N1. Even when the second transistor TR2 is turned off, capacitor CAP can maintain the voltage between the gate electrode and the source electrode of the first transistor TR1 so that the light-emitting element EL can emit light.

[0111] The first electrode of the light-emitting element EL can be connected to the pixel circuit PC, and a second power supply voltage VSS can be applied to the second electrode of the light-emitting element EL. In one or more embodiments, the second power supply voltage VSS can be less than the first power supply voltage VDD. The light-emitting element EL can emit light based on a drive current transmitted from the pixel circuit PC.

[0112] Figure 13 For along Figure 11 The cross-sectional view taken by line B-B'.

[0113] refer to Figure 13 A display device according to one or more embodiments of the present disclosure may include a transistor TR, a capacitor CAP, a first electrode 191, a second electrode 192, a light-emitting element EL, and an encapsulation layer 260 disposed on a substrate 100. (Refer to...) Figure 13 The described display device may include references Figure 1 and Figure 2 The described display substrate. Accordingly, in the reference... Figure 13 In the described display device, compared with the reference Figure 1 and Figure 2 Descriptions of components that are substantially the same as or similar to those of the components described for the display substrate will no longer be provided.

[0114] In one or more embodiments, transistor TR may be Figure 12 One of the first transistor TR1, the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7.

[0115] A planarization layer 200 may be disposed on the second interlayer insulating layer 180 to cover the first electrode 191 and the second electrode 192. The planarization layer 200 may provide a flat surface on the first electrode 191 and the second electrode 192. The planarization layer 200 may include an organic insulating material, such as polyimide (PI).

[0116] A light-emitting element EL, including a pixel electrode 210, a counter electrode 240 overlapping the pixel electrode 210 (e.g., in the thickness direction), and a light-emitting layer 230 disposed between the pixel electrode 210 and the counter electrode 240, can be disposed on the planarization layer 200.

[0117] Pixel electrode 210 may be disposed on planarization layer 200. Pixel electrode 210 may include conductive materials, such as metals, alloys, and / or transparent conductive oxides. For example, pixel electrode 210 may include silver (Ag) and / or indium tin oxide (ITO), etc.

[0118] A pixel defining layer 220 may be disposed on the planarization layer 200 to cover the pixel electrode 210. The pixel defining layer 220 may have a pixel opening OP that exposes at least a portion of the pixel electrode 210. In one or more embodiments, the pixel opening OP may expose a central portion of the pixel electrode 210, and the pixel defining layer 220 may cover a peripheral portion of the pixel electrode 210. The pixel defining layer 220 may include an organic insulating material, such as polyimide (PI).

[0119] The light-emitting layer 230 may be disposed on the pixel electrode 210. The light-emitting layer 230 may be disposed on the pixel electrode 210 exposed by the pixel opening OP. The light-emitting layer 230 may include at least one of organic light-emitting materials and quantum dots.

[0120] In one or more embodiments, the organic light-emitting material may include low-molecular-weight organic compounds or high-molecular-weight organic compounds. For example, low-molecular-weight organic compounds may include copper phthalocyanine, N,N'-diphenylbenzidine and / or tri-(8-hydroxyquinoline)aluminum, and high-molecular-weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylenevinylene and / or polyfluorene.

[0121] In one or more embodiments, the quantum dot may include a core comprising Group II-VI compounds, Group III-V compounds, Group IV-VI compounds, Group IV elements, and / or Group IV compounds. In one or more embodiments, the quantum dot may have a core-shell structure comprising a core and a shell surrounding the core. The shell may serve as a protective layer for preventing or substantially preventing nuclear chemical denaturation to maintain semiconductor properties, and may also serve as a charging layer for imparting electrophoretic properties to the quantum dot.

[0122] Counter electrode 240 may be disposed on light-emitting layer 230. In one or more embodiments, counter electrode 240 may also be disposed on pixel defining layer 220. Counter electrode 240 may include conductive materials, such as metals, alloys, and transparent conductive oxides. For example, counter electrode 240 may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), and / or titanium (Ti).

[0123] An encapsulation layer 260 may be disposed on the counter electrode 240. The encapsulation layer 260 may cover the light-emitting element EL to protect it from impurities (such as oxygen and moisture). The encapsulation layer 260 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In one or more embodiments, the encapsulation layer 260 may include a first inorganic encapsulation layer 261 disposed on the counter electrode 240, an organic encapsulation layer 262 disposed on the first inorganic encapsulation layer 261, and a second inorganic encapsulation layer 263 disposed on the organic encapsulation layer 262. The inorganic encapsulation layer may include silicon nitride and / or silicon oxynitride, etc., and the organic encapsulation layer may include epoxy resins, acrylic resins, and / or polyimide resins, etc.

[0124] The display substrate according to the embodiments can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs and / or MP3 players, etc.

[0125] The terminology used herein is for the purpose of describing particular exemplary implementations only and is not intended to limit the exemplary implementations described herein.

[0126] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0127] It should be further understood that the terms “includes,” “including,” “comprises,” and / or “comprising,” when used in this specification, indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0128] As used in this article, expressions such as “at least one of…”, “one of…”, and “selected from” modify the entire column of elements after a list of elements, but not individual elements within that column.

[0129] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items.

[0130] Furthermore, when describing embodiments of this disclosure, the word "may" refers to "one or more embodiments of this disclosure".

[0131] As used in this article, phrases such as “plan view” can refer to a view viewed from above or from a direction perpendicular to the surface of the display substrate.

[0132] It will be understood that when an element is referred to as being "on" another element, "connected to" another element, or "attached to" another element, it may be directly on, directly connected to, or directly attached to the other element, or there may be one or more intermediate elements. When an element is referred to as being "directly on" another element, "directly connected to," or "directly attached to" another element, there are no intermediate elements.

[0133] For ease of description, spatial relative terms, such as “below,” “under,” “down,” “above,” “up,” “bottom,” and “top,” are used herein to conveniently describe the relationship between one element or feature and another element (or feature) or feature (or feature) as shown in the figures. It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, the element described as “below” or “under” other elements or features will then be oriented “above” or “on” other elements or features. Thus, the term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0134] As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation rather than as terms of degree, and are intended to explain the inherent biases of measurements or calculations that will be recognized by one of ordinary skill in the art.

[0135] As used herein, the terms “use,” “using,” and “used” can be considered synonymous with the terms “utilize,” “utilizing,” and “utilizing,” respectively.

[0136] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that terms, such as those defined in common dictionaries, shall be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly so specified herein.

[0137] Although the display substrate, the method of manufacturing the display substrate, and the display device according to embodiments have been described with reference to the accompanying drawings, the embodiments shown are examples and may be modified and altered by those skilled in the art without departing from the spirit of the technology described in the appended claims and their equivalents.

Claims

1. A display substrate, comprising: substrate; The first gate electrode on the substrate; A first gate insulating layer is applied to the substrate to cover the first gate electrode. The active layer on the first gate insulating layer; A second gate insulating layer is placed on the first gate insulating layer to cover the active layer; A second gate electrode on the second gate insulating layer, the second gate electrode overlapping the first gate electrode such that the active layer is inserted between the first gate electrode and the second gate electrode; An interlayer insulating layer covering the second gate electrode is placed on the second gate insulating layer. A first electrode is located on the interlayer insulating layer to contact the top surface, sidewall, and bottom surface of the active layer via a first contact hole passing through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer. as well as The second electrode is located on the interlayer insulating layer and contacts the first gate electrode via a second contact hole passing through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, but not through the active layer. The second electrode is spaced apart from the active layer.

2. The display substrate of claim 1, wherein the second electrode contacts the top surface of the first gate electrode via the second contact hole.

3. The display substrate as claimed in claim 1, wherein the first contact hole comprises: The first portion is formed to expose the top surface of the active layer through the second gate insulating layer; The second part is formed through the active layer to expose the sidewalls of the active layer; as well as The third portion is formed through the portion of the first gate insulating layer to expose the bottom surface of the active layer.

4. The display substrate of claim 3, wherein the width of the first portion is greater than the width of the second portion, and The width of the third part is greater than the width of the second part.

5. The display substrate of claim 1, wherein the first gate insulating layer comprises: A first sub-insulating layer is placed on the substrate to cover the first gate electrode; as well as A second sub-insulating layer on top of the first sub-insulating layer, and The portion of the first gate insulating layer includes the second sub-insulating layer.

6. A method for manufacturing a display substrate, the method comprising: A first gate electrode is formed on the substrate; A first gate insulating layer is formed on the substrate to cover the first gate electrode; An active layer is formed on the first gate insulating layer; A second gate insulating layer is formed on the first gate insulating layer to cover the active layer; A second gate electrode is formed on the second gate insulating layer, and the second gate electrode overlaps with the first gate electrode so that the active layer is inserted between the first gate electrode and the second gate electrode; An interlayer insulating layer is formed on the second gate insulating layer to cover the second gate electrode; A first contact hole is formed through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer to expose the top surface, sidewalls, and bottom surface of the active layer; A second contact hole is formed through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, but not through the active layer, to expose the first gate electrode; as well as A first electrode is formed on the interlayer insulating layer to fill the first contact hole, and a second electrode is formed to fill the second contact hole and spaced apart from the active layer. The first contact hole and the second contact hole are formed simultaneously.

7. The method of claim 6, wherein the first contact hole and the second contact hole are formed using an etching gas via a dry etching process.

8. The method of claim 6, wherein the first contact hole and the second contact hole are formed using at least two different etching materials.

9. The method of claim 8, wherein the formation of the first contact hole comprises: A first portion of the first contact hole is formed by etching the second gate insulating layer to expose the top surface of the active layer; A second portion of the first contact hole, exposing the sidewall of the active layer, is formed by etching the active layer; as well as By etching the portion of the first gate insulating layer, a third portion of the first contact hole, exposing the bottom surface of the active layer, is formed, and The first etching material used to form the first part is different from the second etching material used to form the second part.

10. The method of claim 9, wherein the third etch material used to form the third portion is different from the second etch material, and The third etching material is the same as the first etching material.

11. A display device, comprising: substrate; The first gate electrode on the substrate; A first gate insulating layer is applied to the substrate to cover the first gate electrode. The active layer on the first gate insulating layer; A second gate insulating layer is placed on the first gate insulating layer to cover the active layer; A second gate electrode on the second gate insulating layer, the second gate electrode overlapping the first gate electrode such that the active layer is inserted between the first gate electrode and the second gate electrode; An interlayer insulating layer covering the second gate electrode is placed on the second gate insulating layer. A first electrode is located on the interlayer insulating layer to contact the top surface, sidewall, and bottom surface of the active layer via a first contact hole passing through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer. The second electrode is on the interlayer insulating layer to contact the first gate electrode via a second contact hole passing through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, but not through the active layer, and the second electrode is spaced apart from the active layer; A planarization layer is applied to the interlayer insulating layer to cover the first electrode and the second electrode. Pixel electrodes on the planarization layer; The counter electrode overlapping the pixel electrode; and The light-emitting layer between the pixel electrode and the counter electrode.

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