Semiconductor device package

Abstract

A semiconductor device package includes a carrier, a stop layer, a barrier layer, and an encapsulant. The carrier has a first surface and a second surface that is recessed relative to the first surface. The stop layer is disposed on the second surface of the carrier. The barrier layer is disposed on the stop layer and protrudes from the first surface of the carrier. The encapsulant is disposed on the first surface of the carrier. Furthermore, the encapsulant has a side surface that is disposed on the barrier layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package and a semiconductor device package having a region or space without encapsulating material, etc. Background Technology

[0002] Molding is a packaging technique used for semiconductor packaging to protect a substrate and components on it. However, in some implementations, not all areas of the substrate are covered by the encapsulation material (also known as molding material), such as in antenna-on-package (AoP) implementations where impedance matching may be desired along the component-to-antenna path. Therefore, semiconductor device packages can have non-molded areas or spaces (areas or spaces free of encapsulation material), and users can easily adjust impedance matching by adjusting surface mount technology (SMT) passive components after the molding process. Summary of the Invention

[0003] According to an example embodiment of this disclosure, a semiconductor device package includes a carrier, a stop layer, a barrier layer, and an encapsulating material. The carrier has a first surface and a second surface recessed relative to the first surface. The stop layer is disposed on the second surface of the carrier. The barrier layer is disposed on the stop layer and protrudes from the first surface of the carrier. The encapsulating material is disposed on the first surface of the carrier. Furthermore, the encapsulating material has side surfaces disposed on the barrier layer.

[0004] According to another example embodiment of this disclosure, a semiconductor device package includes a carrier, a stop layer, a first barrier layer, and an encapsulating material. The carrier has a first surface and a second surface recessed relative to the first surface. The stop layer is disposed on the second surface of the carrier. The first barrier layer is disposed on the stop layer and has a third surface coplanar with or recessed relative to the first surface. The encapsulating material is disposed on the first surface of the carrier. Furthermore, the encapsulating material has side surfaces disposed on the third surface of the barrier layer.

[0005] According to another example embodiment of this disclosure, a semiconductor device package includes a carrier, a stop layer, and an encapsulating material. The carrier has a first surface, a second surface recessed relative to the first surface, and a third surface connected to the first surface. The stop layer is disposed on the second surface of the carrier. The encapsulating material is disposed on the first surface of the carrier. The third surface of the carrier is disposed on the stop layer, and the encapsulating material has side surfaces coplanar with the third surface of the carrier.

[0006] To further understand this disclosure, the following embodiments are provided together with the accompanying drawings to facilitate understanding of this disclosure; however, the drawings are provided for reference and illustration only and are not intended to limit the scope of this disclosure. Attached Figure Description

[0007] Figure 1 This is a schematic perspective view of a semiconductor device package according to an embodiment of the present disclosure.

[0008] Figure 2 This is a schematic perspective view of a semiconductor device package according to another embodiment of the present disclosure.

[0009] Figure 3 This is a schematic perspective view of a semiconductor device package according to another embodiment of the present disclosure.

[0010] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F A method for manufacturing a semiconductor device package according to embodiments of the present disclosure is illustrated.

[0011] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F A method for manufacturing a semiconductor device package according to embodiments of the present disclosure is illustrated.

[0012] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E and Figure 6F A method for manufacturing a semiconductor device package according to embodiments of the present disclosure is illustrated.

[0013] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F A method for manufacturing a semiconductor device package according to embodiments of the present disclosure is illustrated.

[0014] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F A method for manufacturing a semiconductor device package according to embodiments of the present disclosure is illustrated.

[0015] Figure 9A , Figure 9B, Figure 9C , Figure 9D , Figure 9E and Figure 9F A method for manufacturing a semiconductor device package according to embodiments of the present disclosure is illustrated. Detailed Implementation

[0016] The above illustrations and the following detailed description are exemplary for the purpose of further explaining the scope of this disclosure. Other objects and advantages relating to this disclosure will be shown in the following description and drawings.

[0017] Figure 1 A semiconductor device package 1 according to an embodiment of the present disclosure is illustrated. Specifically, the semiconductor device package 1 may have a molded region 13 and a non-molded region 15. As used herein, the term "molded region" may refer to a region covered by molding material (e.g., a region of the substrate), and the term "non-molded region" may refer to a region (e.g., a region of the substrate) or space that is substantially free of molding material. Reference Figure 1 The semiconductor device package 1 may include a carrier 10. The carrier 10 has an upper surface 11. An encapsulation material 131 may be disposed on the upper surface 11 of the carrier 10. A die 133 and an assembly 135 (e.g., an electronic assembly, such as a passive electronic assembly) are disposed on the upper surface 11 of the carrier 10, and the die and assembly are covered by the encapsulation material 131. Figure 1 As shown, the area covered by the encapsulating material 131 is the molding area 13. Furthermore, refer to... Figure 1 A region of the upper surface 11 of the carrier 10 is exposed from the encapsulating material 131 (e.g., substantially free of encapsulating material 131). This exposed region is the unmolded region 15. In the unmolded region 15, substantially no encapsulating material 131 is disposed on the upper surface 11 of the carrier 10, and the die 151 and assembly 153 disposed on the upper surface 11 of the carrier 10 are not covered by the encapsulating material 131 and are therefore exposed. Furthermore, a conductive layer 14 is disposed on the upper surface 11 of the carrier 10. The conductive layer 14 may include a stop layer or include both a stop layer and a barrier layer. The conductive layer 14 may be substantially located at and / or along the interface between the molded region 13 and the unmolded region 15. That is, the conductive layer 14 may be substantially located between the molded region 13 and the unmolded region 15. Reference Figure 1 The conductive layer 14 looks like zigzag stripes, and the molded region 13 and the non-molded region 15 are separated from each other by the zigzag stripes.

[0018] Figure 2A semiconductor device package 2 according to an embodiment of the present disclosure is illustrated. Specifically, the semiconductor device package 2 may have a molded region 23 and a non-molded region 25. As used herein, the term "molded region" may refer to a region covered by molding material (e.g., a region of the substrate), and the term "non-molded region" may refer to a region (e.g., a region of the substrate) or space that is substantially free of molding material. Reference Figure 2 The semiconductor device package 2 may include a carrier 20. The carrier 20 has an upper surface 21. An encapsulation material 231 may be disposed on the upper surface 21 of the carrier 20. A die 233 and an assembly 235 (e.g., an electronic assembly, such as a passive electronic assembly) are disposed on the upper surface 21 of the carrier 20, and the die and assembly are covered by the encapsulation material 231. Figure 2 As shown, the area covered by the encapsulating material 231 is the molding area 23. Furthermore, refer to... Figure 2 A region of the upper surface 21 of the carrier 20 is exposed from the encapsulation material 231 (e.g., substantially free of encapsulation material 231). This exposed region is the unmolded region 25. In the unmolded region 25, substantially no encapsulation material 231 is disposed on the upper surface 21 of the carrier 20, and the die 251 and assembly 253 disposed on the upper surface 21 of the carrier 20 are not covered by the encapsulation material 231 and are therefore exposed. Additionally, a connector can be disposed on the upper surface 21 of the carrier 20 and can be left uncovered by the encapsulation material 231 (not shown), wherein the connector can be electrically connected to external components via a flexible printed circuit board (FPC). Furthermore, a conductive layer 24 is disposed on the upper surface 21 of the carrier 20. The conductive layer 24 may include a stop layer or include both a stop layer and a barrier layer. The conductive layer 24 may be substantially positioned at and / or extending along the interface between the molded region 23 and the unmolded region 25. In other words, the conductive layer 24 can be substantially positioned between the molded region 23 and the unmolded region 25. (Reference) Figure 2 The two ends of the conductive layer 24 are respectively positioned at two adjacent sides 201 and 202 of the carrier 20. Therefore, the non-molded area 25 is basically positioned at the corner of the upper surface 21 of the carrier 20.

[0019] Figure 3 A semiconductor device package 3 according to an embodiment of the present disclosure is illustrated. Specifically, the semiconductor device package 3 may have a molded region 33 and a non-molded region 35. As used herein, the term "molded region" may refer to a region covered by molding material (e.g., a region of the substrate), and the term "non-molded region" may refer to a region (e.g., a region of the substrate) or space that is substantially free of molding material. Reference Figure 3The semiconductor device package 3 may include a carrier 30. The carrier 30 has an upper surface 31. An encapsulation material 331 may be disposed on the upper surface 31 of the carrier 30. A die 333 and an assembly 335 (e.g., an electronic assembly, such as a passive electronic assembly) are disposed on the upper surface 31 of the carrier 30, and the die and assembly are covered by the encapsulation material 331. Figure 3 As shown, the area covered by the encapsulating material 331 is the molding area 33. Furthermore, refer to... Figure 3 A region of the upper surface 31 of the carrier 30 is exposed from the encapsulation material 331 (e.g., substantially free of encapsulation material 331). This exposed region is the unmolded region 35. In the unmolded region 35, substantially no encapsulation material 331 is disposed on the upper surface 31 of the carrier 30, and the die 351 and assembly 353 disposed on the upper surface 31 of the carrier 30 are not covered by the encapsulation material 331 and are therefore exposed. Furthermore, a conductive layer 34 is disposed on the upper surface 31 of the carrier 30. The conductive layer 34 may include a stop layer or include both a stop layer and a barrier layer. The conductive layer 34 may be substantially located at and / or along the interface between the molded region 33 and the unmolded region 35. That is, the conductive layer 34 may be substantially located between the molded region 33 and the unmolded region 35. Reference Figure 3 The conductive layer 34 is annular. Therefore, the non-molded region 35 is essentially surrounded by the molded region 33.

[0020] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F The manufacturing of a semiconductor device package 4 (e.g., according to an embodiment of the present disclosure) is illustrated. Figure 4F The method shown is as follows. Figure 4A As shown, the carrier 41 has an upper surface 411 and two recesses 410 formed in the upper surface 411. The carrier 41 may have a recessed surface 412 that is recessed relative to the upper surface 411 (e.g., defining the bottom of the recesses 410). Stop layers 42 can be received in the recesses 410 respectively, and therefore the stop layers can be disposed on the recessed surfaces 412 respectively. In other words, the stop layers 42 can be embedded in the carrier 41. A barrier layer 43 can be disposed on the stop layers 42 and the barrier layer can protrude from the upper surface 411 of the carrier 41. The barrier layer 43 and the stop layer 42 can be integrated with each other. Furthermore, the stop layer 42 and the barrier layer 43 can be made of the same material. Reference Figure 4A The cross-sectional width of the stop layer 42 is greater than that of the barrier layer 43. In particular, the combination of the stop layer 42 and the barrier layer 43 can be substantially inverted T-shaped. At least two electronic components 481 and 482 are disposed on the upper surface 411 of the carrier 41.

[0021] like Figure 4A As shown, the barrier layer 43 may have a side surface 431 connected to the upper surface 421 of the stop layer 42. Furthermore, a space may exist between the side surface 431 of the barrier layer 43 and the carrier 41. Additionally, the barrier layer 43 may further have a side surface 432 opposite to the side surface 431. At least a portion of the side surface 432 may be substantially attached to the carrier 41. Furthermore, the portion of the upper surface 411 of the carrier 41 positioned between the recesses 410 may further include a wetting layer 49.

[0022] In addition, refer to Figure 4B Adhesive is applied to the portion of the upper surface 411 of the carrier 41 located between the recesses 410. Since the barrier layer 43 protrudes from the upper surface 411 of the carrier 41, the adhesive will not flow across the barrier layer 43. That is, a removable / sacrificial layer 47 will be formed between the barrier layers 43. Furthermore, adhesive can flow into the space between the side surfaces 431 of the barrier layer 43 and the carrier 41. Additionally, since the portion of the upper surface 411 of the carrier 41 located between the recesses 410 may further include a wetting layer 49, the adhesive will be smoothly distributed, and ultimately a removable / sacrificial layer 47 will be uniformly formed between the barrier layers 43.

[0023] refer to Figure 4C Encapsulating material 40 is placed on carrier 41, and the encapsulating material encapsulates the upper surface 411, stop layer 42, barrier layer 43, removable / sacrificial layer 47, and components 481 and 482 of carrier 41. That is, encapsulating material 40 covers the upper surface 411, stop layer 42, barrier layer 43, removable / sacrificial layer 47, and components 481 and 482 of carrier 41.

[0024] refer to Figure 4D A portion of the encapsulating material 40 is removed using a laser process, thereby exposing a portion of the barrier layer 43. Thus, the encapsulating material 40 is divided into three parts 44 and 45, with encapsulating material part 44 attached to the upper surface 411 of the carrier 41 and the barrier layer 43, and encapsulating material part 45 attached to the removable / sacrificial layer 47. Specifically, when the portion of the encapsulating material 40 is removed by the laser process, the laser beam is projected onto the barrier layer 43 or onto the barrier layer 43 and the stop layer 42, and therefore will not damage the carrier 41.

[0025] refer to Figure 4EThe removable / sacrificial layer 47 is removed by physical or chemical methods (such as a water washing process). Additionally, the encapsulating material portion 45 attached to the removable / sacrificial layer 47 is removed (e.g., simultaneously with the removal of the removable / sacrificial layer 47). After removing the removable / sacrificial layer 47 and the encapsulating material portion 45, the encapsulating material portion 44 remains on the carrier 41, and the portion of the upper surface 411 located between the recesses 410 and the wetting layer 49 are exposed. Furthermore, the portion of the barrier layer 43 protruding from the upper surface 411 of the carrier 41 (e.g., the portion of the side surface 431 above the upper surface 411 of the carrier 41) is also exposed. Furthermore, the encapsulating material portion 44 is disposed on the upper surface 411 of the carrier 41.

[0026] like Figure 4E As shown, the encapsulating material portion 44 may have a side surface 441 located on the barrier layer 43. Additionally, adhesive may flow into the space between the side surface 431 of the barrier layer 43 and the carrier 41. Therefore, after removing the removable / sacrificial layer 47, the entire side surface 431 of the barrier layer 43 can be exposed.

[0027] refer to Figure 4F At least one electronic component 483 is disposed on the portion of the upper surface 411 located between the recesses 410. Furthermore, a shielding layer 445 may be formed on the encapsulation material portion 44 and said shielding layer may be connected to the stop layer 42 and the barrier layer 43. The shielding layer 445 may be grounded via the stop layer 42 and the barrier layer 43.

[0028] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F This illustrates the manufacture of a semiconductor device package 5 (such as...) according to another embodiment of the present disclosure. Figure 5F The method shown is as follows. Figure 5A As shown, the carrier 51 has an upper surface 511 and two recesses 510 formed in the upper surface 511. The carrier 51 may have a recessed surface 512 that is recessed relative to the upper surface 511 (e.g., defining the bottom of the recesses 510). Stop layers 52 can be received in the recesses 510 respectively, and therefore the stop layers can be disposed on the recessed surfaces 512 respectively. In other words, the stop layers 52 can be embedded in the carrier 51. A barrier layer 53 can be disposed on the stop layers 52 and the barrier layer can protrude from the upper surface 511 of the carrier 51. The barrier layer 53 and the stop layer 52 can be integrated with each other. Furthermore, the stop layer 52 and the barrier layer 53 can be made of the same material. Reference Figure 5AThe cross-sectional width of the stop layer 52 is greater than that of the barrier layer 53. In particular, the combination of the stop layer 52 and the barrier layer 53 can be substantially L-shaped. At least two electronic components 581 and 582 are disposed on the upper surface 511 of the carrier 51.

[0029] like Figure 5A As shown, the barrier layer 53 has a side surface 531 connected to the upper surface 521 of the stop layer 52. Furthermore, a space may exist between the side surface 531 of the barrier layer 53 and the carrier 51. Additionally, the barrier layer 53 may further have a side surface 532 opposite to the side surface 531. At least a portion of the side surface 532 may be substantially attached to the carrier 51. Furthermore, the portion of the upper surface 511 of the carrier 51 positioned between the recesses 510 may further include a wetting layer 59.

[0030] In addition, refer to Figure 5B Adhesive is applied to the portion of the upper surface 511 of the carrier 51 located between the recesses 510. Since the barrier layer 53 protrudes from the upper surface 511 of the carrier 51, the adhesive will not flow across the barrier layer 53. That is, a removable / sacrificial layer 57 will be formed between the barrier layers 53. Furthermore, adhesive can flow into the space between the side surfaces 531 of the barrier layer 53 and the carrier 51. Additionally, since the portion of the upper surface 511 of the carrier 51 located between the recesses 510 may further include a wetting layer 59, the adhesive will be smoothly distributed, and ultimately a removable / sacrificial layer 57 will be uniformly formed between the barrier layers 53.

[0031] refer to Figure 5C Encapsulating material 50 is placed on carrier 51, and the encapsulating material encapsulates the upper surface 511, stop layer 52, barrier layer 53, removable / sacrificial layer 57, and components 581 and 582 of carrier 51. That is, encapsulating material 50 covers the upper surface 511, stop layer 52, barrier layer 53, removable / sacrificial layer 57, and components 581 and 582 of carrier 51.

[0032] refer to Figure 5D A portion of the encapsulating material 50 is removed using a laser process, thereby exposing a portion of the barrier layer 53. Thus, the encapsulating material 50 is divided into three parts 54 and 55, where encapsulating material part 54 is attached to the upper surface 511 of the carrier 51 and the barrier layer 53, and encapsulating material part 55 is attached to the removable / sacrificial layer 57. Specifically, when the portion of the encapsulating material 50 is removed by the laser process, the laser is projected onto the barrier layer 53 or onto the barrier layer 53 and the stop layer 52 without damaging the carrier 51.

[0033] refer to Figure 5EThe removable / sacrificial layer 57 is removed by physical or chemical methods (such as a water washing process). Additionally, the encapsulating material portion 55 attached to the removable / sacrificial layer 57 is removed (e.g., simultaneously with the removal of the removable / sacrificial layer 57). After removing the removable / sacrificial layer 57 and the encapsulating material portion 55, the encapsulating material portion 54 remains on the carrier 51, and the portion of the upper surface 511 located between the recesses 510 and the wetting layer 59 are exposed. Furthermore, the portion of the barrier layer 53 protruding from the upper surface 511 of the carrier 51 (e.g., the portion of the side surface 531 above the upper surface 511 of the carrier 51) is also exposed. Furthermore, the encapsulating material portion 54 is disposed on the upper surface 511 of the carrier 51.

[0034] like Figure 5E As shown, the encapsulating material portion 54 may have a side surface 541 located on the barrier layer 53. Additionally, adhesive may flow into the space between the side surface 531 of the barrier layer 53 and the carrier 51. Therefore, after removing the removable / sacrificial layer 57, the entire side surface 531 of the barrier layer 53 can be exposed.

[0035] refer to Figure 5F At least one electronic component 583 is disposed on the portion of the upper surface 511 located between the recesses 510.

[0036] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E and Figure 6F A semiconductor device package 6 (such as) according to another embodiment of the present disclosure is shown. Figure 6F The method shown is as follows. Figure 6A As shown, the carrier 61 has an upper surface 611 and two recesses 610 formed in the upper surface 611. The carrier 61 may have a recessed surface 612 that is recessed relative to the upper surface 611 (e.g., defining the bottom of the recesses 610). Stop layers 62 may be received in the recesses 610 and thus may be disposed on the recessed surfaces 612. In other words, the stop layers 62 may be embedded in the carrier 61. A barrier layer 63 may be disposed on the stop layers 62 and may protrude from the upper surface 611 of the carrier 61. Furthermore, the stop layer 62 may be a pad and the barrier layer 63 may be composed of solder balls. Reference Figure 6A The cross-sectional width of the stop layer 62 is greater than the maximum cross-sectional width of the barrier layer 63. At least two electronic components 681 and 682 are mounted on the upper surface 611 of the carrier 61.

[0037] like Figure 6AAs shown, the barrier layer 63 has a side surface 631 connected to the upper surface 621 of the stop layer 62. Furthermore, a space may exist between the side surface 631 of the barrier layer 63 and the carrier 61. Additionally, the portion of the upper surface 611 of the carrier 61 positioned between the recesses 610 may further include a wetting layer 69.

[0038] In addition, refer to Figure 6B Adhesive is applied to the portion of the upper surface 611 of the carrier 61 located between the recesses 610. Since the barrier layer 63 protrudes from the upper surface 611 of the carrier 61, the adhesive will not flow across the barrier layer 63. That is, a removable / sacrificial layer 67 will be formed between the barrier layers 63. Furthermore, adhesive can flow into the space between the side surfaces 631 of the barrier layer 63 and the carrier 61. Additionally, since the portion of the upper surface 611 of the carrier 61 located between the recesses 610 may further include a wetting layer 69, the adhesive will be smoothly distributed, and ultimately a removable / sacrificial layer 67 will be uniformly formed between the barrier layers 63.

[0039] refer to Figure 6C Encapsulating material 60 is placed on carrier 61, and the encapsulating material encapsulates the upper surface 611, stop layer 62, barrier layer 63, removable / sacrificial layer 67, and components 681 and 682 of carrier 61. That is, encapsulating material 60 covers the upper surface 611, stop layer 62, barrier layer 63, removable / sacrificial layer 67, and components 681 and 682 of carrier 61.

[0040] refer to Figure 6D A portion of the encapsulating material 60 is removed using a laser process, thereby exposing a portion of the barrier layer 63. Thus, the encapsulating material 60 is divided into three parts 64 and 65, where encapsulating material part 64 is attached to the upper surface 611 of the carrier 61 and the barrier layer 63, and encapsulating material part 65 is attached to the removable / sacrificial layer 67. Specifically, when the portion of the encapsulating material 60 is removed by the laser process, the laser is projected onto the barrier layer 63 or onto the barrier layer 63 and the stop layer 62 without damaging the carrier 61.

[0041] refer to Figure 6EThe removable / sacrificial layer 67 is removed by physical or chemical methods (such as a water washing process). Additionally, the encapsulating material portion 65 attached to the removable / sacrificial layer 67 is removed (e.g., simultaneously with the removal of the removable / sacrificial layer 67). After removing the removable / sacrificial layer 67 and the encapsulating material portion 65, the encapsulating material portion 64 remains on the carrier 61, and the portion of the upper surface 611 located between the recesses 610 and the wetting layer 69 are exposed. Furthermore, the portion of the barrier layer 63 protruding from the upper surface 611 of the carrier 61 (e.g., the portion of the side surface 631 above the upper surface 611 of the carrier 61) is also exposed. Furthermore, the encapsulating material portion 64 is disposed on the upper surface 611 of the carrier 61.

[0042] like Figure 6E As shown, the encapsulating material portion 64 may have a side surface 641 located on the barrier layer 63. Additionally, adhesive may flow into the space between the side surface 631 of the barrier layer 63 and the carrier 61. Therefore, after removing the removable / sacrificial layer 67, the entire side surface 631 of the barrier layer 63 can be exposed.

[0043] refer to Figure 6F At least one electronic component 683 is disposed on the portion of the upper surface 611 located between the recesses 610.

[0044] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F The manufacturing of a semiconductor device package 7 (e.g., according to an embodiment of the present disclosure) is illustrated. Figure 7F The method shown is as follows. Figure 7A As shown, the carrier 71 has an upper surface 711 and two recesses 710 formed in the upper surface 711. The carrier 71 has a recessed surface 712 that is recessed relative to the upper surface 711 (e.g., defining the bottom of the recesses 710). Stop layers 72 can be received within the recesses 710 and therefore can be disposed on the recessed surfaces 712 respectively. In other words, the stop layers 72 can be embedded in the carrier 71. A barrier layer 73 can be disposed on the stop layers 72. The barrier layer 73 and the stop layers 72 can be integrated with each other. The barrier layer 73 has a top surface 733 that can be substantially coplanar with the upper surface 711 of the carrier 71. Furthermore, the stop layers 72 and the barrier layer 73 can be made of the same material. (Reference) Figure 7A The cross-sectional width of the stop layer 72 is greater than that of the barrier layer 73. In particular, the combination of the stop layer 72 and the barrier layer 73 can be substantially inverted T-shaped. At least two electronic components 781 and 782 are disposed on the upper surface 711 of the carrier 71.

[0045] like Figure 7AAs shown, the barrier layer 73 has a side surface 731 connected to the upper surface 721 of the stop layer 72. Furthermore, a space may exist between the side surface 731 of the barrier layer 73 and the carrier 71. Additionally, the barrier layer 73 may further have a side surface 732 opposite to the side surface 731. The side surface 732 may be substantially attached to the carrier 71. Furthermore, the portion of the upper surface 711 of the carrier 71 positioned between the recesses 710 may further include a wetting layer 79.

[0046] In addition, refer to Figure 7B Adhesive is applied to the portion of the upper surface 711 of the carrier 71 located between the recesses 710. The adhesive will flow into the space between the side surface 731 of the barrier layer 73 and the carrier 71, and therefore, the adhesive will not flow across the barrier layer 73. That is, a removable / sacrificial layer 77 will be formed between the barrier layers 73. In addition, since the portion of the upper surface 711 of the carrier 71 located between the recesses 710 may further include a wetting layer 79, the adhesive will be smoothly distributed, and ultimately a removable / sacrificial layer 77 will be uniformly formed between the barrier layers 73.

[0047] refer to Figure 7C Encapsulating material 70 is placed on carrier 71, and the encapsulating material encapsulates the upper surface 711, stop layer 72, barrier layer 73, removable / sacrificial layer 77, and components 781 and 782 of carrier 71. That is, encapsulating material 70 covers the upper surface 711, stop layer 72, barrier layer 73, removable / sacrificial layer 77, and components 781 and 782 of carrier 71.

[0048] refer to Figure 7D A portion of the encapsulating material 70 is removed using a laser process, thereby exposing a portion of the barrier layer 73. Thus, the encapsulating material 70 is divided into three parts 74 and 75, where encapsulating material part 74 is attached to the upper surface 711 of the carrier 71 and the barrier layer 73, and encapsulating material part 75 is attached to the removable / sacrificial layer 77. Specifically, when the portion of the encapsulating material 70 is removed by the laser process, the laser is projected onto the barrier layer 73 or onto the barrier layer 73 and the stop layer 72 without damaging the carrier 71.

[0049] refer to Figure 7EThe removable / sacrificial layer 77 is removed by physical or chemical methods (such as a water washing process). Additionally, the encapsulating material portion 75 attached to the removable / sacrificial layer 77 is removed (e.g., simultaneously with the removal of the removable / sacrificial layer 77). After removing the removable / sacrificial layer 77 and the encapsulating material portion 75, the encapsulating material portion 74 remains on the carrier 71, and the portion of the upper surface 711 located between the recesses 710 and the wetting layer 79 are exposed. Furthermore, the side surfaces 731 of the barrier layer 73 are also exposed. The encapsulating material portion 74 is disposed on the upper surface 711 of the carrier 71 and the top surface 733 of the barrier layer 73. Specifically, as... Figure 7E As shown, the encapsulating material portion 74 may have a side surface 741 located on the top surface 733 of the barrier layer 73.

[0050] refer to Figure 7F At least one electronic component 783 is disposed on the portion of the upper surface 711 located between the recesses 710.

[0051] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F The manufacturing of a semiconductor device package 8 (e.g., according to an embodiment of the present disclosure) is illustrated. Figure 8F The method shown is as follows. Figure 8A As shown, the carrier 81 has an upper surface 811 and two recesses 810 formed in the upper surface 811. The carrier 81 may have a recessed surface 812 that is recessed relative to the upper surface 811 (e.g., defining the bottom of the recesses 810). Stop layers 82 may be received in the recesses 810 and thus may be disposed on the recessed surfaces 812 respectively. In other words, the stop layers 82 may be embedded in the carrier 81. Barrier layers 83 and 85 may be disposed on the stop layers 82. The barrier layers 83 and 85 and the stop layer 82 may be integrated with each other. The recesses 810 have two opposite side surfaces 813, 815 connected to the upper surface 811 of the carrier 81. The side surfaces 813, 815 of the recesses 810 are located on the barrier layers 83, 85 respectively. That is, the top surfaces 833, 853 of the barrier layers 83, 85 are recessed relative to the upper surface 811 of the carrier 81. Furthermore, the stop layer 82 and the barrier layers 83 and 85 can be made of the same material. (Reference) Figure 8A The barrier layers 83 and 85 can be positioned adjacent to two opposite sides of the stop layer 82, and thus the combination of the stop layer 82 and the barrier layers 83 and 85 can be substantially U-shaped. At least two electronic components 881 and 882 are disposed on the upper surface 811 of the carrier 81. Furthermore, the portion of the upper surface 811 of the carrier 81 positioned between the recesses 810 may further include a wetting layer 89.

[0052] In addition, refer to Figure 8B Adhesive is applied to the portion of the upper surface 811 of the carrier 81 located between the recesses 810. The adhesive will flow into the recesses 810 but will not flow across the barrier layers 83. That is, a removable / sacrificial layer 87 will be formed between the barrier layers 83. In addition, since the portion of the upper surface 811 of the carrier 81 located between the recesses 810 may further include a wetting layer 89, the adhesive will be smoothly distributed and will ultimately form a removable / sacrificial layer 87 uniformly between the barriers 83.

[0053] refer to Figure 8C Encapsulating material 80 is placed on carrier 81, and the encapsulating material encapsulates the upper surface 811, stop layer 82, barrier layers 83 and 85, removable / sacrificial layer 87, and components 881 and 882 of carrier 81. That is, encapsulating material 80 covers the upper surface 811, stop layer 82, barrier layer 83, removable / sacrificial layer 87, and components 881 and 882 of carrier 81.

[0054] refer to Figure 8D A portion of the encapsulating material 80 is removed using a laser process, thereby exposing a portion of the barrier layer 83. Thus, the encapsulating material 80 is divided into three parts 84 and 86, where encapsulating material part 84 is attached to the upper surface 811 of the carrier 81 and the barrier layer 83, and encapsulating material part 86 is attached to the removable / sacrificial layer 87. Specifically, when the portion of the encapsulating material 80 is removed by the laser process, the laser is projected onto the barrier layer 83 or onto the barrier layer 83 and the stop layer 82 without damaging the carrier 81.

[0055] refer to Figure 8E The removable / sacrificial layer 87 is removed by physical or chemical methods (such as a water washing process). Additionally, the encapsulating material portion 86 attached to the removable / sacrificial layer 87 is removed (e.g., simultaneously with the removal of the removable / sacrificial layer 87). After removing the removable / sacrificial layer 87 and the encapsulating material portion 86, the encapsulating material portion 84 remains on the carrier 81, and the portion of the upper surface 811 located between the recesses 810 and the wetting layer 89 are exposed. Furthermore, portions of the barrier layers 83 and 85 are also exposed. The encapsulating material portion 84 is disposed on the upper surface 811 of the carrier 81.

[0056] like Figure 8E As shown, the encapsulating material portion 84 may have a side surface 841 located on the barrier layer 83. Furthermore, the encapsulating material portion 84 may cover the side surface 813 of the recess 810. The barrier layer 83 has a side surface 831, and the barrier layer 85 has a side surface 851 opposite to the side surface 831. Both side surfaces 831 and 851 are exposed.

[0057] refer to Figure 8F At least one electronic component 883 is disposed on the portion of the upper surface 81 located between the recesses 810.

[0058] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F The manufacturing of a semiconductor device package 9 (e.g., according to an embodiment of the present disclosure) is illustrated. Figure 9F The method shown is as follows. Figure 9A As shown, the carrier 91 has an upper surface 911 and two recesses 910 formed in the upper surface 911. The carrier 91 may have a recessed surface 912 that is recessed relative to the upper surface 911 (e.g., defining the bottom of the recesses 910). Stop layers 92 can be received in the recesses 910 and thus can be disposed on the recessed surfaces 912. In other words, the stop layers 92 are embedded in the carrier 91. The recesses 910 have two opposite side surfaces 913, 914 connected to the upper surface 911 of the carrier 91. The side surfaces 913, 914 of the recesses 910 are located on the stop layers 92. That is, the top surface 923 of the stop layers 92 is recessed relative to the upper surface 911 of the carrier 91. The stop layers 92 may have two opposite side surfaces 921 and 922. The distance between the side surface 921 of the stop layer 92 and the side surface 913 of the recess 910 can be the same as the distance between the side surface 922 of the stop layer 92 and the side surface 914 of the recess 910. At least two electronic components 981 and 982 are disposed on the upper surface 911 of the carrier 91. Furthermore, the portion of the upper surface 911 of the carrier 91 positioned between the recesses 910 may further include a wetting layer 99.

[0059] In addition, refer to Figure 9B Adhesive is applied to the portion of the upper surface 911 of the carrier 91 located between the recesses 910. The adhesive will flow into the recesses 910, but will not flow across the recesses 910. That is, a removable / sacrificial layer 97 will be formed between the side surfaces 913 of the recesses 910. In addition, since the portion of the upper surface 911 of the carrier 91 located between the recesses 910 may further include a wetting layer 99, the adhesive will be smoothly distributed, and the removable / sacrificial layer 97 will ultimately be uniformly formed between the recesses 910.

[0060] refer to Figure 9C Encapsulating material 90 is placed on carrier 91, and the encapsulating material encapsulates the upper surface 911, stop layer 92, removable / sacrificial layer 97, and components 981 and 982 of carrier 91. That is, encapsulating material 90 covers the upper surface 911, stop layer 92, removable / sacrificial layer 97, and components 981 and 982 of carrier 91.

[0061] refer to Figure 9D A portion of the encapsulating material 90 is removed using a laser process, thereby exposing a portion of the stop layer 92. Specifically, during the removal of the encapsulating material 90, the laser may contact a portion of the carrier 91, thus damaging the side surface 913' of the carrier 91. Consequently, the encapsulating material 90 is divided into three portions 94 and 95, where encapsulating material portion 94 is attached to the upper surface 911 of the carrier 91, and encapsulating material portion 95 is attached to the removable / sacrificial layer 97.

[0062] refer to Figure 9E The removable / sacrificial layer 97 is removed by physical or chemical methods (such as a water washing process). Additionally, the encapsulating material portion 95 attached to the removable / sacrificial layer 97 is removed (e.g., simultaneously with the removal of the removable / sacrificial layer 97). After removing the removable / sacrificial layer 97 and the encapsulating material portion 95, the encapsulating material portion 94 remains on the carrier 91, and the portion of the upper surface 911 located between the recesses 910 and the wetting layer 99 are exposed. Furthermore, a portion of the stop layer 92 is also exposed. The encapsulating material portion 94 is disposed on the upper surface 911 of the carrier 91.

[0063] As described above, the laser may contact a portion of the carrier 91 and damage the side surface 913' of the recess 910. Therefore, the encapsulating material portion 94 may have a side surface 941, which may be coplanar with the damaged side surface 913' of the recess 910. Furthermore, since the side surface 913' of the recess 910 is damaged by the laser, the roughness of the damaged side surface 913' of the recess may be greater than the roughness of the side surface 914 of the recess 910. Additionally, the distance between the side surface 921 of the stop layer 92 and the damaged side surface 913' of the recess 910 may be less than the distance between the side surface 922 of the stop layer 92 and the side surface 914 of the recess 910. The angle θ1 between the upper surface 911 of the carrier 91 and the damaged side surface 913' of the recess 910 may be greater than 90 degrees and also greater than the angle θ2 between the upper surface 911 of the carrier 91 and the side surface 914 of the recess 910.

[0064] refer to Figure 9F At least one electronic component 983 is disposed on the portion of the upper surface 911 located between the recesses 910.

[0065] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurred precisely or instances where the event or situation was close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variations less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

[0066] For example, "basically parallel" can refer to an angle range of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "basically perpendicular" can refer to an angle range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0067] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the surface can be considered substantially flat.

[0068] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may contain plural referents.

[0069] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity and should be flexibly interpreted to include not only the numerical values ​​that are explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0070] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the spirit and scope of this disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically shown. The specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor device package comprising: A carrier having a first surface and a second surface recessed relative to the first surface; A stop layer, the stop layer being disposed on the second surface of the carrier; A barrier layer, which is disposed on the stop layer and protrudes from the first surface of the carrier; as well as Encapsulating material, the encapsulating material being disposed on the first surface of the carrier; The encapsulating material has a side surface disposed on the barrier layer. The stop layer and the barrier layer together form a conductive layer, and the conductive layer is located between the first region of the carrier and the second region of the carrier, wherein the first region of the carrier is encapsulated by the encapsulating material, and the second region of the carrier is not encapsulated by the encapsulating material; The first electronic component is disposed in the second region of the carrier.

2. The semiconductor device package of claim 1, wherein the stop layer and the barrier layer are made of the same material.

3. The semiconductor device package of claim 1, wherein the barrier layer is composed of solder balls.

4. The semiconductor device package of claim 1, further comprising a second electronic component disposed in the first region of the carrier and encapsulated by encapsulating material.

5. The semiconductor device package of claim 4, wherein the conductive layer extends from a first side of the carrier to a second side of the carrier.

6. The semiconductor device package of claim 5, wherein the first side of the carrier and the second side of the carrier are adjacent to each other.

7. The semiconductor device package according to claim 4, wherein, Viewed from above, the conductive layer is ring-shaped.

8. The semiconductor device package of claim 1, wherein the barrier layer has a side facing a second region of the carrier, and a space exists between the side of the barrier layer and the carrier.

9. The semiconductor device package of claim 8, wherein the stop layer has a portion protruding from the side of the barrier layer, and the portion of the stop layer and the second region of the carrier partially overlap in the vertical direction.

10. The semiconductor device package of claim 9, wherein the portion of the stop layer and the space partially overlap in the vertical direction.

11. The semiconductor device package of claim 9, further comprising a shielding layer disposed on the side surface of the encapsulant, wherein the shielding layer extends into the space.

12. The semiconductor device package of claim 11, wherein the shielding layer contacts the portion of the stop layer.

13. The semiconductor device package of claim 1, wherein the side surface of the encapsulant faces the first electronic component and partially overlaps with the first region of the carrier in a vertical direction.

14. The semiconductor device package of claim 1, further comprising a wetting layer disposed on the second region of the carrier.

15. A semiconductor device package comprising: A carrier having a first surface and a second surface recessed relative to the first surface; A stop layer, the stop layer being disposed on the second surface of the carrier; A first barrier layer is disposed on the stop layer and has a third surface, the third surface being coplanar with the first surface or recessed relative to the first surface; as well as Encapsulating material, the encapsulating material being disposed on the first surface of the carrier; The encapsulating material has a side surface disposed on the third surface of the first barrier layer; The stop layer and the first barrier layer are located between the first region of the carrier and the second region of the carrier, wherein the first region of the carrier is encapsulated by the encapsulating material, and the second region of the carrier is not encapsulated by the encapsulating material; The first electronic component is disposed in the first region of the carrier and encapsulated by encapsulating material.

16. The semiconductor device package of claim 15, wherein the stop layer and the first barrier layer are made of the same material.

17. The semiconductor device package of claim 15, wherein the stop layer has a fourth surface, and the first barrier layer has a fifth surface connected to the fourth surface of the stop layer, and wherein the fifth surface of the barrier layer is exposed.

18. The semiconductor device package of claim 15, wherein the carrier has a sixth surface connected to the first surface and covered by the encapsulating material.

19. The semiconductor device package of claim 15, further comprising a second barrier layer, wherein the first barrier layer and the second barrier layer are disposed on the stop layer and are adjacent to two opposite sides of the stop layer, respectively.

20. The semiconductor device package of claim 19, wherein the first barrier layer, the second barrier layer, and the stop layer are made of the same material.

21. The semiconductor device package of claim 19, wherein the carrier has a sixth surface connected to the first surface and covered by the encapsulant, and wherein the carrier has a seventh surface opposite to the sixth surface and disposed on the second barrier layer.

22. The semiconductor device package of claim 15, further comprising a second electronic component disposed in the first region of the carrier and encapsulated by encapsulating material.

23. The semiconductor device package of claim 22, wherein the stop layer and the first barrier layer together extend from a first side of the carrier to a second side of the carrier.

24. The semiconductor device package of claim 23, wherein the first side of the carrier and the second side of the carrier are adjacent to each other.

25. The semiconductor device package of claim 22, wherein, Viewed from above, the stop layer and the first barrier layer extend together in a ring shape.

26. A semiconductor device package comprising: A carrier having a first surface, a second surface recessed relative to the first surface, and a third surface connected to the first surface; A stop layer, the stop layer being disposed on the second surface of the carrier; Encapsulating material, the encapsulating material being disposed on the first surface of the carrier; The third surface of the carrier is disposed on the stop layer, and the encapsulating material has a side surface that is coplanar with the third surface of the carrier; The stop layer is located between a first region and a second region of the carrier, wherein the first region of the carrier is encapsulated by the encapsulating material, and the second region of the carrier is not encapsulated by the encapsulating material; The first electronic component is disposed in the second region of the carrier.

27. The semiconductor device package of claim 26, wherein the carrier further comprises a fourth surface opposite to the third surface and disposed on the stop layer.

28. The semiconductor device package of claim 27, wherein the distance between the third surface and the fourth surface is less than or equal to the cross-sectional width of the stop layer.

29. The semiconductor device package of claim 27, wherein the roughness of the third surface is greater than the roughness of the fourth surface.

30. The semiconductor device package of claim 27, wherein the stop layer includes a fifth surface adjacent to the third surface and a sixth surface adjacent to and opposite to the fourth surface, and wherein the distance between the third surface and the fifth surface is less than the distance between the fourth surface and the sixth surface.

31. The semiconductor device package of claim 27, wherein the angle between the first surface and the third surface is greater than the angle between the first surface and the fourth surface.

32. The semiconductor device package of claim 26, further comprising a second electronic component disposed in the first region of the carrier and encapsulated by encapsulating material.

33. The semiconductor device package of claim 32, wherein the stop layer extends from a first side of the carrier to a second side of the carrier.

34. The semiconductor device package of claim 33, wherein the first side of the carrier and the second side of the carrier are adjacent to each other.

35. The semiconductor device package according to claim 32, wherein, Viewed from above, the stop layer is ring-shaped.

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