Memory array and method for forming a memory array including memory cell strings

Abstract

The present application relates to a memory array and a method for forming a memory array including a string of memory cells. The method for forming a memory array including a string of memory cells includes forming a stack including a first layer and a second layer that alternate vertically. Intervening material is formed into the stack laterally between directly laterally adjacent memory block areas and longitudinally along the directly laterally adjacent memory block areas. The forming of the intervening material includes forming pillars laterally between the directly laterally adjacent memory block areas and longitudinally spaced along the directly laterally adjacent memory block areas. The pillars extend individually through multiple of each of the first layer and the second layer. After forming the pillars, intervening openings are individually formed along the directly longitudinally adjacent pillars and between the directly longitudinally adjacent pillars. Filling material is formed in the intervening openings. Other embodiments including structures are disclosed.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and methods for forming memory arrays including strings of memory cells. Background Art

[0002] Memory is a type of integrated circuit and is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written or read using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Sense lines can conductively interconnect memory cells along the columns of the array, and access lines can conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Conventionally, non-volatile memory is designated as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to hold or store memory in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two information levels or states.

[0004] Field effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductor channel region between them. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region, as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and has many uses in modern computers and devices. For example, a modern personal computer may have a BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices to enhance features.

[0006] NAND may be the basic architecture for integrated flash memory. A NAND cell component includes at least one selection device coupled in series to a series combination of memory cells (the series combination is often referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement that includes vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuits or other circuits may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

[0007] The memory array may be arranged into memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, such as shown and described in any of U.S. Patent Application Publications Nos. 2015 / 0228659, 2016 / 0267984, and 2017 / 0140833. The memory blocks may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact areas for individual word lines, with vertically extending conductive paths contacting the "steps" to provide electrical access to the word lines. Summary of the invention

[0008] On the one hand, the present application relates to a method for forming a memory array including a string of memory cells, comprising: forming a stack including vertically alternating first and second layers; and forming an intervening material into the stack laterally between and longitudinally along directly laterally adjacent memory block areas, the forming of the intervening material comprising: forming pillars laterally between and longitudinally spaced along the directly laterally adjacent memory block areas, the pillars individually extending through a plurality of each of the first and second layers; after forming the pillars, individually forming intervening openings along and between the directly longitudinally adjacent pillars; and forming a filling material in the intervening openings.

[0009] On the other hand, the present application relates to a method for forming a memory array including a string of memory cells, comprising: forming a stack including vertically alternating first and second layers; and forming an intervening material into the stack laterally between and longitudinally along directly laterally adjacent memory block areas, the forming of the intervening material comprising: forming first pillars laterally between and longitudinally spaced along the directly laterally adjacent memory block areas, the first pillars individually extending through multiple of each of the first and second layers; after forming the first pillars, forming intervening openings individually along and longitudinally across the directly longitudinally adjacent first pillars; and filling the intervening openings with a filling material to form individual second pillars in individual of the intervening openings, the first and second pillars alternating longitudinally relative to each other laterally between the directly laterally adjacent memory block areas.

[0010] On the other hand, the present application relates to a method for forming a memory array including a string of memory cells, comprising: forming a stack including a first layer and a second layer alternating vertically, the first layer including a sacrificial material, the stack including laterally spaced memory block regions; forming pillars laterally between the directly laterally adjacent memory block regions and longitudinally spaced along the directly laterally adjacent memory block regions, the pillars individually extending through multiple of each of the second layer and the first layer; after forming the pillars, individually forming openings along the directly longitudinally adjacent pillars and between the directly longitudinally adjacent pillars; isotropically etching away the sacrificial material in the first layer through the openings and replacing the sacrificial material with conductive material of individual conductive lines; and forming an intervening material in the openings after the etching.

[0011] On the other hand, the present application relates to a memory array including strings of memory cells, comprising: laterally spaced memory blocks, each of which comprises a vertical stack of alternating insulating layers and conductive layers, through which strings of operating channel materials of the memory cells extend; and intervening material, laterally between and longitudinally along directly laterally adjacent memory blocks, the intervening material comprising at least one pillar extending through at least a majority of the insulating layers and the conductive layers through which the string of channel material extends, the at least one pillar being wider at its base than at its top in a horizontal longitudinal orientation of the memory blocks.

[0012] On the other hand, the present application relates to a memory array including a string of memory cells, comprising: laterally spaced memory blocks, each of which individually comprises a vertical stack of alternating insulating layers and conductive layers, through which strings of operating channel materials of the memory cells extend; and intervening material, laterally between and longitudinally along directly laterally adjacent memory blocks, the intervening material comprising longitudinally alternating first and second regions of at least one column each comprising extending through at least a majority of the insulating layers and the conductive layers through which the string of channel material extends, wherein in the direction of the horizontal longitudinal orientation of the memory blocks, the at least one first region column or the at least one second region column is wider at its bottom than at its top.

[0013] On the other hand, the present application relates to a memory array including strings of memory cells, comprising: laterally spaced memory blocks, each of which individually comprises a vertical stack of alternating insulating layers and conductive layers, through which strings of operating channel materials of the memory cells extend; and intervening material, laterally between and longitudinally along directly laterally adjacent memory blocks, the intervening material comprising longitudinally alternating first and second columns that individually extend through at least a majority of the insulating layers and the conductive layers through which the strings of channel material extend, the first columns individually being wider at their bottoms than at their tops in a direction of horizontal longitudinal orientation of the memory blocks, and the second columns individually being wider at their tops than at their bottoms in the direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic cross-sectional view of a portion of a substrate in process according to an embodiment of the present invention and ... Figure 2 Intercepted by line 1-1.

[0015] Figure 2 It runs through Figure 1 Schematic cross-sectional view taken along line 2-2 in FIG.

[0016] Figures 3 to 20 According to some embodiments of the present invention, Figure 1 and 2 Schematic sequential cross-sectional and / or enlarged views of the structure or parts thereof.

[0017] Figures 21 to 23 is a schematic cross-sectional view of a portion of a substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Some aspects of the invention are directed to overcoming problems associated with so-called "block bow" (lateral tilting / leaning of a block stack relative to its longitudinal orientation during manufacture), but the invention is not limited thereto.

[0019] Embodiments of the present invention encompass methods for forming memory arrays, such as NAND memory cell arrays or other memory cell arrays with peripheral control circuitry under the array (e.g., under-array CMOS). Embodiments of the present invention encompass so-called "gate last" or "replacement gate" processing, so-called "gate first" processing, and other processes now known or developed in the future that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass memory arrays that are independent of the manufacturing method (e.g., NAND architecture). Reference Figures 1 to 20 A first example method embodiment is described, which may be considered a "gate last" or "replacement gate" process.

[0020] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of conductive / conductive / conductive, semiconductive / semiconductive / semiconductive, or insulating / insulator / insulating (i.e., electrical herein) materials. Various materials have been formed vertically over base substrate 11. The materials may be Figure 1 and 2 The depicted material may be on one side, vertically inside, or vertically outside. For example, other parts or all of the fabricated components of the integrated circuit system may be provided somewhere on, around, or inside the base substrate 11. Control and / or other peripheral circuitry for operating components within an array (e.g., array 12) of vertically extending memory cell strings may also be fabricated and may or may not be fully or partially within the array or sub-array. In addition, multiple sub-arrays may also be fabricated and operated independently, in series, or otherwise relative to each other. In this document, a "sub-array" may also be considered an array.

[0021] A conductor layer 16 including conductive material 17 has been formed over substrate 11. Conductor layer 16 may include portions of control circuitry (e.g., under-array peripheral circuitry and / or common source lines or plates) used to control read and write access to transistors and / or memory cells to be formed within array 12. A stack 18 including vertically alternating insulating layers 20 and conductive layers 22 has been formed over conductor layer 16. An example thickness for each of layers 20 and 22 is 22 to 60 nanometers. Only a small number of layers 20 and 22 are shown, with a more likely stack 18 including tens, a hundred, or more, etc. of layers 20 and 22. Other circuitry that may or may not be part of peripheral and / or control circuitry may be between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below a lowermost layer of conductive layer 22 and / or above an uppermost layer of conductive layer 22. For example, one or more select gate layers (not shown) may be between conductor layer 16 and lowermost conductive layer 22, and one or more select gate layers may be above an uppermost layer of conductive layer 22. Regardless, conductive layer 22 (alternatively referred to as a first layer) may not include conductive material, and insulating layer 20 (alternatively referred to as a second layer) may not include insulating material or be insulating when processed in conjunction with example method embodiments initially described herein as "gate last" or "replacement gate." Example conductive layer 22 includes a first material 26 (e.g., silicon nitride) that may be sacrificial in whole or in part. Example insulating layer 20 includes a second material 24 (e.g., silicon dioxide) that has a composition different from that of first material 26 and may be sacrificial in whole or in part. Uppermost insulating layer 20 may be considered to have a top surface 21.

[0022] A channel opening 25 has been formed (e.g., by etching) through the insulating layer 20 and the conductive layer 22 to the conductor layer 16. In some embodiments, the channel opening 25 may partially enter the conductive material 17 of the conductor layer 16 as shown, or may stop on top thereof (not shown). Alternatively, as an example, the channel opening 25 may stop on top of or inside the lowermost insulating layer 20. The reason for extending the channel opening 25 to at least the conductive material 17 of the conductor layer 16 is to ensure that a subsequently formed channel material (not shown) is directly electrically coupled to the conductor layer 16 without having to use alternative processes and structures to do so when such a connection is desired. An etch stop material (not shown) may be inside or on top of the conductive material 17 of the conductor layer 16 to facilitate stopping the etching of the channel opening 25 relative to the conductor layer 16 when desired. This etch stop material may be sacrificial or non-sacrificial. Merely by way of example and for simplicity, the channel openings 25 are shown arranged in groups or columns of staggered rows of four and five openings 25 per row, and arranged in laterally spaced memory block regions 58 that will comprise laterally spaced memory blocks 58 in the completed circuit system construction. In this document, "block" is generic to include "sub-blocks." The memory block regions 58 and resulting memory blocks 58 (not yet shown) may be considered to be longitudinally elongated and oriented, for example, horizontally along direction 55. Otherwise, the memory block regions 58 may not be discernible at this processing point. Any alternative existing or future developed arrangements and constructions may be used.

[0023] The transistor channel material may be formed vertically in individual channel openings along the insulating layer and the conductive layer, thus including individual strings of channel material that may be electrically coupled directly to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge channel material. The storage material of the individual memory cells (e.g., a floating gate material such as doped or undoped silicon or a charge trapping material such as silicon nitride, metal dots, etc.) is vertically along individual ones of the charge blocking regions. The insulating charge channel material (e.g., a bandgap engineering structure having a nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material.

[0024] Figure 3 , 3A, 4 and 4A show an embodiment in which charge blocking material 30, storage material 32 and charge channel material 34 have been formed vertically in individual channel openings 25 along insulating layer 20 and conductive layer 22. For example, transistor material 30, 32 and 34 (e.g., memory cell material) are formed by depositing respective thin layers of transistor material 30, 32 and 34 (e.g., memory cell material) over stack 18 and within individual channel openings 25, followed by planarizing such thin layers back to at least the top surface of stack 18. Channel material 36 has also been formed vertically in channel openings 25 along insulating layer 20 and conductive layer 22, thus comprising individually operated strings of channel material 53. Due to the scale, in Figure 3 and 4 37. Examples of channel material 36 include appropriately doped crystalline semiconductor materials such as one or more of silicon, germanium, and so-called III / V semiconductor materials such as GaAs, InP, GaP, and GaN. Examples of thicknesses for each of materials 30, 32, 34, and 36 are 25 to 100 angstroms. A punch-etch may be performed as shown to remove materials 30, 32, and 34 from the base of channel opening 25 to expose conductor layer 16 so that channel material 36 is directly against conductive material 17 of conductor layer 16. This punch-etch may occur with respect to each of materials 30, 32, and 34 individually (as shown), or may occur with respect to all collectively after deposition of material 34 (not shown). Alternatively, and by way of example only, a punch-etch may not be performed, and channel material 36 may be electrically coupled directly to conductive material 17 of conductor layer 16 by separate conductive interconnects (not shown). The channel opening 25 is shown as including a radially centered solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel opening 25 may include void space (not shown) and / or be free of solid material (not shown). A conductive plug (not shown) may be formed on top of the channel material string 53 to better make a conductive connection with the overlying circuitry (not shown).

[0025] Intervening material is formed into the stack 18 laterally between immediately laterally adjacent memory block regions 58 and longitudinally along immediately laterally adjacent memory block regions 58. Figures 5 to 20 Example embodiments for doing so are described.

[0026] refer to Figures 5 to 7, a pillar 60, referred to in some embodiments as a first pillar 60, has been formed laterally between directly laterally adjacent memory block areas 58 and longitudinally along directly laterally adjacent memory block areas 58. Pillar 60 individually extends through multiple of each of insulating layer 20 and conductive layer 22, and in one embodiment extends through at least a majority of insulating layer 20 and conductive layer 22 through which channel material string 53 extends. In an example embodiment, pillar 60 extends through all of insulating layer 20 and conductive layer 22 through which channel material string 53 extends. An example manner of forming pillar 60 is by etching an opening through stack 18 to have an example profile of pillar 60, as shown. Pillar 60 and other pillars described below may remain in the finished construction of the memory array or may be removed entirely so that they are not retained in the finished construction. If removed entirely, the conductive / semiconductive / insulating properties of pillar 60 are not important. If pillar 60 remains in the finished construction of the memory array, the conductive / semiconductive / insulating properties of pillar 60 may be important. Regardless, in one embodiment, pillars 60 are individually insulating everywhere. In another embodiment, pillars 60 individually have an insulating horizontal periphery vertically along them, and individually have a vertically extending core material (not shown) radially inward of the insulating horizontal periphery, and at least some of which are at least one of semiconducting and conductive. In the horizontal longitudinally oriented direction 55 of memory block 58, pillars 60 may be formed, at least initially as shown, to be wider at their tops 63 (dimension 63T) than at their bottoms 64 (dimension 64B).

[0027] refer to Figures 8 to 10 , and in one embodiment, mask 59 including masking material 91 (e.g., photoresist) and individual mask openings 62 have been formed over stack 18. In direction 55, individual mask openings 62 horizontally overlap at least a portion of horizontal longitudinal length 63T of top 63 of immediately longitudinally adjacent pillar 60. In one such embodiment and as shown, in direction 55, individual mask openings 62 horizontally overlap only a portion of horizontal longitudinal length 63T of top 63 of immediately longitudinally adjacent pillar 60.

[0028] refer to Figures 11 to 13, after forming pillars 60, mask 59 (not shown) has been used to form intervening openings 61 (e.g., by etching through the mask openings) individually along and between directly longitudinally adjacent pillars 60, and mask 59 (not shown) has then been removed. In one embodiment and as shown, intervening openings 61 span horizontally (i.e., completely) longitudinally between directly longitudinally adjacent pillars 60. Alternatively, by way of example, a plurality of intervening openings (not shown) spaced relative to one another in direction 55 may be between directly longitudinally adjacent pillars 60. Regardless, and in one embodiment, intervening openings 61 are formed using a mask (e.g., 59) that includes mask openings (e.g., 62) that are not always longitudinally continuous and laterally between directly laterally adjacent memory block regions 58. In one embodiment, the act of forming intervening openings 61 results in forming pillars 60 to be individually wider at their bottoms 64 (new dimension 64N) than at their tops 63 (new dimension 63N) in direction 55, and forming pillar sides 70. Fig.13 60 is shown in dashed lines in FIG. 6A. This transformation may occur, for example, when the uppermost portion of the pillar 60 is exposed to the etching chemistry longer than the lowermost portion of the pillar 60 to form the intervening opening 61. Some of the bottom 64 may also be slightly laterally recessed, as shown. Alternatively, consider that the formation of the mask opening 62 of the mask 59 continues long enough to ensure that some lateral recessing of the lowermost portion of the pillar 60 occurs, which is sufficient to ensure that the lowermost portion of the pillar 60 is not exposed to the etching chemistry longer than the lowermost portion of the pillar 60 to form the intervening opening 16. Fig.13 The entire etching is performed through the stack 18 (as shown).

[0029] The above process shows that the channel opening 25 is formed and filled before the pillar 60 is formed. This can be reversed. Alternatively, the pillar 60 can be formed between the formation and filling of the channel opening 25 (not ideal). Any manufacturing sequence can be used to form all features of the example construction 10, such as in Figures 11 to 13 Additionally, and regardless, the one or more masks used to form openings in which posts 60 are received and / or to form intervening openings 61 may be combined with other masks, such as masks used to form through-array via openings (not shown).

[0030] refer to Figures 14 to 17, and in one embodiment, material 26 (not shown) of conductive layer 22 has been removed, such as by isotropically etching away through intervening openings 61 (e.g., using liquid or vapor H3PO4 as a primary etchant in the case where material 26 is silicon nitride and the other materials include one or more oxides or polysilicon) ideally selectively relative to other exposed materials (e.g., insulating layer 20 and pillars 60). In an example embodiment, material 26 (not shown) in conductive layer 22 is sacrificial and has been replaced with conductive material 48, which has thereafter been removed from intervening openings 61, thereby forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0031] A thin insulating liner (e.g., Al2O3, and not shown) may be formed prior to forming the conductive material 48. The approximate location of the transistor and / or memory cell 56 is Fig.14 Indicated by brackets, and some Fig.14 and 15 4 and 5. The conductive material 48 may be shown as having a terminal 50 ( 40 ) corresponding to the control gate region 52 of the individual transistor and / or memory cell 56. The conductive material 48 may be shown as having a terminal 50 ( 40 ) corresponding to the control gate region 52 of the individual transistor and / or memory cell 56. The conductive material 48 may be shown as having a terminal 50 ( 40 ) corresponding to the control gate region 52 of the individual transistor and / or memory cell 56. Fig.17 ). The control gate region 52 in the depicted embodiment includes individual portions of the individual conductive lines 29. The materials 30, 32, and 34 may be viewed as a memory structure 65 laterally between the control gate region 52 and the channel material 36. In one embodiment and as shown with respect to an example "gate last" process, the conductive material 48 of the conductive layer 22 is formed after forming the pillar 61. Alternatively, the conductive material of the conductive layer may be formed prior to forming the pillar 61 and / or prior to forming the channel opening 25 (not shown), such as with respect to a "gate first" process.

[0032] The charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and the individual control gate region 52. The charge block may have the following functions in the memory cell: in the programming mode, the charge block may prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate, and in the erase mode, the charge block may prevent charge carriers from flowing into the storage material from the control gate. Thus, the charge block may function to block charge migration between the control gate region and the storage material of the individual memory cell. The example charge blocking region as shown includes an insulator material 30. By way of further example, the charge blocking region may include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32), where this storage material is insulating (e.g., in the absence of any different composition material between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, in the absence of any separate composition insulator material 30, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region. Furthermore, the interface of conductive material 48 and material 30 (when present) in conjunction with insulator material 30 may together act as a charge blocking region and may alternatively or additionally be a lateral outer region of an insulating storage material such as silicon nitride material 32. Example material 30 is one or more of hafnium oxide of silicon and silicon dioxide.

[0033] refer to Figures 18 to 20, fill material 57 has been formed in intervening openings 61, and in one embodiment as shown, this is formed to fill intervening openings 61 to form individual pillars 67, referred to in some embodiments as second pillars 67 in individual intervening openings 61. In one such embodiment, pillars 60 (e.g., first pillars 60) and pillars 67 (e.g., second pillars 67) alternate longitudinally relative to each other laterally between directly laterally adjacent memory block regions 58. In one embodiment and as shown, pillars 67 have been formed to be wider at their tops 68 (dimension 68T) than at their bottoms 69 (dimension 69B) in direction 55, individually. Fill material 57 may be considered an intervening material in some embodiments. Pillars 60 and pillars 67 may also be considered an intervening material. This intervening material 57 / 60 / 67 may provide lateral electrical isolation (insulation) between directly laterally adjacent memory blocks 58. This may include one or more of insulating, semiconductive, and conductive materials, and in any case, may facilitate preventing conductive layers 22 from shorting relative to each other in the completed circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. In one embodiment, intervening material 57 includes a laterally outermost insulating material (e.g., silicon dioxide and / or silicon nitride and not shown) and a laterally inner material (e.g., undoped polysilicon and not shown) having a composition different from that of the laterally outermost insulating material. In one embodiment, intervening material 57 / 60 / 67 is insulating everywhere between directly laterally adjacent memory blocks.

[0034] Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used with respect to the embodiments described above.

[0035] Figure 18-20 An example embodiment is shown in which posts 60 and 67 extend completely vertically between the top and bottom of stack 18. Alternatively, this may not extend as such. For example, and by way of example only, in Fig.21 An alternative example construction 10a is shown in FIG. Where appropriate, like numerals from the embodiments described above have been used, with some construction differences being indicated with a suffix "a" or with different numerals. Fig.21 An example array 12 is shown where the top 63 of pillar 60a is vertically recessed relative to the top of the stack. Similarly and / or alternatively, the top of pillar 67 may be recessed (not shown) regardless of any recessing of pillars 60 / 60a, and if both are vertically recessed, this may be to the same or different depths. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0036] Fig. 22 Shown in horizontal cross section corresponding to Fig.18Example alternative embodiment configuration 10b of example configuration of example configuration. Where appropriate, similar numbers from the embodiments described above have been used, with some of the construction differences indicated by the suffix "b" or by different numbers. Example configuration 10b has a plurality of side-by-side pillars 60b laterally between directly adjacent memory blocks 58 orthogonal to direction 55, and in one embodiment, the side-by-side pillars 60b do not directly abut against each other. In one embodiment and as shown, the side-by-side pillars 60b have the same horizontal cross-sectional peripheral shape. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0037] Fig.23 An alternative example configuration 10c is shown. Where appropriate, similar numbers from the embodiments described above have been used, with some of the construction differences indicated by the suffix "c" or by different numbers. Example configuration 10c also has a plurality of directly adjacent side-by-side columns 60c, but they are directly against each other in this example. By way of example only, this further shows an embodiment in which a plurality of columns 60c include a plurality of groups 71 of such columns, wherein the groups are longitudinally spaced from each other along directly laterally adjacent memory blocks 58. Other columns (e.g., 67c) are individually between directly longitudinally adjacent groups 71 of columns 60c, wherein in one embodiment, one and only one of such other columns (e.g., 67c) is present between directly longitudinally adjacent groups 71 of columns 61c. Any attributes (not shown) of configurations 10, 10a, 10b, and / or 10c may be combined. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0038] Alternative embodiment configurations may be derived from the method embodiments described above or in other ways. Regardless, embodiments of the present invention encompass memory arrays that are independent of the method of manufacture. However, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the method embodiments described above may incorporate, form and / or have any of the properties described with respect to the device embodiments.

[0039] Embodiments of the invention include a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56), the strings of memory cells individually comprising laterally spaced memory blocks (e.g., 58) comprising a vertical stack (e.g., 18) of alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). The strings of operating channel materials (e.g., 53) of the memory cells extend through the insulating and conductive layers. Intervening material (e.g., 57 / 60, 60b, 60c / 67, 67c) is laterally between and longitudinally along the immediately laterally adjacent memory blocks 58. The intervening material includes at least one pillar (e.g., 60, 60b, 60c) extending through at least a majority of the insulating and conductive layers through which the string of channel material extends. In the direction of the horizontal longitudinal orientation of the memory blocks (e.g., 55), at least one pillar is wider at its base (e.g., 64) than at its top (e.g., 63). In one embodiment, at least one pillar is directly against the side of the immediately laterally adjacent memory block. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0040] Embodiments of the present invention include a memory array (e.g., 12) comprising a string (e.g., 49) of memory cells (e.g., 56) comprising laterally spaced memory blocks (e.g., 58) individually comprising a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). An operating channel material string (e.g., 53) of the memory cells extends through the insulating layer and the conductive layer. Intervening material (e.g., 57 / 60, 60b, 60c / 67, 67c) is laterally between and longitudinally along the directly laterally adjacent memory blocks 58. The intervening material comprises longitudinally alternating first and second regions (e.g., each comprising a different column type) of at least one column that individually comprises at least a majority of the insulating layer and the conductive layer through which the channel material string extends. In the direction of the horizontal longitudinal orientation of the memory blocks (e.g., 55), at least one first region column or at least one second region column is wider at its bottom than at its top. In one such embodiment, at least one first pillar or at least one second pillar is longest horizontally in the direction compared to orthogonal to the direction.Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0041] Embodiments of the invention include a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56) comprising laterally spaced memory blocks (e.g., 58) that individually include a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). A string (e.g., 53) of operating channel material of the memory cells extends through the insulating and conductive layers. Intervening material (e.g., 57 / 60, 60b, 60c / 67, 67c) is laterally between and longitudinally along the immediately laterally adjacent memory blocks 58. The intervening material includes longitudinally alternating first and second pillars (e.g., 60 / 60b / 60c and 67, 67c, respectively) that individually extend through at least a majority of the insulating and conductive layers through which the string of channel material extends. In the direction (e.g., 55) of the horizontal longitudinal orientation of the memory blocks, the first pillars are individually wider at their bases (e.g., 64) than at their tops (e.g., 63). In that direction, the second posts are individually wider at their tops (eg, 68) than at their bases (eg, 69).Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0042] The above processing or construction may be considered to be relative to a single stack or single layer of such components or an array of components therein formed on or as part of an underlying base substrate (although a single stack / layer may have multiple layers). Control circuits and / or other peripheral circuits for operating or accessing such components in the array may also be formed anywhere as part of the completed construction, and in some embodiments, may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / layers may be provided or manufactured above and / or below the stacks / layers shown in the drawings or described above. In addition, the arrays of components may be the same or different in different stacks / layers relative to each other, and different stacks / layers may have the same thickness or different thickness relative to each other. Intervening structures (e.g., additional circuit systems and / or dielectric layers) may be provided between directly vertically adjacent stacks / layers. In addition, different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers may be manufactured individually and sequentially (e.g., one above the other), or two or more stacks / layers may be manufactured substantially simultaneously.

[0043] The assemblies and structures discussed above can be used in integrated circuits and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0044] In this document, unless otherwise indicated, "vertical", "higher", "up", "down", "top", "on the top of...", "bottom", "above", "below", "below", "below", "upward", and "downward" are generally with reference to a vertical direction. "Horizontal" refers to a general direction along the surface of the main substrate (i.e., within 10 degrees), and may be relative to the direction in which the substrate is handled during manufacturing, and vertical is a direction generally orthogonal to the horizontal. By "completely horizontal" is meant a direction along the surface of the main substrate (i.e., no angle with the surface of the main substrate), and may be relative to the direction in which the substrate is handled during manufacturing. In addition, as used herein, "vertical" and "horizontal" are generally with respect to directions perpendicular to each other, and are independent of the orientation of the substrate in three-dimensional space. In addition, "extending vertically" and "extending vertically" refer to a direction that is at least 45° from completely horizontal. In addition, "extending vertically", "extending vertically", "extending horizontally", "extending horizontally" and the like with respect to a field effect transistor are with reference to the orientation of the channel length of the transistor along which current flows between the source / drain regions in operation. For bipolar junction transistors, "vertically extending", "vertically extending", "horizontally extending", and "horizontally extending", and the like, refer to the orientation of the base length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0045] Furthermore, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to one another. Furthermore, the use of "above" without being preceded by "directly" requires only that some portion of the stated region / material / component that is above another portion of the stated region / material / component is vertically outside of the other portion (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "below" and "beneath" without being preceded by "directly" requires only that some portion of the stated region / material / component that is below / beneath the other is vertically inside of the other (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components).

[0046] Any of the materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any case may be continuous or discontinuous over any material overlying any of the materials, regions, and structures. Where one or more example components are provided for any material, the material may include, consist essentially of, or consist of such one or more components. Furthermore, unless otherwise specified, each material may be formed using any suitable present or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0047] In addition, "thickness" itself (without a preceding directional adjective) is defined as the average straight-line distance through a given material or region perpendicular to the closest surface of an adjacent material or adjacent region with different composition. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and since the thickness is variable, this material or region will have a certain minimum thickness and a certain maximum thickness. As used herein, "different composition" requires only that those parts of the two stated materials or regions that may be directly against each other are chemically and / or physically different, for example, if such materials or regions are not homogeneous. If the two stated materials or regions are not directly against each other, then "different composition" requires only that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different (if this material or region is not homogeneous). In this document, when the materials, regions or structures are in at least some physical touching contact relative to each other, the stated materials, regions or structures are "directly against" each other. In contrast, "over," "on," "adjacent," "along," and "against" without the word "directly" in front of them encompass "directly against" as well as configurations in which intervening materials, regions, or structures result in no physical touching contact between the stated materials, regions, or structures relative to each other.

[0048] Here, region-material-components are "electrically coupled" relative to each other if, in normal operation, electrical current can flow continuously from one region-material-component to another and the flow is achieved primarily by the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when the region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0049] Any use of "row" and "column" in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or may be formed. "Row" and "column" are used synonymously with respect to any series of regions, components and / or features that are not related to function. Regardless, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may columns. Furthermore, rows and columns may intersect at 90° or at one or more other angles (i.e., other than right angles) relative to each other.

[0050] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconductive / semiconductive materials. "Metallic material" is any or a combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0051] As used herein, any use of "selective" with respect to etching, etched, removing, removing, depositing, forming, and / or forming refers to the action of doing so at a rate of at least 2:1 by volume on one stated material relative to another stated material. Additionally, any use of selective deposition, selective growth, or selective formation refers to depositing, growing, or forming one material relative to another stated material at a rate of at least 2:1 by volume for at least the first 75 angstroms of deposition, growth, or formation.

[0052] Unless stated otherwise, the use of "or" herein includes either and both.

[0053] in conclusion

[0054] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a stack including vertically alternating first and second layers. Intervening material is formed into the stack laterally between directly laterally adjacent memory block regions and longitudinally along the directly laterally adjacent memory block regions. The forming of the intervening material includes forming pillars laterally between the directly laterally adjacent memory block regions and longitudinally spaced along the directly laterally adjacent memory block regions. The pillars individually extend through a plurality of each of the first and second layers. After forming the pillars, intervening openings are individually formed along the directly longitudinally adjacent pillars and between the directly longitudinally adjacent pillars. Filling material is formed in the intervening openings.

[0055] In some embodiments, a method for forming a memory array including a string of memory cells includes forming a stack including first and second layers that alternate vertically. Intervening material is formed into the stack laterally between directly laterally adjacent memory block areas and longitudinally along the directly laterally adjacent memory block areas. The forming of the intervening material includes forming a first column laterally between the directly laterally adjacent memory block areas and longitudinally spaced along the directly laterally adjacent memory block areas. The first column extends individually through multiple of each of the first layer and the second layer. After forming the first column, an intervening opening is formed that horizontally spans along the directly longitudinally adjacent first columns individually and longitudinally between the directly longitudinally adjacent first columns. The intervening opening is filled with a filling material to form individual second columns in individual of the intervening openings. The first and second columns alternate longitudinally relative to each other laterally between the directly laterally adjacent memory block areas.

[0056] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a stack including a first layer and a second layer that alternate vertically. The first layer includes a sacrificial material, and the stack includes laterally spaced memory blocks. The pillars are formed laterally between the directly laterally adjacent memory blocks and longitudinally spaced apart along the directly laterally adjacent memory blocks, and extend individually through multiple of each of the second layer and the first layer. After forming the pillars, openings are individually formed along the directly longitudinally adjacent pillars and between the directly longitudinally adjacent pillars. Through the openings, the sacrificial material in the first layer is isotropically etched away and replaced with conductive material of individual conductive lines. Intervening material is formed in the openings after the etching.

[0057] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks that individually include a vertical stack of alternating insulating layers and conductive layers. Strings of operating channel materials of memory cells extend through the insulating layers and the conductive layers. Intervening material is laterally between and longitudinally along directly laterally adjacent memory blocks. The intervening material includes at least one pillar extending through at least a majority of the insulating layers and the conductive layers through which the string of channel materials extends. In a horizontal longitudinal orientation of the memory blocks, the at least one pillar is wider at its base than at its top.

[0058] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks that individually include a vertical stack of alternating insulating layers and conductive layers. Strings of operating channel materials of the memory cells extend through the insulating layers and the conductive layers. Intervening material is laterally between and longitudinally along the directly laterally adjacent memory blocks. The intervening material includes longitudinally alternating first and second regions of at least one column that individually includes at least a majority of the insulating layers and the conductive layers through which the string of channel materials extends. In a horizontal longitudinal orientation of the memory blocks, the at least one first region column or the at least one second region column is wider at its bottom than at its top.

[0059] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks that individually include a vertical stack of alternating insulating layers and conductive layers. Strings of operating channel materials of the memory cells extend through the insulating layers and the conductive layers. Intervening material is laterally between and longitudinally along directly laterally adjacent memory blocks. The intervening material includes longitudinally alternating first and second columns that individually extend through at least a majority of the insulating layers and the conductive layers through which the strings of channel materials extend. In a direction of a horizontal longitudinal orientation of the memory blocks, the first columns are individually wider at their bottoms than at their tops. In the direction, the second columns are individually wider at their tops than at their bottoms.

[0060] In accordance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. It should be understood, however, that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims should be given the full scope according to their literal wording and appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array including a string of memory cells, comprising: forming a stack comprising vertically alternating first and second layers; and forming an intervening material into the stack laterally between and longitudinally along immediately laterally adjacent memory block regions, the forming of the intervening material comprising: forming pillars laterally between and longitudinally spaced along the immediately laterally adjacent memory block regions, the pillars individually extending through a plurality of each of the first layer and the second layer, wherein in a completed construction of the memory array the pillars are formed to be individually wider at their bases than at their tops in a direction of the horizontal longitudinal orientation of the memory blocks; After forming the posts, individually forming intervening openings along and between immediately longitudinally adjacent posts; and A filling material is formed in the intervening opening.

2. The method of claim 1, wherein the intervening openings are formed using a mask comprising mask openings that are not always continuous longitudinally and laterally between the immediately laterally adjacent memory block regions. The method of claim 1 , wherein the fill material is formed to completely fill the intervening opening. The method of claim 1 , wherein the pillars remain in a completed configuration of the memory array.

5. The method of claim 1 including removing all of the pillars so that they do not remain in a completed configuration of the memory array.

6. The method of claim 1 , comprising forming individual memory cells in the string of memory cells to include a channel material of an operating channel material string, a gate region as part of a conductive line in an individual of the first layer, and a memory structure laterally between the gate region and the channel material of the operating channel material string in the individual first layer, the conductive material of the first layer being formed after forming the pillar.

7. The method according to claim 6, comprising: The sacrificial material in the first layer is isotropically etched away through the intervening openings and replaced with the conductive material of the individual conductive lines.

8. The method of claim 1 , comprising forming individual memory cells in the string of memory cells to include channel material of an operating channel material string, a gate region as part of a conductive line in an individual of the first layer, and a memory structure laterally between the gate region and the channel material of the operating channel material string in the individual first layer, the conductive material of the first layer being formed prior to forming the pillar.

9. The method of claim 1, comprising forming the pillar to be initially wider at its top than at its bottom in the direction.

10. A method for forming a memory array including strings of memory cells, comprising: forming a stack comprising vertically alternating first and second layers; and forming an intervening material into the stack laterally between and longitudinally along immediately laterally adjacent memory block regions, the forming of the intervening material comprising: forming pillars laterally between and longitudinally spaced apart along the immediately laterally adjacent memory block regions, the pillars individually extending through a plurality of each of the first layer and the second layer; After forming the posts, individually forming intervening openings along and between immediately longitudinally adjacent posts; and forming a filler material in the intervention opening; The intervening openings are formed using a mask including individual mask openings corresponding to individual ones of the intervening openings, the individual mask openings horizontally overlapping at least a portion of a horizontal longitudinal extent of a top of the immediately longitudinally adjacent pillar in a horizontally longitudinally oriented direction of the memory block.

11. The method of claim 10, wherein the individual mask openings horizontally overlap only a portion of the horizontal longitudinal extent of the tops of the immediately longitudinally adjacent pillars in the direction.

12. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack comprising vertically alternating first and second layers; and forming an intervening material into the stack laterally between and longitudinally along immediately laterally adjacent memory block regions, the forming of the intervening material comprising: forming first pillars laterally between and longitudinally spaced along the immediately laterally adjacent memory block regions, the first pillars individually extending through a plurality of each of the first layer and the second layer, wherein in a completed construction of the memory array, the first pillars are formed to be individually wider at their bases than at their tops in a direction of the horizontal longitudinal orientation of the memory blocks; After forming the first posts, forming intervening openings horizontally spanning individually along and longitudinally between immediately longitudinally adjacent first posts; and The intervening openings are filled with a filling material to form respective second pillars in respective ones of the intervening openings, laterally between the immediately laterally adjacent memory block regions relative to the first and second pillars alternating longitudinally with respect to each other.

13. The method of claim 12, comprising forming the second pillars to be individually wider at their tops than at their bottoms in a horizontal longitudinally oriented direction of the memory blocks in a completed configuration of the memory array.

14. The method according to claim 12, comprising: In a completed configuration of the memory array, the first pillars are formed to be individually wider at their bases than at their tops in a horizontal longitudinally oriented direction of the memory blocks; and The second posts are formed in the finished configuration to be wider at their tops than at their bases individually in the direction.

15. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack comprising vertically alternating first and second layers, the first layers comprising a sacrificial material, the stack comprising laterally spaced memory blocks; forming pillars laterally between and longitudinally spaced along immediately laterally adjacent memory block regions, the pillars individually extending through a plurality of each of the second layer and the first layer, wherein in a completed construction of the memory array the pillars are formed to be individually wider at their bases than at their tops in a direction of a horizontal longitudinal orientation of the memory blocks; After forming the posts, individually forming openings along and between immediately longitudinally adjacent posts; isotropically etching away the sacrificial material in the first layer through the opening and replacing the sacrificial material with conductive material of individual conductive lines; and An intervening material is formed in the opening after the etching.

16. The method of claim 15, wherein said isotropically etching away said sacrificial material is performed selectively to said second layer.

17. The method of claim 15, wherein said isotropically etching away said sacrificial material is performed selectively with respect to said posts.

18. A memory array comprising a memory cell string, comprising: laterally spaced memory blocks, individually comprising a vertical stack of alternating insulating and conductive layers through which operating channel material of a string of memory cells extends; and Intervening material laterally between and longitudinally along directly laterally adjacent said memory blocks, said intervening material comprising at least one pillar extending through said insulating layer and at least a majority of said conductive layer through which a string of channel material extends, said at least one pillar being wider at its base than at its top in a horizontal longitudinal orientation of said memory blocks.

19. The memory array of claim 18, wherein the at least one pillar is longest horizontally in the direction compared to orthogonal to the direction.

20. The memory array of claim 18 wherein the at least one pillar is directly against a side of the immediately laterally adjacent memory block.

21. The memory array of claim 18 comprising a plurality of said pillars side-by-side between said immediately laterally adjacent memory blocks laterally orthogonal to said direction.

22. The memory array of claim 21 wherein immediately adjacent said side-by-side pillars do not directly abut one another.

23. The memory array of claim 21 wherein immediately adjacent said side-by-side pillars abut directly against each other.

24. The memory array of claim 21 wherein the side-by-side pillars have the same horizontal cross-sectional peripheral shape.

25. The memory array of claim 18 comprising a plurality of said pillars spaced longitudinally from one another along said immediately laterally adjacent memory blocks.

26. The memory array of claim 25 wherein the plurality of the pillars comprises groups of a plurality of the pillars, the groups being longitudinally spaced from one another along the immediately laterally adjacent memory blocks, the groups individually comprising the plurality of the pillars side-by-side orthogonal to the direction.

27. The memory array of claim 25, comprising additional pillars individually between immediately longitudinally adjacent said plurality of pillars.

28. The memory array of claim 27 wherein in said direction said other pillars are individually wider at their tops than at their bases.

29. The memory array of claim 28 including one and only one of the other pillars between immediately longitudinally adjacent pillars.

30. The memory array of claim 18 comprising NAND.

31. A memory array comprising a string of memory cells, comprising: laterally spaced memory blocks, individually comprising a vertical stack of alternating insulating and conductive layers through which strings of operating channel material of memory cells extend; and Interposing material laterally between and longitudinally along directly laterally adjacent memory blocks, the interposing material comprising longitudinally alternating first and second regions of at least one column individually comprising at least a majority of the insulating layer and the conductive layer extending through the string of channel material, wherein in a horizontal longitudinal orientation of the memory blocks, at least one first region column or at least one second region column is wider at its base than at its top.

32. The memory array of claim 31, wherein the at least one first pillar or the at least one second pillar is horizontally longest in the direction compared to orthogonal to the direction.

33. A memory array comprising a string of memory cells, comprising: laterally spaced memory blocks, individually comprising a vertical stack of alternating insulating and conductive layers through which strings of operating channel material of memory cells extend; and Interposing material laterally between and longitudinally along immediately laterally adjacent memory blocks, the interposing material comprising longitudinally alternating first and second pillars individually extending through at least a majority of the insulating layer and the conductive layer through which the string of channel material extends, the first pillars individually being wider at their bases than at their tops in a direction of the horizontal longitudinal orientation of the memory blocks, and the second pillars individually being wider at their tops than at their bases in said direction.

34. The memory array of claim 33 wherein the first pillars are individually insulated at each location.

35. The memory array of claim 33 wherein the first pillars individually have an insulating horizontal periphery vertically there along and individually have a core material radially inward of the insulating horizontal periphery at least some of which is at least one of semiconducting and conductive.

36. The memory array of claim 33 wherein the second pillars are individually insulated at each location.

37. The memory array of claim 33 wherein the second pillars individually have an insulating horizontal periphery vertically there along and individually have a core material radially inward of the insulating horizontal periphery at least some of which is at least one of semiconducting and conductive.

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