Memory device and operating method thereof

Abstract

A memory device and an operating method thereof are provided. The memory device includes a plurality of memory cells each including a switching device and an information storage device connected to the switching device and having a phase change material, the plurality of memory cells being connected to a plurality of word lines and a plurality of bit lines; a decoder circuit determining at least one of the plurality of memory cells as a selected memory cell; and a programming circuit configured to input a programming current to the selected memory cell to perform a programming operation, and configured to detect a resistance of the selected memory cell to adjust a magnitude of the programming current.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0131416, filed on October 22, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates generally to memory devices and methods of operating thereof, and more specifically to memory devices employing resistors. Background Technology

[0003] Traditional memory devices write or erase data by charging or discharging electrical charges. Memory devices that use resistors differ in that they write or erase data by utilizing changes in resistance.

[0004] Some examples of memory devices that use resistors include phase-change random access memory (PRAM), resistive random access memory (RRAM), and magnetic RAM (MRAM). Summary of the Invention

[0005] In one aspect of the present invention, a memory device capable of improving programming characteristics is provided.

[0006] According to one aspect of the present invention, a memory device includes: a plurality of memory cells, each memory cell including a switching device and an information storage device having a phase change material connected to the switching device, the plurality of memory cells being connected to a plurality of word lines and a plurality of bit lines; a decoder circuit that determines at least one of the plurality of memory cells as a selected memory cell; and a programming circuit configured to apply a programming current to the selected memory cell to perform a programming operation, and configured to detect the resistance of the selected memory cell to adjust the amplitude of the programming current.

[0007] According to one aspect of the present invention, a memory device includes: a memory cell array including a plurality of memory cells disposed at locations where a plurality of word lines and a plurality of bit lines intersect each other; a decoder circuit that determines at least one of the plurality of memory cells as a selected memory cell; and a programming circuit that, in a programming operation for the selected memory cell, generates a sampling current during a sampling period whose amplitude decreases as the resistance of the selected memory cell increases, and generates a programming current based on the sampling current during a programming period.

[0008] According to one aspect of the present invention, a method of operating a memory device includes: turning on a selected memory cell connected to a selected word line and a selected bit line; detecting the resistance of the selected memory cell; inputting a bias current to the selected word line connected to the selected memory cell and generating an initial programming current corresponding to the bias current; generating an additional programming current whose amplitude decreases as the detected resistance increases; and programming the selected memory cell using the initial programming current and the additional programming current. Attached Figure Description

[0009] The above and other aspects, features, and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a schematic plan view of a memory device according to an example embodiment;

[0011] Figure 2 This is a functional block diagram of a memory device according to an example embodiment;

[0012] Figure 3A and Figure 3B These are schematic diagrams / layout diagrams illustrating memory cell arrays according to their respective exemplary embodiments;

[0013] Figure 4A and Figure 4B These are perspective views illustrating respective example structures of memory cells included in a memory device according to respective example embodiments;

[0014] Figure 5A and Figure 5B These are respective perspective views illustrating the respective structures of memory cells included in a memory device according to respective exemplary embodiments;

[0015] Figure 6 This is a view illustrating the operation of a memory device according to an example embodiment;

[0016] Figure 7 This is a diagram illustrating programming operations of a memory device according to an example embodiment;

[0017] Figure 8A Joule heating based on the resistance of a memory cell, according to an example embodiment, is shown;

[0018] Figure 8B The distribution of memory cells according to the resistance of memory cells is shown according to an example embodiment;

[0019] Figure 9 This is a circuit diagram of a memory device according to an example embodiment;

[0020] Figure 10This is a diagram illustrating programming operations of a memory device according to an example embodiment;

[0021] Figure 11 It is a graph showing the voltage-current diagram of a memory cell during programming operation of a memory device according to an example embodiment;

[0022] Figure 12 This is a circuit diagram of a memory device according to an example embodiment;

[0023] Figure 13 , Figure 14 and Figure 15 This is a diagram illustrating programming operations of a memory device according to an example embodiment;

[0024] Figure 16A , Figure 16B and Figure 16C This is a diagram illustrating programming operations of a memory device according to an example embodiment;

[0025] Figure 17A Joule heating based on the resistance of a memory cell, according to an example embodiment, is shown;

[0026] Figure 17B The distribution of memory cells according to the resistance of memory cells is shown according to an example embodiment;

[0027] Figure 18 This is a diagram illustrating a memory device according to an example embodiment;

[0028] Figure 19 This is a flowchart illustrating the operation of a memory device according to an example embodiment; and

[0029] Figure 20 This is a block diagram schematically illustrating an electronic device including a memory device according to an example embodiment. Detailed Implementation

[0030] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic plan view of a memory device 1 according to an example embodiment. The memory device 1 may have a bank region 2, a circuit region 3, and a pad (or "solder pad") region 4. The pad region 4 may be a region having multiple pads formed for input and output control signals and data. The circuit region 3 may be a region having various circuits formed for the operation of the memory device 1. In the bank region 2, a memory cell array having multiple memory cells may be formed. The memory cell array may be organized in multiple banks.

[0032] Each of the multiple memory cells formed in memory cell region 2 can be divided into multiple regions. For example, at least a portion of the multiple regions of each memory cell can share decoder circuitry and / or read / write circuitry included in circuitry region 3. Optional arrangements are also available.

[0033] Circuit region 3 may include decoder circuitry, read / write circuitry, control logic for the decoder circuitry and the read / write circuitry, etc. The decoder circuitry can, in response to an address, identify at least one of a plurality of memory cells formed in memory region 2 as the selected memory cell. The read / write circuitry can read data from or write data to the selected memory cell.

[0034] Figure 2 This is a functional block diagram of a memory device 10 according to an embodiment, which may be an example of a memory device 1. The memory device 10 may include a memory controller 20 and a memory cell array 30. The memory controller 20 may include a first decoder circuit 21, a second decoder circuit 22, a read / write circuit 23, and control logic 24. The memory cell array 30 may include a plurality of memory cells. The first decoder circuit 21 is connected to the plurality of memory cells via word lines WL, and the second decoder circuit 22 is connected to the plurality of memory cells via bit lines BL. The operation of the first decoder circuit 21, the second decoder circuit 22, and the read / write circuit 23 may be controlled by the control logic 24. In an example embodiment, the read / write circuit 23 may include programming circuitry for writing data to at least one selected memory cell specified by the first decoder circuit 21 and the second decoder circuit 22, and readout circuitry for reading data from the selected memory cell.

[0035] Multiple memory cells included in the memory cell array 30 can have different resistance levels. When the read / write circuit 23 programs data in a selected memory cell, the memory device 10 can supply programming current to the selected memory cell. The lower the resistance of the selected memory cell when programming current flows through it, the worse the programming operation. Conversely, the higher the resistance of the selected memory cell, the worse the storage durability.

[0036] According to the example embodiment, when the read / write circuit 23 programs data into the selected memory cell, the memory device 10 can determine the programming current based on the resistance of the selected memory cell. Because the memory device 10 can supply different programming currents depending on the resistance of the selected memory cell, the memory device 10 can compensate for changes in programming characteristics based on the resistance of the selected memory cell.

[0037] Figure 3A and Figure 3BThese are schematic / layout diagrams of memory cell arrays according to their respective exemplary embodiments. (Refer to...) Figure 2 and Figure 3A The memory cell array 30A according to the example embodiment may include a plurality of memory cells MC. The plurality of memory cells MC may be located at the intersection of bit line BL and word line WL. For example, each of the plurality of memory cells MC may be connected to a bit line BL and a word line WL.

[0038] As an example, each of the plurality of memory cells MC may include a switching device SW and an information storage device VR. In an example embodiment, the switching device SW may include at least one of a PN junction diode, a Schottky diode, and a bidirectional threshold switch (OTS). Furthermore, in an example embodiment, the information storage device VR may be formed of a phase change material comprising chalcogenide materials and superlattices. For example, the information storage device VR may include a phase change material capable of performing a phase transition between an amorphous phase and a crystalline phase depending on heating time and temperature. The information storage device VR and the switching device SW may be connected in series with each other.

[0039] The memory controller 20 can record or erase data by shifting the phase change material of the information storage device VR included in each of the plurality of memory cells MC to an amorphous or crystalline phase via the bit line BL and word line WL. In an example embodiment, the memory controller 20 can increase the resistance of the information storage device VR by shifting the phase change material of the information storage device VR included in the memory cell MC to an amorphous phase. Conversely, the memory controller 20 can decrease the resistance of the information storage device VR by shifting the phase change material of the information storage device VR included in the memory cell MC to a crystalline phase. The relationship between the resistance value of the information storage device VR and whether data is recorded can be defined in various ways according to the example embodiment. The memory controller 20 can perform a read operation by comparing the read voltage detected from the plurality of memory cells MC with a predetermined reference voltage.

[0040] Reference Figure 3A In each of the multiple memory cells MC, one end of the information storage device VR can be connected to the bit line, and one end of the switching device SW can be connected to the word line. In this case... Figure 3A Each of the multiple memory cells MC shown in the figure may have a first orientation (or orientation).

[0041] Based on Figure 3A To describe the differences in comparison Figure 3B . Reference Figure 3BIn each of the multiple memory cells MC, one end of the information storage device VR can be connected to the word line, and one end of the switching device SW can be connected to the bit line. In this case... Figure 3B Each of the multiple memory cells MC shown can have a second orientation.

[0042] according to Figure 2 The memory cell array 30 shown in the example embodiment may include a plurality of memory cells formed on different layers. For example, the memory cell array 30 may include a first layer and a second layer stacked on top of each other, with memory cells in the first layer having a first orientation and memory cells in the second layer having a second orientation. However, according to other example embodiments, the orientation of the memory cells included in the respective first and second layers may be modified in various ways.

[0043] Figure 4A and Figure 4B It is a perspective view showing the structure of a memory cell included in a memory device according to respective exemplary embodiments.

[0044] Reference Figure 4A The memory device 100A according to an example embodiment may include a first memory cell MC1 and a second memory cell MC2 disposed between a pair of wires 101 and 102. The first memory cell MC1 and the second memory cell MC2 may operate as independent memory cells. As an example, when the first wire 101 and the second wire 102 are word lines, a third wire 103 between the first memory cell MC1 and the second memory cell MC2 may be a bit line. When the first wire 101 and the second wire 102 are bit lines, the third wire 103 may be a word line. Hereinafter, for ease of description, examples will be described where the first wire 101 and the second wire 102 are respectively a first word line and a second word line.

[0045] The first memory cell MC1 may include a first heating electrode 110, a first information storage device 120, and a first switching device 130. The first switching device 130 may include a first switching electrode 131, a second switching electrode 132, and a first selection layer 133 disposed between the first switching electrode 131 and the second switching electrode 132. In an example embodiment, the first selection layer 133 may include a bidirectional threshold switch (OTS) material. When a voltage higher than a threshold voltage is applied between the first switching electrode 131 and the second switching electrode 132, current can flow through the first selection layer 133.

[0046] The first information storage device 120 may include a phase change material, such as a chalcogenide material. As an example, the first information storage device 120 may include Ge-Sb-Te (GST), and the crystallization temperature, melting point, and phase change rate of the first information storage device 120 based on the crystallization energy can be determined according to the type and chemical composition ratio of the elements included in the first information storage device 120.

[0047] The second memory cell MC2 may have the same or similar structure as the first memory cell MC1. (Refer to...) Figure 4A The second memory cell MC2 may include a second heating electrode 140, a second information storage device 150, a second switching device 160, etc. The structure and characteristics of each of the second heating electrode 140, the second information storage device 150, and the second switching device 160 may be the same as or similar to the structure and characteristics of the first heating electrode 110, the first information storage device 120, and the first switching device 130. In the following description, methods for writing and erasing data will be described with reference to the first memory cell MC1 as an example.

[0048] When voltage is supplied through the first word line 101 and the bit line 103, Joule heating based on the voltage can be generated at the interface between the first heating electrode 110 and the first information storage device 120. The phase change material constituting the first information storage device 120 can change from an amorphous phase to a crystalline phase or from a crystalline phase to an amorphous phase due to Joule heating. The first information storage device 120 can have high resistance in the amorphous phase and low resistance in the crystalline phase. In an example embodiment, data "0" or "1" can be defined based on the resistance value of the first information storage device 120.

[0049] To write data into the first memory cell MC1, a programming voltage can be supplied via the first word line 101 and the bit line 103. The programming voltage is higher than the threshold voltage of the bidirectional threshold switching material included in the first switching device 130, thus allowing current to flow through the first switching device 130. The phase change material included in the first information storage device 120 can change from an amorphous phase to a crystalline phase due to the programming voltage, thus allowing data to be recorded in the first memory region. In an example embodiment, when the phase change material included in the first information storage device 120 has a crystalline phase, the state of the first memory cell MC1 can be defined as a set state.

[0050] On the other hand, in order to erase the data written to the first memory cell MC1, the phase change material included in the first information storage device 120 can be made to change from a crystalline phase to an amorphous phase. For example, a predetermined erase voltage can be supplied through the first word line 101 and the bit line 103. Due to the erase voltage, the phase change material included in the first information storage device 120 can change from a crystalline phase to an amorphous phase. When the phase change material included in the first information storage device 120 has an amorphous phase, the state of the first memory cell MC1 can be defined as a reset state. For example, the maximum value of the erase voltage can be greater than the maximum value of the programming voltage, and the time period for which the erase voltage is supplied can be shorter than the time period for which the programming voltage is supplied.

[0051] As described above, the resistance values ​​of information storage devices 120 and 150 can be changed according to the state of the phase change material included in the information storage devices 120 and 150, and the memory controller can distinguish between data "0" and "1" from the resistance of the information storage devices 120 and 150. Therefore, due to the increase in the resistance difference between information storage devices 120 and 150 caused by the state of the phase change material included in the information storage devices 120 and 150, the memory controller can correctly read the data stored in the memory cells MC1 and MC2.

[0052] Based on Figure 4A To describe the differences in comparison Figure 4B . Reference Figure 4A and Figure 4B When the first wire 101 and the second wire 102 are the first word line and the second word line, respectively, the first memory cell MC1 and the second memory cell MC2 can have the same or different orientations. For example, refer to... Figure 4A The first memory cell MC1 and the second memory cell MC2 may each have a second orientation. (Refer to...) Figure 4B The first memory cell MC1 may have a second orientation, and the second memory cell MC2 may have a first orientation.

[0053] Figure 5A and Figure 5B This is a schematic diagram illustrating the structure of a memory cell included in a memory device according to an example embodiment.

[0054] Figure 5A and Figure 5B The structure and features of the first memory cell MC1 and the second memory cell MC2 shown in the figure can be compared with those of the second memory cell MC2. Figure 4A and Figure 4B The first memory cell MC1 and the second memory cell MC2 have similar structures and features. On the other hand, in Figure 5A and Figure 5BIn this context, the first memory cell MC1 connected to the first word line formed on the first layer and the second memory cell MC2 connected to the second word line formed on the second layer may not share bit lines.

[0055] Reference Figure 5A The first memory cell MC1 can be located at the point where the first word line 101 and the first bit line 102 formed on the first layer intersect. The second memory cell MC2 can be located at the point where the second word line 103 and the second bit line 104 formed on the second layer intersect. The first memory cell MC1 can have a second orientation, and the second memory cell MC2 can have a first orientation.

[0056] Based on Figure 5A To describe the differences in comparison Figure 5B . Reference Figure 5B The first memory cell MC1 and the second memory cell MC2 may each have a second orientation.

[0057] Figure 6 This is a diagram illustrating the operation of a memory device 200 according to an example embodiment. The memory device 200 can be operated by power supplied to the memory cell 210 by a memory controller 220. The memory cell 210 may include a lower electrode 211, a heating electrode 212, an information storage device 214, a switching device 215, and an upper electrode 216. The lower electrode 211 and the upper electrode 216 may receive voltages output by the memory controller 220 via word lines or bit lines. An insulating layer 213 may be disposed around the heating electrode 212, and a phase transition may occur in a local region 214a of the information storage device 214 adjacent to the heating electrode 212 by power supplied by the memory controller 220.

[0058] In this embodiment, during the programming operation for writing data to memory cell 210, a predetermined bias voltage can be input to each of the lower electrode 211 and the upper electrode 216. Because the bias voltage is higher than the threshold voltage of the bidirectional threshold switching material included in the switching device 215, the memory cell 210 can be turned on. Thereafter, a programming current can be supplied to the memory cell 210. The phase change material included in the information storage device 214 can change from an amorphous phase to a crystalline phase due to the programming current. Therefore, data can be recorded in the memory region.

[0059] Figure 7 This is a diagram provided to explain the programming operations of a memory device 300 according to an example embodiment. (See diagram for example.) Figure 7As shown, the memory device 300 may include a memory cell array 310, a first decoder circuit 320, a second decoder circuit 330, a read / write circuit 340, and control logic 350. The memory cell array 310 may include first bit lines BL1 to fourth bit lines BL4, first word lines WL1 to fourth word lines WL4, and a plurality of memory cells MC. The plurality of memory cells MC may be disposed at the positions where the first bit lines BL1 to fourth bit lines BL4 intersect with the first word lines WL1 to fourth word lines WL4.

[0060] Multiple memory cells MC included in the memory cell array 310 can have different current paths. In this regard, "current path" can refer to the distance between the decoder circuits 320 and 330 and the memory cells. Memory cells with long current paths can have relatively higher path resistance compared to memory cells with short current paths. Conversely, memory cells with short current paths can have relatively lower path resistance compared to memory cells with long current paths. Path resistance can include bit line resistance, word line resistance, switching resistance, etc.

[0061] The memory cell array 310 may include a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 may be the memory cell furthest from the first decoder circuit 320 and the second decoder circuit 330. The second memory cell MC2 may be the memory cell closest to the first decoder circuit 320 and the second decoder circuit 330. The first memory cell MC1, furthest from the first decoder circuit 320 and the second decoder circuit 330, has the largest path resistance, and the second memory cell MC2, closest to the first decoder circuit 320 and the second decoder circuit 330, has the smallest path resistance.

[0062] Furthermore, the multiple memory cells included in the memory cell array 310 can have different levels of resistance, regardless of the current path. For example, the resistance of a memory cell can be classified as low resistance, intermediate resistance (or medium resistance), and high resistance in the range of 3.1KΩ to 8.3KΩ.

[0063] Simultaneously, during the programming operation, the first decoder circuit 320 and the second decoder circuit 330 can select the memory cell to be programmed from the memory cells. The memory cell to be programmed by the memory device 300 can be referred to as the selected memory cell. Each of the word lines and bit lines connected to the selected memory cell can be referred to as the selected word line and the selected bit line.

[0064] When the read / write circuit 340 programs the selected memory cell, a current source connected to the selected word line can supply programming current to the selected memory cell. The programming current can flow from the selected bit line to the selected word line through the selected memory cell.

[0065] During programming operations, programming characteristics may vary depending on the current path of the selected memory cell. Furthermore, even with the same current path, programming characteristics may vary depending on the resistance of the selected memory cell. For example, depending on the current path and / or resistance of the selected memory cell, programming operations may not be performed properly, or persistence / storage durability may deteriorate.

[0066] In the prior art, programming currents of the same magnitude are supplied to memory cells with different programming characteristics. According to Equation 1, the Joule heat generated in the memory cell when the programming current Ipgm flows in the memory cell can be proportional to the resistance Rdyn of the memory cell.

[0067] [Formula 1]

[0068] Joule fever ∝ Ipgm 2 *Rdyn

[0069] Figure 8A Joule heating based on the resistance of a memory cell, according to an example embodiment, is illustrated. (Refer to...) Figure 8A The programming current is determined based on the memory cell with the lowest resistance Rdyn. For example, the minimum programming current can be determined based on the minimum Joule heat Pmelt_min required to program a memory cell with the lowest resistance Rdyn_min. Therefore, when the programming current flows in the memory cell, excessive heat may be generated in the memory cell because the resistance Rdyn of the memory cell is higher than the minimum resistance Rdyn_min.

[0070] Figure 8B The diagram illustrates the distribution of memory cells according to the resistance of the memory cells, based on an example embodiment. For example... Figure 8B As shown, based on the intermediate resistance Rdyn2, memory cells in region a, which has a resistance Rdyn1 lower than the intermediate resistance Rdyn2, may not generate sufficient Joule heat. Therefore, memory cells in region a may not be properly programmed. Conversely, memory cells in region b, which has a resistance Rdyn3 higher than the intermediate resistance Rdyn2, may generate excessive Joule heat. Therefore, memory cells in region b may have poor durability or longevity.

[0071] Return to Figure 7When the memory device 300 according to an embodiment of the present disclosure programs a selected memory cell of the memory cell array 310, a programming current is determined based on the resistance of the selected memory cell. The determined programming current can be supplied to the selected memory cell. Therefore, the memory device 300 can compensate for changes in programming characteristics based on the resistance of the selected memory cell during programming operations.

[0072] Furthermore, when the memory device 300 determines the programming current, it can consider the current path of the selected memory cell. Therefore, the memory device 300 can compensate for changes in programming characteristics during programming operations based on the current path of the selected memory cell.

[0073] Figure 9 This is a circuit diagram of a memory device 400 according to an embodiment of the present invention. The memory device 400 may include a path switch Psw, a global bit line GBL, a local bit line LBL, a global word line GWL, a local word line LWL, and a memory cell CELL. The memory device 400 may also include a first current source CS1, a second current source CS2, a first NMOS transistor NM1 connected in diode form, a second NMOS transistor NM2 connected in diode form, a third NMOS transistor NM3, a first switch SW1, and a second switch SW2.

[0074] The memory cell (CELL) can be located in the region where the local bit line (LBL) and the local word line (LWL) intersect. A path switch (Psw) can selectively form an electrical path for supplying the power supply voltage (VPP) to the global bit line (GBL) in response to a selection signal (Pphase). For this purpose, the path switch (Psw) can include a switching transistor (GY1) having a gate that receives the selection signal (Pphase). Note that the switch symbol within the path switch (Psw) adjacent to the switching transistor (GY1), as well as other similar switch symbols in subsequent diagrams containing path switches, are included as indicators of the switching state of the corresponding switching transistors (GY1, etc.).

[0075] Global bit line (GBL) may include a global bit line selection transistor (GY2) and a global bit line resistor (R). GBL Global bit line resistor R GBL This can represent the parasitic resistance included in the global bit line (GBL). The local bit line (LBL) can include the local bit line selection transistor (LY) and the local bit line resistor (R). LBL Local bit line resistor R LBL This can represent the parasitic resistance included in the local bit line LBL.

[0076] The global word line (GWL) may include a global word line selection transistor (GX) and a global word line resistor (R). GWL Global word line resistor RGWL This can represent the parasitic resistance included in the global word line GWL. The local word line LWL may include a local word line selection transistor LX and a local word line resistor R. LWL Local word line resistor R LWL This can represent the parasitic resistance included in the local word line LWL.

[0077] The path resistance included in the current path of the memory cell (CELL) can be expressed as shown in Equation 2.

[0078] [Equation 2]

[0079] Rpara = R GY_SW +R GBL +R LY_SW +R LBL +R LWL +R LX_SW +R GWL +R GX_SW

[0080] In this case, Rpara represents the path resistance, R GY_SW R represents the switching resistor of the global bit line selection transistor GY2. LY_SW R represents the switching resistor of the local bit line selection transistor LY. LX_SW R represents the switching resistor of the local word line selection transistor LX. GX_SW This represents the switching resistor for the global word line selection transistor GX.

[0081] Figure 10 It is used to describe according to the example embodiments Figure 9 A diagram illustrating the programming operations of the memory device 400. (Refer to...) Figure 9 and Figure 10 The selected word line WL can be precharged to a first voltage level (e.g., lower than 0V) before the "on-time" period, and the selected bit line BL can be precharged to a second voltage level (e.g., 0V). As a result, a first voltage ΔV1 higher than a threshold voltage can be supplied across the opposite end of the selected memory cell CELL during the on-time period. When the first voltage ΔV1 higher than the first threshold voltage is supplied across the selected memory cell CELL, the selected memory cell CELL can be turned on. For example, the first threshold voltage can represent the voltage at which the selected memory cell CELL is turned on.

[0082] When the selected memory cell CELL is turned on, in order to prevent the turned-on selected memory cell CELL from being turned off, the memory device 400 can supply a holding current Ihold to the selected memory cell CELL. The holding current Ihold can refer to the minimum current required to prevent the selected memory cell CELL from being turned off. In order to supply the holding current Ihold to the selected memory cell CELL, the memory device 400 can close the first switch SW1 to connect the first current source CS1 to the selected word line WL.

[0083] When the first switch SW1 is closed, the third NMOS transistor NM3 and the first NMOS transistor NM1, which is connected in the form of a diode, can form a current mirror. Through the current mirror, the holding current Ihold, which corresponds to the first bias current Ibias1, can flow in the selected memory cell CELL (Icell = Ihold).

[0084] During the "programming period" following the conduction period, the memory device 400 can supply a programming current Ipgm to the selected memory cell CELL. The amplitude of the programming current Ipgm can be higher than the amplitude of the holding current Ihold. To supply a programming current Ipgm with an amplitude higher than the holding current Ihold, the memory device 400 precharges the selected word line WL to a third voltage level (e.g., lower than the first voltage level) and precharges the selected bit line BL to a fourth voltage level, for example, higher than the previous level. As a result, a second voltage ΔV2, higher than the first voltage ΔV1, can be supplied at the opposite end of the selected memory cell CELL during the programming period. The memory device 400 can connect a second current source CS2 to the selected word line WL by opening the first switch SW1 and closing the second switch SW2.

[0085] When the second switch SW2 is closed, the third NMOS transistor NM3 and the second NMOS transistor NM2, which is connected in the form of a diode, can form a current mirror. Through the current mirror, the programming current Ipgm, which corresponds to the second bias current Ibias2, can flow in the memory cell CELL (Icell = Ipgm).

[0086] Figure 11 It is a graph showing the voltage-current diagram of a memory cell during programming operation of a memory device according to an example embodiment.

[0087] Reference Figure 10 and Figure 11 Because a first voltage ΔV1 is supplied to the selected word line WL and the selected bit line BL during the conduction period, the voltage across the selected memory cell can be increased to the threshold voltage Vth. Therefore, the selected memory cell can be turned on.

[0088] A holding current Ihold can be supplied to the selected memory cell to prevent it from turning off after it has been turned on. Therefore, the voltage across the selected memory cell can be the holding voltage Vhold.

[0089] Meanwhile, the voltage-current graph of the memory cell can vary depending on whether the resistance of the selected memory cell is low (a), medium (b), or high (c). The slope of the voltage-current graph of the memory cell can correspond to the reciprocal of the resistance Rdyn of the memory cell.

[0090] When the programming current Ipgm is supplied to the selected memory cell during the programming period following the conduction period, the voltage across the selected memory cell can vary depending on the resistance of the selected memory cell. For example, when the resistance of the selected memory cell is low (a), the voltage across the selected memory cell can be a first voltage. When the resistance of the selected memory cell is intermediate (b), the voltage across the selected memory cell can be a second voltage. When the resistance of the selected memory cell is high (c), the voltage across the selected memory cell can be a third voltage. The second voltage can be higher than the first voltage and lower than the third voltage.

[0091] For example, when the programming current Ipgm is supplied to the selected memory cell, the voltage across the selected memory cell increases as the resistance of the selected memory cell increases. Therefore, when the programming current Ipgm is supplied to the selected memory cell, excessive heat will be generated in the selected memory cell as the resistance of the selected memory cell increases.

[0092] According to embodiments of this disclosure, when a memory device programs a selected memory cell, the programming current can be determined differently based on the resistance of the selected memory cell. For example, a lower resistance of the selected memory cell can increase the amplitude of the programming current, while a higher resistance can decrease the amplitude of the programming current. Therefore, the memory device can compensate for changes in programming characteristics based on the resistance of the selected memory cell during programming operations.

[0093] Figure 12 This is a circuit diagram of a memory device 500 according to an embodiment of the present invention. The memory device 500 may include a path switch Psw, a voltage regulator RG, a selection switch Ssw, a memory cell CELL, a path resistor Rpara, a sampling circuit SC, and a bias current circuit BC. The voltage regulator RG, the sampling circuit SC, and the bias current circuit BC may be included in a programming circuit.

[0094] The path switch Psw can selectively form an electrical path for supplying the power supply voltage VPP to the global bit line based on the selection signal Pphase.

[0095] The voltage regulator RG can receive a sampled voltage Vsample. The voltage regulator RG can stably supply the sampled voltage Vsample to the memory cell CELL connected to the voltage regulator RG. The sampled voltage Vsample can be a voltage used to compensate for the location of the memory cell CELL. Therefore, the sampled voltage Vsample can be a voltage determined based on the current path of the memory cell.

[0096] For example, a memory cell with a long current path located at the far end has a higher path resistance than a memory cell with a short current path located at the near end, so the sampling voltage Vsample can be relatively large. Conversely, a memory cell with a current path located at the near end has a lower path resistance than a memory cell with a current path located at the far end, so the sampling voltage Vsample can be relatively small.

[0097] The voltage regulator RG may include an amplifier and a first NMOS transistor NM1.

[0098] The selector switch Ssw can selectively form an electrical path for supplying the sampled voltage Vsample to the memory cell CELL via the voltage regulator RG.

[0099] The path resistor Rpara can refer to the path resistor described in Equation 2 for the memory cell.

[0100] The sampling circuit SC may include first switches SW1 to fourth switches SW4, a second NMOS transistor NM2 connected in diode form, a third NMOS transistor NM3, and a capacitor C. When the selection switch SW1 is closed, the sampling voltage Vsample can be supplied to the memory cell CELL, and the sampling current Isample can flow through the memory cell CELL. At this time, when the first switch SW1 and the second switch SW2 are closed, the capacitor C can be charged using the sampling current Isample flowing through the memory cell CELL.

[0101] The sampling current Isample can be expressed as shown in Equation 3 below.

[0102] [Formula 3]

[0103]

[0104] In this case, Vsample can be the sampling voltage determined based on the location of the memory cell, Vhold can be the holding voltage across the memory cell, Rpara can be the path resistance, and Rdyn can represent the resistance of the memory cell.

[0105] The holding voltage Vhold can have a fixed value depending on the characteristics of the memory cell. Meanwhile, although the path resistor Rpara depends on the location of the memory cell, the sampling voltage Vsample is determined based on the location of the memory cell, and therefore the sampling current Isample can have a value that compensates for the location of the memory cell. Thus, the sampling current Isample can be a value that varies according to the resistance Rdyn of the memory cell.

[0106] For example, when the resistance Rdyn of the memory cell is high, the sampling current Isample can be relatively reduced. When the resistance Rdyn of the memory cell is low, the sampling current Isample can be relatively increased. For example, the resistance Rdyn of the memory cell can be sampled by detecting the sampling current Isample.

[0107] When the selector switch Ssw is open and the path switch Psw is closed, the power supply voltage VPP can be supplied to the memory cell CELL. At this time, when the first switch SW1 and the second switch SW2 are open and the third switch SW3 and the fourth switch SW4 are closed, the charge stored in the capacitor C can be released. Therefore, an additional programming current Ib corresponding to the sampling current Isample can be generated. Thus, the additional programming current Ib can be a current whose magnitude is adjusted according to the resistance Rdyn of the memory cell.

[0108] The bias current circuit BC may include a fifth switch SW5, a current mirror CM, and a current source CS. The current mirror CM may include a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5 connected in diode form. When the fifth switch SW5 is closed when the power supply voltage VPP is supplied to the memory cell CELL, the current source CS may be connected to the selected word line. The initial programming current Ia corresponding to the bias current Ibias may be generated by the current mirror CM.

[0109] Therefore, when the power supply voltage VPP is supplied to the memory cell, the final programming current Icell flowing in the memory cell can correspond to the sum of the initial programming current Ia and the additional programming current Ib (Icell = Ia + Ib). By adding the additional programming current Ib, scaled according to the resistance Rdyn of the memory cell, to the initial programming current Ia, the memory device changes its programming characteristics during programming operations according to the resistance Rdyn of the memory cell to compensate for the location of the memory cell.

[0110] Furthermore, because the sampling current Isample has a value that compensates for the location of the memory cell, the memory device can compensate for changes in programming characteristics during programming operations based on the current path of the memory cell CELL.

[0111] In the following text, reference will be made to Figures 13 to 15 The operation of the memory device according to an embodiment of the present invention will be described in more detail.

[0112] Figures 13 to 15 This is a diagram illustrating programming operations of a memory device according to an example embodiment. The memory device according to embodiments of this disclosure can operate in a manner divided into sampling periods and programming periods. Figure 13 and Figure 14 It is a diagram used to describe the operation of a memory device during a sampling period. Figure 15 It is a diagram used to describe the operation of a memory device during the programming period.

[0113] Reference Figure 13 and Figure 14 When the memory device 600A operates during the sampling period, the selection switch Ssw, the first switch SW1, and the second switch SW2 can be closed. In this case, a sampling voltage Vsample, determined based on the location of the memory cell CELL, can be supplied to the memory cell CELL. When the sampling voltage Vsample is supplied to the memory cell CELL, a sampling current Isample, whose magnitude is adjusted according to the resistance Rdyn of the memory cell, can flow in the memory cell CELL (Icell = Isample).

[0114] For example, when the resistance of the memory cell is a low resistance 'a', the first sampling current Isample_a can flow in the memory cell CELL. When the resistance of the memory cell is an intermediate resistance 'b', the second sampling current Isample_b can flow in the memory cell CELL. When the resistance of the memory cell is a high resistance 'c', the third sampling current Isample_c can flow in the memory cell CELL. The amplitude of the second sampling current Isample_b can be lower than the amplitude of the first sampling current Isample_a and higher than the amplitude of the third sampling current Isample_c.

[0115] The capacitor C can be charged using the sampled current Isample. The resistance Rdyn of the memory cell can be sampled by detecting the amount of charge in the capacitor C charged by the sampled current Isample.

[0116] Reference Figure 15 When the memory device 600B operates during the programming period after the sampling period, the selection switch Ssw can be opened and the path switch Psw can be closed. In this case, the power supply voltage VPP can be supplied to the memory cell CELL. Furthermore, the first switch SW1 and the second switch SW2 can be opened, and the third switch SW3 through the fifth switch SW5 can be closed.

[0117] The sampling circuit SC generates an additional programming current Ib by releasing the charge charged into the capacitor C. The bias current circuit BC generates an initial programming current Ia corresponding to the bias current Ibias.

[0118] Therefore, when the memory device 600B operates during the programming period, the final programming current Icell flowing in the memory cell CELL can correspond to the sum of the initial programming current Ia and the additional programming current Ib (Icell = Ia + Ib).

[0119] Because the final programming current Icell is a current whose magnitude is adjusted according to the resistance Rdyn of the memory cell, the memory device 600B can compensate for changes in programming characteristics during programming operations based on the resistance Rdyn of the memory cell.

[0120] In addition, since the final programming current Icell is determined taking into account the current path of the memory cell CELL, the memory device 600B can compensate for changes in programming characteristics during programming operations based on the current path of the memory cell.

[0121] Figures 16A to 16C This is a diagram used to describe the programming operations of a memory device according to an example embodiment.

[0122] Reference Figure 16A The selected word line WL can be precharged to a first voltage level, and the selected bit line BL can be precharged to a second voltage level. As a result, a third voltage ΔV3, higher than a threshold voltage, can be supplied to the opposite end of the selected memory cell CELL during the first time period D1 of the sampling period. When the third voltage ΔV3, higher than the threshold voltage, is supplied across the selected memory cell CELL, the selected memory cell CELL can be turned on. For example, the threshold voltage can represent the voltage at which the selected memory cell CELL is turned on.

[0123] When the selected memory cell CELL is turned on, a sampling voltage Vsample can be supplied to the memory cell CELL during the second sampling period D2. The sampling voltage Vsample can be lower than the third voltage ΔV3. A first sampling current Isample1, whose magnitude is adjusted according to the resistance Rdyn of the memory cell, can flow in the selected memory cell CELL using the sampling voltage Vsample. For example, the first sampling current Isample1 can be the current flowing through the memory cell when the resistance Rdyn of the memory cell is high.

[0124] During the programming phase following the sampling period, the power supply voltage VPP can be supplied to the memory cell. Using the power supply voltage VPP, a fourth voltage ΔV4, higher than the third voltage ΔV3, can be supplied to the opposite terminal of the selected memory cell CELL. The sampling voltage Vsample can be lower than the fourth voltage ΔV4.

[0125] Simultaneously, the memory device can generate an additional programming current corresponding to the first sampling current Isample1 during the programming period. This additional programming current can be a current whose magnitude is adjusted according to the resistance Rdyn of the memory cell. Furthermore, the memory device can be connected to a current source for supplying a bias current to the selected word line during the programming period. The initial programming current corresponding to the bias current can be generated by a current mirror.

[0126] During the programming period, the first final programming current Ipgm1 flowing in the memory cell can correspond to the sum of the additional programming current and the initial programming current.

[0127] Based on Figure 16A To describe the differences in comparison Figure 16B and Figure 16C . Reference Figure 16B During the sampling period, the second sampling current Isample2 can be the current flowing through the memory cell when the resistance Rdyn of the memory cell is an intermediate resistance. The memory device can generate an additional programming current corresponding to the second sampling current Isample2. The amplitude of the second sampling current Isample2 can be higher than the amplitude of the first sampling current Isample1.

[0128] During the programming period following the sampling period, the additional programming current can flow together with the initial programming current in the second final programming current Ipgm2 flowing in the memory cell. The amplitude of the second final programming current Ipgm2 can be higher than the amplitude of the first final programming current Ipgm1.

[0129] Reference Figure 16C During the sampling period, the third sampling current Isample3 can be the current flowing in the memory cell when the resistance Rdyn of the memory cell is low. The memory device can generate an additional programming current corresponding to the third sampling current Isample3. The amplitude of the third sampling current Isample3 can be higher than the amplitude of the first sampling current Isample1 and the amplitude of the second sampling current Isample2.

[0130] During the programming period following the sampling period, the additional programming current can flow together with the initial programming current in the third final programming current Ipgm3 flowing in the memory cell. The amplitude of the third final programming current Ipgm3 can be higher than the amplitude of the first final programming current Ipgm1 and the amplitude of the second final programming current Ipgm2.

[0131] Figure 17A Joule heating based on the resistance of a memory cell, according to an example embodiment, is shown. Figure 17A In this context, Rdyn_typ is a reference voltage that determines the type of the (dynamic) resistor Rdyn. An example embodiment of the present invention allows the memory device to increase the programming current as the resistance Rdyn of the memory cell decreases, and decreases the programming current as the resistance Rdyn of the memory cell increases.

[0132] like Figure 17A As shown, because the programming current increases as the resistance Rdyn of the memory cell decreases, sufficient Joule heat can be generated in the memory cell. Conversely, the higher the resistance Rdyn of the memory cell, the greater the decrease in programming current, thus preventing excessive Joule heat from being generated in the memory cell.

[0133] Figure 17B The diagram illustrates the distribution of memory cells based on the resistance of the memory cells according to an example embodiment. Based on the intermediate resistance Rdyn2, sufficient Joule heat can be generated in memory cells (region "a") with a resistance Rdyn1 lower than the intermediate resistance Rdyn2, allowing the distributed region "a" to shift to the right. Therefore, programming operations can be performed normally. Conversely, excessive Joule heat can be prevented from being generated in memory cells (region "b") with a resistance Rdyn3 higher than the intermediate resistance Rdyn2, allowing the distributed region "b" to shift to the left. Therefore, the persistence / durability of the memory cells can be improved. Overall, there is an effect of narrowing the distribution of memory cells.

[0134] Figure 18 This is a diagram illustrating an example of a memory device. Figure 19 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0135] Reference Figure 18 and Figure 19 When the selected word line and selected bit line are precharged, a voltage higher than the threshold voltage can be supplied across the selected memory cell CELL. When a voltage higher than the threshold voltage is supplied across the selected memory cell CELL, the selected memory cell CELL can be turned on (S110).

[0136] When the memory device 700 is operating during the sampling period, the selection switch Ssw, the first switch SW1, and the second switch SW2 can be closed. In this case, the voltage regulator RG can supply the sampling voltage Vsample, determined based on the location of the memory cell, to the memory cell CELL.

[0137] When the sampling voltage Vsample is supplied to the memory cell CELL, the sampling current Isample, whose magnitude is adjusted according to the resistance Rdyn of the memory cell, can flow through the memory cell CELL. The capacitor C can be charged using the sampling current Isample. The resistance Rdyn of the memory cell can be sampled by detecting the sampling current Isample (S120).

[0138] When the selection switch Ssw is opened and the path switch Psw is closed during the programming period following the sampling period, the power supply voltage VPP can be supplied to the memory cell. In this case, the first switch SW1 and the second switch SW2 can be opened, and the third switch SW3 through the fifth switch SW5 can be closed.

[0139] The sampling circuit SC generates an additional programming current by releasing the charge charged into the capacitor C. The bias current circuit BC generates an initial programming current corresponding to the bias current Ibias. Therefore, during the programming period, the memory device determines the final programming current (Icell = Ipgm) by adding the additional programming current determined based on the sampling current Isample to the initial programming current. The memory device can then supply the final programming current to the selected memory cell (S130).

[0140] Figure 20 This is a block diagram schematically illustrating an electronic device including a memory device according to an example embodiment.

[0141] according to Figure 20 The computer device 1000 shown in the example embodiment may include a display 1010, an input / output unit 1020, a memory 1030, a processor 1040, a port 1050, etc. Furthermore, the computer device 1000 may also include wired / wireless communication devices, a power supply, etc. Figure 20 Among the components shown, port 1050 may be a device provided for communication between computer device 1000 and video cards, sound cards, memory cards, USB devices, etc. In addition to ordinary desktop or laptop computers, computer device 1000 may also be a device including smartphones, tablet PCs, smart wearable devices, etc.

[0142] Processor 1040 can perform specific operations, instructions, tasks, etc. Processor 1040 can be a central processing unit (CPU), microprocessor unit (MCU), system on chip (SoC), etc., and can communicate with other devices connected to port 1050, as well as display 1010, input / output unit 1020 and memory 1030 via bus 1060.

[0143] The memory 1030 may be a storage medium for storing data, multimedia data, etc., required for the operation of the computer device 1000. Examples of the memory 1030 include volatile memory such as random access memory (RAM) or non-volatile memory such as flash memory. Other examples of the memory 1030 include at least one of solid-state drives (SSDs), hard disk drives (HDDs), and optical drives (ODDs) as storage devices. The input / output unit 1020 may include input devices such as a keyboard, mouse, and touchscreen for the user, and output devices such as a display and an audio output unit.

[0144] The memory 1030 may include a phase-change memory device that writes / deletes and reads data by utilizing the resistance change of a phase-change material. Figure 20 In the example embodiment shown, memory 1030 may include components according to the above references. Figures 1 to 19 Memory devices of various embodiments described.

[0145] As described above, according to the example embodiment, when the memory device programs a selected memory cell, the amplitude of the programming current can be determined differently depending on the resistance of the selected memory cell. Therefore, the memory device has the effect of compensating for changes in programming characteristics based on the resistance of the selected memory cell during programming operations.

[0146] Furthermore, when determining the programming current, the memory device can take into account the location of the selected memory cell. Therefore, the memory device has the effect of compensating for changes in programming characteristics based on the location of the selected memory cell during programming operations.

[0147] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, the memory device comprising: Multiple memory cells, each memory cell including a switching device and an information storage device having a phase change material connected to the switching device, the multiple memory cells being connected to multiple word lines and multiple bit lines; The decoder circuit is configured to determine at least one memory cell among the plurality of memory cells as the selected memory cell in response to an address. as well as A programming circuit is configured to apply a programming current to the selected memory cell to perform a programming operation, and during the programming operation, detect the resistance of the selected memory cell to adjust the amplitude of the programming current. The programming current is determined by taking into account the location of the selected memory cell, and The programming circuit includes a voltage regulator configured to supply a sampling voltage for compensating the location of the selected memory cell to the selected bit line connected to the selected memory cell.

2. The memory device according to claim 1, wherein, The programming circuit applies a bias current to the selected word line connected to the selected memory cell and generates an initial programming current corresponding to the bias current.

3. The memory device according to claim 2, wherein, The programming circuit generates an additional programming current scaled according to the detected resistance. The programming current is the sum of the initial programming current and the additional programming current.

4. The memory device according to claim 1, wherein, The programming circuit also includes: A sampling circuit is configured to detect a sampling current flowing through the selected memory cell via the sampling voltage and generate an additional programming current corresponding to the sampling current; and A bias current circuit is configured to apply a bias current to the selected word line connected to the selected memory cell and generate an initial programming current corresponding to the bias current.

5. The memory device according to claim 4, wherein, In the programming operation for the selected memory cell, the programming current is the sum of the initial programming current and the additional programming current.

6. The memory device according to claim 4, wherein, The sampling voltage is determined based on the distance between the selected memory cell and the decoder circuit.

7. The memory device according to claim 4, wherein, The amplitude of the sampling voltage is determined based on the location of the selected memory cell.

8. The memory device according to claim 4, wherein, The additional programming current is a current scaled according to the detected resistance.

9. The memory device according to claim 4, wherein, The magnitude of the additional programming current is higher than the minimum current required to maintain the selected memory cell in the on state.

10. The memory device according to claim 4, wherein, The sampling circuit includes: The capacitor is charged using the sampled current; and An NMOS transistor connected in the form of a diode is configured to connect the capacitor to the selected word line through which the sampling current flows.

11. A memory device, the memory device comprising: A memory cell array includes multiple memory cells located at the intersections of multiple word lines and multiple bit lines; The decoder circuit is configured to determine at least one memory cell among the plurality of memory cells as the selected memory cell in response to an address. as well as The programming circuit is configured to, during a programming operation targeting the selected memory cell, generate a sampling current during a sampling period whose amplitude decreases as the resistance of the selected memory cell increases, and to generate a programming current based on the sampling current during the programming period. The programming current is determined by taking into account the location of the selected memory cell, and The programming circuit supplies a sampling voltage for compensating the location of the selected memory cell to the selected bit line connected to the selected memory cell.

12. The memory device according to claim 11, wherein, The programming circuit supplies a sampling voltage, used to compensate for the location of the selected memory cell, to the selected bit line connected to the selected memory cell during the first period of the sampling period.

13. The memory device according to claim 12, wherein, The programming circuit supplies a first voltage higher than the threshold voltage of the selected memory cell to the opposite end of the selected memory cell during the second period of the sampling period.

14. The memory device according to claim 13, wherein, The sampling voltage is lower than the first voltage.

15. The memory device according to claim 12, wherein, During the programming period, a second voltage is supplied across the selected memory cell.

16. A method of operating a memory device, the method comprising the steps of: Turn on the selected memory cell connected to the selected word line and the selected bit line; Detect the resistance of the selected memory cell; A bias current is input to the selected word line connected to the selected memory cell, and an initial programming current corresponding to the bias current is generated. An additional programming current is generated, the magnitude of which decreases as the detected resistance increases; as well as The selected memory cell is programmed using the initial programming current and the additional programming current. Specifically, the selected memory cell is programmed by taking into account its location, and The step of detecting the resistance of the selected memory cell includes supplying a sampling voltage for compensating the location of the selected memory cell to the selected bit line connected to the selected memory cell.

17. The method according to claim 16, wherein, The step of detecting the resistance of the selected memory cell further includes: When the sampling voltage is supplied to the selected memory cell, the capacitor is charged using the sampling current flowing through the selected memory cell.

18. The method according to claim 17, wherein, The step of generating the additional programming current includes discharging the charged capacitor.

19. The method of claim 16, wherein, The steps for programming the selected memory cell include: The final programming current is supplied to the selected memory cell, which is the sum of the initial programming current and the additional programming current.

20. The method according to claim 19, wherein, The magnitude of the final programming current decreases as the resistance of the selected memory cell increases.

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