Device for improving carrier mobility in MOSFET channel on silicon carbide

Abstract

The invention relates to a MOSFET device arranged on a substrate 10, comprising a heavily doped first strip 11 and a heavily doped second strip 14, covered respectively by a first contact 13 and a second contact 15, the two strips being separated by a channel 18 also present on the substrate 10, the channel being covered by a dielectric layer 20, the third contact 21 being on the dielectric layer 20 itself. The device is remarkable in that the channel 18 comprises, at the interface with the dielectric layer 20, a thin film 19 lightly doped with dopant atoms of the same type as the channel, these dopant atoms being distributed on both sides of the interface.

Description

Technical Field

[0001] The present invention relates to devices for improving carrier mobility in a MOSFET channel on silicon carbide. Background Art

[0002] The field of the invention is that of electronic power components made on silicon carbide (SiC), since this material exhibits a high carrier saturation velocity and very good thermal conductivity. These components include diodes, thyristors, bipolar transistors, MOSFETs and more recently insulated gate bipolar transistors (IGBTs).

[0003] Patent US 6 639 273 thus discloses a MOSFET device on a SiC substrate, which includes a channel region 50 (p-channel region) with a low concentration of P-type dopants between a source region 43 and a drain region 44, both of which are N-type (D1, column 5, lines 49 to 61, Figure 1 a). The gate insulating layer 45 is formed directly on the channel region 50 .

[0004] However, it is found that in components of MOSFET or IGBT type, the carrier mobility in the channel is low compared to the mobility present in the core of the material. This causes a limitation on the current carrying capacity of such components. This is due to the high density of interface states between SiC and the oxide of the SiO2 gate. These interface states are caused by the presence of defects such as carbon clusters or indeed defects in the interface layer below the oxide, which are generated at the end of the oxidation process.

[0005] In this regard, researchers and industry have developed techniques for improving the quality of the SiO2 / SiC interface. Thus, it is known to perform oxidation under nitrogen oxides NO or N2O and on this topic reference may be made to:

[0006] ·GYChung, CCTin, JRWilliams, K.McDonald, RKChanana, RAWeller, STPantelides, LCFelldman, OXHolland, MKDas, and JWPalmour—IEEE Electronic Device Letters 22,176(2001);

[0007] ·R. P. Friedrichs, D. Pstephani, S. Dimitrijev and P. Jamet-Applied Physics Letters 80, 4253 (2002);

[0008] LA Lipkin, MK Das and JW Palmour - Material Science Forum 389-393, 985 (2002); and

[0009] ·K.Shiraishi et al.-First Principle Study of SiC / SiO2 InterfacesTowards Future Power Devices-International Electron Device Meeting IEDM2014 conference proceeding.

[0010] These techniques provide improvements, but they are still insufficient given the expected performance.

[0011] It is also known to perform a post-annealing treatment under nitrogen or by preparing the surface of the SiC by a plasma enhanced chemical vapor deposition (PECVD) process before oxidizing the gate. Reference may be made in particular to document CN105047539 (A) entitled "Method for improving channel mobility of SiC metal-oxide-semiconductor-field-effect-transistor (MOSFET)".

[0012] Also known is the article "Phosphorous passivation of the SiO2 / 4H-SiC interface" by YK Sharma, ACAhyi, T. Isaac-Smith, X. Shen, STPantelides, X. Zhu, LC Feldman and JR Williams in Solid-State Electronics, Vol. 68 - February 2012 - pp. 103-107. This involves annealing in a P2O5-saturated atmosphere to convert the SiO2 layer into phosphosilicate glass (PSG). This also improves the mobility of the charge carriers.

[0013] In this case, it is necessary to carry out annealing, with all the disadvantages that it entails, and it is difficult to control the amount of phosphorus introduced. This leads to a high degree of instability in the operation of the component. Summary of the invention

[0014] It is therefore an object of the present invention to significantly increase the carrier mobility in a MOSFET channel without exhibiting the limitations of the prior art mentioned above.

[0015] According to the present invention, a MOSFET device arranged on a substrate comprises a heavily doped first strip and a heavily doped second strip, the heavily doped first strip and the heavily doped second strip being covered by a first contact and a second contact respectively, the two strips being separated by a channel also present on the substrate, the channel being covered by a dielectric layer, and the third contact being on the dielectric layer itself; the device is notable in that a lightly doped thin film is located at the interface between the channel and the dielectric layer, and in that the first strip and the second strip and the thin film exhibit a doping of the same type as the channel and opposite to the doping type of the substrate, so as to produce a charge fixed at the interface between the channel and the dielectric layer, so that carriers are repelled from the dielectric layer and its defects.

[0016] Thus, fixed charges are generated right at the interface between the channel and the dielectric layer, so that carriers are repelled away from the dielectric layer and its defects.

[0017] Advantageously, the substrate is made of silicon carbide.

[0018] Preferably, the dielectric layer is made of silicon dioxide.

[0019] In a preferred embodiment, in a method for manufacturing such a MOSFET device, the thin film is produced by ion implantation.

[0020] Thus, for example, ion implantation is performed by plasma immersion ion implantation.

[0021] In a first option, the substrate is of P-type and the channel is of N-type.

[0022] In this case, the dopant of the film is N-type.

[0023] For example, the dopant is phosphorus.

[0024] In a second option, the substrate is N-type and the channel is P-type.

[0025] In such a case, the dopant of the film is P-type.

[0026] For example, the dopant of the film is boron.

[0027] Furthermore, the film is optionally doped with dipole effect elements.

[0028] For example, a dipole effect element is fluorine.

[0029] Preferably, in the method for manufacturing such a MOSFET device, the dipole effect element is added by plasma immersion ion implantation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The invention will be seen in more detail in the context of the following description of an embodiment given by way of example and with reference to the sole accompanying drawing, which is a perspective view of a MOSFET device. DETAILED DESCRIPTION

[0031] Referring to the figure, the device is formed on a substrate 10, which in this example is of P-type. It can be solid, or epitaxially grown, or indeed epitaxially grown and doped.

[0032] On the top surface of the substrate 10 there is a heavy N + A doped first strip 11 (on the left in the figure). This first strip is generally referred to as the drain. The drain has a first metal contact 13 applied to it.

[0033] Still on the top surface of the substrate 10, there is also a layer of N + A doped second strip 14 (on the right in the figure). It is arranged parallel to and at a distance from the first strip 11. This second strip 14 is generally referred to as the source. The source has a second metal contact 15 applied to it.

[0034] The gap between the drain and the source forms a channel 18 .

[0035] Conventionally, in MOSFET technology, a dielectric layer is added over the channel between the drain 11 and the source 14. In contrast, according to the present invention, a lightly doped thin film 19 is produced over the channel before applying the dielectric layer.

[0036] Advantageously, this thin film 19 is made by ion implantation, in particular in plasma immersion mode, which has the advantage of producing fewer defects. It is lightly doped, for example, wherein the doping is carried out at an acceleration voltage of less than 10 kilovolts (kV), typically in the range of 2 kV to 5 kV, and the implantation dose is 100 volts per square centimeter (cm 2 )10 14 The dopant is of N-type and, for example, it can be phosphorus. The plasma is preferably PH3 or PF x It is also possible to use arsenic as a dopant, in which case the plasma would be AsH3 or AsF x type.

[0037] The doping is isotropic and can cover the sides of the trench independently of the angle created between the trench and the surface.

[0038] It is also desirable to have the film 19 introduced therein with dipole effect elements, with a first choice being fluorine. Again, these elements are introduced by plasma immersion ion implantation.

[0039] Then, a dielectric layer 20 is deposited on the film 19 in register with the channel 18. In MOSFET terminology, this layer is generally called the gate oxide. It is usually silicon oxide made by thermal oxidation of the substrate or by chemical vapor deposition (CVD) or by a combination of these two techniques.

[0040] As a result, the dopant of the thin film 19 is distributed on both sides of the interface with the silicon dioxide 20 .

[0041] A third contact 21 is deposited on the gate oxide 20 to form the gate of the MOSFET device.

[0042] Such a configuration offers major advantages compared to current technological developments.

[0043] First, the mobility of carriers in the channel under the gate is multiplied by a factor greater than 3.

[0044] Second, in the on-state, the drain / source current (IDS) increases by nearly a factor of 10.

[0045] In the above, it is assumed that the device is implanted on a P-type substrate.

[0046] It is entirely possible to apply the present invention to devices implanted on an N-type substrate.

[0047] In such a case, the drain and source are heavily doped with P+ type elements.

[0048] Similarly, the film is then lightly doped with a P-type element such as boron or aluminum.

[0049] Since those skilled in the art can easily transfer the above description for a P-type substrate to an N-type substrate, it is not necessary to give more details about this second device.

[0050] In parallel, the doping techniques are the same and any plasma used forms part of the current technological development, whether involving boron or indeed aluminium.

[0051] The invention is described with reference to a signal processor MOSFET device. The invention also applies to vertical power MOSFET devices, or indeed to "trench" transistors.

[0052] The above-described embodiments of the present invention have been selected because of their specific nature. However, it is not possible to list all embodiments covered by the present invention exclusively. In particular, any means described may be replaced by equivalent means without exceeding the scope of the present invention.

Claims

1. A MOSFET device arranged on a substrate (10), the MOSFET device comprising a heavily doped first strip (11) and a heavily doped second strip (14), the heavily doped first strip (11) and the heavily doped second strip (14) being covered by a first contact (13) and a second contact (15) respectively, the two strips being separated by a channel (18) also present on the substrate (10), the channel being covered by a dielectric layer (20), and a third contact (21) being located above the dielectric layer (20); the device is characterized in that a lightly doped thin film (19) produced by ion implantation is located at the interface between the channel (18) and the dielectric layer (20), and in that the first strip and the second strip and the thin film exhibit a doping of the same type as the channel and opposite to the doping type of the substrate (10) so as to generate charges fixed at the interface between the channel and the dielectric layer so that carriers are repelled from the dielectric layer and its defects.

2. The device according to claim 1, characterized in that The substrate (10) is made of silicon carbide.

3. A device according to any preceding claim, characterised in that The dielectric layer (20) is made of silicon dioxide.

4. The device according to claim 1, characterized in that The substrate (10) is of P type and the channel (18) is of N type.

5. A device according to claim 4, characterized in that The dopant of the film (19) is N-type.

6. A device according to claim 5, characterized in that The dopant of the thin film (19) is phosphorus.

7. The device according to claim 1, characterized in that The substrate (10) is of N type and the channel (18) is of P type.

8. Device according to claim 7, characterized in that The dopant of the film (19) is P type.

9. A device according to claim 8, characterized in that The dopant of the film (19) is boron.

10. The device according to claim 1, characterized in that The thin film (19) is doped with a dipole effect element.

11. Device according to claim 10, characterized in that The dipole effect element is fluorine.

12. A method for manufacturing a device according to claim 10, characterized in that The dipole effect element is added by plasma immersion ion implantation.

13. A method for manufacturing a device according to claim 1, characterized in that The ion implantation is performed by plasma immersion ion implantation.

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