Display device

Abstract

A display device is provided. In order to realize a display device with improved reliability, the present application provides a display device equipped with: a substrate including a first region and a second region equipped with a transmission portion; a main pixel located on the first region and including a first pixel electrode, a first counter electrode, and a first intermediate layer arranged between the first pixel electrode and the first counter electrode; an auxiliary pixel located on the second region and including a second pixel electrode, a second counter electrode, and a second intermediate layer arranged between the second pixel electrode and the second counter electrode; and a metal pattern layer arranged on the second region in a manner surrounding the transmission portion.

Description

Technical Field

[0001] This invention relates to display devices, and more specifically, to display devices that improve the reliability of products. Background Technology

[0002] Recently, the applications of display devices have become increasingly diversified. Furthermore, due to the thinner and lighter nature of display devices, their range of applications is gradually expanding.

[0003] As display devices are used in a variety of ways, their forms can be designed in many ways, and the functions that can be combined with or associated with display devices are increasing. Summary of the Invention

[0004] As a method to increase the functionality that can be combined with or associated with a display device, embodiments of the present invention can provide a display device having an area inside the display area where sensors, etc., can be arranged. However, this technical problem is merely exemplary, and the scope of the present invention is not limited thereto.

[0005] According to one aspect of the present invention, a display device is provided, comprising: a substrate including a first region and a second region having a transmissive portion; a main pixel located on the first region and including a first pixel electrode, a first opposing electrode, and a first intermediate layer disposed between the first pixel electrode and the first opposing electrode; an auxiliary pixel located on the second region and including a second pixel electrode, a second opposing electrode, and a second intermediate layer disposed between the second pixel electrode and the second opposing electrode; and a metal pattern layer disposed on the second region to surround the transmissive portion.

[0006] In this embodiment, it may further include: a first conductive layer disposed on the substrate; an interlayer insulating layer disposed on the first conductive layer; and a second conductive layer disposed on the interlayer insulating layer.

[0007] In this embodiment, the metal pattern layer can be integrally formed with the second conductive layer.

[0008] In this embodiment, the metal pattern layer may at least partially overlap the second pixel electrode.

[0009] In this embodiment, the second conductive layer may be a driving voltage line.

[0010] In this embodiment, the metal pattern layer can be integrally formed with the first conductive layer.

[0011] In this embodiment, the metal pattern layer may at least partially overlap the second pixel electrode.

[0012] In this embodiment, the metal pattern layer and the first conductive layer can be arranged on the same layer, spaced apart from each other.

[0013] In this embodiment, the metal pattern layer can be electrically connected to the second conductive layer through a first contact hole defined in the interlayer insulating layer.

[0014] In this embodiment, the metal pattern layer can be integrally formed with the second pixel electrode.

[0015] In this embodiment, the metal pattern layer may at least partially overlap the first conductive layer and the second conductive layer.

[0016] In this embodiment, it may further include: a third pixel electrode of another main pixel, located on the first region and arranged apart from the first pixel electrode; and a fourth pixel electrode of another auxiliary pixel, located on the second region and arranged apart from the second pixel electrode.

[0017] In this embodiment, the first distance, defined as the shortest distance from the first pixel electrode to the third pixel electrode, can be greater than the second distance, defined as the shortest distance from the second pixel electrode to the fourth pixel electrode.

[0018] In this embodiment, the transparent portion can be circular or elliptical in shape.

[0019] According to another aspect of the present invention, a display device is provided, comprising: a substrate including a first region and a second region provided with a transmissive portion; a first main pixel located on the first region and including a first pixel electrode, a first opposing electrode, and a first intermediate layer disposed between the first pixel electrode and the first opposing electrode; a first auxiliary pixel located on the second region and including a second pixel electrode, a second opposing electrode, and a second intermediate layer disposed between the second pixel electrode and the second opposing electrode; a metal pattern layer disposed on the second region in a manner surrounding the transmissive portion; and an element disposed below the substrate in a manner corresponding to the second region, and including an electronic element that emits or receives light.

[0020] In this embodiment, it may further include: a first conductive layer disposed on the substrate; an interlayer insulating layer disposed on the first conductive layer; and a second conductive layer disposed on the interlayer insulating layer.

[0021] In this embodiment, the metal pattern layer may at least partially overlap the second pixel electrode.

[0022] In this embodiment, the metal pattern layer can be integrally formed with the second conductive layer.

[0023] In this embodiment, the metal pattern layer can be integrally formed with the first conductive layer.

[0024] In this embodiment, the metal pattern layer can be integrally formed with the second pixel electrode.

[0025] Other aspects, features, and advantages not described above will become apparent from the specific details for carrying out the invention, the scope of the claims, and the accompanying drawings.

[0026] According to an embodiment of the present invention configured as described above, a display device can be realized that expands the display area in a manner that allows images to be displayed even in areas where elements are arranged. The scope of the present invention is not necessarily limited by these effects. Attached Figure Description

[0027] Figure 1 This is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0028] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment of the present invention.

[0029] Figure 3 This is a schematic plan view of a display device according to an embodiment of the present invention.

[0030] Figure 4 and Figure 5 This is an equivalent circuit diagram showing pixels that may be included in a display device according to an embodiment of the present invention.

[0031] Figure 6 It is Figure 3 An enlarged view of part A.

[0032] Figures 7a to 7d This is a schematic cross-sectional view of a display device according to an embodiment of the present invention.

[0033] Figure 8a and Figure 8b This is a schematic cross-sectional view of a display device according to an embodiment of the present invention.

[0034] Figure 9 It is Figure 3 An enlarged view of part A.

[0035] Figures 10a to 10d This is a schematic cross-sectional view of a display device according to an embodiment of the present invention.

[0036] Symbol Explanation

[0037] DA: Display area 1A: First area

[0038] 2A: Second Area TA: Through Section

[0039] 1: Display device 10: Display panel

[0040] 20: Component 100: Substrate

[0041] 108: First conductive layer; 109: Second conductive layer

[0042] 111: Metal Pattern Layer; 200: Display Element Layer

[0043] 210a, 210b, 210c, 210d: First pixel electrode to fourth pixel electrode Detailed Implementation

[0044] This invention can be modified in various ways and has many embodiments, but specific embodiments are shown in the accompanying drawings and described in detail in the description. The effects and features of the invention, as well as the methods of achieving them, will be explained by referring to the accompanying drawings. Figure 1 As will become clear from the detailed embodiments described below. However, the invention is not limited to the embodiments disclosed below, but can be implemented in many different forms.

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing the invention with reference to the accompanying drawings, the same or corresponding constituent elements will be given the same reference numerals and repeated descriptions thereof will be omitted.

[0046] In the following embodiments, terms such as "first" and "second" are not used in a limiting sense, but are used for the purpose of distinguishing one constituent element from other constituent elements.

[0047] Furthermore, singular expressions include plural expressions unless the context explicitly indicates otherwise.

[0048] Furthermore, the use of terms such as "include" or "have" to indicate the presence of features or constituent elements described in the specification does not preclude the possibility of adding more than one other feature or constituent element.

[0049] In the following embodiments, when referring to a portion of a membrane, region, constituent element, etc., as being located "on" or "above" another portion, it includes not only the case where it is "immediately above" or "immediately above" the other portion, but also the case where other membranes, regions, constituent elements, etc., exist in between.

[0050] For ease of explanation, the sizes of the constituent elements in the accompanying drawings may be exaggerated or reduced. For example, for ease of explanation, the sizes and thicknesses of the various components shown in the drawings are arbitrarily depicted, and therefore the invention is not necessarily limited to the content shown in the drawings.

[0051] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system; they can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can intersect each other perpendicularly, but they can also refer to different directions that do not intersect perpendicularly.

[0052] In cases where a particular embodiment can be implemented in different ways, a specific sequence of operations may be performed in a different order than that described. For example, two operations described consecutively may be performed substantially simultaneously, or they may be performed in the reverse order of the description.

[0053] Figure 1 This is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0054] Reference Figure 1 The display device 1 includes a display area DA for displaying an image and a non-display area NDA for not displaying an image. The display area DA includes a first area 1A and a second area 2A, which is equipped with a transmission portion TA. The display device 1 can provide a main image using light emitted from a plurality of main pixels Pm arranged in the first area 1A, and provide an auxiliary image using light emitted from a plurality of auxiliary pixels Pa arranged in the second area 2A.

[0055] As will refer to Figure 2 As will be described later, the second region 2A may be a region in which elements including optical elements are arranged at its lower part. The second region 2A may include a transmissive portion TA through which light and / or sound can be transmitted from the elements to the outside or from the outside to the elements. As an embodiment of the present invention, when ultraviolet light passes through the second region 2A, the light transmittance may be approximately 30% or more, more preferably 50% or more, 75% or more, 80% or more, 85% or more, or 90% or more.

[0056] In this embodiment, a plurality of auxiliary pixels Pa can be arranged in the second region 2A, and a predetermined image can be provided using light emitted from the plurality of auxiliary pixels Pa. The image provided by the second region 2A is an auxiliary image, and its resolution may be lower than that of the image provided by the first region 1A. That is, the second region 2A has a transmissive portion TA through which light and / or sound can pass, therefore, the number of auxiliary pixels Pa that can be arranged per unit area of ​​the second region 2A may be less than the number of main pixels Pm arranged per unit area of ​​the first region 1A.

[0057] Although the organic light-emitting display device is described below as a display device 1 according to an embodiment of the present invention, the display device of the present invention is not limited thereto. As an embodiment, display devices of various types, such as inorganic light-emitting displays and quantum dot light-emitting displays, can be used.

[0058] Although Figure 1 The illustration shows a second region 2A positioned above a quadrilateral display area DA, but the invention is not limited thereto. The shape of the display area DA can be a polygon, such as a circle, an ellipse, or a triangle, and the position and number of the second regions 2A can also be varied.

[0059] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment of the present invention.

[0060] Reference Figure 2 The display device 1 may include: a display panel 10, including display elements; and an element 20, located at the lower part of the display panel 10 and arranged corresponding to the second region 2A.

[0061] The display panel 10 may include a substrate 100, a display element layer 200 disposed on the substrate 100, and a thin film encapsulation layer 300 serving as a sealing member for sealing the display element layer 200. Furthermore, the display panel 10 may also include a lower protective film 175 disposed on the lower portion of the substrate 100.

[0062] The substrate 100 may comprise glass or a polymer resin, which may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc. The substrate 100 comprising the polymer resin may possess flexible, rollable, or bendable properties. The substrate 100 may be a multilayer structure comprising a layer containing the aforementioned polymer resin and an inorganic layer (not shown).

[0063] The display element layer 200 includes a circuit layer comprising thin-film transistors (TFTs) and TFT', organic light-emitting diodes (OLEDs) and OLED' as display elements, and an insulating layer IL between them. A main pixel Pm comprising a main thin-film transistor (TFT) and a main organic light-emitting diode (OLED) connected thereto can be arranged in a first region 1A, and an auxiliary pixel Pa comprising an auxiliary thin-film transistor (TFT) and an auxiliary organic light-emitting diode (OLED) connected thereto can be arranged in a second region 2A.

[0064] Furthermore, a transparent portion TA may be arranged in the second region 2A, regardless of whether an auxiliary thin-film transistor (TFT) or display element is arranged. The transparent portion TA can be understood as a region that allows light / signals emitted from element 20 or incident on element 20 to be transmitted.

[0065] Component 20 may be located in the second region 2A. Component 20 may be an electronic element that utilizes light or sound. For example, component 20 may be a sensor that receives light, such as an optical element or an infrared sensor; a sensor that outputs light or sound and senses to determine distance or identify fingerprints; a small lamp that outputs light; or a speaker that outputs sound.

[0066] The thin-film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Relatedly, Figure 2 The diagram shows a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between them.

[0067] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulators such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include polymer materials. Polymer materials may include acrylic resins, epoxy resins, polyimides, and polyethylene, etc.

[0068] The lower protective film 175 can be attached to the lower part of the substrate 100 to support and protect the substrate 100. The lower protective film 175 may be equipped with an opening 175OP corresponding to the second region 2A. By providing the opening 175OP in the lower protective film 175, the light transmittance of the second region 2A can be improved. The lower protective film 175 may be made of polyethylene terephthalate or polyimide.

[0069] The area of ​​the second region 2A can be configured to be larger than the area where the element 20 is arranged. Accordingly, the area of ​​the opening 175OP provided in the lower protective film 175 may not be the same as the area of ​​the second region 2A. For example, the area of ​​the opening 175OP may be configured to be smaller than the area of ​​the second region 2A.

[0070] Furthermore, multiple elements 20 can be arranged in the second region 2A. The multiple elements 20 can have different functions.

[0071] Although not shown, the display panel 10 may also include components such as an input sensing component for sensing touch input, an anti-reflective component including a polarizer and a retarder or a filter and a black matrix, and a transparent window.

[0072] Furthermore, although this embodiment shows a case where the thin-film encapsulation layer 300 is used as an encapsulation component for sealing the display element layer 200, the present invention is not limited thereto. For example, as a component for sealing the display element layer 200, a sealing substrate bonded to the substrate 100 by a sealant or glass frit can be used.

[0073] Figure 3 This is a schematic plan view of a display device according to an embodiment of the present invention.

[0074] Reference Figure 3 Various components constituting the display device 1 are arranged on a substrate 100. The substrate 100 includes a display area DA and a non-display area NDA surrounding the display area DA. The display area DA includes a first area 1A and a second area 2A. The display area DA is referenced in advance. Figure 2 The encapsulated components are covered to protect them from external air or moisture.

[0075] The display device 1 includes a plurality of main pixels Pm arranged in a first region 1A. Each main pixel Pm may include a display element such as an organic light-emitting diode (OLED). Each main pixel Pm can emit light, for example, red, green, blue, or white, through the organic light-emitting diode. As previously described, the main pixel Pm in this specification can be understood as a pixel that emits light of one of the colors red, green, blue, or white.

[0076] The second region 2A can be arranged on one side of the first region 1A, and a plurality of auxiliary pixels Pa are arranged in the second region 2A. The auxiliary pixels Pa may include display elements such as organic light-emitting diodes (OLEDs). Each auxiliary pixel Pa can emit light, for example, red, green, blue, or white light through an organic light-emitting diode. As mentioned above, the auxiliary pixel Pa in this specification can be understood as a pixel that emits light of one color among red, green, blue, and white. Furthermore, the second region 2A may be equipped with a transmissive portion TA arranged between the auxiliary pixels Pa. At least one element 20 may be arranged in the portion of the display device 1 corresponding to the lower part of the second region 2A. Figure 2 ).

[0077] In one embodiment, a main pixel Pm and an auxiliary pixel Pa may include the same pixel circuitry. However, the invention is not limited thereto. The pixel circuitry included in the main pixel Pm and the pixel circuitry included in the auxiliary pixel Pa may also be different from each other.

[0078] The second region 2A is equipped with a transparent section TA, and the resolution of the second region 2A may be less than the resolution of the first region 1A. For example, the resolution of the second region 2A may be approximately half the resolution of the first region 1A. In some embodiments, the resolution of the first region 1A may be 400 ppi or more, and the resolution of the second region 2A may be approximately 200 ppi.

[0079] Each pixel Pm and Pa can be electrically connected to the outline circuit arranged in the non-display area NDA. The non-display area NDA can be equipped with a first scan driving circuit 110, a first light-emitting driving circuit 115, a second scan driving circuit 120, a terminal 140, a data driving circuit 150, a first power supply wiring 160, and a second power supply wiring 170.

[0080] The first scan driving circuit 110 can provide scan signals to each pixel Pm and Pa via scan line SL. The first light-emitting driving circuit 115 can provide light-emitting control signals to each pixel via light-emitting control line EL. The second scan driving circuit 120 and the first scan driving circuit 110 can be arranged parallel to each other with the display area DA placed between them. A portion of the pixels Pm and Pa arranged in the display area DA can be electrically connected to the first scan driving circuit 110, and the others can be connected to the second scan driving circuit 120. As an embodiment, the second light-emitting driving circuit (not shown) and the first light-emitting driving circuit 115 can be arranged parallel to each other with the display area DA placed between them.

[0081] The first light-emitting driving circuit 115 may be spaced apart from the first scanning driving circuit 110 in the x-direction and arranged on the non-display area NDA. As an embodiment, the first light-emitting driving circuit 115 may be arranged alternately with the first scanning driving circuit 110 in the y-direction.

[0082] Terminal 140 may be disposed on one side of substrate 100. Terminal 140 may be exposed and electrically connected to printed circuit board (PCB) without being covered by an insulating layer. Terminal PCB-P of printed circuit board (PCB) may be electrically connected to terminal 140 of display device 1. Printed circuit board (PCB) transmits signals or power from control unit (not shown) to display device 1. Control signals generated in control unit may be transmitted through printed circuit board (PCB) to first scan drive circuit 110, second scan drive circuit 120, and first light emission drive circuit 115, respectively. Control unit may provide first power and second power to first power supply wiring 160 and second power supply wiring 170, respectively, through first connection wiring 161 and second connection wiring 171. First power supply voltage ELVDD may be provided to each pixel Pm, Pa through drive voltage line PL connected to first power supply wiring 160, and second power supply voltage ELVSS (or common voltage) may be provided to the opposing electrodes of each pixel Pm, Pa connected to second power supply wiring 170.

[0083] The data driving circuit 150 is electrically connected to the data line DL. The data signal from the data driving circuit 150 can be provided to each pixel Pm and Pa through the connection wiring 151 connected to terminal 140 and the data line DL connected to the connection wiring 151. Although Figure 3 The illustration shows the data driver circuit 150 arranged on a printed circuit board (PCB), but as an embodiment, the data driver circuit 150 can be arranged on the substrate 100. For example, the data driver circuit 150 can be arranged between the terminal 140 and the first power supply wiring 160.

[0084] The first power supply cabling 160 may include a first auxiliary cabling 162 and a third auxiliary cabling 163 that place the display area DA in the center and extend parallel to each other in the x-direction. The second power supply cabling 170 may partially surround the display area DA in a ring shape with one side open.

[0085] Figure 4 and Figure 5 This is an equivalent circuit diagram showing pixels that may be included in a display device according to an embodiment of the present invention.

[0086] Reference Figure 4Each pixel Pm and Pa includes a pixel circuit PC connected to the scan line SL and the data line DL, and an organic light-emitting element OLED connected to the pixel circuit PC (for ease of explanation, the "organic light-emitting element" is referred to by the same reference numeral as the "main organic light-emitting diode" described later).

[0087] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and transmits the data signal Dm input through the data line DL to the driving thin-film transistor T1 according to the scan signal Sn input through the scan line SL.

[0088] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and stores a voltage equivalent to the difference between the voltage received from the switching thin-film transistor T2 and the first power supply voltage ELVDD (or drive voltage) supplied to the drive voltage line PL.

[0089] The driving thin-film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst. The driving current flowing from the driving voltage line PL to the organic light-emitting element (OLED) can be controlled according to the voltage value stored in the storage capacitor Cst. The OLED can emit light with a predetermined brightness through the driving current.

[0090] Although Figure 4 The illustration describes a pixel circuit PC comprising two thin-film transistors and a storage capacitor, but the invention is not limited thereto. Figure 5 As shown, the pixel circuit PC can include seven thin-film transistors and a storage capacitor.

[0091] Reference Figure 5 Each pixel Pm and Pa includes a pixel circuit PC and an organic light-emitting element (OLED) connected to the pixel circuit PC. The pixel circuit PC may include multiple thin-film transistors and storage capacitors. The thin-film transistors and storage capacitors may be connected to signal lines SL, SL-1, EL, DL, initialization voltage line VL, and drive voltage line PL.

[0092] Although Figure 5 The diagram illustrates the connection of each pixel Pm, Pa to signal lines SL, SL-1, EL, DL, initialization voltage line VL, and drive voltage line PL, but the invention is not limited thereto. As one embodiment, at least one of signal lines SL, SL-1, EL, DL, initialization voltage line VL, and drive voltage line PL can be shared with adjacent pixels.

[0093] The multiple thin-film transistors may include: driving thin-film transistor (TFT) T1, switching thin-film transistor (TFT) T2, compensation thin-film transistor T3, first initialization thin-film transistor T4, operation control thin-film transistor T5, light emission control thin-film transistor T6, and second initialization thin-film transistor T7.

[0094] The signal lines include: a scan line SL, which transmits the scan signal Sn; a previous scan line SL-1, which transmits the previous scan signal Sn-1 to the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7; a light emission control line EL, which transmits the light emission control signal En to the operation control thin-film transistor T5 and the light emission control thin-film transistor T6; and a data line DL, which intersects with the scan line SL and transmits the data signal Dm. The drive voltage line PL transmits the drive voltage ELVDD to the drive thin-film transistor T1, and the initialization voltage line VL transmits the initialization voltage Vint to the initialization drive thin-film transistor T1 and the pixel electrode.

[0095] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the first storage plate Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin-film transistor T1 is connected to the lower driving voltage line PL through the operation control thin-film transistor T5. The driving drain electrode D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting element OLED through the light-emitting control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2 and supplies the driving current I to the organic light-emitting element OLED. OLED .

[0096] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL, the switching source electrode S2 of the switching thin-film transistor T2 is connected to the data line DL, and the switching drain electrode D2 of the switching thin-film transistor T2 is connected to the driving source electrode S1 of the driving thin-film transistor T1. Furthermore, it is connected to the lower driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 can be turned on according to the scan signal Sn received through the scan line SL, thereby performing a switching operation to transmit the data signal Dm transmitted to the data line DL to the driving source electrode S1 of the driving thin-film transistor T1.

[0097] The compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL, the compensation source electrode S3 of the compensation thin-film transistor T3 is connected to the driving drain electrode D1 of the driving thin-film transistor T1, and is connected to the pixel electrode of the organic light-emitting element OLED through the light-emitting control thin-film transistor T6. The compensation drain electrode D3 of the compensation thin-film transistor T3 is connected to the first storage plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on according to the scan signal Sn received through the scan line SL, thereby electrically connecting the driving gate electrode G1 and the driving drain electrode D1 of the driving thin-film transistor T1, thus connecting the driving thin-film transistor T1 in a diode manner.

[0098] The first initialization gate electrode G4 of the first initialization thin-film transistor T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization thin-film transistor T4 is connected to the second initialization drain electrode D7 and the initialization voltage line VL of the second initialization thin-film transistor T7. The first initialization drain electrode D4 of the first initialization thin-film transistor T4 is connected to the first storage plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin-film transistor T3, and the driving gate electrode G1 of the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1, thereby performing an initialization operation that transmits the initialization voltage Vint to the driving gate electrode G1 of the driving thin-film transistor T1 to initialize the voltage of the driving gate electrode G1 of the driving thin-film transistor T1.

[0099] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the light emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the lower driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0100] The light-emitting control gate electrode G6 of the light-emitting control thin-film transistor T6 is connected to the light-emitting control line EL. The light-emitting control source electrode S6 of the light-emitting control thin-film transistor T6 is connected to the driving drain electrode D1 of the driving thin-film transistor T1 and the compensation source electrode S3 of the compensation thin-film transistor T3. Furthermore, the light-emitting control drain electrode D6 of the light-emitting control thin-film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin-film transistor T7 and the pixel electrode of the organic light-emitting element OLED.

[0101] The operation control thin-film transistor T5 and the light emission control thin-film transistor T6 are simultaneously turned on according to the light emission control signal En received through the light emission control line EL, thereby transferring the driving voltage ELVDD to the organic light-emitting element OLED, so that the driving current I flows through the organic light-emitting element OLED. OLED .

[0102] The second initialization gate electrode G7 of the second initialization thin-film transistor T7 is connected to the previous scan line SL-1. The second initialization source electrode S7 of the second initialization thin-film transistor T7 is connected to the light-emitting control drain electrode D6 of the light-emitting control thin-film transistor T6 and the pixel electrode of the organic light-emitting element OLED. The second initialization drain electrode D7 of the second initialization thin-film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin-film transistor T4 and the initialization voltage line VL. The second initialization thin-film transistor T7 is turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1, thereby initializing the pixel electrode of the organic light-emitting element OLED.

[0103] Although Figure 5 The illustration shows a scenario where the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are connected to the previous scan line SL-1, but the invention is not limited thereto. As one embodiment, the first initialization thin-film transistor T4 can be connected to the previous scan line SL-1 and driven according to the previous scan signal Sn-1, and the second initialization thin-film transistor T7 can be connected to an additional signal line (e.g., a subsequent scan line) and driven according to the signal transmitted to said signal line.

[0104] The second storage plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the opposing electrode of the organic light-emitting element OLED is connected to the common voltage ELVSS. Accordingly, the organic light-emitting element OLED can receive a driving current I from the driving thin-film transistor T1. OLED It emits light, thereby displaying the image.

[0105] Although Figure 5 The example shown illustrates the case where the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 have dual gate electrodes, but the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 may have a single gate electrode.

[0106] In this embodiment, the main pixel Pm and the auxiliary pixel Pa can be equipped with the same pixel circuit PC. However, this is not a limitation. The main pixel Pm and the auxiliary pixel Pa can also be equipped with pixel circuit PCs of different structures. For example, the main pixel Pm can be implemented using... Figure 5 The pixel circuit and the auxiliary pixel Pa adopt Figure 4 Various transformations, such as pixel circuits.

[0107] Figure 6 It is shown in magnification Figure 3 The diagram for part A. (As will be described later.) Figures 7a to 7d As shown, although in Figure 6 The metal pattern layer 111 may be provided with an interlayer insulating layer 107, a planarization layer 113, a pixel defining film 180, a second opposing electrode 230b, etc., but these have been omitted for ease of explanation.

[0108] Reference Figure 6 According to an embodiment of the present invention, a display device 1 includes: a substrate 100, comprising a first region 1A and a second region 2A having a transmissive portion TA; a main pixel Pm, located on the first region 1A, and including a first pixel electrode 210a, a first opposing electrode 230a, and a first intermediate layer 220a disposed between the first pixel electrode 210a and the first opposing electrode 230a; an auxiliary pixel Pa, located on the second region 2A, and including a second pixel electrode 210b, a second opposing electrode 230b, and a second intermediate layer 220b disposed between the second pixel electrode 210b and the second opposing electrode 230b; and a metal pattern layer 111 disposed on the second region 2A to surround the transmissive portion TA. A third pixel electrode 210c may be disposed on the first region 1A at a distance from the first pixel electrode 210a, and a fourth pixel electrode 210d may be disposed on the second region 2A at a distance from the second pixel electrode 210b.

[0109] Pixel group Pg can be arranged in the first region 1A and the second region 2A. Pixel group Pg can include at least one pixel Pm and at least one pixel Pa. Figure 6 The diagram illustrates a pixel group Pg comprising three pixels Pm and Pa arranged in a single column. However, the invention is not limited to this. The number and arrangement of pixels Pm and Pa in a pixel group Pg can be varied. For example, a pixel group Pg may include four pixels Pm and Pa arranged in two columns or eight pixels Pm and Pa arranged in four columns. In this specification, pixels Pm and Pa may represent pixels emitting red, green, or blue light.

[0110] The transparent portion TA is a region with high light transmittance that does not have any display elements arranged therein, and multiple transparent portions TA can be arranged in the second region 2A. The transparent portions TA can be arranged to surround the pixel group Pg. Alternatively, the transparent portions TA can be arranged alternately with the pixel group Pg along the x-direction and / or y-direction. The transparent portion TA is a region where the metal pattern layer 111 is not arranged, and can represent the region in the second region 2A corresponding to the opening of the metal pattern layer 111. As an embodiment, the transparent portion TA can be circular or elliptical in shape.

[0111] The size of the light-emitting portion TA can be configured to be larger than the light-emitting area of ​​at least one pixel Pm, Pa. In some embodiments, the size of the light-emitting portion TA can be configured to be greater than or equal to the size of a pixel group Pg. In this embodiment, multiple light-emitting portions TA can be configured, and in this case, the light-emitting portions TA can be configured with different sizes.

[0112] Figures 7a to 7d This is a schematic cross-sectional view of a display device according to an embodiment of the present invention.

[0113] The following is for reference Figures 7a to 7d Observe the stacked structure of a display device according to an embodiment of the present invention. Figures 7a to 7d For along Figure 6 A schematic cross-sectional view taken from lines II-II' and III-III' shows partial cross-sections of the first region 1A and the second region 2A.

[0114] Reference Figure 7a A display device according to an embodiment of the present invention includes a first region 1A and a second region 2A. A main pixel Pm is arranged in the first region 1A, and an auxiliary pixel Pa and a transmissive portion TA are arranged in the second region 2A.

[0115] The main pixel Pm may include a main thin-film transistor (TFT), a main storage capacitor (Cst), and a main organic light-emitting diode (OLED). The auxiliary pixel Pa may include an auxiliary thin-film transistor (TFT'), an auxiliary storage capacitor (Cst'), and an auxiliary organic light-emitting diode (OLED').

[0116] Hereinafter, a display device according to an embodiment of the present invention will be described, comprising a structure in which the components are stacked.

[0117] The substrate 100 may comprise glass or a polymer resin, which may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc. The substrate 100 comprising the polymer resin may possess flexible, rollable, or bendable properties. The substrate 100 may be a multilayer structure comprising the aforementioned polymer resin layer and an inorganic layer (not shown).

[0118] A buffer layer 101 is located on the substrate 100, thereby reducing or blocking the penetration of foreign matter, moisture, or external air from the lower part of the substrate 100, and providing a flat surface on the substrate 100. The buffer layer 101 may include inorganic, organic, or inorganic-inorganic composites such as oxides or nitrides, and may be composed of a single-layer or multi-layer structure of inorganic and organic materials. A barrier layer (not shown) may also be included between the substrate 100 and the buffer layer 101 to block the penetration of external air.

[0119] A main thin-film transistor (TFT) and an auxiliary thin-film transistor (TFT') can be disposed on the upper part of the buffer layer 101. The main TFT includes a first semiconductor layer 134a, a first gate electrode 136a, a first source electrode 137a, and a first drain electrode 138a. The auxiliary TFT' includes a second semiconductor layer 134b, a second gate electrode 136b, a second source electrode 137b, and a second drain electrode 138b. The main TFT is connected to the main organic light-emitting diode (OLED) in the first region 1A, thereby driving the OLED. The auxiliary TFT is connected to the auxiliary organic light-emitting diode (OLED') in the second region 2A, thereby driving the OLED.

[0120] The first semiconductor layer 134a and the second semiconductor layer 134b are disposed on the buffer layer 101, and may include a first channel region 131a and a second channel region 131b overlapping the first gate electrode 136a and the second gate electrode 136b respectively, a first source region 132a and a second source region 132b disposed on both sides of the first channel region 131a and the second channel region 131b and containing impurities with a higher concentration than those in the first channel region 131a and the second channel region 131b, and a first drain region 133a and a second drain region 133b. Here, the impurities may include N-type impurities or P-type impurities. The first source region 132a and the second source region 132b, and the first drain region 133a and the second drain region 133b may be electrically connected to the first source electrode 137a, the second source electrode 137b, the first drain electrode 138a, and the second drain electrode 138b of the main thin-film transistor TFT and the auxiliary thin-film transistor TFT', respectively.

[0121] The first semiconductor layer 134a and the second semiconductor layer 134b may comprise oxide semiconductors and / or silicon semiconductors. When the first semiconductor layer 134a and the second semiconductor layer 134b are formed using oxide semiconductors, they may, for example, comprise oxides selected from one or more substances included in the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the first semiconductor layer 134a and the second semiconductor layer 134b may be ITZO (InSnZnO), IGZO (InGaZnO), etc. When the first semiconductor layer 134a and the second semiconductor layer 134b are formed using silicon semiconductors, they may, for example, comprise amorphous silicon (a-Si) or low-temperature polycrystalline silicon (LTPS) formed by crystallizing amorphous silicon (a-Si).

[0122] The first gate electrode 136a and the second gate electrode 136b can be constructed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The first gate electrode 136a and the second gate electrode 136b can be connected to a gate line that applies an electrical signal to the first gate electrode 136a and the second gate electrode 136b.

[0123] A first gate insulating layer 103 may be disposed between the first semiconductor layer 134a and the first gate electrode 136a, and between the second semiconductor layer 134b and the second gate electrode 136b. The first gate insulating layer 103 may include materials selected from silicon oxide (SiO2) and silicon nitride (SiN). x The first gate insulating layer 103 may be a single layer or multiple layers comprising the aforementioned inorganic insulating materials, including silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0124] The second gate insulating layer 105 may be configured to cover the first gate electrode 136a and the second gate electrode 136b. The second gate insulating layer 105 may be selected from silicon oxide (SiO2) and silicon nitride (SiN). xThe second gate insulating layer 105 may be a single layer or multiple layers comprising the aforementioned inorganic insulating materials, including silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0125] A main storage capacitor Cst and an auxiliary storage capacitor Cst' can be disposed on the second gate insulating layer 105. The main storage capacitor Cst may include a first lower electrode 144a and a first upper electrode 146a. The main storage capacitor Cst overlaps with the main thin-film transistor TFT, and the first lower electrode 144a of the main storage capacitor Cst may be integrally disposed with the first gate electrode 136a of the main thin-film transistor TFT. As an embodiment, the main storage capacitor Cst may not overlap with the main thin-film transistor TFT, and the first lower electrode 144a may be an independent component separate from the first gate electrode 136a of the main thin-film transistor TFT. The auxiliary storage capacitor Cst' may include a second lower electrode 144b and a second upper electrode 146b. The auxiliary storage capacitor Cst' overlaps with the auxiliary thin-film transistor TFT', and the second lower electrode 144b of the auxiliary storage capacitor Cst' may be integrally disposed with the second gate electrode 136b of the auxiliary thin-film transistor TFT'. As one embodiment, the auxiliary storage capacitor Cst' may not overlap with the auxiliary thin-film transistor TFT', and the second lower electrode 144b may be an independent component separate from the second gate electrode 136b of the auxiliary thin-film transistor TFT'.

[0126] The first upper electrode 146a and the second upper electrode 146b may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may be a single layer or multiple layers of the aforementioned materials.

[0127] The interlayer insulating layer 107 can be formed to cover the first upper electrode 146a and the second upper electrode 146b. The interlayer insulating layer 107 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2), etc.

[0128] The first source electrode 137a, the second source electrode 137b, and the first drain electrode 138a and the second drain electrode 138b can be disposed on the interlayer insulating layer 107. The first source electrode 137a, the second source electrode 137b, and the first drain electrode 138a and the second drain electrode 138b can include conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can be formed as a multilayer or a single layer comprising said materials. As an example, the first source electrode 137a, the second source electrode 137b, and the first drain electrode 138a and the second drain electrode 138b can be configured as a Ti / Al / Ti multilayer structure.

[0129] The planarization layer 113 can be arranged to cover the first source electrode 137a, the second source electrode 137b, and the first drain electrode 138a and the second drain electrode 138b. The planarization layer 113 can have a flat top surface to enable the pixel electrodes disposed on it to be formed flatly.

[0130] The planarization layer 113 can be formed as a single layer or multiple layers of film composed of organic or inorganic substances. This planarization layer 113 may include general polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives with phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and mixtures thereof. Furthermore, the planarization layer 113 may include silicon oxide (SiO2), silicon nitride (SiN), etc. x Materials used include silicon nitride oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). After forming the planarization layer 113, chemical mechanical polishing can be performed to provide a flat upper surface.

[0131] The planarization layer 113 has an opening that exposes one of the first source electrode 137a and the first drain electrode 138a of the main thin film transistor TFT. The first pixel electrode 210a can be connected to the first source electrode 137a or the first drain electrode 138a through the opening, thereby being electrically connected to the main thin film transistor TFT.

[0132] Furthermore, the planarization layer 113 includes an opening that exposes one of the second source electrode 137b and the second drain electrode 138b of the auxiliary thin film transistor TFT'. The second pixel electrode 210b can be electrically connected to the auxiliary thin film transistor TFT' by connecting to the second source electrode 137b or the second drain electrode 138b through the opening.

[0133] In the first region 1A of the substrate 100, a main organic light-emitting diode (OLED) can be disposed on the planarization layer 113, which includes: a first pixel electrode 210a; a first intermediate layer 220a; and a first opposing electrode 230a, with the first intermediate layer 220a placed in the middle and disposed opposite to the first pixel electrode 210a.

[0134] In the second region 2A of the substrate 100, an auxiliary organic light-emitting diode (OLED) can be disposed on the planarization layer 113, which includes: a second pixel electrode 210b; a second intermediate layer 220b; and a second opposing electrode 230b, with the second intermediate layer 220b placed in the middle and disposed opposite to the second pixel electrode 210b.

[0135] A first pixel electrode 210a and a second pixel electrode 210b may be disposed on the planarization layer 113. The first pixel electrode 210a and the second pixel electrode 210b may be (semi-)transparent electrodes or reflective electrodes. The first pixel electrode 210a and the second pixel electrode 210b may be equipped with a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and their compounds, and a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer may be equipped with one or more electrodes selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). The first pixel electrode 210a and the second pixel electrode 210b may be configured using an ITO / Ag / ITO stacked structure.

[0136] A pixel defining film 180 may be disposed on the planarization layer 113. The pixel defining film 180 may have an opening exposing at least a portion of the first pixel electrode 210a and an opening exposing at least a portion of the second pixel electrode 210b. By increasing the distance between the edge of the first pixel electrode 210a and the first opposing electrode 230a above the first pixel electrode 210a, the pixel defining film 180 can prevent arcing at the edge of the first pixel electrode 210a, and by increasing the distance between the edge of the second pixel electrode 210b and the second opposing electrode 230b above the second pixel electrode 210b, it can prevent arcing at the edge of the second pixel electrode 210b. The pixel defining film 180 may be formed, for example, using organic insulating materials such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin by spin coating or other methods.

[0137] A first intermediate layer 220a may be disposed on a first pixel electrode 210a that exposes at least a portion of itself through the pixel defining film 180, and a second intermediate layer 220b may be disposed on a second pixel electrode 210b. The first intermediate layer 220a and the second intermediate layer 220b may include light-emitting layers, and may optionally include functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) below or above the light-emitting layers.

[0138] The light-emitting layer may include an organic material containing a fluorescent or phosphorescent substance that emits red, green, blue, or white light. The light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material. For example, the light-emitting layers of the first intermediate layer 220a and the second intermediate layer 220b may contain a substance that emits green light.

[0139] When the luminescent layer comprises low-molecular-weight materials, the first intermediate layer 220a and the second intermediate layer 220b can have structures stacked in single or composite forms, such as a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, they can include various organic materials, such as copper phthalocyanine (CuPc), N,N'-di(napthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris-8-hydroxyquinoline aluminum (Alq3). These layers can be formed using vacuum deposition.

[0140] When the light-emitting layer comprises a polymer, the first intermediate layer 220a and the second intermediate layer 220b can generally have a structure including a hole transport layer (HTL) and a light-emitting layer (EML). In this case, the hole transport layer may include PEDOT, and the light-emitting layer may include polymers such as poly-phenylene vinylene (PPV) and polyfluorene. This light-emitting layer can be formed by screen printing, inkjet printing, laser-induced thermal imaging (LITI), etc.

[0141] A first opposing electrode 230a may be disposed on the first intermediate layer 220a. The first opposing electrode 230a may be disposed on the first intermediate layer 220a and may be arranged to cover the entire first intermediate layer 220a. The first opposing electrode 230a is disposed on the upper part of the first region 1A and may be arranged to cover the entire first region 1A. That is, the first opposing electrode 230a may be formed as a single unit to cover multiple main pixels Pm disposed in the first region 1A.

[0142] A second opposing electrode 230b may be disposed on the second intermediate layer 220b. The second opposing electrode 230b may be disposed on the second intermediate layer 220b and may be arranged to cover the entire second intermediate layer 220b. The second opposing electrode 230b is disposed on the upper part of the second region 2A and may be arranged to cover the entire second region 2A. That is, the second opposing electrode 230b may be formed integrally to cover multiple auxiliary pixels Pa disposed in the second region 2A, and may also be disposed on the transmissive portion TA provided in the second region 2A.

[0143] As one embodiment, the first opposing electrode 230a and the second opposing electrode 230b can be formed as a single unit. For example, the first opposing electrode 230a disposed on the first region 1A can extend toward the second region 2A and also be disposed on the second region 2A.

[0144] The first counter electrode 230a and the second counter electrode 230b may include a conductive material with a low work function. For example, the first counter electrode 230a and the second counter electrode 230b may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the first counter electrode 230a and the second counter electrode 230b may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer comprising the aforementioned material.

[0145] A first conductive layer 108 may be disposed on the second gate insulating layer 105 in the second region 2A, and a second conductive layer 109 may be disposed on the interlayer insulating layer 107. The first conductive layer 108 and the second conductive layer 109 may be at least one of the aforementioned scan lines, light emission control lines, data lines, and drive voltage lines. The first conductive layer 108 and the second conductive layer 109 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0146] A metal pattern layer 111 may be disposed on the interlayer insulating layer 107 in the second region 2A. The metal pattern layer 111 and the second conductive layer 109 may be formed in the same layer from the same material. As an embodiment, the metal pattern layer 111 may be integrally formed with the second conductive layer 109. For example, the metal pattern layer 111 may be a portion of the second conductive layer 109 extending toward the transmissive portion TA.

[0147] The metal pattern layer 111 can be arranged to surround the transmissive portion TA provided in the second region 2A, thereby improving or preventing diffraction when light generated by the element 20 arranged in the lower part of the second region 2A passes through the transmissive portion TA.

[0148] Figure 7b The embodiments are similar in that the metal pattern layer 111 and the first conductive layer 108 are integrally formed. Figure 7a The embodiments differ. Figure 7b In its composition, the term "targeting" is omitted. Figure 7a The following explanation focuses on the differences between the similar compositions.

[0149] Reference Figure 7b A first conductive layer 108 may be disposed on the second gate insulating layer 105 in the second region 2A, and a second conductive layer 109 may be disposed on the interlayer insulating layer 107. The first conductive layer 108 and the second conductive layer 109 may be at least one of the aforementioned scan lines, light emission control lines, data lines, and driving voltage lines. The first conductive layer 108 and the second conductive layer 109 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0150] A metal pattern layer 111 may be disposed on the second gate insulating layer 105 in the second region 2A. The metal pattern layer 111 and the first conductive layer 108 may be formed in the same layer from the same material. As an embodiment, the metal pattern layer 111 may be integrally formed with the first conductive layer 108. For example, the metal pattern layer 111 may be a portion of the first conductive layer 108 extending toward the transmissive portion TA.

[0151] The metal pattern layer 111 can be arranged to surround the transmissive portion TA provided in the second region 2A, thereby improving or preventing diffraction when light generated by the element 20 arranged in the lower part of the second region 2A passes through the transmissive portion TA.

[0152] Figure 7c The embodiment is similar in that the metal pattern layer 111 is arranged spaced apart from the first conductive layer 108 and electrically connected to the second conductive layer 109 through the first contact hole CNT1. Figure 7a The embodiments differ. Figure 7c In its composition, the term "targeting" is omitted. Figure 7a The following explanation focuses on the differences between the similar compositions.

[0153] Reference Figure 7cA first conductive layer 108 may be disposed on the second gate insulating layer 105 in the second region 2A, and a second conductive layer 109 may be disposed on the interlayer insulating layer 107. The first conductive layer 108 and the second conductive layer 109 may be at least one of the aforementioned scan lines, light emission control lines, data lines, and driving voltage lines. The first conductive layer 108 and the second conductive layer 109 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0154] A metal pattern layer 111 may be disposed on the second gate insulating layer 105 of the second region 2A. The metal pattern layer 111 and the first conductive layer 108 may be formed in the same layer from the same material. The metal pattern layer 111 and the first conductive layer 108 may be disposed spaced apart from each other. The metal pattern layer 111 may be arranged to surround the transmittance TA provided in the second region 2A, thereby improving or preventing diffraction of light generated by the element 20 disposed in the lower part of the second region 2A when it passes through the transmittance TA.

[0155] As one embodiment, the metal pattern layer 111 can be electrically connected to the second conductive layer 109 via a first contact hole CNT1 defined in the interlayer insulating layer 107. By electrically connecting the metal pattern layer 111 to the second conductive layer 109 via the first contact hole CNT1 defined in the interlayer insulating layer 107, floating of the metal pattern layer 111 can be prevented, and coupling between the metal pattern layer 111 and surrounding wiring can be prevented.

[0156] Figure 7d The embodiment is similar to the one in which the metal pattern layer 111 and the second pixel electrode 210b are integrally formed. Figure 7a The embodiments differ. Figure 7d In its composition, the term "targeting" is omitted. Figure 7a The following explanation focuses on the differences between the similar compositions.

[0157] Reference Figure 7dA first conductive layer 108 may be disposed on the second gate insulating layer 105 in the second region 2A, a second conductive layer 109 may be disposed on the interlayer insulating layer 107, a planarization layer 113 may be disposed on the second conductive layer 109, and a second pixel electrode 210b may be disposed on the planarization layer 113. The first conductive layer 108 and the second conductive layer 109 may be at least one of the aforementioned scan lines, light emission control lines, data lines, and driving voltage lines. The first conductive layer 108 and the second conductive layer 109 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0158] A metal pattern layer 111 may be disposed on the planarization layer 113 in the second region 2A. The metal pattern layer 111 may at least partially overlap the first conductive layer 108 and the second conductive layer 109, and may be disposed on the planarization layer 113. The metal pattern layer 111 and the second pixel electrode 210b may be formed in the same layer from the same material. As an embodiment, the metal pattern layer 111 may be integrally formed with the second pixel electrode 210b. For example, the metal pattern layer 111 may be a portion of the second pixel electrode 210b extending toward the transmissive portion TA.

[0159] The metal pattern layer 111 can be arranged to surround the transmissive portion TA provided in the second region 2A, thereby improving or preventing diffraction when light generated by the element 20 arranged in the lower part of the second region 2A passes through the transmissive portion TA.

[0160] Figure 8a and Figure 8b This is a schematic cross-sectional view of a display device according to an embodiment of the present invention.

[0161] More specifically, Figure 8a The diagram illustrating the substrate 100 arranged on the second region 2A, excluding the first region 1A and the through portion TA, shows... Figure 7a An enlarged view of part B. Figure 8b The diagram used to illustrate the substrate 100 arranged corresponding to the through section TA is shown below. Figure 7a An enlarged view of part C.

[0162] Reference Figure 8a and Figure 8bThe substrate 100 disposed on the second region 2A, excluding the first region 1A and the transmission portion TA, may include: a first substrate 100a; a first barrier layer 100b disposed on the first substrate 100a; a second substrate 100c disposed on the first barrier layer 100b; and a second barrier layer 100d disposed on the second substrate 100c. The substrate 100 disposed corresponding to the transmission portion TA may include: a first substrate 100a; and a first barrier layer 100b disposed on the first substrate 100a. By omitting the second substrate 100c and the second barrier layer 100d disposed on the second substrate 100c from the substrate 100 disposed corresponding to the transmission portion TA, the transmittance of the transmission portion TA can be improved.

[0163] The first substrate 100a and the second substrate 100c may include polyimide. The first barrier layer 100b may be disposed between the first substrate 100a and the buffer layer 101 to block the permeation of external gas, and the second barrier layer 100d may be disposed between the second substrate 100c and the buffer layer 101 to block the permeation of external gas.

[0164] Figure 9 It is Figure 3 An enlarged view of part A.

[0165] Figure 9 The embodiment is similar to the one that arranges the pixel electrodes arranged on the second region 2A more widely. Figure 6 The embodiments differ. Figure 9 In its composition, the term "targeting" is omitted. Figure 6 The following explanation focuses on the differences between the similar compositions.

[0166] exist Figure 9 Metal pattern layer 111 can be like Figures 10a to 10d The diagram shows an interlayer insulating layer 107, a planarization layer 113, a pixel defining film 180, a second opposing electrode 230b, etc., but these have been omitted for ease of explanation.

[0167] The second pixel electrode 210b and the fourth pixel electrode 210d arranged on the second region 2A can be arranged to be wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A. More specifically, by arranging the second pixel electrode 210b and the fourth pixel electrode 210d on the second region 2A to be wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A, a first distance d1, defined as the shortest distance from the first pixel electrode 210a to the third pixel electrode 210c, can be greater than a second distance d2, defined as the shortest distance from the second pixel electrode 210b to the fourth pixel electrode 210d.

[0168] By arranging the second pixel electrode 210b and the fourth pixel electrode 210d arranged on the second region 2A wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A, light generated by the element 20 arranged in the lower part of the second region 2A can be prevented from passing between the auxiliary pixel Pa and the wiring.

[0169] Figures 10a to 10d This is a schematic cross-sectional view of a display device according to an embodiment of the present invention. Figures 10a to 10d For along Figure 9 A schematic cross-sectional view taken by lines IV-IV' and V-V' shows partial cross-sections of the first region 1A and the second region 2A.

[0170] Figure 10a The embodiment in which the second pixel electrode 210b and the fourth pixel electrode 210d arranged on the second region 2A are arranged wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A is similar to... Figure 7a The embodiments differ. Figure 10a In its composition, omission and Figure 7a With the same composition, the following explanation will focus on the differences.

[0171] Reference Figure 10a A third pixel electrode 210c may be arranged on the first region 1A, spaced apart from the first pixel electrode 210a, and a fourth pixel electrode 210d may be arranged on the second region 2A, spaced apart from the second pixel electrode 210b. A second intermediate layer 220b may be arranged on the second pixel electrode 210b, and a second opposing electrode 230b may be arranged on the second intermediate layer 220b. A fourth intermediate layer 220d may be arranged on the fourth pixel electrode 210d, and a second opposing electrode 230b may be arranged on the fourth intermediate layer 220d. As an embodiment, the first opposing electrode 230a and the second opposing electrode 230b may be formed integrally.

[0172] The second pixel electrode 210b and the fourth pixel electrode 210d disposed on the second region 2A can be arranged to be wider than the first pixel electrode 210a and the third pixel electrode 210c disposed on the first region 1A. More specifically, by arranging the second pixel electrode 210b and the fourth pixel electrode 210d on the second region 2A to be wider than the first pixel electrode 210a and the third pixel electrode 210c disposed on the first region 1A, a first distance d1, defined as the shortest distance from the first pixel electrode 210a to the third pixel electrode 210c, can be greater than a second distance d2, defined as the shortest distance from the second pixel electrode 210b to the fourth pixel electrode 210d. As an embodiment, the transmittance of the first region 1A can be higher than the transmittance of the second region 2A excluding the transmittance portion TA.

[0173] By arranging the second pixel electrode 210b and the fourth pixel electrode 210d more widely on the second region 2A to cover the lower part of the second pixel electrode 210b and the fourth pixel electrode 210d, the transmittance of the second region 2A except for the transmittance portion TA can be reduced, and the light generated from the element 20 arranged in the lower part of the second region 2A can be emitted only through the transmittance portion TA.

[0174] A first conductive layer 108 may be disposed on the second gate insulating layer 105 in the second region 2A, and a second conductive layer 109 may be disposed on the interlayer insulating layer 107. The first conductive layer 108 and the second conductive layer 109 may be at least one of the aforementioned scan lines, light emission control lines, data lines, and driving voltage lines. The first conductive layer 108 and the second conductive layer 109 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The second pixel electrode 210b may at least partially overlap the first conductive layer 108 and the second conductive layer 109.

[0175] A metal pattern layer 111 may be disposed on the interlayer insulating layer 107 in the second region 2A. The metal pattern layer 111 may at least partially overlap the second pixel electrode 210b and may be disposed on the interlayer insulating layer 107. The metal pattern layer 111 and the second conductive layer 109 may be formed in the same layer from the same material. As an embodiment, the metal pattern layer 111 may be integrally formed with the second conductive layer 109. For example, the metal pattern layer 111 may be a portion of the second conductive layer 109 extending toward the transmissive portion TA.

[0176] The metal pattern layer 111 can be arranged to surround the transmissive portion TA provided in the second region 2A, thereby improving or preventing diffraction when light generated by the element 20 arranged in the lower part of the second region 2A passes through the transmissive portion TA.

[0177] Figure 10b One embodiment integrates the metal pattern layer 111 with the first conductive layer 108. Figure 10a The embodiments differ. Figure 10b In its composition, the term "targeting" is omitted. Figure 10a The following explanation focuses on the differences between the similar compositions.

[0178] Reference Figure 10b The second pixel electrode 210b and the fourth pixel electrode 210d arranged on the second region 2A can be wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A. More specifically, by arranging the second pixel electrode 210b and the fourth pixel electrode 210d on the second region 2A to be wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A, a first distance d1, defined as the shortest distance from the first pixel electrode 210a to the third pixel electrode 210c, can be greater than a second distance d2, defined as the shortest distance from the second pixel electrode 210b to the fourth pixel electrode 210d. As an embodiment, the transmittance of the first region 1A can be higher than the transmittance of the second region 2A excluding the transmittance portion TA.

[0179] By arranging the second pixel electrode 210b and the fourth pixel electrode 210d more widely on the second region 2A to cover the lower part of the second pixel electrode 210b and the fourth pixel electrode 210d, the transmittance of the second region 2A except for the transmittance portion TA can be reduced, and the light generated from the element 20 arranged in the lower part of the second region 2A can be emitted only through the transmittance portion TA.

[0180] A first conductive layer 108 may be disposed on the second gate insulating layer 105 in the second region 2A, and a second conductive layer 109 may be disposed on the interlayer insulating layer 107. The first conductive layer 108 and the second conductive layer 109 may be at least one of the aforementioned scan lines, light emission control lines, data lines, and driving voltage lines. The first conductive layer 108 and the second conductive layer 109 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0181] A metal pattern layer 111 may be disposed on the second gate insulating layer 105 in the second region 2A. The metal pattern layer 111 and the first conductive layer 108 may be formed in the same layer from the same material. As an embodiment, the metal pattern layer 111 may be integrally formed with the first conductive layer 108. For example, the metal pattern layer 111 may be a portion of the first conductive layer 108 extending toward the transmissive portion TA.

[0182] The metal pattern layer 111 can be arranged to surround the transmissive portion TA provided in the second region 2A, thereby improving or preventing diffraction when light generated by the element 20 arranged in the lower part of the second region 2A passes through the transmissive portion TA.

[0183] Figure 10c The embodiment is arranged with the metal pattern layer 111 spaced apart from the first conductive layer 108, and electrically connected to the second conductive layer 109 through the first contact hole CNT1. Figure 10a The embodiments differ. Figure 10c In its composition, the term "targeting" is omitted. Figure 10a The following explanation focuses on the differences between the similar compositions.

[0184] Reference Figure 10c The second pixel electrode 210b and the fourth pixel electrode 210d arranged on the second region 2A can be wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A. More specifically, by arranging the second pixel electrode 210b and the fourth pixel electrode 210d on the second region 2A to be wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A, a first distance d1, defined as the shortest distance from the first pixel electrode 210a to the third pixel electrode 210c, can be greater than a second distance d2, defined as the shortest distance from the second pixel electrode 210b to the fourth pixel electrode 210d. As an embodiment, the transmittance of the first region 1A can be higher than the transmittance of the second region 2A excluding the transmittance portion TA.

[0185] By arranging the second pixel electrode 210b and the fourth pixel electrode 210d more widely on the second region 2A to cover the lower part of the second pixel electrode 210b and the fourth pixel electrode 210d, the transmittance of the second region 2A except for the transmittance portion TA can be reduced, and the light generated from the element 20 arranged in the lower part of the second region 2A can be emitted only through the transmittance portion TA.

[0186] A first conductive layer 108 may be disposed on the second gate insulating layer 105 in the second region 2A, and a second conductive layer 109 may be disposed on the interlayer insulating layer 107. The first conductive layer 108 and the second conductive layer 109 may be at least one of the aforementioned scan lines, light emission control lines, data lines, and driving voltage lines. The first conductive layer 108 and the second conductive layer 109 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0187] A metal pattern layer 111 may be disposed on the second gate insulating layer 105 of the second region 2A. The metal pattern layer 111 and the first conductive layer 108 may be formed in the same layer from the same material. The metal pattern layer 111 and the first conductive layer 108 may be disposed spaced apart from each other. The metal pattern layer 111 may be arranged to surround the transmittance TA provided in the second region 2A, thereby improving or preventing diffraction of light generated by the element 20 disposed in the lower part of the second region 2A when it passes through the transmittance TA.

[0188] As one embodiment, the metal pattern layer 111 can be electrically connected to the second conductive layer 109 via a first contact hole CNT1 defined in the interlayer insulating layer 107. By electrically connecting the metal pattern layer 111 to the second conductive layer 109 via the first contact hole CNT1 defined in the interlayer insulating layer 107, floating of the metal pattern layer 111 can be prevented, and coupling between the metal pattern layer 111 and surrounding wiring can be prevented.

[0189] Figure 10d The embodiment is similar to the one in which the metal pattern layer 111 and the second pixel electrode 210b are integrally formed. Figure 10a The embodiments differ. Figure 10d In its composition, the term "targeting" is omitted. Figure 10a The following explanation focuses on the differences between the similar compositions.

[0190] Reference Figure 10dThe second pixel electrode 210b and the fourth pixel electrode 210d arranged on the second region 2A can be wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A. More specifically, by arranging the second pixel electrode 210b and the fourth pixel electrode 210d on the second region 2A to be wider than the first pixel electrode 210a and the third pixel electrode 210c arranged on the first region 1A, a first distance d1, defined as the shortest distance from the first pixel electrode 210a to the third pixel electrode 210c, can be greater than a second distance d2, defined as the shortest distance from the second pixel electrode 210b to the fourth pixel electrode 210d. As an embodiment, the transmittance of the first region 1A can be higher than the transmittance of the second region 2A excluding the transmittance portion TA.

[0191] By arranging the second pixel electrode 210b and the fourth pixel electrode 210d more widely on the second region 2A and covering the lower part of the second pixel electrode 210b and the fourth pixel electrode 210d, the transmittance of the second region 2A except for the transmittance portion TA can be reduced, and the light generated from the element 20 arranged in the lower part of the second region 2A can be emitted only through the transmittance portion TA.

[0192] A first conductive layer 108 may be disposed on the second gate insulating layer 105 in the second region 2A, a second conductive layer 109 may be disposed on the interlayer insulating layer 107, a planarization layer 113 may be disposed on the second conductive layer 109, and a second pixel electrode 210b may be disposed on the planarization layer 113. The first conductive layer 108 and the second conductive layer 109 may be at least one of the aforementioned scan lines, light emission control lines, data lines, and driving voltage lines. The first conductive layer 108 and the second conductive layer 109 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0193] A metal pattern layer 111 may be disposed on the planarization layer 113 in the second region 2A. The metal pattern layer 111 may at least partially overlap the first conductive layer 108 and the second conductive layer 109, and may be disposed on the planarization layer 113. The metal pattern layer 111 and the second pixel electrode 210b may be formed in the same layer from the same material. As an embodiment, the metal pattern layer 111 may be integrally formed with the second pixel electrode 210b. For example, the metal pattern layer 111 may be a portion of the second pixel electrode 210b extending toward the transmissive portion TA.

[0194] The metal pattern layer 111 can be arranged to surround the transmissive portion TA provided in the second region 2A, thereby improving or preventing diffraction when light generated by the element 20 arranged in the lower part of the second region 2A passes through the transmissive portion TA.

[0195] In existing display devices that include the area where the element 20 is arranged, a metal pattern is arranged between the substrate and the buffer layer to prevent external light from reaching the auxiliary pixel Pa, including the auxiliary thin film transistor TFT', and to prevent light generated from the element 20 from diffracting through the transmissive portion TA.

[0196] However, when a metal pattern is arranged between the substrate and the buffer layer, additional steps are required compared to the past for patterning the metal pattern, as well as for preparing contact holes for applying voltage to the mask and the metal pattern, and the mask itself. Therefore, there is a problem of an increase in the number of steps and masks used to manufacture the display device.

[0197] Therefore, the present invention addresses the problem described above by utilizing existing signal wiring to form a metal pattern layer 111 for preventing diffraction of light generated from element 20 without the need for additional processes and masks, rather than forming the metal pattern layer 111 using additional processes and masks.

[0198] As one embodiment, when the second conductive layer 109 is formed on the interlayer insulating layer 107, a metal pattern layer 111 can be formed simultaneously on the interlayer insulating layer 107, thereby forming a metal pattern to prevent diffraction of light generated from the element 20 without additional processes and masks. Furthermore, by arranging pixel electrodes more widely on the second region 2A, the transmittance of the second region 2A, excluding the transmittance portion TA, can be reduced.

[0199] As an example, when the first conductive layer 108 is formed on the second gate insulating layer 105, a metal pattern layer 111 can be formed on the second gate insulating layer 105 at the same time, so that a metal pattern for preventing diffraction of light generated from the element 20 can be formed without additional processes and masks.

[0200] As an example, when a pixel electrode is formed on the planarization layer 113 of the second region 2A, a metal pattern layer 111 can be formed on the planarization layer 113 at the same time, so that a metal pattern for preventing diffraction of light generated from the element 20 can be formed without additional processes and masks.

[0201] According to an embodiment of the present invention, in order to solve the problem that additional processes and masks are required to form anti-diffraction metal patterns on areas where elements are arranged in existing display devices, a display device can be provided that can form metal pattern layers using existing signal wiring without additional processes and masks, while improving product reliability.

[0202] While the present invention has been described with reference to the embodiments shown in the accompanying drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments can be implemented accordingly. Therefore, the true scope of protection of the present invention should be determined based on the technical concept of the claims.

Claims

1. A display device, equipped with: The substrate includes a first region and a second region equipped with a plurality of through-holes; The main pixel is located on the first region and includes a first pixel electrode, a first opposing electrode, and a first intermediate layer disposed between the first pixel electrode and the first opposing electrode. An auxiliary pixel is located on the second region and includes a second pixel electrode, a second opposing electrode, and a second intermediate layer disposed between the second pixel electrode and the second opposing electrode. as well as A metallic patterned layer is arranged on the second region in such a way that it surrounds the plurality of transparent portions, and is provided with openings corresponding to the plurality of transparent portions. The metal pattern layer surrounding the plurality of transparent portions is formed as a single unit.

2. The display device of claim 1, wherein, Also includes: A first conductive layer is disposed on the substrate; An interlayer insulating layer is disposed on the first conductive layer; as well as The second conductive layer is disposed on the interlayer insulating layer.

3. The display device as claimed in claim 2, wherein, The metal pattern layer is integrally formed with the second conductive layer.

4. The display device as claimed in claim 3, wherein, The metal pattern layer overlaps at least partially with the second pixel electrode.

5. The display device as claimed in claim 3, wherein, The second conductive layer is the driving voltage line.

6. The display device as claimed in claim 2, wherein, The metal pattern layer is integrally formed with the first conductive layer.

7. The display device as claimed in claim 6, wherein, The metal pattern layer overlaps at least partially with the second pixel electrode.

8. The display device as claimed in claim 2, wherein, The metal patterned layer and the first conductive layer are arranged on the same layer, spaced apart from each other.

9. The display device as claimed in claim 8, wherein, The metal patterned layer is electrically connected to the second conductive layer through a first contact hole defined in the interlayer insulating layer.

10. The display device as claimed in claim 2, wherein, The metal pattern layer is integrally formed with the second pixel electrode.

11. The display device as claimed in claim 10, wherein, The metal patterned layer at least partially overlaps the first conductive layer and the second conductive layer.

12. The display device of claim 1, wherein, Also includes: The third pixel electrode of the other main pixel is located on the first region and is arranged at a distance from the first pixel electrode; as well as The fourth pixel electrode of the other auxiliary pixel is located on the second region and is arranged at a distance from the second pixel electrode.

13. The display device as claimed in claim 12, wherein, A first distance, defined as the shortest distance from the first pixel electrode to the third pixel electrode, is greater than a second distance, defined as the shortest distance from the second pixel electrode to the fourth pixel electrode.

14. The display device as claimed in claim 1, wherein, The permeable portion is circular or elliptical in shape.

15. The display device according to any one of claims 1 to 14, further comprising: The components are arranged below the substrate in a manner corresponding to the second region, and include electronic elements that emit or receive light.

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