Semiconductor components and semiconductor equipment

Abstract

The capacitance of the MOS capacitor increases. The semiconductor element includes a first semiconductor region, an insulating film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulating film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulating film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, is formed with the same conductivity type as the first semiconductor region, and provides carriers to the first semiconductor region when the MOS capacitor is charged and discharged.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a semiconductor device. More particularly, the present invention relates to a semiconductor element including a MOS capacitor and a semiconductor device using the semiconductor element. Background Art

[0002] Conventionally, a semiconductor element using a MOS capacitor formed on a semiconductor substrate as a capacitor has been used. For example, a MOS capacitor having a structure in which a p+ (or n+) type semiconductor region serving as a lower electrode is formed on a surface layer of a well region formed in a p-type manner, and a gate electrode is formed on the semiconductor region via a capacitive insulating film (for example, refer to Patent Document 1) is used.

[0003] The MOS capacitor is used as a charge accumulation unit that is arranged in a pixel of an imaging element and holds charges generated based on photoelectric conversion. Specifically, the MOS capacitor temporarily holds charges generated by photoelectric conversion of light from a subject.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-161868 Summary of the invention

[0007] Problems to be solved by the present invention

[0008] In the above conventional technology, a planar MOS capacitor in which an upper electrode and a lower electrode are formed in a flat plate shape is used. Therefore, there is a problem that it is difficult to increase the capacitance of the MOS capacitor. That is, there is a problem that the occupied area increases as the capacitance of the MOS capacitor increases, so it is difficult to increase the capacitance per unit area.

[0009] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to increase the capacitance of a MOS capacitor.

[0010] Problem Solution

[0011] The present invention is made to solve the above-mentioned problems, and a first aspect of the present invention is a semiconductor element, which includes: a first semiconductor region, which is arranged on a semiconductor substrate and includes a recessed portion on a surface; an insulating film, which is arranged adjacent to the surface of the first semiconductor region; a gate electrode, which is arranged adjacent to the insulating film and forms a MOS capacitor between the gate electrode and the first semiconductor region; and a second semiconductor region, which is arranged on the semiconductor substrate adjacent to the first semiconductor region, is formed with the same conductivity type as the first semiconductor region, and provides carriers to the first semiconductor region when the MOS capacitor is charged and discharged.

[0012] Furthermore, in the first aspect, the first semiconductor region may include a plurality of the recessed portions.

[0013] Furthermore, in the first aspect, the first semiconductor region may include the recessed portion formed in an opening having a substantially rectangular shape.

[0014] Furthermore, in the first aspect, a short side of the rectangular shape of the first semiconductor region is arranged in the vicinity of a boundary with the second semiconductor region.

[0015] Furthermore, in the first aspect, the first semiconductor region may include the recessed portion formed to have a short side having a length less than approximately twice the thickness of the gate electrode.

[0016] Furthermore, in the first aspect, the first semiconductor region may include more than 10 18 / cm 3 impurity concentration.

[0017] In addition, a second aspect of the present invention is a semiconductor device, which includes: a first semiconductor region, which is arranged on a semiconductor substrate and includes a recess on the surface; an insulating film, which is arranged adjacent to the surface of the first semiconductor region; a gate electrode, which is arranged adjacent to the insulating film and constitutes a MOS capacitor between the gate electrode and the first semiconductor region; a second semiconductor region, which is arranged on the semiconductor substrate adjacent to the first semiconductor region, is formed with the same conductivity type as the first semiconductor region, and provides carriers to the first semiconductor region when the MOS capacitor is charged and discharged; and an electronic circuit, which provides current to the MOS capacitor via the gate electrode and the second semiconductor region for charging and discharging.

[0018] By adopting this aspect, the following effects are provided: the first semiconductor region, the insulating film, and the gate electrode are stacked in the region where the recess is formed, and the expansion of the interface between the first semiconductor region and the gate electrode and the insulating film due to the recess is utilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a diagram showing a configuration example of a semiconductor element according to a first embodiment of the present invention.

[0020] Figure 2 is a cross-sectional view showing a configuration example of a semiconductor element according to a first embodiment of the present invention.

[0021] Figure 3 is a cross-sectional view showing a configuration example of a recessed portion according to the first embodiment of the present invention.

[0022] Figure 4 is a cross-sectional view showing a configuration example of a recessed portion according to the first embodiment of the present invention.

[0023] Figure 5 is a graph showing an example of characteristics of a MOS capacitor according to the first embodiment of the present invention.

[0024] Figure 6 is a diagram showing an example of a method for manufacturing a semiconductor element according to a second embodiment of the present invention.

[0025] Figure 7 is a diagram showing an example of a method for manufacturing a semiconductor element according to a second embodiment of the present invention.

[0026] Figure 8 is a diagram showing an example of a method for manufacturing a semiconductor element according to a second embodiment of the present invention.

[0027] Fig. 9 is a diagram showing another example of the method for manufacturing a semiconductor element according to the second embodiment of the present invention.

[0028] Fig.10 : is a block diagram showing a configuration example of an imaging element which is an example of a semiconductor device to which the present invention can be applied.

[0029] Fig.11 is a block diagram showing a configuration example of a column signal processing unit of an imaging element to which the present invention can be applied.

[0030] Fig.12 is a circuit diagram showing a configuration example of a comparison unit of an imaging element to which the present invention can be applied. DETAILED DESCRIPTION

[0031] Next, the mode for implementing the present invention (hereinafter, referred to as an embodiment) will be described with reference to the accompanying drawings. In the following drawings, the same or similar reference numerals are assigned to the same or similar parts. However, the drawings are schematic, and the size ratios of the various parts, etc. are not always consistent with the actual size ratios. In addition, it is needless to say that the drawings may include some parts with different size relationships and ratios between the drawings. In addition, it is noted that the embodiments will be described in the following order.

[0032] 1. First Embodiment (Structure of Semiconductor Element)

[0033] 2. Second Embodiment (Method for Manufacturing Semiconductor Element)

[0034] 3. Application examples of imaging elements

[0035] <1. First Embodiment>

[0036] [Structure of semiconductor element]

[0037] Figure 1 1 is a diagram showing a configuration example of a semiconductor element according to a first embodiment of the present invention. The figure is a plan view showing a configuration example of a MOS capacitor 100. The semiconductor element of the present invention will be described by taking the MOS capacitor 100 as an example. Note that the MOS capacitor 100 is an example of a semiconductor element described in the claims.

[0038] The MOS capacitor 100 in the drawings is formed on a semiconductor substrate 101 (not shown) and includes a gate electrode 110. The gate electrode 110 is arranged adjacent to a semiconductor region (a first semiconductor region 140 described later) formed on the semiconductor substrate 101 via an insulating film, thereby constituting a capacitor. In addition, similar to a MOS transistor, second semiconductor regions 103 and 104 corresponding to the source and drain, respectively, are formed in the MOS capacitor 100. The second semiconductor regions 103 and 104 can be used as wiring (leads) of the capacitor. The separation region 102 is arranged around the MOS capacitor 100. Note that the dotted rectangle in the drawings represents a recess 120 arranged in the first semiconductor region 140. The recess 120 in the drawings is formed in a rectangular groove shape, and represents an example in which a plurality of recesses 120 are arranged.

[0039] [Structure of a cross section of a MOS capacitor]

[0040] Figure 2 1 is a cross-sectional view showing a configuration example of a semiconductor element according to a first embodiment of the present invention. This figure is a cross-sectional view showing a configuration example of a MOS capacitor 100, and is taken along Figure 11 is a cross-sectional view taken along line AA' in FIG. The MOS capacitor 100 in the drawing includes a semiconductor substrate 101, a separation region 102, a first semiconductor region 140, an insulating film 130, a gate electrode 110, and second semiconductor regions 103 and 104. In addition, in the drawing, the MOS capacitor 100 and an electronic circuit 200 constituting the semiconductor device 1 are shown together.

[0041] The semiconductor substrate 101 is a semiconductor substrate on which a semiconductor region of the MOS capacitor 100 is formed. The semiconductor substrate 101 may include, for example, silicon (Si). In a well region formed on the semiconductor substrate 101, a first semiconductor region 140, second semiconductor regions 103 and 104, etc. are formed. For convenience, it is assumed that the semiconductor substrate 101 in the drawings is formed in a p-type well region. The semiconductor substrate 101 in the drawings may be grounded. Specifically, the semiconductor substrate 101 may be connected to a ground line via a well contact for connection from the surface of the semiconductor substrate 101 to the well region.

[0042] The separation region 102 separates the region of the MOS capacitor 100 in the semiconductor substrate 101. By arranging the separation region 102, the MOS capacitor 100 can be electrically separated from other semiconductor elements formed on the semiconductor substrate 101. It is assumed that the separation region 102 in the drawing is a separation region 102 formed by shallow trench isolation (STI). That is, the separation region 102 may include silicon oxide (SiO2) embedded in a trench formed in the semiconductor substrate 101. Note that the separation region 102 may be formed by, for example, local oxidation of silicon (LOCOS).

[0043] The first semiconductor region 140 is arranged on the semiconductor substrate 101, thereby constituting an electrode of the MOS capacitor 100. The first semiconductor region 140 in the drawing includes, for example, an n-type semiconductor region. Figure 1 The recess 120 described in the figure is arranged in the first semiconductor region 140. As the recess 120, a groove (groove) having an opening formed in the first semiconductor region 140, the opening having a substantially rectangular shape, can be used. In addition, one or more recesses 120 may be arranged in the first semiconductor region 140. In addition, the figure shows an example of a recess 120 formed to have a substantially rectangular cross section.

[0044] The insulating film 130 is an insulating material film constituting a dielectric layer of the MOS capacitor 100. The insulating film 130 is arranged adjacent to the first semiconductor region 140. For example, the insulating film 130 may include an oxide such as SiO2 or a nitride such as silicon nitride (SiN).

[0045] The gate electrode 110 is an electrode arranged adjacent to the insulating film 130. The gate electrode 110 is arranged to face the first semiconductor region 140 across the insulating film 130, thereby constituting a MOS capacitor. In addition, as shown in the figure, the gate electrode 110 is formed in a shape filling the recess 120 remaining on the surface of the insulating film 130. The gate electrode 110 may include, for example, polysilicon doped with a donor (P, As, etc.) or an acceptor (B, etc.).

[0046] As shown in the figure, the insulating film 130 is formed to have a thickness less than 1 / 2 of the width of the recess 120 of the first semiconductor region 140. Therefore, even after the insulating film 130 is arranged so as to cover the surface of the recess 120 of the first semiconductor region 140, the insulating film 130 can still have a shape that allows the recess to remain on its surface. In addition, the shape of the recess 120 can be defined based on the thickness of the gate electrode 110. Specifically, the recess 120 can be formed to have a width less than about twice the thickness of the gate electrode 110. This is to make the surface of the gate electrode 110 flatter. Note that, as described above, in the case of forming the recess 120 in an opening having a rectangular shape, the short side of the recess 120 can be formed to have a length less than about twice the thickness of the gate electrode 110.

[0047] By forming the recess 120 in the first semiconductor region 140 and embedding the insulating film 130 in the recess 120 in this way, the surface area of ​​the capacitor composed of the first semiconductor region 140 and the gate electrode 110 can be increased. Therefore, the capacitance value of the MOS capacitor 100 can be increased. The capacitance per unit area of ​​the MOS capacitor 100 can be increased.

[0048] Note that the shape of the recess 120 is not limited to this example. For example, a recess 120 formed in an elliptical opening may also be used. In addition, a recess 120 having a rectangular shape with chamfered or rounded corners may also be used. Needless to say, even in the case where the corners of a rectangle or the like are deformed when forming the recess 120, the recess still corresponds to the recess 120 of the present invention.

[0049] The second semiconductor regions 103 and 104 are diffusion regions of the semiconductor substrate 101 arranged adjacent to the first semiconductor region 140. When the MOS capacitor 100 is charged and discharged, the second semiconductor regions 103 and 104 provide carriers to the first semiconductor region 140. That is, it can be regarded as a wiring connected to the first semiconductor region 140. In addition, the second semiconductor regions 103 and 104 can be formed in the same conductivity type as the first semiconductor region 140. Therefore, the resistance at the connection with the first semiconductor region 140 can be reduced. The MOS capacitor 100 in the drawings is formed in the same n-type as the first semiconductor region 140. In addition, by forming a shape in which the first semiconductor region 140 is sandwiched between the second semiconductor regions 103 and 104, the current of the first semiconductor region 140 can be shunted and the resistance can be reduced. In addition, since the configuration of the MOS capacitor 100 can be the same as that of the MOS transistor formed on the semiconductor substrate 101, the MOS capacitor 100 can be formed by a common manufacturing process.

[0050] Note that the configuration of the MOS capacitor 100 is not limited to this example. For example, the first semiconductor region 140 and the second semiconductor regions 103 and 104 formed in p-type may also be used. In addition, the semiconductor substrate 100 may also be applied to an n-type well region of the same conductivity type as the first semiconductor region 140 and the second semiconductor regions 103 and 104 described above.

[0051] The electronic circuit 200 is a circuit using the MOS capacitor 100 as a capacitor. In the drawing, one end of the electronic circuit 200 is grounded and the other end is connected to the gate electrode 110. The second semiconductor regions 103 and 104 are similarly grounded to form a circuit in which the MOS capacitor 100 and the electronic circuit 200 are connected in series. Any circuit can be used for the electronic circuit 200.

[0052] [Concave structure]

[0053] Figure 3 and Figure 4 is a cross-sectional view showing a configuration example of a recessed portion according to the first embodiment of the present invention. Figure 3 and Figure 4 Along Figure 1 The cross-sectional view taken along the lines BB′ and CC′ in FIG. Figure 4 1 is a diagram showing an example of the structure of the concave portion 120 in the longitudinal direction. Figures 1 to 4 As shown, the short side of the recess 120 formed in the opening having a rectangular shape may be arranged near the boundary between the first semiconductor region 140 and the second semiconductor regions 103 and 104. That is, the recess 120 may be arranged along the direction from the second semiconductor region 103 to the second semiconductor region 104.

[0054] As described above, when the MOS capacitor 100 is charged and discharged, carriers are supplied from the second semiconductor regions 103 and 104 to the first semiconductor region 140. At this time, the supplied carriers are charged and discharged while they move in the lateral direction of the first semiconductor region 140 in the drawing. The carriers move along the long sides of the recesses 120, so that they can move smoothly. Due to this arrangement of the recesses 120, the increase in the effective wiring length can be reduced compared to the case where the short sides of the recesses 120 are arranged in the direction from the second semiconductor region 103 to the second semiconductor region 104. The wiring resistance and parasitic inductance can be reduced, and the high-frequency characteristics of the MOS capacitor 100 can be improved. In the case where a large number of recesses 120 are arranged, a more significant effect is obtained.

[0055] Note that the configuration of the MOS capacitor 100 is not limited to this example. For example, a side wall may be arranged adjacent to the gate electrode 110, and a lightly doped drain (LDD: lightly doped drain) may be formed in the second semiconductor regions 103 and 104. In addition, a configuration in which either of the second semiconductor regions 103 and 104 is arranged is also possible. In addition, a channel region of another MOS transistor may be used as the second semiconductor regions 103 and 104.

[0056] Furthermore, for example, the recessed portion 120 may be formed in a cylindrical shape. Furthermore, a recessed portion 120 having a tapered (V-shaped) cross section may also be used.

[0057] [Characteristics of MOS capacitors]

[0058] Figure 5 1 is a diagram showing an example of the characteristics of a MOS capacitor according to a first embodiment of the present invention. The figure is a diagram showing the relationship between the applied voltage (gate voltage) and the capacitance value of the MOS capacitor 100. The horizontal axis in the figure represents the gate voltage, and the vertical axis represents the capacitance value. Note that the gate voltage is a voltage based on the voltage of the grounded first semiconductor region 140. When a negative gate voltage is applied to the first semiconductor region 140, a capacitance value having a value based on the shape (for example, the film thickness of the insulating film 130 and the area of ​​the interface between the insulating film 130 and the first semiconductor region 140) and based on the dielectric constant is obtained. This area is called an accumulation area. Since the MOS capacitor 100 in the figure is formed in a p-type well region (semiconductor substrate 101), holes are accumulated when a relatively high negative gate voltage is applied.

[0059] On the other hand, when the applied voltage of the gate is increased, a capacitance characteristic depending on the gate voltage is exhibited. Specifically, the following characteristics are obtained: when the gate voltage changes to a voltage close to 0V, the capacitance decreases. This is because a depletion layer is formed near the interface between the first semiconductor region 140 and the insulating film 130 in the first semiconductor region 140, and the effective film thickness of the insulating film 130 increases. Thereafter, when the gate voltage is further increased, the reduced capacitance value increases. This is because a surface inversion layer with an increased electron concentration is formed near the interface between the first semiconductor region 140 and the insulating film 130 in the first semiconductor region 140. The surface inversion layer expands as the gate voltage increases, and obtains a capacitance value of approximately the same value as the capacitance value in the accumulation region. This region is referred to as an inversion region.

[0060] When the MOS capacitor 100 is used for general capacitor applications, it is preferred to use it at an applied voltage corresponding to the accumulation region and the inversion region in the accompanying drawings. This is because the change in circuit characteristics due to the change in capacitance value can be reduced. In the case where the operating voltage is a voltage close to 0V, for example, in the case where the operating voltage range is as low as -3.3 to 3.3V and the capacitance value is used in the region depending on the applied voltage, the characteristics of the MOS capacitor 100 are adjusted. Specifically, the characteristics of the MOS capacitor 100 are adjusted so that the accumulation region or the inversion region overlaps the operating voltage range.

[0061] In that case, it is preferred that the first semiconductor region 140 should have a higher impurity concentration. Specifically, the first semiconductor region 140 should have an impurity concentration higher than 10 18 / cm 3 The solid line in the figure represents the characteristics when the impurity concentration of the first semiconductor region 140 is low, and the dotted line represents the characteristics when the impurity concentration of the first semiconductor region 140 is high. By increasing the impurity concentration of the first semiconductor region 140, the voltage dependence can be reduced within the operating voltage range.

[0062] As described above, in the MOS capacitor 100 of the first embodiment of the present invention, the recess 120 is arranged in the first semiconductor region 140, thereby expanding the first semiconductor region 140 as an electrode and the interface between the gate electrode 110 and the insulating film 130. Therefore, the capacitance of the MOS capacitor 100 can be increased.

[0063] <2. Second Embodiment>

[0064] In the MOS capacitor 100 of the first embodiment described above, the recess 120 is formed in the first semiconductor region 140. In the second embodiment of the present invention, a method for manufacturing the MOS capacitor 100 having such a configuration will be described.

[0065] [Method for manufacturing semiconductor element]

[0066] Figures 6 to 8 is a diagram showing an example of a method for manufacturing a semiconductor element according to a second embodiment of the present invention. Figures 6 to 8 1 is a diagram showing an example of a manufacturing process of the MOS capacitor 100. Figures 6 to 8 A process for manufacturing the recessed portion 120 and the like near the gate electrode 110 will be described.

[0067] First, a well region is formed on the semiconductor substrate 101, and a separation region 102 is formed. The separation region 102 ( Figure 6 A).

[0068] Next, a resist 401 is formed on the surface of the semiconductor substrate 101. An opening 402 is arranged in the resist 401 at a position where the recess 120 is formed. The resist 401 can be formed by photolithography ( Figure 6 Next, the semiconductor substrate 101 is etched using the resist 401 as a mask. This etching can be performed, for example, by dry etching. Thus, the recess 120 ( Figure 6 C in FIG. 4). Next, the resist 401 is removed (residues from etching, etc.). This can be done, for example, by wet etching ( Figure 7 D).

[0069] Next, ion implantation is performed on the surface of the semiconductor substrate 101 to form the first semiconductor region 140. At this time, similarly, the second semiconductor regions 103 and 104 (not shown) are formed by ion implantation. Before this ion implantation, a sacrificial oxide film ( Figure 7 E). Note that after ion implantation, the sacrificial oxide film is removed.

[0070] Next, an insulating film 130 is formed on the surface of the first semiconductor region 140. This can be done, for example, by thermal oxidation ( Figure 7 F).

[0071] Next, the gate electrode 110 is formed on the surface of the insulating film 130. This can be formed, for example, by chemical vapor deposition (CVD). Figure 8 G in.

[0072] The MOS capacitor 100 can be manufactured through the above process. Note that in the case where the first semiconductor region 140 is formed by ion implantation as described above, preferably, the depth of the recess 120 is less than 200 nm. This is to form the first semiconductor region 140 with a uniform impurity concentration.

[0073] [Another method for manufacturing a semiconductor element]

[0074] Fig. 9 1 is a diagram showing another example of a method for manufacturing a semiconductor element according to a second embodiment of the present invention. Figure 6 A to Figure 7 E in the figure corresponds to the manufacturing process.

[0075] Ion implantation is performed on the surface of the semiconductor substrate 101 on which the separation region 102 is formed, thereby forming a first semiconductor region 140 ( Fig. 9 Next, a resist 401 is formed on the surface of the first semiconductor region 140 ( Fig. 9 Next, etching is performed to form the recess 120 ( Fig. 9 C in the figure). After that, the resist 401 is removed. Figure 7 F and Figure 8 are similar, so the description will not be repeated.

[0076] Note that the manufacturing process of the MOS capacitor 100 is not limited to this example. For example, the first semiconductor region 140 may be formed by thermal diffusion instead of ion implantation.

[0077] As described above, in the second embodiment of the present invention, the MOS capacitor 100 having the first semiconductor region 140 in which the recess 120 is formed can be manufactured.

[0078] <3. Application examples of imaging elements>

[0079] The technology according to the present invention (the present technology) is applicable to various products. For example, the present technology can be implemented as a semiconductor element mounted on a semiconductor device such as an imaging element.

[0080] [Structure of imaging element]

[0081] Fig.10 1 is a block diagram showing a configuration example of an imaging element which is an example of a semiconductor device to which the present invention can be applied. An imaging element 1 in the drawing includes a pixel array unit 10, a vertical drive unit 20, a column signal processing unit 300, and a control unit 40.

[0082] The pixel array unit 10 is constructed by arranging the pixels 11 into a two-dimensional grid pattern. Here, the pixel 11 generates an image signal depending on the irradiated light. The pixel 11 has a photoelectric conversion unit that generates a charge depending on the irradiated light. In addition, the pixel 11 also has a pixel circuit. The pixel circuit generates an image signal based on the charge generated by the photoelectric conversion unit. The generation of the image signal is controlled by a control signal generated by a vertical drive unit 20 described later. In the pixel array unit 10, signal lines 51 and 52 are arranged in an XY matrix pattern. The signal line 51 is a signal line that transmits a control signal for the pixel circuit in the pixel 11, arranged for each row of the pixel array unit 10, and wired to the pixels 11 arranged in each row in common. The signal line 52 is a signal line that transmits an image signal generated by the pixel circuit of the pixel 11, arranged for each column of the pixel array unit 10, and wired to the pixels 11 arranged in each column in common. These photoelectric conversion units and pixel circuits are formed on a semiconductor substrate. For example, they can be formed on the above-mentioned semiconductor substrate 101.

[0083] The vertical driving unit 20 generates a control signal for the pixel circuit of the pixel 11. The vertical driving unit 20 transmits the generated control signal to the pixel 11 through the signal line 51 in the drawing. The column signal processing unit 300 processes the image signal generated by the pixel 11. The column signal processing unit 300 processes the image signal transmitted from the pixel 11 via the signal line 52 in the drawing. The processing in the column signal processing unit 300 corresponds to, for example, analog-to-digital conversion, which converts the analog image signal generated in the pixel 11 into a digital image signal. The image signal processed by the column signal processing unit 300 is output as an image signal of the imaging element 1. The control unit 40 controls the entire imaging element 1. The control unit 40 controls the imaging element 1 by generating and outputting a control signal for controlling the vertical driving unit 20 and the column signal processing unit 300. The control signal generated by the control unit 40 is transmitted to the vertical driving unit 20 and the column signal processing unit 300 through the signal lines 53 and 54, respectively.

[0084] [Structure of column signal processing unit]

[0085] Fig.11 The column signal processing unit 300 in the figure includes a reference signal generating unit 311, a timing control unit 312, a horizontal transfer unit 313, and an analog-to-digital conversion (ADC) unit 314.

[0086] The reference signal generating unit 311 generates a reference signal. Here, the reference signal is a signal used as a reference for analog-to-digital conversion in the analog-to-digital conversion unit 314 described later. As the reference signal, for example, a signal whose voltage decreases like a ramp function can be used. The reference signal generating unit 311 generates a reference signal according to the control of the control unit 40, and provides the reference signal to the analog-to-digital conversion unit 314 via the signal line 301.

[0087] The timing control unit 312 controls the operation timing of each component in the column signal processing unit 300. The timing control unit 312 generates a control signal for each component of the column signal processing unit 300 according to the control of the control unit 40 and outputs the control signal via the signal lines 302 to 304.

[0088] The analog-to-digital conversion unit 314 converts an analog image signal generated by the pixel 11 into a digital image signal. The analog-to-digital conversion unit 314 is arranged for each signal line 52. A plurality of analog-to-digital conversion units 314 simultaneously perform analog-to-digital conversion of image signals in the pixels 11 in one row of the pixel array unit 10. The digital image signal converted by the analog-to-digital conversion unit 314 is output to the horizontal transfer unit 313 via the signal line 307.

[0089] The horizontal transfer unit 313 transfers the digital image signal. The horizontal transfer unit 313 sequentially transfers the digital image signals generated by the plurality of analog-to-digital conversion units 314 and outputs the signals from the signal line 55.

[0090] The analog-to-digital conversion unit 314 in the figure includes a comparison unit 315 , a counting unit 316 , and a holding unit 317 .

[0091] The comparison unit 315 compares the analog image signal generated by the pixel 11 with the reference signal, and outputs the comparison result to the counting unit 316. For example, as a result of the comparison, in the case where the reference signal has a higher voltage than the analog image signal, a value of "0" may be output, and in the case where the reference signal has shifted to a voltage lower than the analog image signal, a value of "1" may be output. Thus, the moment when the reference signal has substantially the same value as the analog image signal can be detected.

[0092] The counting unit 316 measures the time from the start of the comparison in the comparison unit 315 to the time when the reference signal and the analog image signal have substantially the same value. Specifically, the time from the start of the output of the reference signal in the reference signal generating unit 311 to the time when the output of the comparison unit 315 changes to the value "1" is measured. As described above, the reference signal is a signal having a value that changes like a ramp function. Therefore, there is a one-to-one correspondence between the time until the reference signal has substantially the same value as the analog image signal and the voltage of the analog image signal. Therefore, analog-to-digital conversion can be performed by generating and outputting a digital signal corresponding to the time until the reference signal has substantially the same value as the analog image signal. Specifically, the counting unit 316 can count the clock signal during the period from the start of the output of the reference signal to the time when the output of the comparison unit 315 changes to the value "1", and output the count value as the analog-to-digital conversion result. Note that the clock signal is input from the timing control unit 312 via the signal line 302.

[0093] The holding unit 317 holds the count value of the counting unit 316. According to the control of the timing control unit 312, each count value held by each of the plurality of holding units 317 is sequentially output to the horizontal transfer unit 313 as a digital image signal.

[0094] [Comparison unit structure]

[0095] Fig.12 315 is a circuit diagram showing a configuration example of a comparison unit of an imaging element to which the present invention can be applied. The comparison unit 315 in the accompanying drawings includes capacitors 341 to 344, MOS transistors 351 to 355, and MOS transistors 361 to 365. As the MOS transistors 351 to 355, p-channel MOS transistors can be used. In addition, as the MOS transistors 361 to 365, n-channel MOS transistors can be used. In addition, a power supply line Vdd for power supply, a signal line BIAS for providing a bias voltage, and signal lines NSEL and PSEL for providing a selection signal are connected to the comparison unit 315 in the accompanying drawings.

[0096] The capacitor 341 is connected between the signal line 301 and the gate of the MOS transistor 361. The drain of the MOS transistor 353 is also connected to the gate of the MOS transistor 361. The drain of the MOS transistor 361 is connected to the source of the MOS transistor 353, the drain and gate of the MOS transistor 351, and the gate of the MOS transistor 352. The source of the MOS transistor 351 and the source of the MOS transistor 352 are commonly connected to the power supply line Vdd. The source of the MOS transistor 361 is connected to the source of the MOS transistor 362 and the drain of the MOS transistor 363. The gate of the MOS transistor 363 is connected to the signal line BIAS, and the source is grounded.

[0097] Capacitor 342 is connected between signal line 52 and the gate of MOS transistor 362. The drain of MOS transistor 354 is also connected to the gate of MOS transistor 362. The drain of MOS transistor 362 is connected to the source of MOS transistor 354, the drain of MOS transistor 352, the gate of MOS transistor 355, and one end of capacitor 344. The other end of capacitor 344 is connected to power supply line Vdd. The gate of MOS transistor 353 and the gate of MOS transistor 354 are commonly connected to signal line PSEL. The source of MOS transistor 355 is connected to power supply line Vdd, and the drain is connected to the drain of MOS transistor 364, the drain of MOS transistor 365, and signal line 305.

[0098] The gate of the MOS transistor 364 is connected to the signal line NSEL, and the source is connected to the gate of the MOS transistor 365 and one end of the capacitor 343. The other end of the capacitor 343 and the source of the MOS transistor 365 are grounded.

[0099] Capacitors 341 and 342 constitute a coupling capacitor. In addition, capacitors 341 and 342 hold a reference signal and an analog image signal, respectively. MOS transistors 361 and 362 constitute a differential amplifier, and amplify the difference between the reference signal and the analog image signal input via capacitors 341 and 342. MOS transistor 363 constitutes a constant current circuit commonly connected to the sources of MOS transistors 361 and 362. A source current based on a bias voltage of a signal line BIAS flows through MOS transistor 363. MOS transistors 351 and 352 constitute a current mirror circuit, and constitute a load connected to the drains of MOS transistors 361 and 362, respectively. The current mirror circuit can increase the gain of the differential amplifier including MOS transistors 361 and 362.

[0100] By amplifying the difference between the reference signal and the analog image signal using a high-gain differential amplifier, the reference signal and the analog image signal can be compared. Note that MOS transistors 353 and 354 are switches that control amplification (comparison) of MOS transistors 361 and 362. MOS transistors 353 and 354 perform control based on a selection signal of the signal line PSEL.

[0101] The output of the differential amplifier is taken from the drain of the MOS transistor 362 and input to the gate of the MOS transistor 355. The MOS transistor 355 further amplifies the output of the differential amplifier, inverts the polarity of the signal, and outputs the signal to the signal line 305. The MOS transistor 365 is a transistor that holds the output of the MOS transistor 355. The output of the MOS transistor 355 is held by the capacitor 343 via the MOS transistor 364. Since the gate of the MOS transistor 365 is connected to the capacitor 343, the MOS transistor 365 outputs a drain voltage corresponding to the voltage of the capacitor 343. The MOS transistor 364 is a switch that controls the holding of the output of the MOS transistor 355 by the capacitor 343, and is controlled by the selection signal of the signal line NSEL.

[0102] In addition, a capacitor 344 is connected between the gate of the MOS transistor 355 and the power supply line Vdd. The capacitor 344 is a band-limiting capacitor for reducing the output noise of the differential amplifier including the MOS transistors 361 and 362. As described above, the reference signal and the analog image signal are compared in the differential amplifier including the MOS transistors 361 and 362. However, in the case where the gain in the high frequency range of the differential amplifier is too high, noise components such as the analog image signal are also amplified, which causes a malfunction of the analog-to-digital conversion unit 314. By connecting the capacitor 344 as the above-mentioned band-limiting capacitor, the frequency band of the differential amplifier including the MOS transistors 361 and 362 can be narrowed to reduce the gain in the high frequency range, and the output noise can be reduced.

[0103] The MOS capacitor 100 of the present invention can be applied to the capacitors 341 to 344 of the comparison unit 315 in the drawings. For example, the MOS capacitor 100 can be applied to the capacitor 344, and the MOS capacitor 100 can be charged and discharged by a differential amplifier including MOS transistors 361 and 362. By applying the MOS capacitor 100 of the present invention capable of increasing the capacitance to the capacitors 341 to 344, the area occupied by the capacitors 341 to 344 can be reduced. The size of the analog-to-digital conversion unit 314 and the imaging element 1 can be reduced. Note that the differential amplifier including the MOS transistors 361 and 362 is an example of an electronic circuit described in the claims. The analog-to-digital conversion unit 314 and the imaging element 1 are examples of semiconductor devices described in the claims.

[0104] Finally, the description of each embodiment described above is an example of the present invention, and the present invention is not limited to the above embodiments. Therefore, it is needless to say that various changes can be made according to the design, etc., even changes different from the above embodiments, without departing from the technical concept according to the present invention.

[0105] Note that the present technology can be configured as follows.

[0106] (1) A semiconductor device comprising:

[0107] a first semiconductor region disposed on the semiconductor substrate and including a recessed portion on a surface;

[0108] an insulating film arranged adjacent to the surface of the first semiconductor region;

[0109] a gate electrode disposed adjacent to the insulating film and constituting a MOS capacitor between the gate electrode and the first semiconductor region; and

[0110] A second semiconductor region, which is arranged adjacent to the first semiconductor region on the semiconductor substrate, is formed with the same conductivity type as the first semiconductor region, and supplies carriers to the first semiconductor region when the MOS capacitor is charged and discharged.

[0111] (2) The semiconductor element according to (1), wherein the first semiconductor region includes a plurality of the recessed portions.

[0112] (3) The semiconductor element according to (1) or (2), wherein the first semiconductor region includes the recessed portion formed in an opening having a substantially rectangular shape.

[0113] (4) The semiconductor element according to (3), wherein a short side of the rectangular shape of the first semiconductor region is arranged in the vicinity of a boundary with the second semiconductor region.

[0114] (5) The semiconductor element according to (3), wherein the first semiconductor region includes the recessed portion formed to have a short side whose length is less than approximately twice the thickness of the gate electrode.

[0115] (6) The semiconductor element according to any one of (1) to (5), wherein the impurity concentration of the first semiconductor region is higher than 10 18 / cm 3 .

[0116] (7) A semiconductor device comprising:

[0117] a first semiconductor region disposed on the semiconductor substrate and including a recessed portion on a surface;

[0118] an insulating film arranged adjacent to the surface of the first semiconductor region;

[0119] a gate electrode disposed adjacent to the insulating film and constituting a MOS capacitor between the gate electrode and the first semiconductor region;

[0120] a second semiconductor region which is arranged adjacent to the first semiconductor region on the semiconductor substrate, is formed with the same conductivity type as the first semiconductor region, and supplies carriers to the first semiconductor region when the MOS capacitor is charged and discharged; and

[0121] An electronic circuit supplies current to the MOS capacitor through the gate electrode and the second semiconductor region for charging and discharging.

[0122] Reference numerals list

[0123] 1 Imaging element

[0124] 100 MOS capacitors

[0125] 101 Semiconductor substrate

[0126] 102 Separation Area

[0127] 103, 104 second semiconductor region

[0128] 110 Gate electrode

[0129] 120 recess

[0130] 130 Insulation film

[0131] 140 first semiconductor region

[0132] 200 Electronic Circuits

[0133] 300 columns of signal processing units

[0134] 314 Analog-to-digital conversion unit

[0135] 315 Comparison Unit

[0136] 341 to 344 capacitors

[0137] 351 to 355, 361 to 365 MOS transistors

Claims

1. A semiconductor device, comprising: a first semiconductor region disposed on the semiconductor substrate and including a recessed portion on a surface; an insulating film arranged adjacent to the surface of the first semiconductor region; a gate electrode disposed adjacent to the insulating film and constituting a MOS capacitor between the gate electrode and the first semiconductor region; and a second semiconductor region which is arranged on the semiconductor substrate to be adjacent to both left and right sides of the first semiconductor region, is formed with the same conductivity type as the first semiconductor region, and supplies carriers to the first semiconductor region when the MOS capacitor is charged and discharged, wherein the second semiconductor region has the same thickness as the first semiconductor region in the depth direction of the recess, The first semiconductor region includes the recess formed in an opening having a rectangular shape, and A short side of the rectangular shape of the first semiconductor region is arranged in the vicinity of a boundary with the second semiconductor region.

2. The semiconductor element according to claim 1, wherein The first semiconductor region includes a plurality of the recessed portions.

3. The semiconductor element according to claim 1, wherein The first semiconductor region includes the recessed portion formed to have a short side whose length is less than twice the thickness of the gate electrode.

4. The semiconductor element according to any one of claims 1 to 3, wherein The impurity concentration of the first semiconductor region is higher than 10 18 / cm 3 .

5. A semiconductor device comprising: The semiconductor element according to any one of claims 1 to 4; and An electronic circuit supplies current to the MOS capacitor through the gate electrode and the second semiconductor region for charging and discharging.

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