Method of fabricating a semiconductor structure

Abstract

A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided, the semiconductor wafer including integrated circuit components, seal rings each surrounding an integrated circuit component, and test structures disposed between the seal rings. A first wafer sawing process is performed along at least a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including one of the test structures. When the first wafer sawing process is performed, a test contact pad of a test structure is located alongside the first path such that the test contact pad of a corresponding one of the test structures in the first singulated integrated circuit components is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and its fabrication method. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the iterative reduction in the minimum feature size (e.g., shrinking semiconductor process nodes towards the sub-20nm node), which allows more components to be integrated into a given area. With the recent growth in demand for miniaturization, higher speeds and greater bandwidth, as well as lower power consumption and latency, the need for smaller and more innovative semiconductor die packaging technologies has also increased.

[0003] With the further development of semiconductor technology, stacked and bonded semiconductor devices have become an effective alternative for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, and processor circuits are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device. This bonding process utilizes complex techniques, and improvements are expected. Summary of the Invention

[0004] This invention provides a method comprising: providing a semiconductor wafer, the semiconductor wafer including a plurality of integrated circuit components, a plurality of sealing rings respectively surrounding the plurality of integrated circuit components, and a plurality of test structures disposed between the plurality of sealing rings; and performing a first wafer sawing process at least along a first path to monomerize the semiconductor wafer into a plurality of first monomerized integrated circuit components, each of the plurality of first monomerized integrated circuit components including a test structure among the plurality of test structures, wherein, when performing the first wafer sawing process, a plurality of test pads of the plurality of test structures are located next to the first path, such that the test pad of a corresponding test structure among the plurality of test structures in the first monomerized integrated circuit component is laterally spaced from the sidewall of the first monomerized integrated circuit component by a certain distance.

[0005] This invention provides a method comprising: providing a semiconductor wafer, the semiconductor wafer including a plurality of integrated circuit components, a plurality of sealing rings respectively surrounding the plurality of integrated circuit components, and a plurality of test structures disposed between the plurality of sealing rings; and performing a wafer sawing process at least along a path to monomerize the semiconductor wafer into a plurality of monomerized integrated circuit components, wherein, when performing the wafer sawing process, the plurality of test structures are arranged along the path such that each of the plurality of monomerized integrated circuit components includes a residual structure corresponding to one of the plurality of test structures, wherein the residual structure does not have an aluminum pad.

[0006] This invention provides an apparatus including a first semiconductor die. The first semiconductor die includes an integrated circuit assembly, a sealing ring, and a test structure. The sealing ring surrounds the integrated circuit assembly. A portion of the sealing ring is located between the integrated circuit assembly and the test structure, and the test structure includes a test pad that is laterally spaced from the sidewall of the first semiconductor die. Attached Figure Description

[0007] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1A , Figure 1C and Figure 1D This is a schematic cross-sectional view illustrating a process flow for fabricating a top semiconductor die according to some embodiments of the present disclosure. Figure 1B This is an illustrative representation of some embodiments according to the present disclosure. Figure 1A The diagram shows a top view of the integrated circuit assembly, the annular seal, and the test structure.

[0009] Figure 2A , Figure 2C and Figure 2D This is a schematic cross-sectional view illustrating a process flow for fabricating a top semiconductor die according to some other embodiments of this disclosure. Figure 2B This is an illustrative representation of some embodiments according to the present disclosure. Figure 2A The diagram shows a top view of the integrated circuit assembly, sealing ring, and test structure.

[0010] Figure 3A , Figure 3C and Figure 3D This is a schematic cross-sectional view illustrating a process flow for fabricating a top semiconductor die according to some other embodiments of this disclosure. Figure 3B This is an illustrative representation of some embodiments according to the present disclosure. Figure 3AThe diagram shows a top view of the integrated circuit assembly, the annular seal, and the test structure.

[0011] Figure 4A , Figure 4C and Figure 4D This is a schematic cross-sectional view illustrating a process flow for fabricating a top semiconductor die according to some other embodiments of this disclosure. Figure 4B This is an illustrative representation of some embodiments according to the present disclosure. Figure 4A The diagram shows a top view of the integrated circuit assembly, sealing ring, and test structure.

[0012] Figures 5A to 5H This is a schematic cross-sectional view illustrating the process flow for fabricating a package structure for a system-on-an-integrated circuit (SoIC) chip according to some embodiments of the present disclosure.

[0013] Figures 6A to 6D Various embodiments according to this disclosure Figure 5H An enlarged view of region X' shown in the diagram. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the description in the following text of a first feature being formed "on" or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing the first and second features from being in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, an indication of a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature illustrated in the figures and another element or feature. In addition to the orientations shown in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0016] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of three-dimensional (3D) packaged or 3D integrated circuit (3DIC) devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate, which allow testing of the 3D package or 3DIC, and allow the use of probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that include verifying known good dies in the intermediate stages to improve yield and reduce costs.

[0017] Fabrication of top semiconductor dies

[0018] Figure 1A , Figure 1C and Figure 1D This is a cross-sectional view schematically illustrating the process flow for fabricating a top semiconductor die according to some embodiments of the present disclosure. Figure 1B This is an illustrative description of some embodiments according to the present disclosure. Figure 1A The diagram shows a top view of the integrated circuit assembly, annular seal, and test structure. For illustrative purposes, Figure 1B The diagram also illustrates the sawing path used for the wafer sawing process. In some embodiments, an integrated circuit assembly is shown to represent multiple integrated circuit assemblies of a semiconductor wafer.

[0019] refer to Figure 1A and Figure 1B A semiconductor wafer 100A is provided. The semiconductor wafer 100A may include a semiconductor substrate 110a, an integrated circuit assembly 120, a seal ring 130, and a test structure 140. The integrated circuit assembly 120 may be formed in and / or on the semiconductor substrate 110a and may be arranged along the X and / or Y directions. Seal rings 130 may surround the integrated circuit assembly 120. Test structures 140 may be disposed between the seal rings 130. In some embodiments, each of the integrated circuit assemblies 120 includes a plurality of interconnect wirings 122, through substrate vias (TSVs) 124, conductive pads 126, and integrated circuit devices (not shown).

[0020] An integrated circuit device of integrated circuit assembly 120 may be formed in and / or on semiconductor substrate 110a. The integrated circuit device of integrated circuit assembly 120 may include active components (e.g., transistors, etc.) and / or passive components (e.g., resistors, capacitors, inductors, etc.).

[0021] Interconnect wiring 122 of an integrated circuit assembly 120 may be formed on a semiconductor substrate 110a, and the interconnect wiring 122 may be electrically connected to integrated circuit devices of the integrated circuit assembly 120. Integrated circuit devices may be interconnected by the interconnect wiring 122 to form an integrated circuit. The interconnect wiring 122 of the integrated circuit assembly 120 may be embedded in a dielectric layer 150a of a semiconductor wafer 100A. In some embodiments, the interconnect wiring 122 may be formed of copper, a copper alloy, or other suitable conductive material. In some embodiments, the material of the dielectric layer 150a may include silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y , where x>0 and y>0) or other suitable dielectric materials.

[0022] A through-substrate via (TSV) 124 of the integrated circuit assembly 120 may be formed in the semiconductor substrate 110a, and the through-substrate via 124 extends into the dielectric layer 150a. The through-substrate via (TSV) 124 may be electrically connected to the interconnect wiring 122 of the integrated circuit assembly 120. In some embodiments, the number of TSVs 124 may be one or more, and the TSVs 124 may be arranged in a line, column, or array. In some embodiments, the TSVs 124 may be formed of copper, a copper alloy, or other suitable conductive material.

[0023] Conductive pads 126 of the integrated circuit assembly 120 may be formed in the dielectric layer 150a, and the conductive pads 126 may be stacked on the interconnect wiring 122. The conductive pads 126 may be electrically coupled to the interconnect wiring 122. In some embodiments, the material of the conductive pads 126 is different from the material of the interconnect wiring 122. In some embodiments, the conductive pads 126 may be aluminum pads, but other metal materials may be used.

[0024] Each of the sealing rings 130 may include a bottom portion 132 and a top portion 134 stacked on the bottom portion 132. The bottom portion 132 of the sealing ring 130 may surround an internal interconnect wiring 122 in the integrated circuit assembly 120, and the top portion 134 of the sealing ring 130 may surround a conductive pad 126 in the integrated circuit assembly 120. The sealing ring 130 may serve as a protective wall to protect the integrated circuit assembly 120 from stress. In some embodiments, the sealing ring 130 is electrically grounded or electrically floating. For example, the sealing ring 130 may be electrically insulated from the integrated circuit assembly 120. In some embodiments, the material of the bottom portion 132 is different from the material of the top portion 134.

[0025] Each of the test structures 140 may include a stack structure 142 and test pads 144 stacked on the stack structure 142. In some embodiments, the test pads 144 of the test structure 140 are electrically connected via the stack structure 142 to an underlying test device or test circuit (not shown). In some embodiments, the test pads 144 of the test structure 140 include process monitoring pads, such as wafer acceptance testing (WAT) pads. In some embodiments, during a wafer sawing process (e.g., in the following...) Figure 1B and Figure 1C Before (as shown in the diagram), a test process is performed to verify the conformity of the integrated circuit assembly 120 by testing the test structure 140. During the test process, the test pad 144 is electrically coupled to an external terminal via probes used for testing. The test pad 144 can be selected to test different properties of the semiconductor wafer 100A, such as leakage current, breakdown voltage, threshold voltage, effective channel length, saturation current, etc.

[0026] In some embodiments, the material of the stack structure 142 is different from the material of the test pad 144. In some embodiments, the test pad 144 of the test structure 140 may be shaped like a rectangular pattern when viewed from top view. In some alternative embodiments, the test pad of the test structure 140 may be shaped like a circular pattern when viewed from top view. This disclosure does not elaborate on the shape of the test pads. In some embodiments, there are no conductive features between the sealing ring 130 and the test structure 140. In other words, the test structure 140 is not electrically connected to the integrated circuit assembly 120 within the sealing ring 130. For example, the test structure 140 is electrically isolated from the internal wiring 122, TSV 124, conductive pad 126, and integrated circuit device of the integrated circuit assembly 120. Figure 1B In this figure, four test structures 140 are formed between two adjacent sealing rings 130. However, the number of test structures 140 shown is merely exemplary and not limited thereto. In some embodiments, the pattern density of the stacked structures 142 may be in the range of about 15% to about 40%. The pattern density of the stacked structures 142 is defined as the ratio of the area of ​​the stacked structures (i.e., the total area of ​​all stacked structures 142) to the area between the sealing rings 130.

[0027] In some embodiments, the interconnect wiring 122 of the integrated circuit assembly 120, the bottom portion 132 of the sealing ring 130, and the stacked structure 142 of the test structure 140 are formed simultaneously. In other words, the interconnect wiring 122 of the integrated circuit assembly 120, the bottom portion 132 of the sealing ring 130, and the stacked structure 142 of the test structure 140 may be formed of the same material and at the same horizontal height (e.g., a first horizontal height). In some embodiments, the conductive pad 126 of the integrated circuit assembly 120, the top portion 134 of the sealing ring 130, and the test pad 144 of the test structure 140 are formed simultaneously. In other words, the conductive pad 126 of the integrated circuit assembly 120, the top portion 134 of the sealing ring 130, and the test pad 144 of the test structure 140 may be formed of the same material and at the same horizontal height (e.g., a second horizontal height).

[0028] like Figure 1A As shown, the integrated circuit assembly 120 may further include a plurality of bonding metal pads 128. The bonding metal pads 128 are formed in the dielectric layer 150a. In some embodiments, some of the bonding metal pads 128 are electrically connected to underlying interconnect wiring 122 via vias 129. In some embodiments, vias 129 are not formed between some of the bonding metal pads 128 and the interconnect wiring 122. The bonding metal pads 128 may be formed of copper, aluminum, nickel, tungsten, or alloys thereof. In some embodiments, the top surface of the dielectric layer 150a is flush with the top surface of the bonding metal pads 128, the flushing being achieved by planarization performed during the formation of the bonding metal pads 128. Planarization may include a chemical mechanical polishing (CMP) process.

[0029] In some embodiments, after forming the bonding metal pads 128, a back-side polishing process is performed on the back surface of the semiconductor wafer 100A. During the back-side polishing process of the semiconductor wafer 100A, the semiconductor substrate 110a is polished to reduce the thickness of the semiconductor wafer 100A.

[0030] refer to Figure 1B and Figure 1CThe wafer sawing process is performed to monomerize the semiconductor wafer 100A. In some embodiments, a keep-out zone (KOZ) is imposed around the sealing ring 130 to provide sawing paths SP (e.g., kerfs) for the wafer sawing process, and the formation of the test pads 144 of the test structure 140 within the KOZ is constrained. That is, the test pads 144 of the test structure 140 may not be aligned along the sawing path SP. In other words, the sawing path SP may not be aligned with the test pads 144 of the test structure 140, and the test pads 144 of the test structure 140 may be kept at a distance from the sawing path SP. In some embodiments, the test pads 144 of the test structure 140 are located between a sawing path SP and an adjacent sealing ring 130, and there is no sawing path SP between the test structure 140 and an adjacent sealing ring 130. In some embodiments, the stacked structure 142 of the test structure 140 is located outside the KOZ, and the stacked structure 142 of the test structure 140 is also kept at a distance from the sawing path SP. In some embodiments, the KOZ is grid-shaped, and the sawing paths SP extending in the X direction and the sawing paths SP extending in the Y direction are aligned with the KOZ.

[0031] In some embodiments, such as Figure 1B As shown, test structure 140 is located adjacent to and distributed in the Y direction of the sawing path SP extending in the Y direction. In an alternative embodiment, test structure 140 is located adjacent to and distributed in the X direction of the sawing path SP extending in the X direction. In still some alternative embodiments, some test structures in test structure 140 are located adjacent to and distributed in the Y direction of the sawing path SP extending in the Y direction, and some test structures in test structure 140 are located adjacent to and distributed in the X direction of the sawing path SP extending in the X direction.

[0032] In some embodiments, the wafer sawing process involves using a rotating blade 210 (in... Figure 1CThe wafer 100A is cut through by sawing. During the wafer sawing process, the blade 210 cuts into the semiconductor wafer 100A along a sawing path SP aligned with the KOZ. In some embodiments, the area between the sealing ring 130 and the test pad 144 of the test structure 140 is the KOZ, and the width W1 of the KOZ is greater than the width W2 of the blade 210. The width W1 of the KOZ can be measured between the sidewall of the top portion 134 of the sealing ring 130 and the sidewall of the test pad 144 of the test structure 140. That is, the test pad 144 of the test structure 140 is laterally spaced from the adjacent sealing ring 130 by a distance greater than the width W2 of the blade 210 (i.e., width W1). In some embodiments, for example, the width W2 of the blade 210 may be approximately 40 micrometers. In some embodiments, for example, the width W1 of the KOZ may be greater than approximately 40 micrometers or approximately 50 micrometers and less than approximately 80 micrometers. In some embodiments, the test structure 140 is spaced apart from two adjacent sealing rings 130 on opposite sides by different distances.

[0033] like Figure 1C As shown, the blade 210 is positioned laterally between the sidewall of the top portion 134 of the sealing ring 130 and the sidewall of the test pad 144 of the test structure 140, and therefore does not overlap or contact the sidewall of the top portion 134 of the sealing ring 130 or the sidewall of the test pad 144 of the test structure 140 during the wafer sawing process. Because the blade 210 maintains a certain distance from the test pad 144 of the test structure 140 during the wafer sawing process, the blade 210 will not cut into the test pad 144 of the test structure 140, thus preventing the test pad from curling.

[0034] refer to Figure 1C and Figure 1D The semiconductor wafer 100A is modularized into multiple modular integrated circuit components 300A. For example... Figure 1D As described herein, each monolithic integrated circuit assembly 300A may include a semiconductor substrate 110, an integrated circuit assembly 120 (including interconnect wiring 122, TSV 124, conductive pad 126, metal pad 128, and via 129), a sealing ring 130, a test structure 140, and a dielectric layer 150. For example... Figure 1C and Figure 1D As shown, Figure 1D The materials and properties of the semiconductor substrate 110 and dielectric layer 150 are similar to those of the semiconductor substrate 110 and dielectric layer 150. Figure 1CThe semiconductor substrate 110a and dielectric layer 150a in the 300A have the same materials and characteristics, and will not be described again herein. In some embodiments, a portion of the sealing ring 130 in the 300A is located between the integrated circuit component 120 and the test structure 140 in the 300A. In some embodiments, when a wafer sawing process is performed, the test pad 144 of the test structure 140 is located next to the sawing path SP, such that the test pad 144 of a corresponding test structure in the 300A is laterally spaced from the sidewall SW1 of the 300A. In some embodiments, the stacked structure 142 of the test structure 140 in the 300A is also laterally spaced from the sidewall SW1 of the 300A. In other words, the test pad 144 and the stacked structure 142 of the test structure 140 may not be exposed at the sidewall SW1 of the 300A and may still be covered by the dielectric layer 150. In some embodiments, no aluminum pads (e.g., the top portion 134 of the sealing ring 130 and / or the test pad 144 of the test structure 140) are exposed at the sidewall SW1 of the monolithic integrated circuit assembly 300A.

[0035] Figure 2A , Figure 2C and Figure 2D This is a cross-sectional view schematically illustrating the process flow for fabricating a top semiconductor die according to some other embodiments of this disclosure. Figure 2B This is an illustrative description of some embodiments according to the present disclosure. Figure 2A The diagram shows a top view of the integrated circuit components, annular seal, and test structure. For illustrative purposes, Figure 2B The diagram also illustrates the sawing path used for the wafer sawing process. In some embodiments, an integrated circuit assembly is shown to represent multiple integrated circuit assemblies of a semiconductor wafer.

[0036] Figures 2A to 2D The process flow shown is similar to Figures 1A to 1D The process flow shown differs in that a separate wafer sawing process is performed to remove the test structure 140 from the monolithic integrated circuit assembly.

[0037] exist Figure 2A and Figure 2B In the middle, the semiconductor chip 100B is similar to Figure 1A and Figure 1BThe semiconductor wafer 100A differs in that the test pad 144 of the test structure 140 is spaced laterally from two adjacent sealing rings 130 on the opposite side by a distance greater than the width W2 (i.e., width W1) of the blade 210. In some embodiments, the test pad 144 of the test structure 140 is located laterally between two sawing paths SP. In some embodiments, the two sawing paths SP extending in the Y direction are located between two adjacent sealing rings 130.

[0038] exist Figure 2C and Figure 2D In this process, a semiconductor wafer 100B is monomerized into multiple monomerized integrated circuit components 300B. During a wafer dicing process, a test structure 140 is removed from the semiconductor wafer 100B to obtain the multiple monomerized integrated circuit components 300B without the test structure 140. In other words, the test structure 140 is completely removed during the wafer dicing process. Figure 2D As described herein, each monolithic integrated circuit assembly 300B may include a semiconductor substrate 110, an integrated circuit assembly 120 (including interconnect wiring 122, TSV 124, conductive pad 126, metal pad 128, and via 129), a sealing ring 130, and a dielectric layer 150. In some embodiments, the sealing ring 130 in the monolithic integrated circuit assembly 300B is spaced laterally from the sidewall SW2 of the monolithic integrated circuit assembly 300B. In some embodiments, no aluminum pads (e.g., the top portion 134 of the sealing ring 130 and / or the test pad 144 of the test structure 140) are exposed at the sidewall SW2 of the monolithic integrated circuit assembly 300B.

[0039] Figure 3A , Figure 3C and Figure 3D This is a cross-sectional view schematically illustrating the process flow for fabricating a top semiconductor die according to some other embodiments of this disclosure. Figure 3B This is an illustrative description of some embodiments according to the present disclosure. Figure 3A The diagram shows a top view of the integrated circuit components, annular seal, and test structure. For illustrative purposes, Figure 3B The diagram also shows the sawing path used for the wafer sawing process. In some embodiments, an integrated circuit assembly is shown to represent multiple integrated circuit assemblies of a semiconductor wafer.

[0040] Figures 3A to 3D The process flow shown is similar to Figures 1A to 1D The process flow shown differs in that a portion of the stacked structure 142 of the test structure 140 is arranged along the sawing path SP, while the test pad 144 of the test structure 140 is not arranged along the sawing path SP.

[0041] exist Figure 3A and Figure 3B In the middle, the semiconductor chip 100C is similar to Figure 1A and Figure 1B The semiconductor wafer 100A differs in that a portion of the stacked structure 142 of the test structure 140 is located within the KOZ, wherein the test pads 144 forming the test structure 140 in the KOZ are constrained. In other words, the stacked structure 142 of the test structure 140 partially overlaps with the sawing path SP.

[0042] exist Figure 3C and Figure 3D In this process, a semiconductor wafer 100C is individualized into multiple individualized integrated circuit components 300C. During a wafer dicing process, a portion of the stacked structure 142 of the test structure 140 is removed from the semiconductor wafer 100C to obtain the multiple individualized integrated circuit components 300C. Figure 3D As described herein, each monolithic integrated circuit assembly 300C may include a semiconductor substrate 110, an integrated circuit assembly 120 (including interconnect wiring 122, TSV 124, conductive pad 126, metal pad 128, and via 129), a sealing ring 130, a portion 142R1 of a stacked structure 142, a test pad 144, and a dielectric layer 150. In some embodiments, a portion of the sealing ring 130 in the monolithic integrated circuit assembly 300C is located between the integrated circuit assembly 120 and the test structure 140 in the monolithic integrated circuit assembly 300C. In some embodiments, when a wafer sawing process is performed, the test pad 144 of the test structure 140 is located next to the sawing path SP, such that the test pad 144 of a corresponding test structure in the test structure 140 of the monolithic integrated circuit assembly 300C is laterally spaced from the sidewall SW3 of the monolithic integrated circuit assembly 300C by a certain distance. In other words, the test pad 144 of the test structure 140 may not be exposed at the sidewall SW3 of the monolithic integrated circuit assembly 300C and may still be covered by the dielectric layer 150. In some embodiments, a portion 142R1 of the stacked structure 142 in the first monolithic integrated circuit assembly 300C is exposed at the sidewall SW3 of the monolithic integrated circuit assembly 300C. In some embodiments, the exposed surface of the portion 142R1 of the stacked structure 142 is substantially aligned with the sidewall SW3 of the monolithic integrated circuit assembly 300C. In some embodiments, no aluminum pads (e.g., the top portion 134 of the sealing ring 130 and / or the test pad 144 of the test structure 140) are exposed at the sidewall SW3 of the monolithic integrated circuit assembly 300C.

[0043] Figure 4A , Figure 4C and Figure 4DThis is a cross-sectional view schematically illustrating the process flow for fabricating a top semiconductor die according to some other embodiments of this disclosure. Figure 4B This is an illustrative description of some embodiments according to the present disclosure. Figure 4A The diagram shows a top view of the integrated circuit components, annular seal, and test structure. For illustrative purposes, Figure 4B The diagram also shows the sawing path used for the wafer sawing process. In some embodiments, an integrated circuit assembly is shown to represent multiple integrated circuit assemblies of a semiconductor wafer.

[0044] Figures 4A to 4D The process flow shown is similar to Figures 1A to 1D The process flow shown differs in that the test structure 140 is arranged along the sawing path SP and the test structure 140 does not include the test pads stacked on the stacked structure 142.

[0045] exist Figure 4A and Figure 4B In the context of semiconductor wafer 100D, it is similar to... Figure 1A and Figure 1B The semiconductor wafer 100A differs in that the test structure 140 does not include test pads. In other words, the test structure 140 may not have aluminum pads. In some embodiments, no test pads are formed on the stacked structure 142 when the conductive pads 126 of the integrated circuit assembly 120 and the top portion 134 of the sealing ring 130 are formed. In some embodiments, the stacked structure 142 of the test structure 140 is located within a KOZ in which the test pads forming the test structure 140 are constrained. In some embodiments, the area between the sealing rings 130 is a KOZ.

[0046] exist Figure 4C and Figure 4D In this process, a semiconductor wafer 100D is monomerized into multiple monomerized integrated circuit components 300D. During a wafer sawing process, test structures 140 (i.e., stacked structures 142) are arranged along the sawing path SP, and test structures 140 are partially removed from the semiconductor wafer 100D to obtain multiple monomerized integrated circuit components 300D with residual structures 142R2 of the test structures 140. For example... Figure 4DAs described herein, each monolithic integrated circuit assembly 300D may include a semiconductor substrate 110, an integrated circuit assembly 120 (including interconnect wiring 122, TSV 124, conductive pad 126, metal pad 128, and via 129), a sealing ring 130, a dielectric layer 150, and a residual structure 142R2. In some embodiments, the residual structure 142R2 is exposed at the sidewall SW4 of the monolithic integrated circuit assembly 300D. In some embodiments, the residual structure 142R2 does not have test pads (e.g., aluminum pads), such that no test pads (e.g., aluminum pads) are exposed at the sidewall SW4 of the monolithic integrated circuit assembly 300D. In some embodiments, the exposed surface of the residual structure 142R2 is substantially aligned with the sidewall SW4 of the monolithic integrated circuit assembly 300D. In some embodiments, no aluminum pads (e.g., the top portion 134 of the sealing ring 130 and / or the test pad 144 of the test structure 140) are exposed at the sidewall SW4 of the monolithic integrated circuit assembly 300D.

[0047] Packaging structure fabrication

[0048] Figures 5A to 5H This is a cross-sectional view schematically illustrating the process flow for fabricating a package structure for a system-on-integrated circuit (SoIC) chip according to some embodiments of the present disclosure. In some embodiments, an integrated circuit assembly is shown to represent a plurality of integrated circuit assemblies of a semiconductor wafer, and a package structure is shown to represent a plurality of package structures obtained in accordance with a manufacturing method.

[0049] refer to Figure 5A A semiconductor wafer 400a is provided. In some embodiments, the semiconductor wafer 400a includes a semiconductor substrate 410a and a bonding portion 420a located on the semiconductor substrate 410a. The semiconductor substrate 410a may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate 410a may contain other suitable semiconductor materials. In some embodiments, the semiconductor substrate 410a may include active components (e.g., transistors, etc.) and / or passive components (e.g., resistors, capacitors, inductors, etc.) formed in the semiconductor substrate 410a. In some embodiments, the semiconductor substrate 410a may include a semiconductor die embedded therein. The bonding portion 420a may include a dielectric layer 422a and a metal pad 424. In some embodiments, the metal pad 424 is embedded in the dielectric layer 422a, but the top surface of the metal pad 424 is exposed. The material of the dielectric layer 422a may include silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x(where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0) or other suitable dielectric materials. The material of the metal pad 424 may include copper, a copper alloy, or other suitable metallic materials. In some embodiments, the top surface of the dielectric layer 422a is flush with the top surface of the metal pad 424, said flushing being achieved by planarization performed during the formation of the metal pad 424. Planarization may include a chemical mechanical polishing (CMP) process.

[0050] refer to Figure 5B A plurality of top semiconductor dies 300 are provided and bonded to a bonding portion 420a of a semiconductor wafer 400a. The top semiconductor dies 300 may be qualified monolithic integrated circuit components among the aforementioned monolithic integrated circuit components 300A, 300B, 300C, or 300D. In some embodiments, qualified monolithic integrated circuit components are determined according to the aforementioned test process performed by testing the test structure 140. Each top semiconductor die 300, including a metal pad 128 and a dielectric layer 150, may be flipped and pressed onto the bonding portion 420a of the semiconductor wafer 400a, such that the metal pad 128 and the dielectric layer 150 contact the bonding portion 420a of the semiconductor wafer 400a. A bonding process is performed to bond a top semiconductor die 300 to a semiconductor wafer 400a via hybrid bonding, wherein the dielectric layer 150 of the top semiconductor die 300 is bonded to the dielectric layer 422a of the semiconductor wafer 400a, and the metal pad 128 of the top semiconductor die 300 is bonded to the metal pad 424 of the semiconductor wafer 400a. Specifically, the dielectric layer 150 of the top semiconductor die 300 and the dielectric layer 422a of the semiconductor wafer 400a are bonded by dielectric-to-dielectric bonding, while the metal pad 128 of the top semiconductor die 300 and the metal pad 424 of the semiconductor wafer 400a are bonded by metal-to-metal bonding.

[0051] refer to Figure 5B and Figure 5CAfter bonding the top semiconductor die 300 to the semiconductor wafer 400a, an insulating encapsulation 510a is formed on the semiconductor wafer 400a to laterally encapsulate the top semiconductor die 300. The insulating encapsulation 510a can be formed by an overlay molding process or a deposition process followed by a polishing process. In some embodiments, the material of the insulating encapsulation 510a includes deposited polyimide, deposited oxide, deposited nitride, or other suitable deposited dielectric material. In some alternative embodiments, the material of the insulating encapsulation 510a includes epoxy resin or other suitable molding compounds. In some embodiments, an insulating material is formed on the bonding portion 420a of the semiconductor wafer 400a by an overlay molding process or a deposition process to cover the sidewalls SW and bottom surface BS1 of the top semiconductor die 300. Figure 5B (as shown in the figure), and then the insulating material is polished by, for example, mechanical polishing and / or CMP processes, such that an insulating encapsulation 510a is formed and the bottom surface BS2 of the top semiconductor die 300 is exposed. Figure 5C (As shown in the diagram). During the polishing process of the insulating material, the semiconductor substrate 110 of the top semiconductor die 300 is polished and thinned downwards to expose the bottom surface BS3 of the TSV 124. In some embodiments, the bottom surface BS3 of the TSV 124 may be substantially coplanar with the bottom surface BS2 of the top semiconductor die 300. Figure 5C In some alternative embodiments not described herein, the TSV 124 may protrude slightly from the bottom surface BS2 of the top semiconductor die 300.

[0052] refer to Figure 5C and Figure 5D A recessed process is performed to remove a portion of the semiconductor substrate 110 of the top semiconductor die 300, exposing the bottom surface BS3 and upper sidewall USW of the TSV 124. In other words, the TSV 124 can penetrate through the semiconductor substrate 110 of the top semiconductor die 300 and protrude from the bottom surface BS4 of the top semiconductor die 300. In some embodiments, the semiconductor substrate 110 of the top semiconductor die 300 is recessed by performing a dry etching process. Figure 5D In some alternative embodiments not described herein, a portion of the insulating encapsulation 510a is removed during the recessing process, causing the TSV 124 to protrude above the top surface S1 of the insulating encapsulation 510a.

[0053] refer to Figure 5D and Figure 5EAn isolation layer 520 is formed to cover the bottom surface BS4 of the top semiconductor die 300 to separate the semiconductor substrate 110 of the top semiconductor die 300 from the subsequently formed overlay redistribution layer. In some embodiments, an isolation dielectric material (not shown) is formed on the bottom surface BS4 of the top semiconductor die 300 and the top surface S1 of the insulating encapsulation 510a, and the isolation dielectric material can be formed by deposition (e.g., CVD, etc.). Then, a planarization process is performed to planarize the isolation dielectric material to form the isolation layer 520. In some embodiments, the isolation dielectric material and TSV 124 are partially removed by polishing or grinding until the bottom surface BS3 of TSV 124 is coplanar with the top surface S1 of the insulating encapsulation 510a. After the planarization process, the isolation layer 520 covers the bottom surface BS4 of the top semiconductor die 300 and the upper sidewall USW of TSV 124. In some embodiments, the isolation dielectric material is planarized by performing a mechanical polishing process and / or a CMP process. Following the polishing or grinding step, a cleaning step may be selectively performed to clean and remove any residues resulting from the grinding or polishing step. In some alternative embodiments, the insulating encapsulation 510a may be lightly ground or polished during a planarization process performed on the insulating dielectric material. In some embodiments, after the planarization process, the top surface S2 of the insulating layer 520 is substantially flush with the bottom surface BS3 of the TSV 124 and the top surface S1 of the insulating encapsulation 510a.

[0054] In some embodiments, the insulating layer 520 may be made of an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride) or any suitable dielectric material. In some alternative embodiments, the insulating layer 520 may be made of an organic material (e.g., polybenzoxazole (PBO), polyimide (PI)) or other suitable polymers.

[0055] refer to Figure 5E and Figure 5FConductive vias 520 can be formed in an insulating encapsulation 510a. The conductive vias 520 can be electrically connected to a semiconductor wafer 400a via metal pads 424. In some embodiments, through-via holes are formed in the insulating encapsulation 510a using, for example, photolithography and etching processes. Conductive material is deposited on the insulating encapsulation 510a to fill the through-via holes. A removal process can be performed to partially remove the deposited conductive material until the insulating encapsulation 510a is exposed, thus forming the conductive via 520 in the insulating encapsulation 510a. The conductive material deposited for forming the conductive via 520 can be partially removed by etching, mechanical polishing, CMP, or other suitable removal processes or combinations thereof. For example, a seed layer is formed on the top semiconductor die 300 and the insulating encapsulation 510a by a sputtering process, a conductive material is formed on the seed layer by an electroplating process, and then a CMP process is performed to remove the conductive material and the seed layer outside the via to form a conductive via 520. The material of the conductive via 520 may include copper, copper alloy, or other suitable metal materials.

[0056] like Figure 5F As described herein, a redistribution layer 530a and electrical terminals 540 may be formed on the top semiconductor die 300 and the insulating enclosure 510a for electrical connection to the top semiconductor die 300 and the conductive via 520. In some embodiments, the redistribution layer 530a comprises alternating stacked dielectric layers and redistribution layers. The number of dielectric layers or redistribution layers is not limited by this disclosure. In some embodiments, the electrical terminals 540 include controlled collapse chip connection (C4) bumps, microbumps, solder balls, ball grid array (BGA) balls, or other suitable terminals for providing external connectivity. Other possible forms and shapes of the electrical terminals 540 may be utilized depending on design requirements. In some embodiments, soldering and reflow processes are selectively performed to enhance adhesion between the electrical terminals 540 and the redistribution layer 530a.

[0057] refer to Figure 5F and Figure 5G After forming the redistribution layer 530a and electrical terminals 540, the wafer-level package including semiconductor wafer 400a, top semiconductor die 300, insulating encapsulator 510a, redistribution layer 530a and electrical terminals 540 is flipped and placed on the tape TP.

[0058] refer to Figure 5G and Figure 5HA wafer sawing process is performed to monolithize the structure mounted on the strip TP. The sawed structure is then removed from the strip TP to form multiple monolithized SoIC packages 10. In some embodiments, the wafer sawing process is, for example, a laser cutting process, a mechanical cutting process, or other suitable processes. Reference will be made to... Figure 5H The detailed structure of the monolithic SoIC package 10 is described.

[0059] like Figure 5H As described, the SoIC package 10 may include a bottom semiconductor die 400, a top semiconductor die 300, an insulating encapsulator 510, a conductive via 520, a redistribution layer 530, and electrical terminals 540. The bottom semiconductor die 400 may include a semiconductor substrate 410 and a bonding portion 420 located on the semiconductor substrate 410. The bonding portion 420 may include a dielectric layer 422 and metal pads 424. The top semiconductor die 300 may be located on top of the bottom semiconductor die 400 and electrically connected to the bottom semiconductor die 400. The insulating encapsulator 510 may laterally encapsulate the top semiconductor die 300 and the conductive via 520. The redistribution layer 530 may be located on top of the top semiconductor die 300 and the conductive via 520 and electrically connected to the top semiconductor die 300 and the conductive via 520. Electrical terminal 540 may be located above the redistribution layer 530 and electrically connected to the top semiconductor die 300 and conductive via 520 through the redistribution layer 530. For example... Figure 5G and Figure 5H As shown, Figure 5H The materials and characteristics of the bottom semiconductor die 400, insulating encapsulation 510, and redistribution layer 530 are similar to those of the bottom semiconductor die 400, insulating encapsulation 510, and redistribution layer 530. Figure 5G The semiconductor wafer 400a, insulating encapsulator 510a, and redistribution layer 530a in the SoIC package have the same materials and characteristics, and will not be described again here. The SoIC package 10 may include hybrid bonding interfaces, which include dielectric-to-dielectric bonding interfaces (i.e., dielectric-to-dielectric bonding interfaces between dielectric layer 150 and dielectric layer 422) and metal-to-metal bonding interfaces (i.e., metal-to-metal bonding interfaces between metal pad 128 and metal pad 424). At this point, the fabrication of the SoIC package 10 is substantially completed.

[0060] Figures 6A to 6D Various embodiments according to this disclosure Figure 5H An enlarged view of region X' shown in the diagram.

[0061] refer to Figure 5H and Figure 6A In it Figure 5H The top semiconductor die 300 is Figure 1DIn an embodiment of the monolithic integrated circuit assembly 300A, the test structure 140 is spaced apart from the insulating encapsulation 510 by a portion of the dielectric layer 150. In other words, the sidewall SW1 of the monolithic integrated circuit assembly 300A is located between the test structure 140 and the insulating encapsulation 510. In some embodiments, the test structure 140 is located between the semiconductor substrate 110 of the top semiconductor die 300 and the bonding portion 420 of the bottom semiconductor die 400. In some embodiments, the test structure 140 is embedded in the dielectric layer 150 and spaced apart from the bottom semiconductor die 400 by a portion of the dielectric layer 150.

[0062] refer to Figure 5H and Figure 6B In it Figure 5H The top semiconductor die 300 is Figure 2D In an embodiment of the monolithic integrated circuit assembly 300B, the sealing ring 130 is spaced apart from the insulating encapsulation 510 by a portion of the dielectric layer 150. In other words, the sidewall SW2 of the monolithic integrated circuit assembly 300B is located between the sealing ring 130 and the insulating encapsulation 510.

[0063] refer to Figure 5H and Figure 6C In it Figure 5H The top semiconductor die 300 is Figure 3D In an embodiment of the monolithic integrated circuit assembly 300C, the test pad 144 of the test structure 140 is spaced apart from the insulating encapsulation 510 by a portion of the dielectric layer 150, and a portion 142R1 of the stacked structure 142 contacts the insulating encapsulation 510. In other words, the sidewall SW3 of the monolithic integrated circuit assembly 300C is located between the test pad 144 of the test structure 140 and the insulating encapsulation 510. In some embodiments, the test structure 140 is located between the semiconductor substrate 110 of the top semiconductor die 300 and the bonding portion 420 of the bottom semiconductor die 400. In some embodiments, the test structure 140 is embedded in the dielectric layer 150 and spaced apart from the bottom semiconductor die 400 by a portion of the dielectric layer 150.

[0064] refer to Figure 5H and Figure 6D In it Figure 5H The top semiconductor die 300 is Figure 4DIn an embodiment of the monolithic integrated circuit assembly 300D, the residual structure 142R2 of the test structure 140 is in contact with the insulating encapsulation 510. In some embodiments, the residual structure 142R2 of the test structure 140 is located between the semiconductor substrate 110 of the top semiconductor die 300 and the bonding portion 420 of the bottom semiconductor die 400. In some embodiments, the residual structure 142R2 of the test structure 140 is embedded in the dielectric layer 150 and spaced apart from the bottom semiconductor die 400 by a portion of the dielectric layer 150.

[0065] Since the blade 210 does not contact or cut the test pads 144 of the test structure 140 during the wafer sawing process, the problem of test pad curling is prevented. Therefore, the bonding yield of SoIC chips can be improved.

[0066] According to some embodiments of this disclosure, a method includes the following steps: A semiconductor wafer is provided, the semiconductor wafer including an integrated circuit assembly, sealing rings respectively surrounding the integrated circuit assembly, and test structures disposed between the sealing rings. A first wafer sawing process is performed at least along a first path to monomerize the semiconductor wafer into a plurality of first monomerized integrated circuit assemblies, each of the plurality of first monomerized integrated circuit assemblies including one of the test structures. When the first wafer sawing process is performed, the test pads of the test structures are located adjacent to the first path, such that the test pads of a corresponding test structure in the first monomerized integrated circuit assembly are laterally spaced from the sidewall of the first monomerized integrated circuit assembly.

[0067] In the above method, providing the semiconductor wafer includes: forming a plurality of stacked structures of the plurality of test structures on a semiconductor substrate; and forming a plurality of test pads on the plurality of stacked structures.

[0068] In the above method, providing the semiconductor wafer further includes: forming a plurality of interconnect wirings of the plurality of integrated circuit components on the semiconductor substrate; and forming a plurality of conductive pads on the plurality of interconnect wirings, wherein the plurality of interconnect wirings and the plurality of stacked structures of the plurality of test structures are simultaneously formed at a first horizontal height, and the plurality of conductive pads and the plurality of test pads of the plurality of test structures are simultaneously formed at a second horizontal height.

[0069] In the above method, the material of the plurality of test pads is different from the material of the plurality of stacked structures.

[0070] In the above method, the plurality of stacked structures of the plurality of test structures are located next to the first path and at a certain distance from the first path, such that the stacked structures of the test structures in the first monolithic integrated circuit assembly are spaced apart from the sidewalls of the first monolithic integrated circuit assembly in the lateral direction.

[0071] In the above method, the plurality of stacked structures of the plurality of test structures partially overlap with the first path, such that a portion of the stacked structure in the first monolithic integrated circuit assembly is exposed at the sidewall of the first monolithic integrated circuit assembly.

[0072] The above method further includes: after performing the first wafer sawing process, performing a second wafer sawing process along a second path between the plurality of test structures and the plurality of sealing rings to cut the plurality of test structures from the plurality of first monolithic integrated circuit components, thereby obtaining a plurality of second monolithic integrated circuit components.

[0073] The above method further includes: performing a test process to verify whether the plurality of integrated circuit components are qualified by testing the plurality of test structures; and bonding a qualified first monolithic integrated circuit component among the plurality of first monolithic integrated circuit components to a semiconductor device according to the test process.

[0074] In the above method, the first wafer sawing process is performed using a blade.

[0075] According to some embodiments of this disclosure, a method includes the following steps: A semiconductor wafer is provided, the semiconductor wafer including an integrated circuit assembly, sealing rings respectively surrounding the integrated circuit assembly, and test structures disposed between the sealing rings. A wafer sawing process is performed at least along a path to monomerize the semiconductor wafer into a plurality of monomerized integrated circuit assemblies. When the wafer sawing process is performed, the test structures are arranged along the path such that each of the monomerized integrated circuit assemblies includes a residual structure of a corresponding test structure, wherein the residual structure does not have an aluminum pad.

[0076] In the above method, no aluminum pads are exposed on the sidewalls of the monolithic integrated circuit assembly.

[0077] In the above method, providing the semiconductor wafer further includes: simultaneously forming a plurality of interconnect wirings of the plurality of integrated circuit components and a plurality of stacked structures of the plurality of test structures on a semiconductor substrate at a first horizontal height; and forming a plurality of conductive pads on the plurality of interconnect wirings at a second horizontal height, wherein the plurality of stacked structures of the plurality of test structures are partially removed during the wafer sawing process to form the residual structure of the test structures in the monolithic integrated circuit components.

[0078] In the above method, the wafer sawing process is performed using a blade.

[0079] According to some embodiments of this disclosure, an apparatus includes a first semiconductor die. The first semiconductor die includes an integrated circuit assembly, a sealing ring, and a test structure. The sealing ring surrounds the integrated circuit assembly. A portion of the sealing ring is located between the integrated circuit assembly and the test structure, and the test structure includes a test pad spaced laterally from a sidewall of the first semiconductor die.

[0080] In the above-described apparatus, the test structure further includes a stacked structure, and the test pads are stacked on the stacked structure.

[0081] In the above-described apparatus, the integrated circuit assembly includes interconnect wiring and conductive pads stacked on the interconnect wiring, the interconnect wiring of the integrated circuit assembly and the stacked structure of the test structure are located at a first horizontal height, and the conductive pads of the integrated circuit assembly and the test pads of the test structure are located at a second horizontal height.

[0082] In the above-described apparatus, the material of the test pad is different from the material of the stacked structure.

[0083] In the above-described apparatus, the stacked structure of the test structure is laterally spaced from the sidewall of the first semiconductor die.

[0084] In the above-described apparatus, a portion of the stacked structure of the test structure is exposed at the sidewall of the first semiconductor die.

[0085] The device further includes: a second semiconductor die bonded to the first semiconductor die; an insulating encapsulation located on the second semiconductor die and laterally encapsulating the first semiconductor die; and a redistribution layer located on the insulating encapsulation and the first semiconductor die.

[0086] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor wafer is provided, the semiconductor wafer including a plurality of integrated circuit components, a plurality of sealing rings respectively surrounding the plurality of integrated circuit components, and a plurality of test structures disposed between the plurality of sealing rings; A first wafer sawing process is performed at least along a first path to monomerize the semiconductor wafer into a plurality of first monomerized integrated circuit components, each of the plurality of first monomerized integrated circuit components including a test structure among the plurality of test structures. When the first wafer sawing process is performed, the multiple test pads of the multiple test structures are located next to the first path, such that the test pads of one of the multiple test structures in the first monolithic integrated circuit assembly are spaced apart from the sidewall of the first monolithic integrated circuit assembly by a certain distance in the lateral direction. as well as A second wafer sawing process is performed along a second path between the plurality of test structures and the plurality of sealing rings to cut the plurality of test structures from the plurality of first monolithic integrated circuit components, thereby obtaining a plurality of second monolithic integrated circuit components.

2. The manufacturing method according to claim 1, characterized in that, The semiconductor wafer includes: a plurality of stacked structures on which the plurality of test structures are formed on a semiconductor substrate; and a plurality of test pads are formed on the plurality of stacked structures.

3. The manufacturing method according to claim 2, characterized in that, The semiconductor wafer further includes: forming a plurality of interconnect wirings of the plurality of integrated circuit components on the semiconductor substrate; and forming a plurality of conductive pads on the plurality of interconnect wirings, wherein the plurality of interconnect wirings and the plurality of stacked structures of the plurality of test structures are simultaneously formed at a first horizontal height, and the plurality of conductive pads and the plurality of test pads of the plurality of test structures are simultaneously formed at a second horizontal height.

4. The manufacturing method according to claim 2, characterized in that, The materials of the multiple test pads are different from the materials of the multiple stacked structures.

5. The manufacturing method according to claim 2, characterized in that, The multiple stacked structures of the multiple test structures are located next to the first path and at a certain distance from the first path, such that the stacked structures of the test structures in the first monolithic integrated circuit assembly are spaced apart from the sidewalls of the first monolithic integrated circuit assembly in the lateral direction.

6. The manufacturing method according to claim 2, characterized in that, The multiple stacked structures of the multiple test structures are not exposed at the sidewall of the first monolithic integrated circuit assembly.

7. The manufacturing method according to claim 1, characterized in that, The first path is separated from the second path.

8. The manufacturing method according to claim 1, characterized in that, Also includes: A testing process is performed to verify the conformity of the multiple integrated circuit components by testing the multiple test structures; as well as According to the test process, a qualified first monolithic integrated circuit component among the plurality of first monolithic integrated circuit components is bonded to a semiconductor device.

9. The manufacturing method according to claim 1, characterized in that, The first wafer sawing process is performed using a blade.

10. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor wafer is provided, the semiconductor wafer including a plurality of integrated circuit components, a plurality of sealing rings respectively surrounding the plurality of integrated circuit components, and a plurality of test structures disposed between the plurality of sealing rings; A first wafer sawing process is performed at least along a first path to monomerize the semiconductor wafer into a plurality of first monomerized integrated circuit components, wherein, when the first wafer sawing process is performed, the plurality of test structures are arranged along the first path such that each of the plurality of first monomerized integrated circuit components includes a residual structure of a corresponding test structure of the plurality of test structures, wherein the residual structure does not have an aluminum pad. as well as A second wafer sawing process is performed along a second path between the plurality of test structures and the plurality of sealing rings to cut the plurality of test structures from the plurality of first monolithic integrated circuit components, thereby obtaining a plurality of second monolithic integrated circuit components.

11. The manufacturing method according to claim 10, characterized in that, The multiple test structures do not come into contact with the blades used in the first wafer sawing process.

12. The manufacturing method according to claim 10, characterized in that, The semiconductor wafer also includes: Multiple interconnects of the multiple integrated circuit components and multiple stacked structures of the multiple test structures are simultaneously formed on a semiconductor substrate at a first horizontal height; and Multiple conductive pads are formed at a second horizontal height on the multiple interconnecting wires.

13. The manufacturing method according to claim 10, characterized in that, The first wafer sawing process and the second wafer sawing process are performed using blades.

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